Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	64655677	1			T1	113490		T2	224535		T3	17327
all_pins[1]	64655677	1			T1	113490		T2	224535		T3	17327
all_pins[2]	64655677	1			T1	113490		T2	224535		T3	17327

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	193364271	1			T1	340117		T2	673011		T3	51744
values[0x1]	602760	1			T1	353		T2	594		T3	237
transitions[0x0=>0x1]	600624	1			T1	353		T2	594		T3	237
transitions[0x1=>0x0]	600647	1			T1	353		T2	594		T3	237

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	64355418	1			T1	113137		T2	223941		T3	17145
all_pins[0]	values[0x1]	300259	1			T1	353		T2	594		T3	182
all_pins[0]	transitions[0x0=>0x1]	300246	1			T1	353		T2	594		T3	182
all_pins[0]	transitions[0x1=>0x0]	4902	1			T3	55		T34	3		T9	12
all_pins[1]	values[0x0]	64650762	1			T1	113490		T2	224535		T3	17272
all_pins[1]	values[0x1]	4915	1			T3	55		T34	3		T9	12
all_pins[1]	transitions[0x0=>0x1]	4615	1			T3	55		T34	3		T9	3
all_pins[1]	transitions[0x1=>0x0]	297286	1			T9	4283		T20	284		T16	4848
all_pins[2]	values[0x0]	64358091	1			T1	113490		T2	224535		T3	17327
all_pins[2]	values[0x1]	297586	1			T9	4292		T20	284		T16	4864
all_pins[2]	transitions[0x0=>0x1]	295763	1			T9	4270		T20	283		T16	4832
all_pins[2]	transitions[0x1=>0x0]	298459	1			T1	353		T2	594		T3	182