Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	590	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	4983	1			T3	16		T7	15		T8	8
len_601_800	11057	1			T3	42		T7	35		T8	20
len_401_600	7252	1			T3	33		T7	22		T8	8
len_201_400	8676	1			T3	8		T33	251		T7	8
len_65_200	34597	1			T3	7		T33	680		T7	6
len_min_for_xof_require_squeeze	460	1			T33	10		T172	1		T212	9
len_keccak_block_sizes[72]	354	1			T33	5		T105	1		T212	9
len_keccak_block_sizes[104]	344	1			T33	5		T212	9		T213	2
len_keccak_block_sizes[136]	357	1			T33	5		T105	1		T212	9
len_keccak_block_sizes[144]	140	1			T33	5		T62	1		T214	5
len_keccak_block_sizes[168]	141	1			T33	5		T105	1		T215	1
len_datapath_width	13644	1			T1	246		T3	1		T33	5
len_2_63	125026	1			T2	390		T3	12		T33	1329
len_1	62	1			T69	3		T131	1		T216	1