Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7891614 |
1 |
|
|
T1 |
3936 |
|
T2 |
2730 |
|
T3 |
19863 |
auto[1] |
7891551 |
1 |
|
|
T1 |
3936 |
|
T2 |
2730 |
|
T3 |
19863 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
15651925 |
1 |
|
|
T1 |
7872 |
|
T2 |
5460 |
|
T3 |
39556 |
triple_byte_access |
43664 |
1 |
|
|
T3 |
50 |
|
T33 |
620 |
|
T7 |
38 |
halfword_access |
43854 |
1 |
|
|
T3 |
60 |
|
T33 |
632 |
|
T7 |
38 |
byte_access |
43722 |
1 |
|
|
T3 |
60 |
|
T33 |
620 |
|
T7 |
46 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
7825994 |
1 |
|
|
T1 |
3936 |
|
T2 |
2730 |
|
T3 |
19778 |
auto[0] |
triple_byte_access |
21832 |
1 |
|
|
T3 |
25 |
|
T33 |
310 |
|
T7 |
19 |
auto[0] |
halfword_access |
21927 |
1 |
|
|
T3 |
30 |
|
T33 |
316 |
|
T7 |
19 |
auto[0] |
byte_access |
21861 |
1 |
|
|
T3 |
30 |
|
T33 |
310 |
|
T7 |
23 |
auto[1] |
word_access |
7825931 |
1 |
|
|
T1 |
3936 |
|
T2 |
2730 |
|
T3 |
19778 |
auto[1] |
triple_byte_access |
21832 |
1 |
|
|
T3 |
25 |
|
T33 |
310 |
|
T7 |
19 |
auto[1] |
halfword_access |
21927 |
1 |
|
|
T3 |
30 |
|
T33 |
316 |
|
T7 |
19 |
auto[1] |
byte_access |
21861 |
1 |
|
|
T3 |
30 |
|
T33 |
310 |
|
T7 |
23 |