Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
92.59 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 2 16 88.89


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 2 16 88.89 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 275 1 T143 7 T144 7 T145 4
all_values[1] 275 1 T143 7 T144 7 T145 4
all_values[2] 275 1 T143 7 T144 7 T145 4


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 437 1 T143 12 T144 14 T145 3
auto[1] 388 1 T143 9 T144 7 T145 9


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 372 1 T143 9 T144 10 T145 6
auto[1] 453 1 T143 12 T144 11 T145 6


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 479 1 T143 13 T144 12 T145 9
auto[1] 346 1 T143 8 T144 9 T145 3


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 2 16 88.89 2
Automatically Generated Cross Bins 18 2 16 88.89 2
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Element holes
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTNUMBERSTATUS
[all_values[1]] [auto[0]] * [auto[1]] -- -- 2


Covered bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 60 1 T143 3 T144 3 T192 5
all_values[0] auto[0] auto[0] auto[1] 30 1 T186 1 T193 1 T194 1
all_values[0] auto[0] auto[1] auto[0] 47 1 T143 1 T144 2 T145 2
all_values[0] auto[0] auto[1] auto[1] 30 1 T143 1 T145 1 T195 1
all_values[0] auto[1] auto[0] auto[1] 55 1 T144 2 T186 1 T192 1
all_values[0] auto[1] auto[1] auto[1] 53 1 T143 2 T145 1 T187 1
all_values[1] auto[0] auto[0] auto[0] 78 1 T143 4 T144 3 T145 1
all_values[1] auto[0] auto[1] auto[0] 78 1 T143 1 T144 2 T145 2
all_values[1] auto[1] auto[0] auto[1] 59 1 T143 1 T144 1 T186 1
all_values[1] auto[1] auto[1] auto[1] 60 1 T143 1 T144 1 T145 1
all_values[2] auto[0] auto[0] auto[0] 58 1 T186 4 T192 2 T187 3
all_values[2] auto[0] auto[0] auto[1] 28 1 T143 2 T145 1 T192 1
all_values[2] auto[0] auto[1] auto[0] 51 1 T145 1 T192 1 T187 2
all_values[2] auto[0] auto[1] auto[1] 19 1 T143 1 T144 2 T145 1
all_values[2] auto[1] auto[0] auto[1] 69 1 T143 2 T144 5 T145 1
all_values[2] auto[1] auto[1] auto[1] 50 1 T143 2 T187 1 T196 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%