Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	65549849	1			T2	713		T3	112216		T18	993
all_values[1]	65549849	1			T2	713		T3	112216		T18	993
all_values[2]	65549849	1			T2	713		T3	112216		T18	993

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

530691

1

T2

122

T3

21

T18

5

auto[1]

196118856

1

T2

2017

T3

336627

T18

2974

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

195721338

1

T2

1944

T3

335538

T18

2535

auto[1]

928209

1

T2

195

T3

1110

T18

444

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	194962	1			T2	88		T3	1		T18	3
all_values[0]	auto[0]	auto[1]	1959	1			T2	10		T3	2		T18	2
all_values[0]	auto[1]	auto[0]	65045484	1			T2	560		T3	111845		T18	842
all_values[0]	auto[1]	auto[1]	307444	1			T2	55		T3	368		T18	146
all_values[1]	auto[0]	auto[0]	191359	1			T2	22		T3	6		T30	12
all_values[1]	auto[0]	auto[1]	1402	1			T2	2		T3	5		T30	2
all_values[1]	auto[1]	auto[0]	65049087	1			T2	626		T3	111840		T18	845
all_values[1]	auto[1]	auto[1]	308001	1			T2	63		T3	365		T18	148
all_values[2]	auto[0]	auto[0]	139630	1			T3	4		T30	24		T7	67
all_values[2]	auto[0]	auto[1]	1379	1			T3	3		T30	4		T7	12
all_values[2]	auto[1]	auto[0]	65100816	1			T2	648		T3	111842		T18	845
all_values[2]	auto[1]	auto[1]	308024	1			T2	65		T3	367		T18	148