Summary for Variable entropy_edn_mode_enabled
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
235606 | 
1 | 
 | 
 | 
T2 | 
2 | 
 | 
T3 | 
2 | 
 | 
T18 | 
188 | 
| auto[1] | 
189884 | 
1 | 
 | 
 | 
T2 | 
84 | 
 | 
T3 | 
490 | 
 | 
T7 | 
330 | 
Summary for Variable prescaler_val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
3 | 
0 | 
3 | 
100.00 | 
User Defined Bins for prescaler_val
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| higher_val | 
106375 | 
1 | 
 | 
 | 
T2 | 
18 | 
 | 
T3 | 
88 | 
 | 
T18 | 
52 | 
| lower_val | 
105479 | 
1 | 
 | 
 | 
T2 | 
16 | 
 | 
T3 | 
134 | 
 | 
T18 | 
52 | 
| zero_val | 
1481 | 
1 | 
 | 
 | 
T2 | 
1 | 
 | 
T3 | 
1 | 
 | 
T18 | 
1 | 
Summary for Variable wait_timer_val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
3 | 
0 | 
3 | 
100.00 | 
User Defined Bins for wait_timer_val
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| higher_val | 
164338 | 
1 | 
 | 
 | 
T2 | 
30 | 
 | 
T3 | 
112 | 
 | 
T18 | 
90 | 
| lower_val | 
165070 | 
1 | 
 | 
 | 
T2 | 
22 | 
 | 
T3 | 
134 | 
 | 
T18 | 
98 | 
| zero_val | 
96082 | 
1 | 
 | 
 | 
T2 | 
34 | 
 | 
T3 | 
246 | 
 | 
T7 | 
160 | 
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
18 | 
0 | 
18 | 
100.00 | 
 | 
Automatically Generated Cross Bins for entropy_timer_cross
Bins
| prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| higher_val | 
higher_val | 
auto[0] | 
28941 | 
1 | 
 | 
 | 
T18 | 
20 | 
 | 
T30 | 
19 | 
 | 
T7 | 
38 | 
| higher_val | 
higher_val | 
auto[1] | 
11767 | 
1 | 
 | 
 | 
T2 | 
3 | 
 | 
T3 | 
22 | 
 | 
T7 | 
22 | 
| higher_val | 
lower_val | 
auto[0] | 
29202 | 
1 | 
 | 
 | 
T18 | 
32 | 
 | 
T30 | 
17 | 
 | 
T7 | 
28 | 
| higher_val | 
lower_val | 
auto[1] | 
12094 | 
1 | 
 | 
 | 
T2 | 
7 | 
 | 
T3 | 
19 | 
 | 
T7 | 
24 | 
| higher_val | 
zero_val | 
auto[0] | 
83 | 
1 | 
 | 
 | 
T152 | 
1 | 
 | 
T29 | 
1 | 
 | 
T164 | 
1 | 
| higher_val | 
zero_val | 
auto[1] | 
24288 | 
1 | 
 | 
 | 
T2 | 
8 | 
 | 
T3 | 
47 | 
 | 
T7 | 
52 | 
| lower_val | 
higher_val | 
auto[0] | 
29159 | 
1 | 
 | 
 | 
T18 | 
25 | 
 | 
T30 | 
14 | 
 | 
T7 | 
27 | 
| lower_val | 
higher_val | 
auto[1] | 
11524 | 
1 | 
 | 
 | 
T2 | 
6 | 
 | 
T3 | 
39 | 
 | 
T7 | 
25 | 
| lower_val | 
lower_val | 
auto[0] | 
29319 | 
1 | 
 | 
 | 
T18 | 
27 | 
 | 
T30 | 
14 | 
 | 
T7 | 
38 | 
| lower_val | 
lower_val | 
auto[1] | 
11637 | 
1 | 
 | 
 | 
T2 | 
4 | 
 | 
T3 | 
40 | 
 | 
T7 | 
19 | 
| lower_val | 
zero_val | 
auto[0] | 
82 | 
1 | 
 | 
 | 
T7 | 
1 | 
 | 
T36 | 
1 | 
 | 
T71 | 
1 | 
| lower_val | 
zero_val | 
auto[1] | 
23758 | 
1 | 
 | 
 | 
T2 | 
6 | 
 | 
T3 | 
55 | 
 | 
T7 | 
40 | 
| zero_val | 
higher_val | 
auto[0] | 
450 | 
1 | 
 | 
 | 
T18 | 
1 | 
 | 
T7 | 
2 | 
 | 
T34 | 
1 | 
| zero_val | 
higher_val | 
auto[1] | 
100 | 
1 | 
 | 
 | 
T16 | 
1 | 
 | 
T17 | 
1 | 
 | 
T55 | 
2 | 
| zero_val | 
lower_val | 
auto[0] | 
447 | 
1 | 
 | 
 | 
T30 | 
1 | 
 | 
T35 | 
7 | 
 | 
T37 | 
1 | 
| zero_val | 
lower_val | 
auto[1] | 
105 | 
1 | 
 | 
 | 
T7 | 
2 | 
 | 
T165 | 
1 | 
 | 
T16 | 
1 | 
| zero_val | 
zero_val | 
auto[0] | 
257 | 
1 | 
 | 
 | 
T2 | 
1 | 
 | 
T3 | 
1 | 
 | 
T7 | 
1 | 
| zero_val | 
zero_val | 
auto[1] | 
122 | 
1 | 
 | 
 | 
T165 | 
1 | 
 | 
T17 | 
2 | 
 | 
T55 | 
1 |