Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	65549849	1			T2	713		T3	112216		T18	993
all_pins[1]	65549849	1			T2	713		T3	112216		T18	993
all_pins[2]	65549849	1			T2	713		T3	112216		T18	993

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	196051663	1			T2	2084		T3	336280		T18	2833
values[0x1]	597884	1			T2	55		T3	368		T18	146
transitions[0x0=>0x1]	595846	1			T2	55		T3	368		T18	146
transitions[0x1=>0x0]	595872	1			T2	55		T3	368		T18	146

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	65242405	1			T2	658		T3	111848		T18	847
all_pins[0]	values[0x1]	307444	1			T2	55		T3	368		T18	146
all_pins[0]	transitions[0x0=>0x1]	307429	1			T2	55		T3	368		T18	146
all_pins[0]	transitions[0x1=>0x0]	5138	1			T7	68		T8	10		T62	13
all_pins[1]	values[0x0]	65544696	1			T2	713		T3	112216		T18	993
all_pins[1]	values[0x1]	5153	1			T7	68		T8	10		T62	13
all_pins[1]	transitions[0x0=>0x1]	4924	1			T7	57		T8	10		T62	13
all_pins[1]	transitions[0x1=>0x0]	285058	1			T7	6772		T10	392		T38	466
all_pins[2]	values[0x0]	65264562	1			T2	713		T3	112216		T18	993
all_pins[2]	values[0x1]	285287	1			T7	6783		T10	392		T38	466
all_pins[2]	transitions[0x0=>0x1]	283493	1			T7	6746		T10	392		T38	466
all_pins[2]	transitions[0x1=>0x0]	305676	1			T2	55		T3	368		T18	146