Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8301135 |
1 |
|
|
T2 |
7302 |
|
T3 |
3936 |
|
T18 |
3455 |
auto[1] |
8301101 |
1 |
|
|
T2 |
7302 |
|
T3 |
3936 |
|
T18 |
3455 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
16462364 |
1 |
|
|
T2 |
14536 |
|
T3 |
7872 |
|
T18 |
6782 |
triple_byte_access |
46346 |
1 |
|
|
T2 |
18 |
|
T18 |
60 |
|
T30 |
30 |
halfword_access |
47004 |
1 |
|
|
T2 |
18 |
|
T18 |
42 |
|
T30 |
42 |
byte_access |
46522 |
1 |
|
|
T2 |
32 |
|
T18 |
26 |
|
T30 |
20 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
8231199 |
1 |
|
|
T2 |
7268 |
|
T3 |
3936 |
|
T18 |
3391 |
auto[0] |
triple_byte_access |
23173 |
1 |
|
|
T2 |
9 |
|
T18 |
30 |
|
T30 |
15 |
auto[0] |
halfword_access |
23502 |
1 |
|
|
T2 |
9 |
|
T18 |
21 |
|
T30 |
21 |
auto[0] |
byte_access |
23261 |
1 |
|
|
T2 |
16 |
|
T18 |
13 |
|
T30 |
10 |
auto[1] |
word_access |
8231165 |
1 |
|
|
T2 |
7268 |
|
T3 |
3936 |
|
T18 |
3391 |
auto[1] |
triple_byte_access |
23173 |
1 |
|
|
T2 |
9 |
|
T18 |
30 |
|
T30 |
15 |
auto[1] |
halfword_access |
23502 |
1 |
|
|
T2 |
9 |
|
T18 |
21 |
|
T30 |
21 |
auto[1] |
byte_access |
23261 |
1 |
|
|
T2 |
16 |
|
T18 |
13 |
|
T30 |
10 |