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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.10 97.89 92.58 99.89 76.06 95.53 98.89 97.88


Total test records in report: 1158
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T1014 /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.959399506 Aug 06 04:53:32 PM PDT 24 Aug 06 04:53:34 PM PDT 24 42116234 ps
T1015 /workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.1057130635 Aug 06 04:53:21 PM PDT 24 Aug 06 04:53:24 PM PDT 24 279976631 ps
T1016 /workspace/coverage/cover_reg_top/40.kmac_intr_test.2151887279 Aug 06 04:53:41 PM PDT 24 Aug 06 04:53:42 PM PDT 24 13233598 ps
T159 /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.1838504842 Aug 06 04:53:36 PM PDT 24 Aug 06 04:53:41 PM PDT 24 1216112574 ps
T1017 /workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.1368194463 Aug 06 04:53:24 PM PDT 24 Aug 06 04:53:26 PM PDT 24 103223256 ps
T1018 /workspace/coverage/cover_reg_top/46.kmac_intr_test.3807328505 Aug 06 04:53:43 PM PDT 24 Aug 06 04:53:44 PM PDT 24 24343848 ps
T1019 /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.4098163107 Aug 06 04:53:22 PM PDT 24 Aug 06 04:53:31 PM PDT 24 1975928688 ps
T1020 /workspace/coverage/cover_reg_top/34.kmac_intr_test.3639572645 Aug 06 04:53:55 PM PDT 24 Aug 06 04:53:56 PM PDT 24 57119223 ps
T1021 /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.2077880445 Aug 06 04:53:32 PM PDT 24 Aug 06 04:53:33 PM PDT 24 44780803 ps
T1022 /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.2868823303 Aug 06 04:53:29 PM PDT 24 Aug 06 04:53:31 PM PDT 24 87446618 ps
T1023 /workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.2592891081 Aug 06 04:53:38 PM PDT 24 Aug 06 04:53:41 PM PDT 24 340715997 ps
T114 /workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.317245585 Aug 06 04:53:36 PM PDT 24 Aug 06 04:53:39 PM PDT 24 124953761 ps
T1024 /workspace/coverage/cover_reg_top/26.kmac_intr_test.1561134726 Aug 06 04:53:32 PM PDT 24 Aug 06 04:53:33 PM PDT 24 25228246 ps
T1025 /workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.3320721293 Aug 06 04:53:39 PM PDT 24 Aug 06 04:53:40 PM PDT 24 57883579 ps
T1026 /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.4251638708 Aug 06 04:53:29 PM PDT 24 Aug 06 04:53:32 PM PDT 24 282496809 ps
T1027 /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.2605200357 Aug 06 04:53:36 PM PDT 24 Aug 06 04:53:37 PM PDT 24 99428790 ps
T1028 /workspace/coverage/cover_reg_top/10.kmac_tl_errors.4175034306 Aug 06 04:53:28 PM PDT 24 Aug 06 04:53:31 PM PDT 24 260873093 ps
T1029 /workspace/coverage/cover_reg_top/6.kmac_csr_rw.3630903059 Aug 06 04:53:23 PM PDT 24 Aug 06 04:53:24 PM PDT 24 173794381 ps
T1030 /workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.1273517627 Aug 06 04:53:24 PM PDT 24 Aug 06 04:53:26 PM PDT 24 41517678 ps
T1031 /workspace/coverage/cover_reg_top/4.kmac_tl_errors.3346401851 Aug 06 04:53:41 PM PDT 24 Aug 06 04:53:43 PM PDT 24 112248691 ps
T154 /workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.886184685 Aug 06 04:53:40 PM PDT 24 Aug 06 04:53:43 PM PDT 24 509519418 ps
T156 /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.2292443677 Aug 06 04:53:38 PM PDT 24 Aug 06 04:53:42 PM PDT 24 1319446822 ps
T1032 /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.1046493057 Aug 06 04:53:24 PM PDT 24 Aug 06 04:53:35 PM PDT 24 729766792 ps
T1033 /workspace/coverage/cover_reg_top/8.kmac_intr_test.3639766379 Aug 06 04:53:45 PM PDT 24 Aug 06 04:53:46 PM PDT 24 40991594 ps
T1034 /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.3592500454 Aug 06 04:53:37 PM PDT 24 Aug 06 04:53:40 PM PDT 24 128660976 ps
T100 /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.2076628932 Aug 06 04:53:36 PM PDT 24 Aug 06 04:53:37 PM PDT 24 84691499 ps
T1035 /workspace/coverage/cover_reg_top/4.kmac_mem_walk.1188320267 Aug 06 04:53:24 PM PDT 24 Aug 06 04:53:25 PM PDT 24 140220381 ps
T101 /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.3741015657 Aug 06 04:53:42 PM PDT 24 Aug 06 04:53:43 PM PDT 24 13904678 ps
T1036 /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.903774406 Aug 06 04:53:27 PM PDT 24 Aug 06 04:53:28 PM PDT 24 35110992 ps
T1037 /workspace/coverage/cover_reg_top/22.kmac_intr_test.2010883963 Aug 06 04:53:37 PM PDT 24 Aug 06 04:53:38 PM PDT 24 28118520 ps
T1038 /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.1062189284 Aug 06 04:53:40 PM PDT 24 Aug 06 04:53:42 PM PDT 24 65504606 ps
T1039 /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.1796871368 Aug 06 04:53:40 PM PDT 24 Aug 06 04:53:42 PM PDT 24 67463280 ps
T1040 /workspace/coverage/cover_reg_top/16.kmac_tl_errors.2312611134 Aug 06 04:53:39 PM PDT 24 Aug 06 04:53:41 PM PDT 24 124294709 ps
T1041 /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.1936650568 Aug 06 04:53:21 PM PDT 24 Aug 06 04:53:29 PM PDT 24 137088309 ps
T1042 /workspace/coverage/cover_reg_top/0.kmac_csr_rw.268592874 Aug 06 04:53:26 PM PDT 24 Aug 06 04:53:27 PM PDT 24 34687415 ps
T1043 /workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.1941065680 Aug 06 04:53:41 PM PDT 24 Aug 06 04:53:43 PM PDT 24 402312186 ps
T1044 /workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.564018864 Aug 06 04:53:34 PM PDT 24 Aug 06 04:53:37 PM PDT 24 39838048 ps
T1045 /workspace/coverage/cover_reg_top/15.kmac_csr_rw.2008112648 Aug 06 04:53:27 PM PDT 24 Aug 06 04:53:28 PM PDT 24 30733282 ps
T1046 /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.721106808 Aug 06 04:53:40 PM PDT 24 Aug 06 04:53:43 PM PDT 24 168227614 ps
T1047 /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.634869853 Aug 06 04:53:35 PM PDT 24 Aug 06 04:53:37 PM PDT 24 50562210 ps
T1048 /workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.1001401399 Aug 06 04:53:24 PM PDT 24 Aug 06 04:53:26 PM PDT 24 311211582 ps
T1049 /workspace/coverage/cover_reg_top/14.kmac_csr_rw.1571843478 Aug 06 04:53:37 PM PDT 24 Aug 06 04:53:38 PM PDT 24 46208849 ps
T1050 /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.179119333 Aug 06 04:53:36 PM PDT 24 Aug 06 04:53:38 PM PDT 24 43559519 ps
T126 /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.4124379201 Aug 06 04:53:20 PM PDT 24 Aug 06 04:53:22 PM PDT 24 38884069 ps
T1051 /workspace/coverage/cover_reg_top/42.kmac_intr_test.2408528312 Aug 06 04:53:56 PM PDT 24 Aug 06 04:53:57 PM PDT 24 19838984 ps
T1052 /workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.1032536693 Aug 06 04:53:47 PM PDT 24 Aug 06 04:53:51 PM PDT 24 790171502 ps
T1053 /workspace/coverage/cover_reg_top/11.kmac_intr_test.3641319174 Aug 06 04:53:28 PM PDT 24 Aug 06 04:53:29 PM PDT 24 70162512 ps
T1054 /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.1066282308 Aug 06 04:53:30 PM PDT 24 Aug 06 04:53:38 PM PDT 24 93321630 ps
T1055 /workspace/coverage/cover_reg_top/19.kmac_tl_errors.620270289 Aug 06 04:53:39 PM PDT 24 Aug 06 04:53:41 PM PDT 24 29464990 ps
T96 /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.3953228600 Aug 06 04:53:29 PM PDT 24 Aug 06 04:53:31 PM PDT 24 303010612 ps
T1056 /workspace/coverage/cover_reg_top/13.kmac_tl_errors.3073095439 Aug 06 04:53:22 PM PDT 24 Aug 06 04:53:24 PM PDT 24 173939912 ps
T1057 /workspace/coverage/cover_reg_top/4.kmac_intr_test.1474084426 Aug 06 04:53:37 PM PDT 24 Aug 06 04:53:38 PM PDT 24 40959503 ps
T1058 /workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.2534995242 Aug 06 04:53:32 PM PDT 24 Aug 06 04:53:41 PM PDT 24 382050238 ps
T1059 /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.958150256 Aug 06 04:53:24 PM PDT 24 Aug 06 04:53:34 PM PDT 24 518860099 ps
T1060 /workspace/coverage/cover_reg_top/45.kmac_intr_test.2423345389 Aug 06 04:53:47 PM PDT 24 Aug 06 04:53:48 PM PDT 24 26736104 ps
T1061 /workspace/coverage/cover_reg_top/14.kmac_tl_errors.3496193512 Aug 06 04:53:25 PM PDT 24 Aug 06 04:53:27 PM PDT 24 281956991 ps
T1062 /workspace/coverage/cover_reg_top/11.kmac_tl_errors.417178129 Aug 06 04:53:38 PM PDT 24 Aug 06 04:53:41 PM PDT 24 136678220 ps
T97 /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.2079169919 Aug 06 04:53:44 PM PDT 24 Aug 06 04:53:46 PM PDT 24 76016195 ps
T1063 /workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.847101734 Aug 06 04:53:22 PM PDT 24 Aug 06 04:53:24 PM PDT 24 143802506 ps
T1064 /workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.2419043743 Aug 06 04:53:19 PM PDT 24 Aug 06 04:53:21 PM PDT 24 43428153 ps
T1065 /workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.2215398538 Aug 06 04:53:36 PM PDT 24 Aug 06 04:53:37 PM PDT 24 65817395 ps
T127 /workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.1987645551 Aug 06 04:53:21 PM PDT 24 Aug 06 04:53:23 PM PDT 24 59931328 ps
T1066 /workspace/coverage/cover_reg_top/29.kmac_intr_test.3916462227 Aug 06 04:53:40 PM PDT 24 Aug 06 04:53:41 PM PDT 24 49821025 ps
T157 /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.3520490130 Aug 06 04:53:23 PM PDT 24 Aug 06 04:53:29 PM PDT 24 354705624 ps
T1067 /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.2205618077 Aug 06 04:53:20 PM PDT 24 Aug 06 04:53:21 PM PDT 24 40811484 ps
T1068 /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.2206750373 Aug 06 04:53:26 PM PDT 24 Aug 06 04:53:28 PM PDT 24 240889153 ps
T1069 /workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.3257905230 Aug 06 04:53:32 PM PDT 24 Aug 06 04:53:42 PM PDT 24 570123523 ps
T1070 /workspace/coverage/cover_reg_top/3.kmac_csr_rw.996678724 Aug 06 04:53:37 PM PDT 24 Aug 06 04:53:38 PM PDT 24 60446078 ps
T1071 /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.97708672 Aug 06 04:53:28 PM PDT 24 Aug 06 04:53:38 PM PDT 24 1362878511 ps
T1072 /workspace/coverage/cover_reg_top/21.kmac_intr_test.2818695094 Aug 06 04:53:36 PM PDT 24 Aug 06 04:53:37 PM PDT 24 21009566 ps
T1073 /workspace/coverage/cover_reg_top/19.kmac_csr_rw.2972358470 Aug 06 04:53:40 PM PDT 24 Aug 06 04:53:41 PM PDT 24 12499041 ps
T1074 /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.910944250 Aug 06 04:53:28 PM PDT 24 Aug 06 04:53:29 PM PDT 24 38956359 ps
T1075 /workspace/coverage/cover_reg_top/2.kmac_mem_walk.3480495619 Aug 06 04:53:22 PM PDT 24 Aug 06 04:53:23 PM PDT 24 13642587 ps
T1076 /workspace/coverage/cover_reg_top/3.kmac_tl_errors.539777277 Aug 06 04:53:22 PM PDT 24 Aug 06 04:53:25 PM PDT 24 239128428 ps
T1077 /workspace/coverage/cover_reg_top/32.kmac_intr_test.3409197181 Aug 06 04:53:56 PM PDT 24 Aug 06 04:53:57 PM PDT 24 27759837 ps
T1078 /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.294613353 Aug 06 04:53:19 PM PDT 24 Aug 06 04:53:20 PM PDT 24 103265182 ps
T1079 /workspace/coverage/cover_reg_top/28.kmac_intr_test.2418959068 Aug 06 04:53:42 PM PDT 24 Aug 06 04:53:43 PM PDT 24 11097005 ps
T1080 /workspace/coverage/cover_reg_top/10.kmac_csr_rw.1309202639 Aug 06 04:53:34 PM PDT 24 Aug 06 04:53:35 PM PDT 24 89867522 ps
T1081 /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.2367815602 Aug 06 04:53:31 PM PDT 24 Aug 06 04:53:33 PM PDT 24 468336090 ps
T1082 /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.1527346571 Aug 06 04:53:21 PM PDT 24 Aug 06 04:53:24 PM PDT 24 52722276 ps
T1083 /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.2954925821 Aug 06 04:53:23 PM PDT 24 Aug 06 04:53:24 PM PDT 24 53249090 ps
T1084 /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.2203031382 Aug 06 04:53:40 PM PDT 24 Aug 06 04:53:43 PM PDT 24 232187554 ps
T1085 /workspace/coverage/cover_reg_top/0.kmac_intr_test.2019248383 Aug 06 04:53:20 PM PDT 24 Aug 06 04:53:21 PM PDT 24 15247519 ps
T155 /workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.629971938 Aug 06 04:53:24 PM PDT 24 Aug 06 04:53:28 PM PDT 24 188682137 ps
T1086 /workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.2032904914 Aug 06 04:53:33 PM PDT 24 Aug 06 04:53:41 PM PDT 24 152708846 ps
T1087 /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.2976049457 Aug 06 04:53:40 PM PDT 24 Aug 06 04:53:41 PM PDT 24 46595243 ps
T1088 /workspace/coverage/cover_reg_top/44.kmac_intr_test.467554326 Aug 06 04:53:40 PM PDT 24 Aug 06 04:53:41 PM PDT 24 24100742 ps
T1089 /workspace/coverage/cover_reg_top/17.kmac_tl_errors.2916030068 Aug 06 04:53:36 PM PDT 24 Aug 06 04:53:39 PM PDT 24 153706889 ps
T1090 /workspace/coverage/cover_reg_top/31.kmac_intr_test.1396494773 Aug 06 04:53:52 PM PDT 24 Aug 06 04:53:53 PM PDT 24 13981975 ps
T1091 /workspace/coverage/cover_reg_top/12.kmac_intr_test.688404118 Aug 06 04:53:23 PM PDT 24 Aug 06 04:53:24 PM PDT 24 39328748 ps
T1092 /workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.4178895182 Aug 06 04:53:23 PM PDT 24 Aug 06 04:53:25 PM PDT 24 86688584 ps
T1093 /workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.3042590634 Aug 06 04:53:52 PM PDT 24 Aug 06 04:53:55 PM PDT 24 494298204 ps
T1094 /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.2905987075 Aug 06 04:53:32 PM PDT 24 Aug 06 04:53:33 PM PDT 24 80456373 ps
T1095 /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.2770981536 Aug 06 04:53:34 PM PDT 24 Aug 06 04:53:35 PM PDT 24 93237231 ps
T1096 /workspace/coverage/cover_reg_top/38.kmac_intr_test.1329004153 Aug 06 04:54:15 PM PDT 24 Aug 06 04:54:16 PM PDT 24 90523735 ps
T1097 /workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.28607996 Aug 06 04:53:40 PM PDT 24 Aug 06 04:53:42 PM PDT 24 557230365 ps
T1098 /workspace/coverage/cover_reg_top/36.kmac_intr_test.395644540 Aug 06 04:53:38 PM PDT 24 Aug 06 04:53:39 PM PDT 24 18352116 ps
T1099 /workspace/coverage/cover_reg_top/1.kmac_tl_errors.1226330359 Aug 06 04:53:20 PM PDT 24 Aug 06 04:53:24 PM PDT 24 132137150 ps
T1100 /workspace/coverage/cover_reg_top/19.kmac_intr_test.760860451 Aug 06 04:53:38 PM PDT 24 Aug 06 04:53:39 PM PDT 24 47596825 ps
T1101 /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.4264321056 Aug 06 04:53:26 PM PDT 24 Aug 06 04:53:27 PM PDT 24 43821584 ps
T1102 /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.1407841837 Aug 06 04:53:26 PM PDT 24 Aug 06 04:53:28 PM PDT 24 212614253 ps
T1103 /workspace/coverage/cover_reg_top/23.kmac_intr_test.1644904819 Aug 06 04:53:52 PM PDT 24 Aug 06 04:53:53 PM PDT 24 30604356 ps
T1104 /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.2661706727 Aug 06 04:53:32 PM PDT 24 Aug 06 04:53:35 PM PDT 24 379899989 ps
T1105 /workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.1097798777 Aug 06 04:53:22 PM PDT 24 Aug 06 04:53:25 PM PDT 24 1018584700 ps
T1106 /workspace/coverage/cover_reg_top/9.kmac_csr_rw.363285461 Aug 06 04:53:32 PM PDT 24 Aug 06 04:53:33 PM PDT 24 60331788 ps
T1107 /workspace/coverage/cover_reg_top/39.kmac_intr_test.1941017922 Aug 06 04:53:39 PM PDT 24 Aug 06 04:53:40 PM PDT 24 28804092 ps
T1108 /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.3421620963 Aug 06 04:53:44 PM PDT 24 Aug 06 04:53:45 PM PDT 24 21195171 ps
T1109 /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.747501551 Aug 06 04:53:37 PM PDT 24 Aug 06 04:53:40 PM PDT 24 379444512 ps
T1110 /workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.2802872065 Aug 06 04:53:24 PM PDT 24 Aug 06 04:53:26 PM PDT 24 168259710 ps
T1111 /workspace/coverage/cover_reg_top/1.kmac_intr_test.3623315485 Aug 06 04:53:28 PM PDT 24 Aug 06 04:53:29 PM PDT 24 17084953 ps
T1112 /workspace/coverage/cover_reg_top/15.kmac_intr_test.2159580327 Aug 06 04:53:27 PM PDT 24 Aug 06 04:53:28 PM PDT 24 44704385 ps
T1113 /workspace/coverage/cover_reg_top/17.kmac_csr_rw.3135882269 Aug 06 04:53:41 PM PDT 24 Aug 06 04:53:42 PM PDT 24 71848907 ps
T1114 /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.3100943048 Aug 06 04:53:36 PM PDT 24 Aug 06 04:53:39 PM PDT 24 325383501 ps
T1115 /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.2751444219 Aug 06 04:53:29 PM PDT 24 Aug 06 04:53:30 PM PDT 24 54361115 ps
T1116 /workspace/coverage/cover_reg_top/8.kmac_csr_rw.1938207810 Aug 06 04:53:36 PM PDT 24 Aug 06 04:53:37 PM PDT 24 78835145 ps
T1117 /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.817839457 Aug 06 04:53:24 PM PDT 24 Aug 06 04:53:26 PM PDT 24 150785421 ps
T1118 /workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.2801716724 Aug 06 04:53:36 PM PDT 24 Aug 06 04:53:39 PM PDT 24 89527336 ps
T1119 /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.743084744 Aug 06 04:53:29 PM PDT 24 Aug 06 04:53:31 PM PDT 24 23003852 ps
T1120 /workspace/coverage/cover_reg_top/18.kmac_tl_errors.2568665460 Aug 06 04:53:40 PM PDT 24 Aug 06 04:53:42 PM PDT 24 55113211 ps
T1121 /workspace/coverage/cover_reg_top/7.kmac_csr_rw.217990487 Aug 06 04:53:22 PM PDT 24 Aug 06 04:53:24 PM PDT 24 22963543 ps
T1122 /workspace/coverage/cover_reg_top/7.kmac_tl_errors.1609460535 Aug 06 04:53:28 PM PDT 24 Aug 06 04:53:30 PM PDT 24 126864153 ps
T1123 /workspace/coverage/cover_reg_top/5.kmac_intr_test.1277236275 Aug 06 04:53:40 PM PDT 24 Aug 06 04:53:41 PM PDT 24 31213332 ps
T1124 /workspace/coverage/cover_reg_top/3.kmac_intr_test.1868178272 Aug 06 04:53:20 PM PDT 24 Aug 06 04:53:21 PM PDT 24 12497482 ps
T1125 /workspace/coverage/cover_reg_top/20.kmac_intr_test.1686253368 Aug 06 04:53:38 PM PDT 24 Aug 06 04:53:39 PM PDT 24 13238127 ps
T1126 /workspace/coverage/cover_reg_top/16.kmac_csr_rw.2823130124 Aug 06 04:53:37 PM PDT 24 Aug 06 04:53:38 PM PDT 24 74340966 ps
T1127 /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.3584088921 Aug 06 04:53:28 PM PDT 24 Aug 06 04:53:30 PM PDT 24 77112915 ps
T1128 /workspace/coverage/cover_reg_top/43.kmac_intr_test.4132114609 Aug 06 04:53:44 PM PDT 24 Aug 06 04:53:45 PM PDT 24 25461972 ps
T1129 /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.1831044123 Aug 06 04:53:29 PM PDT 24 Aug 06 04:53:31 PM PDT 24 447986562 ps
T1130 /workspace/coverage/cover_reg_top/0.kmac_tl_errors.3776930359 Aug 06 04:53:26 PM PDT 24 Aug 06 04:53:29 PM PDT 24 436453847 ps
T1131 /workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.828053412 Aug 06 04:53:32 PM PDT 24 Aug 06 04:53:34 PM PDT 24 47940704 ps
T1132 /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.195767999 Aug 06 04:53:21 PM PDT 24 Aug 06 04:53:22 PM PDT 24 112893315 ps
T1133 /workspace/coverage/cover_reg_top/17.kmac_intr_test.3507799657 Aug 06 04:53:40 PM PDT 24 Aug 06 04:53:41 PM PDT 24 46878666 ps
T1134 /workspace/coverage/cover_reg_top/15.kmac_tl_errors.1757165045 Aug 06 04:53:32 PM PDT 24 Aug 06 04:53:34 PM PDT 24 50610655 ps
T1135 /workspace/coverage/cover_reg_top/4.kmac_csr_rw.2372552710 Aug 06 04:53:33 PM PDT 24 Aug 06 04:53:34 PM PDT 24 27253080 ps
T1136 /workspace/coverage/cover_reg_top/1.kmac_csr_rw.1536258020 Aug 06 04:53:23 PM PDT 24 Aug 06 04:53:25 PM PDT 24 29808957 ps
T1137 /workspace/coverage/cover_reg_top/9.kmac_tl_errors.2976128315 Aug 06 04:53:36 PM PDT 24 Aug 06 04:53:39 PM PDT 24 547403149 ps
T1138 /workspace/coverage/cover_reg_top/33.kmac_intr_test.2068366476 Aug 06 04:53:54 PM PDT 24 Aug 06 04:53:54 PM PDT 24 18236263 ps
T1139 /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.1336273397 Aug 06 04:53:27 PM PDT 24 Aug 06 04:53:30 PM PDT 24 143685445 ps
T1140 /workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.3935047090 Aug 06 04:53:24 PM PDT 24 Aug 06 04:53:26 PM PDT 24 26421939 ps
T1141 /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.152515171 Aug 06 04:53:29 PM PDT 24 Aug 06 04:53:31 PM PDT 24 661102371 ps
T1142 /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.1339070445 Aug 06 04:53:33 PM PDT 24 Aug 06 04:53:36 PM PDT 24 80606450 ps
T1143 /workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.3716137835 Aug 06 04:53:21 PM PDT 24 Aug 06 04:53:31 PM PDT 24 1815056221 ps
T1144 /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.3466155291 Aug 06 04:53:23 PM PDT 24 Aug 06 04:53:44 PM PDT 24 6022205509 ps
T1145 /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.4090837583 Aug 06 04:53:20 PM PDT 24 Aug 06 04:53:21 PM PDT 24 73157366 ps
T1146 /workspace/coverage/cover_reg_top/24.kmac_intr_test.1666160875 Aug 06 04:53:37 PM PDT 24 Aug 06 04:53:38 PM PDT 24 35254694 ps
T1147 /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.508535281 Aug 06 04:53:22 PM PDT 24 Aug 06 04:53:23 PM PDT 24 15351597 ps
T1148 /workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.3054169145 Aug 06 04:53:32 PM PDT 24 Aug 06 04:53:34 PM PDT 24 46944406 ps
T1149 /workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.1575704648 Aug 06 04:53:34 PM PDT 24 Aug 06 04:53:37 PM PDT 24 53631382 ps
T1150 /workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.441460665 Aug 06 04:53:38 PM PDT 24 Aug 06 04:53:40 PM PDT 24 281671923 ps
T1151 /workspace/coverage/cover_reg_top/25.kmac_intr_test.361205838 Aug 06 04:53:50 PM PDT 24 Aug 06 04:53:55 PM PDT 24 46242627 ps
T1152 /workspace/coverage/cover_reg_top/8.kmac_tl_errors.1683392457 Aug 06 04:53:26 PM PDT 24 Aug 06 04:53:30 PM PDT 24 312665918 ps
T1153 /workspace/coverage/cover_reg_top/47.kmac_intr_test.1578908703 Aug 06 04:53:40 PM PDT 24 Aug 06 04:53:41 PM PDT 24 19531754 ps
T1154 /workspace/coverage/cover_reg_top/48.kmac_intr_test.762772742 Aug 06 04:53:44 PM PDT 24 Aug 06 04:53:45 PM PDT 24 46108586 ps
T1155 /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.3330003977 Aug 06 04:53:32 PM PDT 24 Aug 06 04:53:33 PM PDT 24 41935402 ps
T128 /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.329890945 Aug 06 04:53:22 PM PDT 24 Aug 06 04:53:23 PM PDT 24 56515664 ps
T1156 /workspace/coverage/cover_reg_top/7.kmac_intr_test.340115893 Aug 06 04:53:40 PM PDT 24 Aug 06 04:53:41 PM PDT 24 19117525 ps
T1157 /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.3099277262 Aug 06 04:53:39 PM PDT 24 Aug 06 04:53:43 PM PDT 24 989334712 ps
T1158 /workspace/coverage/cover_reg_top/16.kmac_intr_test.430723587 Aug 06 04:53:36 PM PDT 24 Aug 06 04:53:36 PM PDT 24 35976762 ps

Test location /workspace/coverage/default/45.kmac_stress_all.1738507546
Short name T7
Test name
Test status
Simulation time 30731056581 ps
CPU time 464.73 seconds
Started Aug 06 06:16:57 PM PDT 24
Finished Aug 06 06:24:42 PM PDT 24
Peak memory 352344 kb
Host smart-98794500-3cfa-4fcf-9a6b-64f8d6b6a2d7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1738507546 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.1738507546 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.1236399495
Short name T108
Test name
Test status
Simulation time 431530551 ps
CPU time 4.95 seconds
Started Aug 06 04:53:22 PM PDT 24
Finished Aug 06 04:53:27 PM PDT 24
Peak memory 216044 kb
Host smart-4be48cd2-970f-45ba-8d28-f7796e4b3444
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236399495 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.12363
99495 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/1.kmac_sec_cm.2031297017
Short name T14
Test name
Test status
Simulation time 3506466193 ps
CPU time 45.55 seconds
Started Aug 06 06:00:18 PM PDT 24
Finished Aug 06 06:01:03 PM PDT 24
Peak memory 262092 kb
Host smart-7177a23c-e5cd-476f-810e-e15dd8bc204b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031297017 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.2031297017 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspace/1.kmac_sec_cm/latest

Test location /workspace/coverage/default/8.kmac_stress_all_with_rand_reset.3376852671
Short name T16
Test name
Test status
Simulation time 37277602935 ps
CPU time 1366.64 seconds
Started Aug 06 06:02:37 PM PDT 24
Finished Aug 06 06:25:24 PM PDT 24
Peak memory 509256 kb
Host smart-3094eda9-6ede-462e-a5de-3d9bb137b098
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3376852671 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all_with_rand_reset.3376852671 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.kmac_lc_escalation.626875175
Short name T28
Test name
Test status
Simulation time 77465603 ps
CPU time 1.27 seconds
Started Aug 06 06:03:45 PM PDT 24
Finished Aug 06 06:03:46 PM PDT 24
Peak memory 227052 kb
Host smart-3085b7cd-6669-450e-994a-b9f2792893b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626875175 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.626875175 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/12.kmac_lc_escalation/latest

Test location /workspace/coverage/default/20.kmac_key_error.564733711
Short name T4
Test name
Test status
Simulation time 2851290518 ps
CPU time 6.69 seconds
Started Aug 06 06:06:32 PM PDT 24
Finished Aug 06 06:06:39 PM PDT 24
Peak memory 226984 kb
Host smart-ca311376-a88d-4609-bcd5-8231ad773ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564733711 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.564733711 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_key_error/latest

Test location /workspace/coverage/default/49.kmac_error.546485212
Short name T21
Test name
Test status
Simulation time 74502715100 ps
CPU time 307.19 seconds
Started Aug 06 06:19:07 PM PDT 24
Finished Aug 06 06:24:14 PM PDT 24
Peak memory 345156 kb
Host smart-5361519a-7825-4ac4-b6ae-a1f860c27c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546485212 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.546485212 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_error/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.3639479211
Short name T98
Test name
Test status
Simulation time 196127386 ps
CPU time 2.57 seconds
Started Aug 06 04:53:40 PM PDT 24
Finished Aug 06 04:53:43 PM PDT 24
Peak memory 218932 kb
Host smart-00d37b7c-490e-4a04-9ab2-c2128848e7cc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639479211 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kma
c_shadow_reg_errors_with_csr_rw.3639479211 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/34.kmac_lc_escalation.2982833485
Short name T9
Test name
Test status
Simulation time 135958564 ps
CPU time 1.45 seconds
Started Aug 06 06:12:00 PM PDT 24
Finished Aug 06 06:12:01 PM PDT 24
Peak memory 227012 kb
Host smart-fa7de7a3-a7a5-422c-a413-ded03cbbf3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982833485 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.2982833485 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/34.kmac_lc_escalation/latest

Test location /workspace/coverage/cover_reg_top/35.kmac_intr_test.687651112
Short name T145
Test name
Test status
Simulation time 16785770 ps
CPU time 0.81 seconds
Started Aug 06 04:53:41 PM PDT 24
Finished Aug 06 04:53:42 PM PDT 24
Peak memory 215804 kb
Host smart-cf20ec18-9de2-4c9a-8f64-7b7b2db88d36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687651112 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.687651112 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/35.kmac_intr_test/latest

Test location /workspace/coverage/default/2.kmac_entropy_ready_error.3294952185
Short name T149
Test name
Test status
Simulation time 3395553848 ps
CPU time 50.7 seconds
Started Aug 06 06:00:46 PM PDT 24
Finished Aug 06 06:01:37 PM PDT 24
Peak memory 227172 kb
Host smart-b854463d-4b86-433c-b9db-ea487586db8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294952185 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.3294952185 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/0.kmac_edn_timeout_error.2045536276
Short name T74
Test name
Test status
Simulation time 21022526 ps
CPU time 0.96 seconds
Started Aug 06 06:00:04 PM PDT 24
Finished Aug 06 06:00:07 PM PDT 24
Peak memory 218612 kb
Host smart-d4586fe3-8c4a-4069-a0e2-fc7dd072b615
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2045536276 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.2045536276 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/37.kmac_lc_escalation.2081061935
Short name T29
Test name
Test status
Simulation time 4750187529 ps
CPU time 50.75 seconds
Started Aug 06 06:13:03 PM PDT 24
Finished Aug 06 06:13:53 PM PDT 24
Peak memory 251760 kb
Host smart-e49d06f9-c38d-44a9-933d-319275e9a2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081061935 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.2081061935 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/37.kmac_lc_escalation/latest

Test location /workspace/coverage/default/27.kmac_lc_escalation.2947926373
Short name T44
Test name
Test status
Simulation time 63324382 ps
CPU time 1.54 seconds
Started Aug 06 06:09:16 PM PDT 24
Finished Aug 06 06:09:18 PM PDT 24
Peak memory 226976 kb
Host smart-735fcc99-8579-46a1-977e-4bdded54f8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947926373 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.2947926373 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/27.kmac_lc_escalation/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_shake_256.3283830058
Short name T64
Test name
Test status
Simulation time 482639292709 ps
CPU time 5756.78 seconds
Started Aug 06 06:07:32 PM PDT 24
Finished Aug 06 07:43:30 PM PDT 24
Peak memory 2258064 kb
Host smart-7600c78b-cfd8-410d-93a9-110b436218d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3283830058 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_256.3283830058 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/0.kmac_entropy_mode_error.160733614
Short name T84
Test name
Test status
Simulation time 26248548 ps
CPU time 0.83 seconds
Started Aug 06 06:00:15 PM PDT 24
Finished Aug 06 06:00:16 PM PDT 24
Peak memory 218524 kb
Host smart-c829e2ac-6439-46da-83c2-c9e3c823d62f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=160733614 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.160733614 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/33.kmac_lc_escalation.3876947352
Short name T86
Test name
Test status
Simulation time 61676513 ps
CPU time 1.24 seconds
Started Aug 06 06:11:37 PM PDT 24
Finished Aug 06 06:11:38 PM PDT 24
Peak memory 227036 kb
Host smart-4e924371-7080-4440-86cc-dcf03a8e7d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876947352 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.3876947352 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/33.kmac_lc_escalation/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.329890945
Short name T128
Test name
Test status
Simulation time 56515664 ps
CPU time 1.22 seconds
Started Aug 06 04:53:22 PM PDT 24
Finished Aug 06 04:53:23 PM PDT 24
Peak memory 215980 kb
Host smart-6cc9ee27-7f09-4078-9f6a-22896db67da7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329890945 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partial
_access.329890945 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.2079169919
Short name T97
Test name
Test status
Simulation time 76016195 ps
CPU time 2.21 seconds
Started Aug 06 04:53:44 PM PDT 24
Finished Aug 06 04:53:46 PM PDT 24
Peak memory 216092 kb
Host smart-b758bb37-c35e-4c07-b027-c0bbdb3fdc1b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079169919 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kma
c_shadow_reg_errors_with_csr_rw.2079169919 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/15.kmac_lc_escalation.2155036114
Short name T786
Test name
Test status
Simulation time 196200552 ps
CPU time 1.58 seconds
Started Aug 06 06:04:54 PM PDT 24
Finished Aug 06 06:04:56 PM PDT 24
Peak memory 226992 kb
Host smart-749a6ca8-fb15-4d5a-aa6a-122fad2c424f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155036114 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.2155036114 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/15.kmac_lc_escalation/latest

Test location /workspace/coverage/default/32.kmac_lc_escalation.2242683523
Short name T25
Test name
Test status
Simulation time 32835857 ps
CPU time 1.24 seconds
Started Aug 06 06:11:08 PM PDT 24
Finished Aug 06 06:11:09 PM PDT 24
Peak memory 226972 kb
Host smart-2b186dc1-5738-4577-b8ae-3761a6f81f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242683523 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.2242683523 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/32.kmac_lc_escalation/latest

Test location /workspace/coverage/default/39.kmac_lc_escalation.3947321408
Short name T66
Test name
Test status
Simulation time 30676231 ps
CPU time 1.33 seconds
Started Aug 06 06:14:01 PM PDT 24
Finished Aug 06 06:14:03 PM PDT 24
Peak memory 226988 kb
Host smart-5ccf0dbe-2875-44db-b3f9-cb69085482e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947321408 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.3947321408 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/39.kmac_lc_escalation/latest

Test location /workspace/coverage/default/0.kmac_alert_test.4215286139
Short name T1
Test name
Test status
Simulation time 33789723 ps
CPU time 0.8 seconds
Started Aug 06 06:00:09 PM PDT 24
Finished Aug 06 06:00:09 PM PDT 24
Peak memory 218552 kb
Host smart-ddb34d2c-8c9d-4329-adc2-4fc855860d2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215286139 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.4215286139 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.1838504842
Short name T159
Test name
Test status
Simulation time 1216112574 ps
CPU time 4.71 seconds
Started Aug 06 04:53:36 PM PDT 24
Finished Aug 06 04:53:41 PM PDT 24
Peak memory 215940 kb
Host smart-d6be0eaf-3992-450b-8c50-0d9c3392b6b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838504842 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.1838
504842 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/31.kmac_stress_all.3176780353
Short name T79
Test name
Test status
Simulation time 70258239257 ps
CPU time 2127.42 seconds
Started Aug 06 06:10:52 PM PDT 24
Finished Aug 06 06:46:20 PM PDT 24
Peak memory 1389404 kb
Host smart-0c7c5c93-c634-4884-884f-e48ca2e3fa19
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3176780353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.3176780353 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_stress_all/latest

Test location /workspace/coverage/default/19.kmac_smoke.3648539461
Short name T32
Test name
Test status
Simulation time 4816130654 ps
CPU time 73.18 seconds
Started Aug 06 06:06:09 PM PDT 24
Finished Aug 06 06:07:23 PM PDT 24
Peak memory 227124 kb
Host smart-de60cd31-2bee-4933-b089-7ab8c4ded328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648539461 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.3648539461 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_smoke/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_intr_test.2094576535
Short name T148
Test name
Test status
Simulation time 42625641 ps
CPU time 0.82 seconds
Started Aug 06 04:53:22 PM PDT 24
Finished Aug 06 04:53:23 PM PDT 24
Peak memory 215700 kb
Host smart-bc6d3a38-f2b6-48c9-912f-8a4c00fb7f64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094576535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.2094576535 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_intr_test/latest

Test location /workspace/coverage/default/0.kmac_sec_cm.1767543147
Short name T27
Test name
Test status
Simulation time 4487603194 ps
CPU time 68.76 seconds
Started Aug 06 06:00:16 PM PDT 24
Finished Aug 06 06:01:24 PM PDT 24
Peak memory 272476 kb
Host smart-831a64d1-db1b-494a-8746-5d1b2aad016c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767543147 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.1767543147 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspace/0.kmac_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.629971938
Short name T155
Test name
Test status
Simulation time 188682137 ps
CPU time 4.13 seconds
Started Aug 06 04:53:24 PM PDT 24
Finished Aug 06 04:53:28 PM PDT 24
Peak memory 216040 kb
Host smart-3129e0d2-b8c7-4890-83e1-b365b46386a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629971938 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.629971
938 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/35.kmac_stress_all.2653892662
Short name T55
Test name
Test status
Simulation time 50893632314 ps
CPU time 1611.86 seconds
Started Aug 06 06:12:27 PM PDT 24
Finished Aug 06 06:39:19 PM PDT 24
Peak memory 1337776 kb
Host smart-589cc22b-fea7-4a0f-b1ce-cb3c954f73c0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2653892662 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.2653892662 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_stress_all/latest

Test location /workspace/coverage/default/12.kmac_error.4104533524
Short name T139
Test name
Test status
Simulation time 18252261563 ps
CPU time 369.66 seconds
Started Aug 06 06:03:43 PM PDT 24
Finished Aug 06 06:09:52 PM PDT 24
Peak memory 344120 kb
Host smart-53efced3-a1e1-4a34-bfbe-ca5eb24572da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104533524 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.4104533524 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_error/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.294613353
Short name T1078
Test name
Test status
Simulation time 103265182 ps
CPU time 1.22 seconds
Started Aug 06 04:53:19 PM PDT 24
Finished Aug 06 04:53:20 PM PDT 24
Peak memory 216268 kb
Host smart-527f7453-7d51-4b29-8b4d-407a1090f50d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294613353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_e
rrors.294613353 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.704636612
Short name T153
Test name
Test status
Simulation time 574690630 ps
CPU time 2.74 seconds
Started Aug 06 04:53:21 PM PDT 24
Finished Aug 06 04:53:24 PM PDT 24
Peak memory 215972 kb
Host smart-940e4b78-c33e-4731-9eaf-6956af2eb997
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704636612 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.704636
612 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.317245585
Short name T114
Test name
Test status
Simulation time 124953761 ps
CPU time 2.89 seconds
Started Aug 06 04:53:36 PM PDT 24
Finished Aug 06 04:53:39 PM PDT 24
Peak memory 215936 kb
Host smart-35a54447-6309-4505-bed9-2cff5219a99e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317245585 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.317245
585 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.kmac_stress_all_with_rand_reset.2558811528
Short name T46
Test name
Test status
Simulation time 732920238188 ps
CPU time 3353.25 seconds
Started Aug 06 06:00:09 PM PDT 24
Finished Aug 06 06:56:02 PM PDT 24
Peak memory 818356 kb
Host smart-5e422308-fe56-4dae-bb80-53be48f4333f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2558811528 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all_with_rand_reset.2558811528 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.2534995242
Short name T1058
Test name
Test status
Simulation time 382050238 ps
CPU time 9.06 seconds
Started Aug 06 04:53:32 PM PDT 24
Finished Aug 06 04:53:41 PM PDT 24
Peak memory 215876 kb
Host smart-2baf3041-fdb6-4cd5-b823-fc5b089b6bb4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534995242 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.2534995
242 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.1046493057
Short name T1032
Test name
Test status
Simulation time 729766792 ps
CPU time 10.93 seconds
Started Aug 06 04:53:24 PM PDT 24
Finished Aug 06 04:53:35 PM PDT 24
Peak memory 215592 kb
Host smart-3039a3c8-aa79-46ca-92ba-ed68d6b15651
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046493057 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.1046493
057 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.508535281
Short name T1147
Test name
Test status
Simulation time 15351597 ps
CPU time 0.95 seconds
Started Aug 06 04:53:22 PM PDT 24
Finished Aug 06 04:53:23 PM PDT 24
Peak memory 215720 kb
Host smart-17d2f7b1-4d32-4e82-8627-c6b01300299c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508535281 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.50853528
1 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.2365782568
Short name T997
Test name
Test status
Simulation time 21819521 ps
CPU time 1.51 seconds
Started Aug 06 04:53:26 PM PDT 24
Finished Aug 06 04:53:28 PM PDT 24
Peak memory 219112 kb
Host smart-910a5245-c1ed-4f11-8dd0-dec7a58ff9f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365782568 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.kmac_csr_mem_rw_with_rand_reset.2365782568 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_rw.268592874
Short name T1042
Test name
Test status
Simulation time 34687415 ps
CPU time 1.01 seconds
Started Aug 06 04:53:26 PM PDT 24
Finished Aug 06 04:53:27 PM PDT 24
Peak memory 215692 kb
Host smart-803db943-faf2-45b1-98ba-b43b54089444
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268592874 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.268592874 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_intr_test.2019248383
Short name T1085
Test name
Test status
Simulation time 15247519 ps
CPU time 0.83 seconds
Started Aug 06 04:53:20 PM PDT 24
Finished Aug 06 04:53:21 PM PDT 24
Peak memory 215776 kb
Host smart-06d9be03-2e37-4c5e-89cc-c6949eab8be1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019248383 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.2019248383 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.817839457
Short name T1117
Test name
Test status
Simulation time 150785421 ps
CPU time 1.54 seconds
Started Aug 06 04:53:24 PM PDT 24
Finished Aug 06 04:53:26 PM PDT 24
Peak memory 216024 kb
Host smart-17edec22-81ee-4bcd-9c9d-d6be7a983231
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817839457 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partial
_access.817839457 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_mem_walk.3376827458
Short name T992
Test name
Test status
Simulation time 14071686 ps
CPU time 0.77 seconds
Started Aug 06 04:53:21 PM PDT 24
Finished Aug 06 04:53:22 PM PDT 24
Peak memory 215688 kb
Host smart-3b529158-94fe-4407-912b-3f3cdffe8b36
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376827458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.3376827458
+enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.1011332718
Short name T134
Test name
Test status
Simulation time 140271798 ps
CPU time 1.85 seconds
Started Aug 06 04:53:21 PM PDT 24
Finished Aug 06 04:53:22 PM PDT 24
Peak memory 216004 kb
Host smart-6dd43a08-61f5-4d9e-a79c-b86c9563b26a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011332718 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr
_outstanding.1011332718 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.903774406
Short name T1036
Test name
Test status
Simulation time 35110992 ps
CPU time 1.16 seconds
Started Aug 06 04:53:27 PM PDT 24
Finished Aug 06 04:53:28 PM PDT 24
Peak memory 216188 kb
Host smart-4e789461-59d9-4985-83d5-f535510916b3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903774406 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_e
rrors.903774406 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.2319518528
Short name T95
Test name
Test status
Simulation time 154620917 ps
CPU time 2.27 seconds
Started Aug 06 04:53:20 PM PDT 24
Finished Aug 06 04:53:22 PM PDT 24
Peak memory 216008 kb
Host smart-f0a133a3-b89a-4575-acbc-2b12e3c43535
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319518528 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac
_shadow_reg_errors_with_csr_rw.2319518528 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_tl_errors.3776930359
Short name T1130
Test name
Test status
Simulation time 436453847 ps
CPU time 3.07 seconds
Started Aug 06 04:53:26 PM PDT 24
Finished Aug 06 04:53:29 PM PDT 24
Peak memory 216064 kb
Host smart-4dfcaba9-3f6a-4049-bf21-fe00b0f02299
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776930359 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.3776930359 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.4098163107
Short name T1019
Test name
Test status
Simulation time 1975928688 ps
CPU time 9.54 seconds
Started Aug 06 04:53:22 PM PDT 24
Finished Aug 06 04:53:31 PM PDT 24
Peak memory 215948 kb
Host smart-3bbed0c5-86b8-49ff-9bb2-22f2e95dcf1f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098163107 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.4098163
107 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.3466155291
Short name T1144
Test name
Test status
Simulation time 6022205509 ps
CPU time 20.57 seconds
Started Aug 06 04:53:23 PM PDT 24
Finished Aug 06 04:53:44 PM PDT 24
Peak memory 216076 kb
Host smart-e502ebdf-9b12-40a1-b549-2d3e640ca2ff
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466155291 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.3466155
291 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.2751444219
Short name T1115
Test name
Test status
Simulation time 54361115 ps
CPU time 1.26 seconds
Started Aug 06 04:53:29 PM PDT 24
Finished Aug 06 04:53:30 PM PDT 24
Peak memory 215868 kb
Host smart-f7f8aac3-1b22-4c86-94ff-57f475fea4a0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751444219 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.2751444
219 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.1057130635
Short name T1015
Test name
Test status
Simulation time 279976631 ps
CPU time 2.59 seconds
Started Aug 06 04:53:21 PM PDT 24
Finished Aug 06 04:53:24 PM PDT 24
Peak memory 221000 kb
Host smart-c2a215b1-80d1-4431-87c9-77ca233b5a7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057130635 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.kmac_csr_mem_rw_with_rand_reset.1057130635 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_rw.1536258020
Short name T1136
Test name
Test status
Simulation time 29808957 ps
CPU time 1.04 seconds
Started Aug 06 04:53:23 PM PDT 24
Finished Aug 06 04:53:25 PM PDT 24
Peak memory 215712 kb
Host smart-e202d095-12c6-4e13-ac17-c4d2cdf42363
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536258020 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.1536258020 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_intr_test.3623315485
Short name T1111
Test name
Test status
Simulation time 17084953 ps
CPU time 0.81 seconds
Started Aug 06 04:53:28 PM PDT 24
Finished Aug 06 04:53:29 PM PDT 24
Peak memory 215468 kb
Host smart-efaabbf4-b111-4d07-807c-6054d58d8f47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623315485 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.3623315485 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_mem_walk.3991798876
Short name T996
Test name
Test status
Simulation time 15089337 ps
CPU time 0.79 seconds
Started Aug 06 04:53:18 PM PDT 24
Finished Aug 06 04:53:19 PM PDT 24
Peak memory 215712 kb
Host smart-e2bfc393-5d55-4ca1-aec9-30743dc764de
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991798876 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.3991798876
+enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.564018864
Short name T1044
Test name
Test status
Simulation time 39838048 ps
CPU time 2.29 seconds
Started Aug 06 04:53:34 PM PDT 24
Finished Aug 06 04:53:37 PM PDT 24
Peak memory 215896 kb
Host smart-c52d9d8d-8d36-4051-8fb1-bd8303b1d56d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564018864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr_
outstanding.564018864 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.3580693183
Short name T1012
Test name
Test status
Simulation time 92339510 ps
CPU time 2.59 seconds
Started Aug 06 04:53:21 PM PDT 24
Finished Aug 06 04:53:24 PM PDT 24
Peak memory 218612 kb
Host smart-d66910ec-c761-4370-b558-54f44e9e8af0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580693183 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac
_shadow_reg_errors_with_csr_rw.3580693183 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_tl_errors.1226330359
Short name T1099
Test name
Test status
Simulation time 132137150 ps
CPU time 3.88 seconds
Started Aug 06 04:53:20 PM PDT 24
Finished Aug 06 04:53:24 PM PDT 24
Peak memory 216084 kb
Host smart-771b9ad4-3cad-4917-afa7-5840ce3a2b46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226330359 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.1226330359 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.3054169145
Short name T1148
Test name
Test status
Simulation time 46944406 ps
CPU time 1.64 seconds
Started Aug 06 04:53:32 PM PDT 24
Finished Aug 06 04:53:34 PM PDT 24
Peak memory 216984 kb
Host smart-13e1b191-13fe-486e-a063-08ca1ff48824
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054169145 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.kmac_csr_mem_rw_with_rand_reset.3054169145 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_csr_rw.1309202639
Short name T1080
Test name
Test status
Simulation time 89867522 ps
CPU time 1.19 seconds
Started Aug 06 04:53:34 PM PDT 24
Finished Aug 06 04:53:35 PM PDT 24
Peak memory 215968 kb
Host smart-d1931b67-363b-4025-a85c-92fc6323e761
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309202639 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.1309202639 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.3145153146
Short name T995
Test name
Test status
Simulation time 49880049 ps
CPU time 1.58 seconds
Started Aug 06 04:53:32 PM PDT 24
Finished Aug 06 04:53:34 PM PDT 24
Peak memory 215904 kb
Host smart-bbb1500e-b0d5-4320-aa5a-3437b669cbd9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145153146 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_cs
r_outstanding.3145153146 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.2968085940
Short name T94
Test name
Test status
Simulation time 25590936 ps
CPU time 1.1 seconds
Started Aug 06 04:53:29 PM PDT 24
Finished Aug 06 04:53:30 PM PDT 24
Peak memory 216348 kb
Host smart-0fe320ff-44f8-4e42-b559-b3283bcc6513
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968085940 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg
_errors.2968085940 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.1336273397
Short name T1139
Test name
Test status
Simulation time 143685445 ps
CPU time 2.84 seconds
Started Aug 06 04:53:27 PM PDT 24
Finished Aug 06 04:53:30 PM PDT 24
Peak memory 218500 kb
Host smart-8bf1d3e6-e092-4199-a5c9-9e105169859b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336273397 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kma
c_shadow_reg_errors_with_csr_rw.1336273397 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_tl_errors.4175034306
Short name T1028
Test name
Test status
Simulation time 260873093 ps
CPU time 2.57 seconds
Started Aug 06 04:53:28 PM PDT 24
Finished Aug 06 04:53:31 PM PDT 24
Peak memory 215996 kb
Host smart-1513d86c-15db-4501-93df-b217c90a8b02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175034306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.4175034306 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.3362442847
Short name T1001
Test name
Test status
Simulation time 62287303 ps
CPU time 2.3 seconds
Started Aug 06 04:53:24 PM PDT 24
Finished Aug 06 04:53:26 PM PDT 24
Peak memory 220756 kb
Host smart-da8432a3-1028-44d5-8a3c-845680724275
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362442847 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.kmac_csr_mem_rw_with_rand_reset.3362442847 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_csr_rw.2188739471
Short name T161
Test name
Test status
Simulation time 48615399 ps
CPU time 0.92 seconds
Started Aug 06 04:53:42 PM PDT 24
Finished Aug 06 04:53:43 PM PDT 24
Peak memory 215760 kb
Host smart-72349d40-3872-48eb-81ea-64fa41cafbaa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188739471 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.2188739471 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_intr_test.3641319174
Short name T1053
Test name
Test status
Simulation time 70162512 ps
CPU time 0.8 seconds
Started Aug 06 04:53:28 PM PDT 24
Finished Aug 06 04:53:29 PM PDT 24
Peak memory 215712 kb
Host smart-ea9c3202-48f1-44db-ae17-e5995615b025
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641319174 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.3641319174 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.3710524176
Short name T1002
Test name
Test status
Simulation time 114486527 ps
CPU time 2.37 seconds
Started Aug 06 04:53:34 PM PDT 24
Finished Aug 06 04:53:37 PM PDT 24
Peak memory 216004 kb
Host smart-cec10146-7d83-44e1-9d2a-a1025f27d17f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710524176 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_cs
r_outstanding.3710524176 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.4021810675
Short name T99
Test name
Test status
Simulation time 56544411 ps
CPU time 1.08 seconds
Started Aug 06 04:53:36 PM PDT 24
Finished Aug 06 04:53:37 PM PDT 24
Peak memory 215672 kb
Host smart-03fde3b6-8c7f-40dc-9043-bc5412ae509c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021810675 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg
_errors.4021810675 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.1527346571
Short name T1082
Test name
Test status
Simulation time 52722276 ps
CPU time 2.44 seconds
Started Aug 06 04:53:21 PM PDT 24
Finished Aug 06 04:53:24 PM PDT 24
Peak memory 218440 kb
Host smart-9514ade3-b3cd-4801-9280-8349806871f2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527346571 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kma
c_shadow_reg_errors_with_csr_rw.1527346571 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_tl_errors.417178129
Short name T1062
Test name
Test status
Simulation time 136678220 ps
CPU time 3.19 seconds
Started Aug 06 04:53:38 PM PDT 24
Finished Aug 06 04:53:41 PM PDT 24
Peak memory 215984 kb
Host smart-51d7ceb8-fcc6-4807-946e-b85580ec2375
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417178129 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.417178129 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/11.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.3592500454
Short name T1034
Test name
Test status
Simulation time 128660976 ps
CPU time 2.77 seconds
Started Aug 06 04:53:37 PM PDT 24
Finished Aug 06 04:53:40 PM PDT 24
Peak memory 215972 kb
Host smart-2c23a1bf-c9e7-49fd-aa37-2c142ab1a44f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592500454 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.3592
500454 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.847101734
Short name T1063
Test name
Test status
Simulation time 143802506 ps
CPU time 2.19 seconds
Started Aug 06 04:53:22 PM PDT 24
Finished Aug 06 04:53:24 PM PDT 24
Peak memory 221068 kb
Host smart-746bdc27-4bf2-4a5c-bc67-eacfdd332fc1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847101734 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.kmac_csr_mem_rw_with_rand_reset.847101734 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_csr_rw.3929842266
Short name T1013
Test name
Test status
Simulation time 21739064 ps
CPU time 1.06 seconds
Started Aug 06 04:53:29 PM PDT 24
Finished Aug 06 04:53:30 PM PDT 24
Peak memory 215988 kb
Host smart-fb7d69ee-415a-49e7-a1ed-f703c4fe26b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929842266 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.3929842266 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_intr_test.688404118
Short name T1091
Test name
Test status
Simulation time 39328748 ps
CPU time 0.78 seconds
Started Aug 06 04:53:23 PM PDT 24
Finished Aug 06 04:53:24 PM PDT 24
Peak memory 215784 kb
Host smart-98a81d95-0053-4a52-92f1-e69c5705d693
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688404118 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.688404118 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/12.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.634869853
Short name T1047
Test name
Test status
Simulation time 50562210 ps
CPU time 1.52 seconds
Started Aug 06 04:53:35 PM PDT 24
Finished Aug 06 04:53:37 PM PDT 24
Peak memory 215988 kb
Host smart-b8724fe3-b26c-4621-b050-a707973dde79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634869853 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_csr
_outstanding.634869853 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.2976049457
Short name T1087
Test name
Test status
Simulation time 46595243 ps
CPU time 1.35 seconds
Started Aug 06 04:53:40 PM PDT 24
Finished Aug 06 04:53:41 PM PDT 24
Peak memory 217320 kb
Host smart-352d1096-8597-49c9-8330-0db7dd493f10
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976049457 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg
_errors.2976049457 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.4251638708
Short name T1026
Test name
Test status
Simulation time 282496809 ps
CPU time 2.03 seconds
Started Aug 06 04:53:29 PM PDT 24
Finished Aug 06 04:53:32 PM PDT 24
Peak memory 218284 kb
Host smart-41082b37-4741-43d8-a12c-d9a22531a098
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251638708 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kma
c_shadow_reg_errors_with_csr_rw.4251638708 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_tl_errors.2814620778
Short name T1004
Test name
Test status
Simulation time 125655007 ps
CPU time 2.27 seconds
Started Aug 06 04:53:30 PM PDT 24
Finished Aug 06 04:53:33 PM PDT 24
Peak memory 216088 kb
Host smart-03539e6e-3357-482f-a616-cc93fc9aaa53
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814620778 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.2814620778 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.3610251674
Short name T160
Test name
Test status
Simulation time 207690904 ps
CPU time 2.87 seconds
Started Aug 06 04:53:38 PM PDT 24
Finished Aug 06 04:53:41 PM PDT 24
Peak memory 216088 kb
Host smart-9ecd5124-2afb-4c77-9c07-344d2b2baf9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610251674 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.3610
251674 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.1273517627
Short name T1030
Test name
Test status
Simulation time 41517678 ps
CPU time 1.91 seconds
Started Aug 06 04:53:24 PM PDT 24
Finished Aug 06 04:53:26 PM PDT 24
Peak memory 220100 kb
Host smart-d5ae6f1a-f47c-4c47-9046-99b411f12869
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273517627 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.kmac_csr_mem_rw_with_rand_reset.1273517627 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_csr_rw.2959154184
Short name T994
Test name
Test status
Simulation time 145631586 ps
CPU time 1.26 seconds
Started Aug 06 04:53:40 PM PDT 24
Finished Aug 06 04:53:42 PM PDT 24
Peak memory 215776 kb
Host smart-81eec127-7b07-4a99-a365-039cc56284c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959154184 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.2959154184 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_intr_test.3854771650
Short name T1005
Test name
Test status
Simulation time 20372496 ps
CPU time 0.79 seconds
Started Aug 06 04:53:26 PM PDT 24
Finished Aug 06 04:53:27 PM PDT 24
Peak memory 215700 kb
Host smart-754208eb-f60c-40c2-89d5-94fdcd0dc45e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854771650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.3854771650 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.2203031382
Short name T1084
Test name
Test status
Simulation time 232187554 ps
CPU time 2.62 seconds
Started Aug 06 04:53:40 PM PDT 24
Finished Aug 06 04:53:43 PM PDT 24
Peak memory 215964 kb
Host smart-e9122aa9-1f52-4973-9513-76f6799d5b1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203031382 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_cs
r_outstanding.2203031382 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.3741015657
Short name T101
Test name
Test status
Simulation time 13904678 ps
CPU time 0.8 seconds
Started Aug 06 04:53:42 PM PDT 24
Finished Aug 06 04:53:43 PM PDT 24
Peak memory 215788 kb
Host smart-d16a3e3a-007b-485a-95fa-92009fb6f342
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741015657 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg
_errors.3741015657 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_tl_errors.3073095439
Short name T1056
Test name
Test status
Simulation time 173939912 ps
CPU time 2.74 seconds
Started Aug 06 04:53:22 PM PDT 24
Finished Aug 06 04:53:24 PM PDT 24
Peak memory 216060 kb
Host smart-9e1f42ac-91ec-4ab2-bdca-0805c5b17432
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073095439 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.3073095439 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.2731363745
Short name T110
Test name
Test status
Simulation time 98842467 ps
CPU time 2.76 seconds
Started Aug 06 04:53:39 PM PDT 24
Finished Aug 06 04:53:42 PM PDT 24
Peak memory 216032 kb
Host smart-afc01014-a9c1-4485-859e-9cb0a9ea6e4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731363745 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.2731
363745 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.1001401399
Short name T1048
Test name
Test status
Simulation time 311211582 ps
CPU time 1.7 seconds
Started Aug 06 04:53:24 PM PDT 24
Finished Aug 06 04:53:26 PM PDT 24
Peak memory 219928 kb
Host smart-e67bc005-73ba-4709-b7d8-ed00ec531493
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001401399 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.kmac_csr_mem_rw_with_rand_reset.1001401399 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_csr_rw.1571843478
Short name T1049
Test name
Test status
Simulation time 46208849 ps
CPU time 1.03 seconds
Started Aug 06 04:53:37 PM PDT 24
Finished Aug 06 04:53:38 PM PDT 24
Peak memory 215852 kb
Host smart-a3d2628d-97cc-47e7-9f52-21401d50f058
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571843478 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.1571843478 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_intr_test.3085691306
Short name T1009
Test name
Test status
Simulation time 51425732 ps
CPU time 0.79 seconds
Started Aug 06 04:53:36 PM PDT 24
Finished Aug 06 04:53:37 PM PDT 24
Peak memory 215608 kb
Host smart-cf427013-6e63-4eee-9492-6ef564683d84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085691306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.3085691306 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.152515171
Short name T1141
Test name
Test status
Simulation time 661102371 ps
CPU time 1.55 seconds
Started Aug 06 04:53:29 PM PDT 24
Finished Aug 06 04:53:31 PM PDT 24
Peak memory 215924 kb
Host smart-66d64559-1678-4d71-9ec3-0115b5bd829e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152515171 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_csr
_outstanding.152515171 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.1062189284
Short name T1038
Test name
Test status
Simulation time 65504606 ps
CPU time 1.22 seconds
Started Aug 06 04:53:40 PM PDT 24
Finished Aug 06 04:53:42 PM PDT 24
Peak memory 216328 kb
Host smart-1cd8bb01-f6c4-47fd-af90-40353c4d0b0a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062189284 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg
_errors.1062189284 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.747501551
Short name T1109
Test name
Test status
Simulation time 379444512 ps
CPU time 2.65 seconds
Started Aug 06 04:53:37 PM PDT 24
Finished Aug 06 04:53:40 PM PDT 24
Peak memory 219832 kb
Host smart-bad76c1d-4c3f-4bd3-9906-ff0da376c564
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747501551 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac
_shadow_reg_errors_with_csr_rw.747501551 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_tl_errors.3496193512
Short name T1061
Test name
Test status
Simulation time 281956991 ps
CPU time 2.24 seconds
Started Aug 06 04:53:25 PM PDT 24
Finished Aug 06 04:53:27 PM PDT 24
Peak memory 216012 kb
Host smart-579c8ce5-3755-404c-a343-4f80e3734453
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496193512 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.3496193512 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.3520490130
Short name T157
Test name
Test status
Simulation time 354705624 ps
CPU time 5.49 seconds
Started Aug 06 04:53:23 PM PDT 24
Finished Aug 06 04:53:29 PM PDT 24
Peak memory 215984 kb
Host smart-77efaf41-50fb-4e04-8f73-ec58eb3a2418
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520490130 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.3520
490130 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.959399506
Short name T1014
Test name
Test status
Simulation time 42116234 ps
CPU time 1.53 seconds
Started Aug 06 04:53:32 PM PDT 24
Finished Aug 06 04:53:34 PM PDT 24
Peak memory 217024 kb
Host smart-70c29462-fd61-4886-9973-0e6c0f984f5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959399506 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.kmac_csr_mem_rw_with_rand_reset.959399506 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_csr_rw.2008112648
Short name T1045
Test name
Test status
Simulation time 30733282 ps
CPU time 1.08 seconds
Started Aug 06 04:53:27 PM PDT 24
Finished Aug 06 04:53:28 PM PDT 24
Peak memory 215812 kb
Host smart-b218c14b-64b8-44c4-af71-641d393b6b62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008112648 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.2008112648 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_intr_test.2159580327
Short name T1112
Test name
Test status
Simulation time 44704385 ps
CPU time 0.77 seconds
Started Aug 06 04:53:27 PM PDT 24
Finished Aug 06 04:53:28 PM PDT 24
Peak memory 215732 kb
Host smart-9aa01d29-2feb-4542-a137-8459706b04fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159580327 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.2159580327 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.1831044123
Short name T1129
Test name
Test status
Simulation time 447986562 ps
CPU time 1.67 seconds
Started Aug 06 04:53:29 PM PDT 24
Finished Aug 06 04:53:31 PM PDT 24
Peak memory 215924 kb
Host smart-e60e3d0b-9dd2-4db3-8de7-321a237eb0ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831044123 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_cs
r_outstanding.1831044123 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.3421620963
Short name T1108
Test name
Test status
Simulation time 21195171 ps
CPU time 0.92 seconds
Started Aug 06 04:53:44 PM PDT 24
Finished Aug 06 04:53:45 PM PDT 24
Peak memory 215764 kb
Host smart-b5c0b472-db35-4dad-9ef0-3977db09c35d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421620963 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg
_errors.3421620963 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.2206750373
Short name T1068
Test name
Test status
Simulation time 240889153 ps
CPU time 1.9 seconds
Started Aug 06 04:53:26 PM PDT 24
Finished Aug 06 04:53:28 PM PDT 24
Peak memory 216380 kb
Host smart-6de29229-26fb-400d-99e8-552bc61484de
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206750373 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kma
c_shadow_reg_errors_with_csr_rw.2206750373 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_tl_errors.1757165045
Short name T1134
Test name
Test status
Simulation time 50610655 ps
CPU time 1.86 seconds
Started Aug 06 04:53:32 PM PDT 24
Finished Aug 06 04:53:34 PM PDT 24
Peak memory 216076 kb
Host smart-c22fa120-35f4-470f-ac0b-4b0a0143a41e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757165045 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.1757165045 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.1575704648
Short name T1149
Test name
Test status
Simulation time 53631382 ps
CPU time 2.48 seconds
Started Aug 06 04:53:34 PM PDT 24
Finished Aug 06 04:53:37 PM PDT 24
Peak memory 216012 kb
Host smart-3cc270af-07b5-4945-bd8d-b37dff87faf1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575704648 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.1575
704648 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.3100943048
Short name T1114
Test name
Test status
Simulation time 325383501 ps
CPU time 2.38 seconds
Started Aug 06 04:53:36 PM PDT 24
Finished Aug 06 04:53:39 PM PDT 24
Peak memory 220732 kb
Host smart-d71cc785-ee36-4401-b50f-5662eb4c1b4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100943048 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.kmac_csr_mem_rw_with_rand_reset.3100943048 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_csr_rw.2823130124
Short name T1126
Test name
Test status
Simulation time 74340966 ps
CPU time 1.09 seconds
Started Aug 06 04:53:37 PM PDT 24
Finished Aug 06 04:53:38 PM PDT 24
Peak memory 215960 kb
Host smart-5055e2bf-ada8-4004-badc-526649f97e84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823130124 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.2823130124 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_intr_test.430723587
Short name T1158
Test name
Test status
Simulation time 35976762 ps
CPU time 0.77 seconds
Started Aug 06 04:53:36 PM PDT 24
Finished Aug 06 04:53:36 PM PDT 24
Peak memory 215332 kb
Host smart-d7067798-a8b4-44e6-b3e9-24e673852c13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430723587 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.430723587 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/16.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.1500298564
Short name T137
Test name
Test status
Simulation time 76329312 ps
CPU time 1.74 seconds
Started Aug 06 04:53:29 PM PDT 24
Finished Aug 06 04:53:31 PM PDT 24
Peak memory 215936 kb
Host smart-862c8c99-1b09-45be-a84c-53fd97ac8871
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500298564 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_cs
r_outstanding.1500298564 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.2954925821
Short name T1083
Test name
Test status
Simulation time 53249090 ps
CPU time 1.1 seconds
Started Aug 06 04:53:23 PM PDT 24
Finished Aug 06 04:53:24 PM PDT 24
Peak memory 216364 kb
Host smart-55977dbc-78ac-4bc0-b707-c3f734be3cd7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954925821 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg
_errors.2954925821 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.2367815602
Short name T1081
Test name
Test status
Simulation time 468336090 ps
CPU time 1.69 seconds
Started Aug 06 04:53:31 PM PDT 24
Finished Aug 06 04:53:33 PM PDT 24
Peak memory 218872 kb
Host smart-bc57af78-c353-4404-88f5-d7c699214bb7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367815602 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kma
c_shadow_reg_errors_with_csr_rw.2367815602 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_tl_errors.2312611134
Short name T1040
Test name
Test status
Simulation time 124294709 ps
CPU time 1.69 seconds
Started Aug 06 04:53:39 PM PDT 24
Finished Aug 06 04:53:41 PM PDT 24
Peak memory 215980 kb
Host smart-e6a92d80-c42b-4e98-a34d-fd6a91cf84a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312611134 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.2312611134 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.2261728925
Short name T158
Test name
Test status
Simulation time 93023742 ps
CPU time 3.92 seconds
Started Aug 06 04:53:46 PM PDT 24
Finished Aug 06 04:53:50 PM PDT 24
Peak memory 216048 kb
Host smart-e5cf9517-0b42-43e9-9dbb-5102b711db41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261728925 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.2261
728925 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.179119333
Short name T1050
Test name
Test status
Simulation time 43559519 ps
CPU time 1.7 seconds
Started Aug 06 04:53:36 PM PDT 24
Finished Aug 06 04:53:38 PM PDT 24
Peak memory 220404 kb
Host smart-92764ab4-22fd-4f04-9818-347d00fd9acc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179119333 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.kmac_csr_mem_rw_with_rand_reset.179119333 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_csr_rw.3135882269
Short name T1113
Test name
Test status
Simulation time 71848907 ps
CPU time 0.95 seconds
Started Aug 06 04:53:41 PM PDT 24
Finished Aug 06 04:53:42 PM PDT 24
Peak memory 215780 kb
Host smart-d1ccc522-e23d-41a6-9fb2-9bd1d01bcc84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135882269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.3135882269 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_intr_test.3507799657
Short name T1133
Test name
Test status
Simulation time 46878666 ps
CPU time 0.81 seconds
Started Aug 06 04:53:40 PM PDT 24
Finished Aug 06 04:53:41 PM PDT 24
Peak memory 215780 kb
Host smart-507ec043-ebdc-4fcc-bb40-fabb668c3f77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507799657 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.3507799657 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.3320721293
Short name T1025
Test name
Test status
Simulation time 57883579 ps
CPU time 1.44 seconds
Started Aug 06 04:53:39 PM PDT 24
Finished Aug 06 04:53:40 PM PDT 24
Peak memory 215908 kb
Host smart-ec729e50-3747-415e-9bb4-78648618c57e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320721293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_cs
r_outstanding.3320721293 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.2770981536
Short name T1095
Test name
Test status
Simulation time 93237231 ps
CPU time 1.39 seconds
Started Aug 06 04:53:34 PM PDT 24
Finished Aug 06 04:53:35 PM PDT 24
Peak memory 216552 kb
Host smart-24a2a4df-4e43-47b8-a398-8a5e9c657f5e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770981536 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg
_errors.2770981536 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.3736170252
Short name T998
Test name
Test status
Simulation time 398462296 ps
CPU time 1.82 seconds
Started Aug 06 04:53:39 PM PDT 24
Finished Aug 06 04:53:41 PM PDT 24
Peak memory 218480 kb
Host smart-9064c591-ed57-4090-834e-d00a983fc568
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736170252 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kma
c_shadow_reg_errors_with_csr_rw.3736170252 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_tl_errors.2916030068
Short name T1089
Test name
Test status
Simulation time 153706889 ps
CPU time 2.49 seconds
Started Aug 06 04:53:36 PM PDT 24
Finished Aug 06 04:53:39 PM PDT 24
Peak memory 216108 kb
Host smart-a5ccb85d-36e5-42db-913f-75bf9f9b027d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916030068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.2916030068 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.3099277262
Short name T1157
Test name
Test status
Simulation time 989334712 ps
CPU time 4.62 seconds
Started Aug 06 04:53:39 PM PDT 24
Finished Aug 06 04:53:43 PM PDT 24
Peak memory 216044 kb
Host smart-ed733281-09c9-4cf4-bf38-3361e9612a70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099277262 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.3099
277262 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.1339070445
Short name T1142
Test name
Test status
Simulation time 80606450 ps
CPU time 2.7 seconds
Started Aug 06 04:53:33 PM PDT 24
Finished Aug 06 04:53:36 PM PDT 24
Peak memory 220888 kb
Host smart-731fcd8f-a727-49bf-8e1c-5443a9c4153b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339070445 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.kmac_csr_mem_rw_with_rand_reset.1339070445 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_csr_rw.744776298
Short name T999
Test name
Test status
Simulation time 25896023 ps
CPU time 1.07 seconds
Started Aug 06 04:53:55 PM PDT 24
Finished Aug 06 04:53:56 PM PDT 24
Peak memory 215660 kb
Host smart-66c2da5c-5560-416d-b5fa-61e473bcb50e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744776298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.744776298 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/18.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_intr_test.967416638
Short name T146
Test name
Test status
Simulation time 29299934 ps
CPU time 0.89 seconds
Started Aug 06 04:53:33 PM PDT 24
Finished Aug 06 04:53:34 PM PDT 24
Peak memory 215700 kb
Host smart-e84d6c6c-a480-4bb4-9d08-2cbb1d0b664e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967416638 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.967416638 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/18.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.3240534119
Short name T132
Test name
Test status
Simulation time 120506589 ps
CPU time 1.7 seconds
Started Aug 06 04:53:47 PM PDT 24
Finished Aug 06 04:53:49 PM PDT 24
Peak memory 215960 kb
Host smart-1d090b73-d894-4cf5-a54c-21107cc4f94b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240534119 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_cs
r_outstanding.3240534119 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.2605200357
Short name T1027
Test name
Test status
Simulation time 99428790 ps
CPU time 1.09 seconds
Started Aug 06 04:53:36 PM PDT 24
Finished Aug 06 04:53:37 PM PDT 24
Peak memory 216024 kb
Host smart-e3b8c5f1-cac0-46d6-85c3-23ca7f9d0881
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605200357 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg
_errors.2605200357 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.721106808
Short name T1046
Test name
Test status
Simulation time 168227614 ps
CPU time 2.29 seconds
Started Aug 06 04:53:40 PM PDT 24
Finished Aug 06 04:53:43 PM PDT 24
Peak memory 219288 kb
Host smart-ae8130ee-d79b-4d6b-9022-e4558b11cb8c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721106808 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac
_shadow_reg_errors_with_csr_rw.721106808 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_tl_errors.2568665460
Short name T1120
Test name
Test status
Simulation time 55113211 ps
CPU time 2.07 seconds
Started Aug 06 04:53:40 PM PDT 24
Finished Aug 06 04:53:42 PM PDT 24
Peak memory 215960 kb
Host smart-0b6be017-d75e-4f8a-8375-ffa2790a80f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568665460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.2568665460 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.886184685
Short name T154
Test name
Test status
Simulation time 509519418 ps
CPU time 2.83 seconds
Started Aug 06 04:53:40 PM PDT 24
Finished Aug 06 04:53:43 PM PDT 24
Peak memory 215840 kb
Host smart-5e2962fe-1ac6-4dec-8ed5-0a80f22a9482
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886184685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.88618
4685 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.441460665
Short name T1150
Test name
Test status
Simulation time 281671923 ps
CPU time 2.44 seconds
Started Aug 06 04:53:38 PM PDT 24
Finished Aug 06 04:53:40 PM PDT 24
Peak memory 221016 kb
Host smart-e8f206e2-561a-4399-b2d1-8bd6db540af4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441460665 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.kmac_csr_mem_rw_with_rand_reset.441460665 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_csr_rw.2972358470
Short name T1073
Test name
Test status
Simulation time 12499041 ps
CPU time 0.93 seconds
Started Aug 06 04:53:40 PM PDT 24
Finished Aug 06 04:53:41 PM PDT 24
Peak memory 215776 kb
Host smart-a26041ea-e04d-429c-85e0-083d3ed75a66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972358470 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.2972358470 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_intr_test.760860451
Short name T1100
Test name
Test status
Simulation time 47596825 ps
CPU time 0.76 seconds
Started Aug 06 04:53:38 PM PDT 24
Finished Aug 06 04:53:39 PM PDT 24
Peak memory 215724 kb
Host smart-7468ef7d-52fb-4d05-8a5e-ea2dcdb988ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760860451 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.760860451 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/19.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.2801716724
Short name T1118
Test name
Test status
Simulation time 89527336 ps
CPU time 2.39 seconds
Started Aug 06 04:53:36 PM PDT 24
Finished Aug 06 04:53:39 PM PDT 24
Peak memory 216008 kb
Host smart-ba203410-632e-420f-aa70-c0b2e0c961c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801716724 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_cs
r_outstanding.2801716724 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.3330003977
Short name T1155
Test name
Test status
Simulation time 41935402 ps
CPU time 1.42 seconds
Started Aug 06 04:53:32 PM PDT 24
Finished Aug 06 04:53:33 PM PDT 24
Peak memory 217376 kb
Host smart-477940f7-62c4-4bf1-a323-5f910ab19655
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330003977 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg
_errors.3330003977 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_tl_errors.620270289
Short name T1055
Test name
Test status
Simulation time 29464990 ps
CPU time 1.98 seconds
Started Aug 06 04:53:39 PM PDT 24
Finished Aug 06 04:53:41 PM PDT 24
Peak memory 216104 kb
Host smart-e8611a70-cfff-4e46-9c98-9bfa58c4cbec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620270289 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.620270289 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/19.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.3042590634
Short name T1093
Test name
Test status
Simulation time 494298204 ps
CPU time 2.79 seconds
Started Aug 06 04:53:52 PM PDT 24
Finished Aug 06 04:53:55 PM PDT 24
Peak memory 215904 kb
Host smart-14a37989-dfac-4ea8-aeaa-7cbeeda7a3d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042590634 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.3042
590634 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.1936650568
Short name T1041
Test name
Test status
Simulation time 137088309 ps
CPU time 7.84 seconds
Started Aug 06 04:53:21 PM PDT 24
Finished Aug 06 04:53:29 PM PDT 24
Peak memory 215916 kb
Host smart-730d9783-3288-4986-b7e7-1c101e13c597
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936650568 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.1936650
568 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.3716137835
Short name T1143
Test name
Test status
Simulation time 1815056221 ps
CPU time 10.4 seconds
Started Aug 06 04:53:21 PM PDT 24
Finished Aug 06 04:53:31 PM PDT 24
Peak memory 215948 kb
Host smart-03ed7b0a-ac97-4474-ad2c-c20cc848639a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716137835 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.3716137
835 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.3269098476
Short name T1008
Test name
Test status
Simulation time 60337895 ps
CPU time 1.13 seconds
Started Aug 06 04:53:28 PM PDT 24
Finished Aug 06 04:53:30 PM PDT 24
Peak memory 215988 kb
Host smart-5edab7d7-a5ef-458b-bd69-1f3f7646e6da
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269098476 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.3269098
476 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.2419043743
Short name T1064
Test name
Test status
Simulation time 43428153 ps
CPU time 2.61 seconds
Started Aug 06 04:53:19 PM PDT 24
Finished Aug 06 04:53:21 PM PDT 24
Peak memory 221996 kb
Host smart-59b37dd6-283e-4cc0-8f54-b78b9e93eb4a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419043743 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.kmac_csr_mem_rw_with_rand_reset.2419043743 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_rw.2762941290
Short name T136
Test name
Test status
Simulation time 89446036 ps
CPU time 1.01 seconds
Started Aug 06 04:53:21 PM PDT 24
Finished Aug 06 04:53:23 PM PDT 24
Peak memory 215756 kb
Host smart-0313717e-c13b-46c7-b93c-a252cee22f64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762941290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.2762941290 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_intr_test.371643283
Short name T1010
Test name
Test status
Simulation time 12123356 ps
CPU time 0.79 seconds
Started Aug 06 04:53:25 PM PDT 24
Finished Aug 06 04:53:26 PM PDT 24
Peak memory 215696 kb
Host smart-b5db73fd-261e-46aa-9d60-08af0155d224
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371643283 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.371643283 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/2.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.403578411
Short name T125
Test name
Test status
Simulation time 181605713 ps
CPU time 1.54 seconds
Started Aug 06 04:53:34 PM PDT 24
Finished Aug 06 04:53:36 PM PDT 24
Peak memory 215896 kb
Host smart-7cc78af4-345f-4b1f-8e6d-2856ea536841
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403578411 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partial
_access.403578411 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_mem_walk.3480495619
Short name T1075
Test name
Test status
Simulation time 13642587 ps
CPU time 0.76 seconds
Started Aug 06 04:53:22 PM PDT 24
Finished Aug 06 04:53:23 PM PDT 24
Peak memory 215732 kb
Host smart-051cb6ec-5c1d-46fc-b077-702415534a73
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480495619 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.3480495619
+enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.1735856453
Short name T133
Test name
Test status
Simulation time 178484348 ps
CPU time 1.81 seconds
Started Aug 06 04:53:23 PM PDT 24
Finished Aug 06 04:53:25 PM PDT 24
Peak memory 215928 kb
Host smart-351edc4c-7735-4278-9605-7819113f73a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735856453 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr
_outstanding.1735856453 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.4090837583
Short name T1145
Test name
Test status
Simulation time 73157366 ps
CPU time 1.43 seconds
Started Aug 06 04:53:20 PM PDT 24
Finished Aug 06 04:53:21 PM PDT 24
Peak memory 216388 kb
Host smart-c522a82f-fdcc-469f-ad02-66a1c0258c08
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090837583 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_
errors.4090837583 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.2661706727
Short name T1104
Test name
Test status
Simulation time 379899989 ps
CPU time 2.46 seconds
Started Aug 06 04:53:32 PM PDT 24
Finished Aug 06 04:53:35 PM PDT 24
Peak memory 216388 kb
Host smart-87f8b9c7-d6d2-436e-9dae-7c6a7256bc1b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661706727 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac
_shadow_reg_errors_with_csr_rw.2661706727 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_tl_errors.2688215068
Short name T119
Test name
Test status
Simulation time 116208552 ps
CPU time 3.31 seconds
Started Aug 06 04:53:24 PM PDT 24
Finished Aug 06 04:53:27 PM PDT 24
Peak memory 216000 kb
Host smart-c8790192-4db1-4ea1-9d2c-8f81606bf7e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688215068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.2688215068 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.1319384073
Short name T109
Test name
Test status
Simulation time 302757140 ps
CPU time 5 seconds
Started Aug 06 04:53:22 PM PDT 24
Finished Aug 06 04:53:27 PM PDT 24
Peak memory 216036 kb
Host smart-9b878e82-6af9-40a8-a3f2-c109440b6936
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319384073 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.13193
84073 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.kmac_intr_test.1686253368
Short name T1125
Test name
Test status
Simulation time 13238127 ps
CPU time 0.78 seconds
Started Aug 06 04:53:38 PM PDT 24
Finished Aug 06 04:53:39 PM PDT 24
Peak memory 215584 kb
Host smart-a4835ae8-6700-4589-94ad-7afc93a20dc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686253368 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.1686253368 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.kmac_intr_test.2818695094
Short name T1072
Test name
Test status
Simulation time 21009566 ps
CPU time 0.86 seconds
Started Aug 06 04:53:36 PM PDT 24
Finished Aug 06 04:53:37 PM PDT 24
Peak memory 215784 kb
Host smart-540292dc-286b-4d00-bc9c-860d139c1600
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818695094 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.2818695094 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.kmac_intr_test.2010883963
Short name T1037
Test name
Test status
Simulation time 28118520 ps
CPU time 0.8 seconds
Started Aug 06 04:53:37 PM PDT 24
Finished Aug 06 04:53:38 PM PDT 24
Peak memory 215632 kb
Host smart-0789c528-dcb9-4a9b-85da-7d310084c74c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010883963 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.2010883963 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.kmac_intr_test.1644904819
Short name T1103
Test name
Test status
Simulation time 30604356 ps
CPU time 0.77 seconds
Started Aug 06 04:53:52 PM PDT 24
Finished Aug 06 04:53:53 PM PDT 24
Peak memory 215536 kb
Host smart-07215e4f-7654-4b10-8174-497b7e143fee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644904819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.1644904819 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.kmac_intr_test.1666160875
Short name T1146
Test name
Test status
Simulation time 35254694 ps
CPU time 0.75 seconds
Started Aug 06 04:53:37 PM PDT 24
Finished Aug 06 04:53:38 PM PDT 24
Peak memory 215708 kb
Host smart-ae7ade77-854e-414d-b01a-ce2acc293c8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666160875 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.1666160875 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.kmac_intr_test.361205838
Short name T1151
Test name
Test status
Simulation time 46242627 ps
CPU time 0.78 seconds
Started Aug 06 04:53:50 PM PDT 24
Finished Aug 06 04:53:55 PM PDT 24
Peak memory 215580 kb
Host smart-c04750b8-b6ec-4707-8f39-818e9365fe2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361205838 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.361205838 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/25.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.kmac_intr_test.1561134726
Short name T1024
Test name
Test status
Simulation time 25228246 ps
CPU time 0.82 seconds
Started Aug 06 04:53:32 PM PDT 24
Finished Aug 06 04:53:33 PM PDT 24
Peak memory 215728 kb
Host smart-65b18088-2b88-478d-bd4f-1302d0f7e4c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561134726 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.1561134726 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.kmac_intr_test.4008727993
Short name T147
Test name
Test status
Simulation time 18690296 ps
CPU time 0.78 seconds
Started Aug 06 04:53:52 PM PDT 24
Finished Aug 06 04:53:53 PM PDT 24
Peak memory 215628 kb
Host smart-1a5b7deb-d4c7-4a69-b364-cc182e1d8d36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008727993 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.4008727993 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.kmac_intr_test.2418959068
Short name T1079
Test name
Test status
Simulation time 11097005 ps
CPU time 0.78 seconds
Started Aug 06 04:53:42 PM PDT 24
Finished Aug 06 04:53:43 PM PDT 24
Peak memory 215628 kb
Host smart-e87a70c6-f316-413d-99af-ff1ac5a89af8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418959068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.2418959068 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.kmac_intr_test.3916462227
Short name T1066
Test name
Test status
Simulation time 49821025 ps
CPU time 0.75 seconds
Started Aug 06 04:53:40 PM PDT 24
Finished Aug 06 04:53:41 PM PDT 24
Peak memory 215740 kb
Host smart-dd4c6dc6-9880-4f18-a284-3b447b12df26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916462227 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.3916462227 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.3257905230
Short name T1069
Test name
Test status
Simulation time 570123523 ps
CPU time 9.55 seconds
Started Aug 06 04:53:32 PM PDT 24
Finished Aug 06 04:53:42 PM PDT 24
Peak memory 215924 kb
Host smart-b7485741-0a9b-4548-b3bb-b749fe65f1a3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257905230 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.3257905
230 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.958150256
Short name T1059
Test name
Test status
Simulation time 518860099 ps
CPU time 9.5 seconds
Started Aug 06 04:53:24 PM PDT 24
Finished Aug 06 04:53:34 PM PDT 24
Peak memory 215984 kb
Host smart-8d4488cc-c368-4226-9208-5df4d2f2e26d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958150256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.95815025
6 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.2720089906
Short name T1011
Test name
Test status
Simulation time 70260188 ps
CPU time 1.04 seconds
Started Aug 06 04:53:37 PM PDT 24
Finished Aug 06 04:53:38 PM PDT 24
Peak memory 215768 kb
Host smart-2e39b99d-8de3-418f-b297-66173bc7fde3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720089906 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.2720089
906 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.3935047090
Short name T1140
Test name
Test status
Simulation time 26421939 ps
CPU time 1.51 seconds
Started Aug 06 04:53:24 PM PDT 24
Finished Aug 06 04:53:26 PM PDT 24
Peak memory 217048 kb
Host smart-f0ca4081-95a8-4a91-a7b2-04dfa458db16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935047090 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.kmac_csr_mem_rw_with_rand_reset.3935047090 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_rw.996678724
Short name T1070
Test name
Test status
Simulation time 60446078 ps
CPU time 0.93 seconds
Started Aug 06 04:53:37 PM PDT 24
Finished Aug 06 04:53:38 PM PDT 24
Peak memory 215640 kb
Host smart-9869ec19-7f11-4b64-bcbc-0a5b66456933
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996678724 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.996678724 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_intr_test.1868178272
Short name T1124
Test name
Test status
Simulation time 12497482 ps
CPU time 0.79 seconds
Started Aug 06 04:53:20 PM PDT 24
Finished Aug 06 04:53:21 PM PDT 24
Peak memory 215732 kb
Host smart-b9b80d55-b08b-470a-84d3-14892375d1e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868178272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.1868178272 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.4124379201
Short name T126
Test name
Test status
Simulation time 38884069 ps
CPU time 1.54 seconds
Started Aug 06 04:53:20 PM PDT 24
Finished Aug 06 04:53:22 PM PDT 24
Peak memory 216036 kb
Host smart-94be6f28-d109-43fb-b052-4856c41a1ee0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124379201 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partia
l_access.4124379201 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_mem_walk.2755128053
Short name T1006
Test name
Test status
Simulation time 11909555 ps
CPU time 0.74 seconds
Started Aug 06 04:53:21 PM PDT 24
Finished Aug 06 04:53:22 PM PDT 24
Peak memory 215680 kb
Host smart-1971ab81-1871-4e14-b5df-e16ebb164ab2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755128053 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.2755128053
+enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.4093011864
Short name T1007
Test name
Test status
Simulation time 142633444 ps
CPU time 2.26 seconds
Started Aug 06 04:53:34 PM PDT 24
Finished Aug 06 04:53:36 PM PDT 24
Peak memory 215984 kb
Host smart-d6a4e163-ca2e-4877-92a0-f20055422a4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093011864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr
_outstanding.4093011864 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.3992758998
Short name T91
Test name
Test status
Simulation time 83540470 ps
CPU time 1.18 seconds
Started Aug 06 04:53:24 PM PDT 24
Finished Aug 06 04:53:25 PM PDT 24
Peak memory 217252 kb
Host smart-b1b16b5f-00af-4d5a-9219-1797fc0a2b9e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992758998 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_
errors.3992758998 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.195767999
Short name T1132
Test name
Test status
Simulation time 112893315 ps
CPU time 1.74 seconds
Started Aug 06 04:53:21 PM PDT 24
Finished Aug 06 04:53:22 PM PDT 24
Peak memory 219604 kb
Host smart-66f4bdd9-e78b-477c-96eb-05bd6c30ca1d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195767999 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_
shadow_reg_errors_with_csr_rw.195767999 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_tl_errors.539777277
Short name T1076
Test name
Test status
Simulation time 239128428 ps
CPU time 3.38 seconds
Started Aug 06 04:53:22 PM PDT 24
Finished Aug 06 04:53:25 PM PDT 24
Peak memory 216080 kb
Host smart-9694e3f2-454f-4184-a106-b94d283da378
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539777277 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.539777277 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/3.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.3082222418
Short name T138
Test name
Test status
Simulation time 236492488 ps
CPU time 2.67 seconds
Started Aug 06 04:53:33 PM PDT 24
Finished Aug 06 04:53:36 PM PDT 24
Peak memory 215860 kb
Host smart-94a555c0-a3b3-450a-93df-698f83812065
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082222418 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.30822
22418 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.kmac_intr_test.4080457594
Short name T144
Test name
Test status
Simulation time 37384637 ps
CPU time 0.75 seconds
Started Aug 06 04:53:56 PM PDT 24
Finished Aug 06 04:53:57 PM PDT 24
Peak memory 215528 kb
Host smart-a974d20c-390b-4a40-abd1-3c5b92c8a8d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080457594 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.4080457594 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.kmac_intr_test.1396494773
Short name T1090
Test name
Test status
Simulation time 13981975 ps
CPU time 0.76 seconds
Started Aug 06 04:53:52 PM PDT 24
Finished Aug 06 04:53:53 PM PDT 24
Peak memory 215628 kb
Host smart-1e9a52e4-720a-493f-970b-c898bf049194
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396494773 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.1396494773 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.kmac_intr_test.3409197181
Short name T1077
Test name
Test status
Simulation time 27759837 ps
CPU time 0.81 seconds
Started Aug 06 04:53:56 PM PDT 24
Finished Aug 06 04:53:57 PM PDT 24
Peak memory 215616 kb
Host smart-43f1a9bc-8787-4bf5-8707-231298de41dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409197181 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.3409197181 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.kmac_intr_test.2068366476
Short name T1138
Test name
Test status
Simulation time 18236263 ps
CPU time 0.75 seconds
Started Aug 06 04:53:54 PM PDT 24
Finished Aug 06 04:53:54 PM PDT 24
Peak memory 215620 kb
Host smart-58c6ace6-08a4-4f12-823b-7d2db2c1faf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068366476 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.2068366476 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.kmac_intr_test.3639572645
Short name T1020
Test name
Test status
Simulation time 57119223 ps
CPU time 0.81 seconds
Started Aug 06 04:53:55 PM PDT 24
Finished Aug 06 04:53:56 PM PDT 24
Peak memory 215624 kb
Host smart-03c7217a-083b-4076-aad5-7dbd3042ba6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639572645 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.3639572645 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.kmac_intr_test.395644540
Short name T1098
Test name
Test status
Simulation time 18352116 ps
CPU time 0.85 seconds
Started Aug 06 04:53:38 PM PDT 24
Finished Aug 06 04:53:39 PM PDT 24
Peak memory 215752 kb
Host smart-d1c6c3b0-d054-4d05-a410-c6f981d3a544
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395644540 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.395644540 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/36.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.kmac_intr_test.473452029
Short name T112
Test name
Test status
Simulation time 22415089 ps
CPU time 0.76 seconds
Started Aug 06 04:53:56 PM PDT 24
Finished Aug 06 04:53:57 PM PDT 24
Peak memory 215620 kb
Host smart-ee88e8c7-fbdd-4068-9834-dcad207433b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473452029 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.473452029 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/37.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.kmac_intr_test.1329004153
Short name T1096
Test name
Test status
Simulation time 90523735 ps
CPU time 0.85 seconds
Started Aug 06 04:54:15 PM PDT 24
Finished Aug 06 04:54:16 PM PDT 24
Peak memory 215688 kb
Host smart-6455458e-858f-43c8-b2e7-31b99b197418
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329004153 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.1329004153 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.kmac_intr_test.1941017922
Short name T1107
Test name
Test status
Simulation time 28804092 ps
CPU time 0.78 seconds
Started Aug 06 04:53:39 PM PDT 24
Finished Aug 06 04:53:40 PM PDT 24
Peak memory 215732 kb
Host smart-25dd63b9-9883-4cbb-80dd-4bcca86cde2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941017922 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.1941017922 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.97708672
Short name T1071
Test name
Test status
Simulation time 1362878511 ps
CPU time 9.56 seconds
Started Aug 06 04:53:28 PM PDT 24
Finished Aug 06 04:53:38 PM PDT 24
Peak memory 215884 kb
Host smart-ab4298da-d536-4741-9813-6ecc706d7394
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97708672 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.97708672
+enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.2032904914
Short name T1086
Test name
Test status
Simulation time 152708846 ps
CPU time 7.98 seconds
Started Aug 06 04:53:33 PM PDT 24
Finished Aug 06 04:53:41 PM PDT 24
Peak memory 215924 kb
Host smart-1f42890d-125d-43a3-90ff-2b573f25ae92
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032904914 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.2032904
914 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.1616988124
Short name T135
Test name
Test status
Simulation time 45920368 ps
CPU time 1.24 seconds
Started Aug 06 04:53:36 PM PDT 24
Finished Aug 06 04:53:42 PM PDT 24
Peak memory 215888 kb
Host smart-6e9bba24-ecd8-4bca-8559-ba2b75834b8d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616988124 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.1616988
124 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.2215398538
Short name T1065
Test name
Test status
Simulation time 65817395 ps
CPU time 1.49 seconds
Started Aug 06 04:53:36 PM PDT 24
Finished Aug 06 04:53:37 PM PDT 24
Peak memory 217840 kb
Host smart-23256457-a78e-4712-9d70-e175e05fadbe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215398538 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.kmac_csr_mem_rw_with_rand_reset.2215398538 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_rw.2372552710
Short name T1135
Test name
Test status
Simulation time 27253080 ps
CPU time 1.05 seconds
Started Aug 06 04:53:33 PM PDT 24
Finished Aug 06 04:53:34 PM PDT 24
Peak memory 215824 kb
Host smart-f8ee092d-7688-4ca4-a729-4438d6423f38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372552710 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.2372552710 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_intr_test.1474084426
Short name T1057
Test name
Test status
Simulation time 40959503 ps
CPU time 0.78 seconds
Started Aug 06 04:53:37 PM PDT 24
Finished Aug 06 04:53:38 PM PDT 24
Peak memory 215640 kb
Host smart-a9d6a020-cc09-49e8-bf18-15fbb49de31a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474084426 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.1474084426 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.1987645551
Short name T127
Test name
Test status
Simulation time 59931328 ps
CPU time 1.17 seconds
Started Aug 06 04:53:21 PM PDT 24
Finished Aug 06 04:53:23 PM PDT 24
Peak memory 215980 kb
Host smart-4ef83f88-300f-4c82-a4ed-28d42c6fba3d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987645551 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partia
l_access.1987645551 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_mem_walk.1188320267
Short name T1035
Test name
Test status
Simulation time 140220381 ps
CPU time 0.76 seconds
Started Aug 06 04:53:24 PM PDT 24
Finished Aug 06 04:53:25 PM PDT 24
Peak memory 215464 kb
Host smart-f0dd9916-6a73-437e-9f98-6c19da799505
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188320267 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.1188320267
+enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.2592891081
Short name T1023
Test name
Test status
Simulation time 340715997 ps
CPU time 2.37 seconds
Started Aug 06 04:53:38 PM PDT 24
Finished Aug 06 04:53:41 PM PDT 24
Peak memory 215884 kb
Host smart-582cf6c2-69ad-48bb-b764-39cc0d1ca228
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592891081 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr
_outstanding.2592891081 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.4264321056
Short name T1101
Test name
Test status
Simulation time 43821584 ps
CPU time 0.93 seconds
Started Aug 06 04:53:26 PM PDT 24
Finished Aug 06 04:53:27 PM PDT 24
Peak memory 215840 kb
Host smart-f32c8429-ff17-4d68-bbdd-9e69cdbce18a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264321056 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_
errors.4264321056 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.2857921969
Short name T92
Test name
Test status
Simulation time 491480996 ps
CPU time 2.9 seconds
Started Aug 06 04:53:26 PM PDT 24
Finished Aug 06 04:53:29 PM PDT 24
Peak memory 219696 kb
Host smart-0296dfdb-ffac-487c-be8c-7f947ad71e51
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857921969 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac
_shadow_reg_errors_with_csr_rw.2857921969 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_tl_errors.3346401851
Short name T1031
Test name
Test status
Simulation time 112248691 ps
CPU time 1.75 seconds
Started Aug 06 04:53:41 PM PDT 24
Finished Aug 06 04:53:43 PM PDT 24
Peak memory 216044 kb
Host smart-02941aec-3ee6-4f8c-93ea-81d773b06e5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346401851 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.3346401851 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.1097798777
Short name T1105
Test name
Test status
Simulation time 1018584700 ps
CPU time 2.86 seconds
Started Aug 06 04:53:22 PM PDT 24
Finished Aug 06 04:53:25 PM PDT 24
Peak memory 216044 kb
Host smart-8b393e09-5161-4e4d-a517-64d146a421d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097798777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.10977
98777 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.kmac_intr_test.2151887279
Short name T1016
Test name
Test status
Simulation time 13233598 ps
CPU time 0.79 seconds
Started Aug 06 04:53:41 PM PDT 24
Finished Aug 06 04:53:42 PM PDT 24
Peak memory 215788 kb
Host smart-bfc25890-5f83-4a7d-9117-d4c9790e373b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151887279 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.2151887279 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.kmac_intr_test.4118083642
Short name T1003
Test name
Test status
Simulation time 25958219 ps
CPU time 0.8 seconds
Started Aug 06 04:53:44 PM PDT 24
Finished Aug 06 04:53:45 PM PDT 24
Peak memory 215632 kb
Host smart-cd482628-d887-49b5-81c6-83422e701eda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118083642 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.4118083642 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.kmac_intr_test.2408528312
Short name T1051
Test name
Test status
Simulation time 19838984 ps
CPU time 0.77 seconds
Started Aug 06 04:53:56 PM PDT 24
Finished Aug 06 04:53:57 PM PDT 24
Peak memory 215620 kb
Host smart-decab59f-601d-4db7-9b78-8745e6947138
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408528312 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.2408528312 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.kmac_intr_test.4132114609
Short name T1128
Test name
Test status
Simulation time 25461972 ps
CPU time 0.78 seconds
Started Aug 06 04:53:44 PM PDT 24
Finished Aug 06 04:53:45 PM PDT 24
Peak memory 215620 kb
Host smart-49ad05c4-4111-4480-9b9e-468ca3e37798
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132114609 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.4132114609 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.kmac_intr_test.467554326
Short name T1088
Test name
Test status
Simulation time 24100742 ps
CPU time 0.79 seconds
Started Aug 06 04:53:40 PM PDT 24
Finished Aug 06 04:53:41 PM PDT 24
Peak memory 215740 kb
Host smart-92e909f3-69a0-4791-84c7-e8d21d790cbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467554326 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.467554326 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/44.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.kmac_intr_test.2423345389
Short name T1060
Test name
Test status
Simulation time 26736104 ps
CPU time 0.74 seconds
Started Aug 06 04:53:47 PM PDT 24
Finished Aug 06 04:53:48 PM PDT 24
Peak memory 215724 kb
Host smart-49be4b97-6b75-43b7-9fac-6da8e404382d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423345389 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.2423345389 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.kmac_intr_test.3807328505
Short name T1018
Test name
Test status
Simulation time 24343848 ps
CPU time 0.77 seconds
Started Aug 06 04:53:43 PM PDT 24
Finished Aug 06 04:53:44 PM PDT 24
Peak memory 215420 kb
Host smart-27fc107a-66f9-4764-837d-8d7688bd2ec3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807328505 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.3807328505 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.kmac_intr_test.1578908703
Short name T1153
Test name
Test status
Simulation time 19531754 ps
CPU time 0.85 seconds
Started Aug 06 04:53:40 PM PDT 24
Finished Aug 06 04:53:41 PM PDT 24
Peak memory 215728 kb
Host smart-66a9b7c2-7db9-47ea-b997-35614937f451
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578908703 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.1578908703 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.kmac_intr_test.762772742
Short name T1154
Test name
Test status
Simulation time 46108586 ps
CPU time 0.77 seconds
Started Aug 06 04:53:44 PM PDT 24
Finished Aug 06 04:53:45 PM PDT 24
Peak memory 215656 kb
Host smart-678d2277-14aa-4993-90f3-238edff24da2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762772742 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.762772742 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/48.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.kmac_intr_test.1940641280
Short name T113
Test name
Test status
Simulation time 67574766 ps
CPU time 0.78 seconds
Started Aug 06 04:54:02 PM PDT 24
Finished Aug 06 04:54:03 PM PDT 24
Peak memory 215732 kb
Host smart-003cceb1-ac3b-45e7-9936-7e4d752bc7c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940641280 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.1940641280 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.1116012196
Short name T118
Test name
Test status
Simulation time 330802145 ps
CPU time 2.48 seconds
Started Aug 06 04:53:44 PM PDT 24
Finished Aug 06 04:53:46 PM PDT 24
Peak memory 220740 kb
Host smart-9dc1d9f2-c293-4776-829b-16e50cea12f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116012196 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.kmac_csr_mem_rw_with_rand_reset.1116012196 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_csr_rw.975572420
Short name T162
Test name
Test status
Simulation time 19976251 ps
CPU time 1.12 seconds
Started Aug 06 04:53:22 PM PDT 24
Finished Aug 06 04:53:23 PM PDT 24
Peak memory 215796 kb
Host smart-1d704246-8f75-4be5-af9d-20554d0ba31c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975572420 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.975572420 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/5.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_intr_test.1277236275
Short name T1123
Test name
Test status
Simulation time 31213332 ps
CPU time 0.79 seconds
Started Aug 06 04:53:40 PM PDT 24
Finished Aug 06 04:53:41 PM PDT 24
Peak memory 215720 kb
Host smart-b8208890-bea8-41ed-b647-1e388b8a32fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277236275 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.1277236275 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.1368194463
Short name T1017
Test name
Test status
Simulation time 103223256 ps
CPU time 2.53 seconds
Started Aug 06 04:53:24 PM PDT 24
Finished Aug 06 04:53:26 PM PDT 24
Peak memory 215960 kb
Host smart-c42f42f2-114f-4097-81cf-c2f0edd80632
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368194463 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr
_outstanding.1368194463 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.910944250
Short name T1074
Test name
Test status
Simulation time 38956359 ps
CPU time 1.17 seconds
Started Aug 06 04:53:28 PM PDT 24
Finished Aug 06 04:53:29 PM PDT 24
Peak memory 216292 kb
Host smart-3b5b804d-2741-4fd8-9a5a-dd3970e65650
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910944250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_e
rrors.910944250 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.593295200
Short name T93
Test name
Test status
Simulation time 60338796 ps
CPU time 1.76 seconds
Started Aug 06 04:53:21 PM PDT 24
Finished Aug 06 04:53:23 PM PDT 24
Peak memory 218324 kb
Host smart-be41998d-df1d-4df8-95e2-f00b3245bbf6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593295200 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_
shadow_reg_errors_with_csr_rw.593295200 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_tl_errors.4215341606
Short name T120
Test name
Test status
Simulation time 202408063 ps
CPU time 2.49 seconds
Started Aug 06 04:53:36 PM PDT 24
Finished Aug 06 04:53:38 PM PDT 24
Peak memory 215516 kb
Host smart-2d481668-ea20-4c84-8925-788d26058a3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215341606 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.4215341606 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.2205618077
Short name T1067
Test name
Test status
Simulation time 40811484 ps
CPU time 1.59 seconds
Started Aug 06 04:53:20 PM PDT 24
Finished Aug 06 04:53:21 PM PDT 24
Peak memory 219168 kb
Host smart-9afcb911-a5e7-4a35-a043-1d7a7b494a92
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205618077 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.kmac_csr_mem_rw_with_rand_reset.2205618077 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_csr_rw.3630903059
Short name T1029
Test name
Test status
Simulation time 173794381 ps
CPU time 1.02 seconds
Started Aug 06 04:53:23 PM PDT 24
Finished Aug 06 04:53:24 PM PDT 24
Peak memory 215756 kb
Host smart-5cce2e89-40fb-4830-8224-b66921e4a8ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630903059 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.3630903059 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_intr_test.2676464639
Short name T143
Test name
Test status
Simulation time 33554860 ps
CPU time 0.75 seconds
Started Aug 06 04:53:38 PM PDT 24
Finished Aug 06 04:53:39 PM PDT 24
Peak memory 215744 kb
Host smart-66abc886-c34e-4673-aa78-c715fe259c31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676464639 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.2676464639 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.2802872065
Short name T1110
Test name
Test status
Simulation time 168259710 ps
CPU time 1.62 seconds
Started Aug 06 04:53:24 PM PDT 24
Finished Aug 06 04:53:26 PM PDT 24
Peak memory 215996 kb
Host smart-18bbcdfc-6e0c-4461-8d15-e928beb1a5a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802872065 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr
_outstanding.2802872065 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.2868823303
Short name T1022
Test name
Test status
Simulation time 87446618 ps
CPU time 1.1 seconds
Started Aug 06 04:53:29 PM PDT 24
Finished Aug 06 04:53:31 PM PDT 24
Peak memory 216044 kb
Host smart-fe3a50f4-54b7-4692-9bcc-531ce130aaca
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868823303 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_
errors.2868823303 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.1066282308
Short name T1054
Test name
Test status
Simulation time 93321630 ps
CPU time 2.58 seconds
Started Aug 06 04:53:30 PM PDT 24
Finished Aug 06 04:53:38 PM PDT 24
Peak memory 219468 kb
Host smart-91a882f4-2c0e-47cc-9d4c-d92283cffd99
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066282308 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac
_shadow_reg_errors_with_csr_rw.1066282308 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_tl_errors.2550261447
Short name T1000
Test name
Test status
Simulation time 92794666 ps
CPU time 2.8 seconds
Started Aug 06 04:53:42 PM PDT 24
Finished Aug 06 04:53:45 PM PDT 24
Peak memory 216068 kb
Host smart-bc27136d-396c-4caf-9327-db71fb16d7d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550261447 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.2550261447 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.28607996
Short name T1097
Test name
Test status
Simulation time 557230365 ps
CPU time 1.88 seconds
Started Aug 06 04:53:40 PM PDT 24
Finished Aug 06 04:53:42 PM PDT 24
Peak memory 216972 kb
Host smart-78992efa-daf5-46df-92b3-bfe66ab14b96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28607996 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.kmac_csr_mem_rw_with_rand_reset.28607996 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_csr_rw.217990487
Short name T1121
Test name
Test status
Simulation time 22963543 ps
CPU time 0.96 seconds
Started Aug 06 04:53:22 PM PDT 24
Finished Aug 06 04:53:24 PM PDT 24
Peak memory 215728 kb
Host smart-9c2d4817-e4c9-44b3-ba3b-136baa783658
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217990487 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.217990487 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/7.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_intr_test.340115893
Short name T1156
Test name
Test status
Simulation time 19117525 ps
CPU time 0.77 seconds
Started Aug 06 04:53:40 PM PDT 24
Finished Aug 06 04:53:41 PM PDT 24
Peak memory 215768 kb
Host smart-4f20c05d-11dd-40fa-ad10-c3e15d2afa8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340115893 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.340115893 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/7.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.4178895182
Short name T1092
Test name
Test status
Simulation time 86688584 ps
CPU time 2.39 seconds
Started Aug 06 04:53:23 PM PDT 24
Finished Aug 06 04:53:25 PM PDT 24
Peak memory 215984 kb
Host smart-b92a4817-452c-45c3-9bcf-2ba6429ab810
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178895182 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr
_outstanding.4178895182 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.1796871368
Short name T1039
Test name
Test status
Simulation time 67463280 ps
CPU time 1.39 seconds
Started Aug 06 04:53:40 PM PDT 24
Finished Aug 06 04:53:42 PM PDT 24
Peak memory 216168 kb
Host smart-0bc3dc90-5e44-48bb-9413-f6911005588e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796871368 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_
errors.1796871368 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.3953228600
Short name T96
Test name
Test status
Simulation time 303010612 ps
CPU time 2.04 seconds
Started Aug 06 04:53:29 PM PDT 24
Finished Aug 06 04:53:31 PM PDT 24
Peak memory 218404 kb
Host smart-979cc442-7939-460d-9084-c5c7c7152306
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953228600 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac
_shadow_reg_errors_with_csr_rw.3953228600 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_tl_errors.1609460535
Short name T1122
Test name
Test status
Simulation time 126864153 ps
CPU time 1.78 seconds
Started Aug 06 04:53:28 PM PDT 24
Finished Aug 06 04:53:30 PM PDT 24
Peak memory 216020 kb
Host smart-5bf0b490-1cbb-4748-a3e4-58d90f7aec05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609460535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.1609460535 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.1941065680
Short name T1043
Test name
Test status
Simulation time 402312186 ps
CPU time 2.45 seconds
Started Aug 06 04:53:41 PM PDT 24
Finished Aug 06 04:53:43 PM PDT 24
Peak memory 216028 kb
Host smart-2371b04e-7169-47b5-96a2-51673f925db3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941065680 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.19410
65680 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.828053412
Short name T1131
Test name
Test status
Simulation time 47940704 ps
CPU time 1.68 seconds
Started Aug 06 04:53:32 PM PDT 24
Finished Aug 06 04:53:34 PM PDT 24
Peak memory 217936 kb
Host smart-5908389a-1cf2-4796-bfee-feb5036ba785
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828053412 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.kmac_csr_mem_rw_with_rand_reset.828053412 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_csr_rw.1938207810
Short name T1116
Test name
Test status
Simulation time 78835145 ps
CPU time 0.96 seconds
Started Aug 06 04:53:36 PM PDT 24
Finished Aug 06 04:53:37 PM PDT 24
Peak memory 215680 kb
Host smart-7355ae39-5ab6-44a3-b983-6f508e6d4579
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938207810 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.1938207810 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_intr_test.3639766379
Short name T1033
Test name
Test status
Simulation time 40991594 ps
CPU time 0.76 seconds
Started Aug 06 04:53:45 PM PDT 24
Finished Aug 06 04:53:46 PM PDT 24
Peak memory 215660 kb
Host smart-1686e874-5c49-429a-95f8-70315acc590a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639766379 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.3639766379 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.3218728754
Short name T993
Test name
Test status
Simulation time 44967028 ps
CPU time 1.44 seconds
Started Aug 06 04:53:29 PM PDT 24
Finished Aug 06 04:53:31 PM PDT 24
Peak memory 215976 kb
Host smart-ba6dddb6-4feb-4382-b12d-945e341e19e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218728754 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr
_outstanding.3218728754 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.2076628932
Short name T100
Test name
Test status
Simulation time 84691499 ps
CPU time 1.4 seconds
Started Aug 06 04:53:36 PM PDT 24
Finished Aug 06 04:53:37 PM PDT 24
Peak memory 217388 kb
Host smart-a512d383-7bb7-4734-857f-3243ef932e6d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076628932 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_
errors.2076628932 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.1407841837
Short name T1102
Test name
Test status
Simulation time 212614253 ps
CPU time 1.92 seconds
Started Aug 06 04:53:26 PM PDT 24
Finished Aug 06 04:53:28 PM PDT 24
Peak memory 219716 kb
Host smart-6b819156-db6a-47a2-b0f0-8e91b4df12c2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407841837 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac
_shadow_reg_errors_with_csr_rw.1407841837 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_tl_errors.1683392457
Short name T1152
Test name
Test status
Simulation time 312665918 ps
CPU time 3.7 seconds
Started Aug 06 04:53:26 PM PDT 24
Finished Aug 06 04:53:30 PM PDT 24
Peak memory 215980 kb
Host smart-f9f19eb6-a86f-4fa1-b4c7-b5fba2b4501b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683392457 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.1683392457 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.1032536693
Short name T1052
Test name
Test status
Simulation time 790171502 ps
CPU time 4.65 seconds
Started Aug 06 04:53:47 PM PDT 24
Finished Aug 06 04:53:51 PM PDT 24
Peak memory 215984 kb
Host smart-1583585c-1cf8-4d4d-93bb-3c13bae4878e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032536693 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.10325
36693 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.2905987075
Short name T1094
Test name
Test status
Simulation time 80456373 ps
CPU time 1.55 seconds
Started Aug 06 04:53:32 PM PDT 24
Finished Aug 06 04:53:33 PM PDT 24
Peak memory 217036 kb
Host smart-46ef3d09-8e0e-4df7-894c-d2cfea20f535
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905987075 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.kmac_csr_mem_rw_with_rand_reset.2905987075 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_csr_rw.363285461
Short name T1106
Test name
Test status
Simulation time 60331788 ps
CPU time 1.15 seconds
Started Aug 06 04:53:32 PM PDT 24
Finished Aug 06 04:53:33 PM PDT 24
Peak memory 216012 kb
Host smart-7391fdc4-630b-45aa-8508-c6fccb730bec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363285461 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.363285461 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/9.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_intr_test.3096924042
Short name T111
Test name
Test status
Simulation time 20543065 ps
CPU time 0.77 seconds
Started Aug 06 04:53:38 PM PDT 24
Finished Aug 06 04:53:39 PM PDT 24
Peak memory 215752 kb
Host smart-0fc6cf13-ca8f-405d-8a81-e374b351af48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096924042 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.3096924042 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.2077880445
Short name T1021
Test name
Test status
Simulation time 44780803 ps
CPU time 1.49 seconds
Started Aug 06 04:53:32 PM PDT 24
Finished Aug 06 04:53:33 PM PDT 24
Peak memory 215976 kb
Host smart-ae75e7f2-63e5-47d8-ad40-b9619d29a07c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077880445 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr
_outstanding.2077880445 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.743084744
Short name T1119
Test name
Test status
Simulation time 23003852 ps
CPU time 1.02 seconds
Started Aug 06 04:53:29 PM PDT 24
Finished Aug 06 04:53:31 PM PDT 24
Peak memory 216180 kb
Host smart-e3cb950d-7386-40f4-884b-4a1ec4248e88
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743084744 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_e
rrors.743084744 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.3584088921
Short name T1127
Test name
Test status
Simulation time 77112915 ps
CPU time 1.9 seconds
Started Aug 06 04:53:28 PM PDT 24
Finished Aug 06 04:53:30 PM PDT 24
Peak memory 219304 kb
Host smart-0c32755f-c279-45b6-bb6c-1556e067d671
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584088921 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac
_shadow_reg_errors_with_csr_rw.3584088921 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_tl_errors.2976128315
Short name T1137
Test name
Test status
Simulation time 547403149 ps
CPU time 2.45 seconds
Started Aug 06 04:53:36 PM PDT 24
Finished Aug 06 04:53:39 PM PDT 24
Peak memory 216128 kb
Host smart-8c73d022-8c0d-4cbb-b22f-46cf655439db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976128315 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.2976128315 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.2292443677
Short name T156
Test name
Test status
Simulation time 1319446822 ps
CPU time 4.92 seconds
Started Aug 06 04:53:38 PM PDT 24
Finished Aug 06 04:53:42 PM PDT 24
Peak memory 216040 kb
Host smart-74c6dd83-8f5e-46aa-9b71-ff64865bbcfc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292443677 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.22924
43677 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.kmac_app.245888474
Short name T428
Test name
Test status
Simulation time 30764631870 ps
CPU time 409.25 seconds
Started Aug 06 06:00:04 PM PDT 24
Finished Aug 06 06:06:55 PM PDT 24
Peak memory 512268 kb
Host smart-505292c7-d2a3-478a-a524-5da3c9a63393
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245888474 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.245888474 +enable_masking=1
+sw_key_masked=0
Directory /workspace/0.kmac_app/latest

Test location /workspace/coverage/default/0.kmac_app_with_partial_data.2610226652
Short name T485
Test name
Test status
Simulation time 9067625594 ps
CPU time 310 seconds
Started Aug 06 06:00:09 PM PDT 24
Finished Aug 06 06:05:19 PM PDT 24
Peak memory 314100 kb
Host smart-039b0940-6f14-4b91-aef9-8802061aeb82
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610226652 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_par
tial_data.2610226652 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/0.kmac_burst_write.2024144732
Short name T459
Test name
Test status
Simulation time 8518878211 ps
CPU time 858.82 seconds
Started Aug 06 06:00:08 PM PDT 24
Finished Aug 06 06:14:27 PM PDT 24
Peak memory 243512 kb
Host smart-1bc758a4-b270-4c59-a5be-15d4eed47e5d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024144732 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.2024144732
+enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_burst_write/latest

Test location /workspace/coverage/default/0.kmac_entropy_ready_error.378884786
Short name T462
Test name
Test status
Simulation time 4882397636 ps
CPU time 50.26 seconds
Started Aug 06 06:00:07 PM PDT 24
Finished Aug 06 06:00:57 PM PDT 24
Peak memory 223832 kb
Host smart-b91de527-d1ab-4626-993e-43dc257b5d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378884786 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.378884786 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_refresh.784231222
Short name T554
Test name
Test status
Simulation time 51229808694 ps
CPU time 193.53 seconds
Started Aug 06 06:00:08 PM PDT 24
Finished Aug 06 06:03:22 PM PDT 24
Peak memory 279568 kb
Host smart-93835ecb-055f-464d-a0b5-fb72faa851d2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784231222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.784
231222 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/0.kmac_error.298722493
Short name T142
Test name
Test status
Simulation time 5491028145 ps
CPU time 483.23 seconds
Started Aug 06 06:00:07 PM PDT 24
Finished Aug 06 06:08:11 PM PDT 24
Peak memory 381540 kb
Host smart-cb89d2e5-8dc5-4082-a2f7-9f65c8a4ea95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298722493 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.298722493 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_error/latest

Test location /workspace/coverage/default/0.kmac_key_error.3070176389
Short name T501
Test name
Test status
Simulation time 9149818335 ps
CPU time 13.37 seconds
Started Aug 06 06:00:06 PM PDT 24
Finished Aug 06 06:00:20 PM PDT 24
Peak memory 226972 kb
Host smart-88e539f7-cc5e-44c5-a776-0b91ef0e338e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070176389 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.3070176389 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_key_error/latest

Test location /workspace/coverage/default/0.kmac_lc_escalation.1747110115
Short name T88
Test name
Test status
Simulation time 1627004486 ps
CPU time 28.45 seconds
Started Aug 06 06:00:05 PM PDT 24
Finished Aug 06 06:00:34 PM PDT 24
Peak memory 251668 kb
Host smart-e80adee5-7184-4ab3-9e82-ee81fdb86a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747110115 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.1747110115 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/0.kmac_lc_escalation/latest

Test location /workspace/coverage/default/0.kmac_long_msg_and_output.3378900240
Short name T644
Test name
Test status
Simulation time 11423106826 ps
CPU time 1172.73 seconds
Started Aug 06 06:00:06 PM PDT 24
Finished Aug 06 06:19:40 PM PDT 24
Peak memory 844656 kb
Host smart-f21cde85-0ffc-411a-ba1a-9d31564948eb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378900240 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_an
d_output.3378900240 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/0.kmac_mubi.3037668921
Short name T764
Test name
Test status
Simulation time 44493056369 ps
CPU time 100.47 seconds
Started Aug 06 06:00:06 PM PDT 24
Finished Aug 06 06:01:47 PM PDT 24
Peak memory 283580 kb
Host smart-8497a09d-bb88-4b53-9412-9abcd1c15a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037668921 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.3037668921 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_mubi/latest

Test location /workspace/coverage/default/0.kmac_sideload.3473048875
Short name T895
Test name
Test status
Simulation time 14205055860 ps
CPU time 215.62 seconds
Started Aug 06 06:00:07 PM PDT 24
Finished Aug 06 06:03:43 PM PDT 24
Peak memory 389568 kb
Host smart-6b8cca25-e722-47e7-938b-3e3c4dd5cb3a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473048875 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.3473048875 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_sideload/latest

Test location /workspace/coverage/default/0.kmac_smoke.1346563925
Short name T891
Test name
Test status
Simulation time 5951202196 ps
CPU time 77.04 seconds
Started Aug 06 06:00:06 PM PDT 24
Finished Aug 06 06:01:24 PM PDT 24
Peak memory 228280 kb
Host smart-4cfe7bac-2e50-48cf-8637-82c9a5b4ef8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346563925 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.1346563925 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_smoke/latest

Test location /workspace/coverage/default/0.kmac_stress_all.4105723961
Short name T547
Test name
Test status
Simulation time 57634609052 ps
CPU time 1295.09 seconds
Started Aug 06 06:00:07 PM PDT 24
Finished Aug 06 06:21:43 PM PDT 24
Peak memory 934696 kb
Host smart-ccfb8bc0-8db4-4403-93fc-60894639573e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4105723961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.4105723961 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_stress_all/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_kmac.4001837452
Short name T407
Test name
Test status
Simulation time 197167773 ps
CPU time 6.9 seconds
Started Aug 06 06:00:09 PM PDT 24
Finished Aug 06 06:00:16 PM PDT 24
Peak memory 219936 kb
Host smart-027318d7-aa2c-4fc2-89ff-13c4d1ae1563
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001837452 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.kmac_test_vectors_kmac.4001837452 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_kmac_xof.3433611944
Short name T808
Test name
Test status
Simulation time 297007519 ps
CPU time 7.29 seconds
Started Aug 06 06:00:11 PM PDT 24
Finished Aug 06 06:00:18 PM PDT 24
Peak memory 227008 kb
Host smart-19eb743c-e881-49fd-a802-98a45c0e70bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433611944 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.kmac_test_vectors_kmac_xof.3433611944 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_224.83030941
Short name T818
Test name
Test status
Simulation time 121671743629 ps
CPU time 2370.65 seconds
Started Aug 06 06:00:13 PM PDT 24
Finished Aug 06 06:39:44 PM PDT 24
Peak memory 1222516 kb
Host smart-76f9195e-47d7-4845-953a-9e7d14afd692
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=83030941 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.83030941 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_256.3930716339
Short name T912
Test name
Test status
Simulation time 113552980412 ps
CPU time 2317.99 seconds
Started Aug 06 06:00:12 PM PDT 24
Finished Aug 06 06:38:51 PM PDT 24
Peak memory 1146936 kb
Host smart-c24c69a0-616d-4f7e-8063-e7b7958554ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3930716339 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.3930716339 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_384.4266023652
Short name T343
Test name
Test status
Simulation time 97059026585 ps
CPU time 2274.78 seconds
Started Aug 06 06:00:07 PM PDT 24
Finished Aug 06 06:38:03 PM PDT 24
Peak memory 2378264 kb
Host smart-4edc51b5-9465-4799-b206-0e774c8b3ae6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4266023652 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.4266023652 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_512.654022141
Short name T736
Test name
Test status
Simulation time 11434522160 ps
CPU time 1409.94 seconds
Started Aug 06 06:00:05 PM PDT 24
Finished Aug 06 06:23:36 PM PDT 24
Peak memory 712092 kb
Host smart-997f9431-2342-4318-a841-dded174e9fc2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=654022141 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.654022141 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/1.kmac_alert_test.3839320310
Short name T502
Test name
Test status
Simulation time 106638609 ps
CPU time 0.79 seconds
Started Aug 06 06:00:24 PM PDT 24
Finished Aug 06 06:00:25 PM PDT 24
Peak memory 218520 kb
Host smart-ba6d4ba3-b550-4b3a-866b-2ef9b4dff96f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839320310 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.3839320310 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_alert_test/latest

Test location /workspace/coverage/default/1.kmac_app.919218603
Short name T715
Test name
Test status
Simulation time 2275681620 ps
CPU time 126.94 seconds
Started Aug 06 06:00:19 PM PDT 24
Finished Aug 06 06:02:26 PM PDT 24
Peak memory 270968 kb
Host smart-41618d0a-4071-4323-9771-d2a283f16753
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919218603 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.919218603 +enable_masking=1
+sw_key_masked=0
Directory /workspace/1.kmac_app/latest

Test location /workspace/coverage/default/1.kmac_app_with_partial_data.2375238260
Short name T197
Test name
Test status
Simulation time 472057233 ps
CPU time 11.53 seconds
Started Aug 06 06:00:23 PM PDT 24
Finished Aug 06 06:00:34 PM PDT 24
Peak memory 235256 kb
Host smart-5184e4c2-72d1-4df7-8669-975a2cec8d74
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375238260 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_par
tial_data.2375238260 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/1.kmac_burst_write.2653649383
Short name T62
Test name
Test status
Simulation time 4371550449 ps
CPU time 424.11 seconds
Started Aug 06 06:00:04 PM PDT 24
Finished Aug 06 06:07:10 PM PDT 24
Peak memory 234308 kb
Host smart-e252e9f2-ee56-436f-bd09-84406773d131
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653649383 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.2653649383
+enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_burst_write/latest

Test location /workspace/coverage/default/1.kmac_edn_timeout_error.1065022986
Short name T72
Test name
Test status
Simulation time 58369212 ps
CPU time 0.96 seconds
Started Aug 06 06:00:19 PM PDT 24
Finished Aug 06 06:00:20 PM PDT 24
Peak memory 218576 kb
Host smart-c4f03cff-43c0-4377-b8ed-1ed908cb9e82
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1065022986 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.1065022986 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_mode_error.2222041836
Short name T809
Test name
Test status
Simulation time 132924517 ps
CPU time 1.22 seconds
Started Aug 06 06:00:19 PM PDT 24
Finished Aug 06 06:00:20 PM PDT 24
Peak memory 218860 kb
Host smart-3a2b4134-df0a-41ea-a47d-3b67e86ffff0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2222041836 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.2222041836 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_ready_error.3485117394
Short name T12
Test name
Test status
Simulation time 16688821490 ps
CPU time 50.68 seconds
Started Aug 06 06:00:24 PM PDT 24
Finished Aug 06 06:01:14 PM PDT 24
Peak memory 227188 kb
Host smart-b735cde0-d5b6-4685-bed8-c9e6b3812937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485117394 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.3485117394 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_refresh.3003126720
Short name T431
Test name
Test status
Simulation time 16244625918 ps
CPU time 314.65 seconds
Started Aug 06 06:00:19 PM PDT 24
Finished Aug 06 06:05:34 PM PDT 24
Peak memory 456992 kb
Host smart-d60bd9ec-9cb0-44a1-a9e0-f421bd82eaf7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003126720 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.30
03126720 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/1.kmac_error.2912423332
Short name T264
Test name
Test status
Simulation time 1388862760 ps
CPU time 9.9 seconds
Started Aug 06 06:00:24 PM PDT 24
Finished Aug 06 06:00:34 PM PDT 24
Peak memory 233548 kb
Host smart-592336bd-5209-42dd-8e62-4542cb306698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912423332 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.2912423332 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_error/latest

Test location /workspace/coverage/default/1.kmac_key_error.1017094039
Short name T702
Test name
Test status
Simulation time 1440079522 ps
CPU time 11.27 seconds
Started Aug 06 06:00:19 PM PDT 24
Finished Aug 06 06:00:31 PM PDT 24
Peak memory 226872 kb
Host smart-65e937f7-3cdc-4e6b-a35d-4851002e7cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017094039 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.1017094039 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_key_error/latest

Test location /workspace/coverage/default/1.kmac_lc_escalation.2418289567
Short name T65
Test name
Test status
Simulation time 36973146 ps
CPU time 1.36 seconds
Started Aug 06 06:00:22 PM PDT 24
Finished Aug 06 06:00:24 PM PDT 24
Peak memory 226940 kb
Host smart-edf55b9b-0191-43f1-adde-cb5da46b7a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418289567 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.2418289567 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/1.kmac_lc_escalation/latest

Test location /workspace/coverage/default/1.kmac_long_msg_and_output.2867367174
Short name T180
Test name
Test status
Simulation time 48064404148 ps
CPU time 858.32 seconds
Started Aug 06 06:00:16 PM PDT 24
Finished Aug 06 06:14:34 PM PDT 24
Peak memory 1085832 kb
Host smart-716703ea-3a7b-4712-9a55-d26e52e24e44
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867367174 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_an
d_output.2867367174 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/1.kmac_mubi.745070813
Short name T58
Test name
Test status
Simulation time 9847522024 ps
CPU time 143.3 seconds
Started Aug 06 06:00:19 PM PDT 24
Finished Aug 06 06:02:43 PM PDT 24
Peak memory 325612 kb
Host smart-70387ccd-2440-4926-a8c5-8aa4a816ee14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745070813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.745070813 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_mubi/latest

Test location /workspace/coverage/default/1.kmac_sideload.2730068325
Short name T627
Test name
Test status
Simulation time 14106013240 ps
CPU time 95.09 seconds
Started Aug 06 06:00:07 PM PDT 24
Finished Aug 06 06:01:42 PM PDT 24
Peak memory 296236 kb
Host smart-fa632c42-f9b9-41ed-a599-9c47284dbe98
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730068325 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.2730068325 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_sideload/latest

Test location /workspace/coverage/default/1.kmac_smoke.3853181374
Short name T509
Test name
Test status
Simulation time 6798705846 ps
CPU time 72.55 seconds
Started Aug 06 06:00:07 PM PDT 24
Finished Aug 06 06:01:20 PM PDT 24
Peak memory 228412 kb
Host smart-b4c639ea-6f63-4242-830a-513a6ad7110f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853181374 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.3853181374 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_smoke/latest

Test location /workspace/coverage/default/1.kmac_stress_all.1527776809
Short name T360
Test name
Test status
Simulation time 1712441822 ps
CPU time 19.95 seconds
Started Aug 06 06:00:23 PM PDT 24
Finished Aug 06 06:00:43 PM PDT 24
Peak memory 243540 kb
Host smart-d16d4164-0fb7-4972-9b4a-29ba144ab668
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1527776809 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.1527776809 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_stress_all/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_kmac.1279984161
Short name T855
Test name
Test status
Simulation time 326616689 ps
CPU time 6.48 seconds
Started Aug 06 06:00:20 PM PDT 24
Finished Aug 06 06:00:27 PM PDT 24
Peak memory 226968 kb
Host smart-e2202f9e-12c0-476c-bc02-f3852ef13839
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279984161 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.kmac_test_vectors_kmac.1279984161 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_kmac_xof.1057283432
Short name T262
Test name
Test status
Simulation time 1391734302 ps
CPU time 6.83 seconds
Started Aug 06 06:00:19 PM PDT 24
Finished Aug 06 06:00:26 PM PDT 24
Peak memory 227072 kb
Host smart-0e4ffc2d-754c-407b-96ee-b387bb338c18
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057283432 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.kmac_test_vectors_kmac_xof.1057283432 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_224.2630462956
Short name T344
Test name
Test status
Simulation time 69187710729 ps
CPU time 2186.33 seconds
Started Aug 06 06:00:06 PM PDT 24
Finished Aug 06 06:36:33 PM PDT 24
Peak memory 1197640 kb
Host smart-95df2955-d6c7-4822-917a-879dfdb474dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2630462956 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.2630462956 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_384.753236881
Short name T244
Test name
Test status
Simulation time 114769890757 ps
CPU time 1892.61 seconds
Started Aug 06 06:00:11 PM PDT 24
Finished Aug 06 06:31:44 PM PDT 24
Peak memory 928764 kb
Host smart-5be0e576-6e65-4d6f-8933-d165ee771f18
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=753236881 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.753236881 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_512.2130834682
Short name T944
Test name
Test status
Simulation time 135513547552 ps
CPU time 1576.85 seconds
Started Aug 06 06:00:09 PM PDT 24
Finished Aug 06 06:26:26 PM PDT 24
Peak memory 1692064 kb
Host smart-256e2f34-91cf-430b-91e2-20015f88336f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2130834682 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.2130834682 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/10.kmac_alert_test.2435210248
Short name T498
Test name
Test status
Simulation time 15733914 ps
CPU time 0.87 seconds
Started Aug 06 06:03:19 PM PDT 24
Finished Aug 06 06:03:20 PM PDT 24
Peak memory 218528 kb
Host smart-718849dc-f768-4bd0-b96e-7a9640282f82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435210248 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.2435210248 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_alert_test/latest

Test location /workspace/coverage/default/10.kmac_app.2300710149
Short name T334
Test name
Test status
Simulation time 134299694 ps
CPU time 7.14 seconds
Started Aug 06 06:03:20 PM PDT 24
Finished Aug 06 06:03:27 PM PDT 24
Peak memory 235284 kb
Host smart-389b102c-bd73-45f7-af1b-b03579272780
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300710149 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.2300710149 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/10.kmac_app/latest

Test location /workspace/coverage/default/10.kmac_burst_write.3790393662
Short name T961
Test name
Test status
Simulation time 18443682788 ps
CPU time 983.2 seconds
Started Aug 06 06:03:02 PM PDT 24
Finished Aug 06 06:19:25 PM PDT 24
Peak memory 254816 kb
Host smart-4b7238d8-6b07-4602-940c-be8eb69103a6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790393662 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.379039366
2 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_burst_write/latest

Test location /workspace/coverage/default/10.kmac_edn_timeout_error.809280549
Short name T266
Test name
Test status
Simulation time 590852840 ps
CPU time 20.74 seconds
Started Aug 06 06:03:20 PM PDT 24
Finished Aug 06 06:03:40 PM PDT 24
Peak memory 235008 kb
Host smart-f2e26f9b-434b-4371-997c-129a8f5af846
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=809280549 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.809280549 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/10.kmac_entropy_mode_error.3291074295
Short name T568
Test name
Test status
Simulation time 83125815 ps
CPU time 1.1 seconds
Started Aug 06 06:03:19 PM PDT 24
Finished Aug 06 06:03:21 PM PDT 24
Peak memory 218752 kb
Host smart-fb84f181-e539-4502-b718-41769d2fb32d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3291074295 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.3291074295 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/10.kmac_entropy_refresh.3785753476
Short name T672
Test name
Test status
Simulation time 37945408675 ps
CPU time 263.57 seconds
Started Aug 06 06:03:19 PM PDT 24
Finished Aug 06 06:07:42 PM PDT 24
Peak memory 397480 kb
Host smart-1334157f-fa0c-49b0-8ba0-3cb376fc658c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785753476 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.3
785753476 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/10.kmac_error.1804955850
Short name T893
Test name
Test status
Simulation time 29097002314 ps
CPU time 260.92 seconds
Started Aug 06 06:03:17 PM PDT 24
Finished Aug 06 06:07:38 PM PDT 24
Peak memory 430320 kb
Host smart-6716f76b-3ae6-405b-9d92-12533956aadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804955850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.1804955850 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_error/latest

Test location /workspace/coverage/default/10.kmac_key_error.965401506
Short name T417
Test name
Test status
Simulation time 6081615779 ps
CPU time 9.04 seconds
Started Aug 06 06:03:17 PM PDT 24
Finished Aug 06 06:03:26 PM PDT 24
Peak memory 227044 kb
Host smart-5aefde23-1acb-4385-9e2f-f8b3ff1eceae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965401506 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.965401506 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_key_error/latest

Test location /workspace/coverage/default/10.kmac_lc_escalation.4083434732
Short name T782
Test name
Test status
Simulation time 155269901 ps
CPU time 1.46 seconds
Started Aug 06 06:03:19 PM PDT 24
Finished Aug 06 06:03:20 PM PDT 24
Peak memory 226996 kb
Host smart-1fee97e4-1f23-4e79-b0b6-b9730c798899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083434732 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.4083434732 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/10.kmac_lc_escalation/latest

Test location /workspace/coverage/default/10.kmac_long_msg_and_output.3040395102
Short name T305
Test name
Test status
Simulation time 65561750783 ps
CPU time 2089.55 seconds
Started Aug 06 06:03:02 PM PDT 24
Finished Aug 06 06:37:52 PM PDT 24
Peak memory 1198784 kb
Host smart-df4d7e10-b122-4257-b341-32b62ba7f5fb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040395102 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_a
nd_output.3040395102 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/10.kmac_sideload.4052641462
Short name T198
Test name
Test status
Simulation time 9020468160 ps
CPU time 236.89 seconds
Started Aug 06 06:03:03 PM PDT 24
Finished Aug 06 06:07:00 PM PDT 24
Peak memory 419852 kb
Host smart-4c847789-a281-4493-9277-2ca32f471b93
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052641462 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.4052641462 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_sideload/latest

Test location /workspace/coverage/default/10.kmac_smoke.452297165
Short name T849
Test name
Test status
Simulation time 16378206968 ps
CPU time 19.81 seconds
Started Aug 06 06:03:02 PM PDT 24
Finished Aug 06 06:03:22 PM PDT 24
Peak memory 227092 kb
Host smart-0c5e4521-5599-47d8-8bdf-7c2494013780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452297165 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.452297165 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_smoke/latest

Test location /workspace/coverage/default/10.kmac_stress_all.428387749
Short name T193
Test name
Test status
Simulation time 8814870660 ps
CPU time 264.65 seconds
Started Aug 06 06:03:18 PM PDT 24
Finished Aug 06 06:07:43 PM PDT 24
Peak memory 349888 kb
Host smart-a2cab53a-fd0b-4fba-8968-809cbb98e795
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=428387749 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.428387749 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_stress_all/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_kmac.2024812768
Short name T578
Test name
Test status
Simulation time 275444759 ps
CPU time 6.11 seconds
Started Aug 06 06:03:18 PM PDT 24
Finished Aug 06 06:03:25 PM PDT 24
Peak memory 227008 kb
Host smart-98dfbc6c-d891-4a33-b171-c99f2a13c720
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024812768 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.kmac_test_vectors_kmac.2024812768 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_kmac_xof.15564502
Short name T263
Test name
Test status
Simulation time 1489774809 ps
CPU time 6.02 seconds
Started Aug 06 06:03:18 PM PDT 24
Finished Aug 06 06:03:24 PM PDT 24
Peak memory 219856 kb
Host smart-7e276225-0a0a-4a38-8a6d-430b5ac7eeb0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15564502 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.kmac_test_vectors_kmac_xof.15564502 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_224.3142583162
Short name T121
Test name
Test status
Simulation time 44172715468 ps
CPU time 2249.17 seconds
Started Aug 06 06:03:02 PM PDT 24
Finished Aug 06 06:40:31 PM PDT 24
Peak memory 1197604 kb
Host smart-edfefd5c-fe83-4553-bc3b-c1760afd181e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3142583162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_224.3142583162 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_256.899374105
Short name T723
Test name
Test status
Simulation time 19850302436 ps
CPU time 2166.92 seconds
Started Aug 06 06:03:02 PM PDT 24
Finished Aug 06 06:39:09 PM PDT 24
Peak memory 1160852 kb
Host smart-6ddda338-7ffd-4fcd-a1f2-df2e48f8cfe1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=899374105 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_256.899374105 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_384.2302546530
Short name T875
Test name
Test status
Simulation time 130916144253 ps
CPU time 2375.9 seconds
Started Aug 06 06:03:03 PM PDT 24
Finished Aug 06 06:42:39 PM PDT 24
Peak memory 2372324 kb
Host smart-ce19a876-6aff-4034-8142-916694b323ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2302546530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_384.2302546530 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_512.625482761
Short name T513
Test name
Test status
Simulation time 186762350382 ps
CPU time 1800.06 seconds
Started Aug 06 06:03:02 PM PDT 24
Finished Aug 06 06:33:02 PM PDT 24
Peak memory 1746316 kb
Host smart-5e6b1a81-1446-4243-91ff-ed79d9913c16
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=625482761 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_512.625482761 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_shake_256.40100782
Short name T166
Test name
Test status
Simulation time 215347006954 ps
CPU time 5640.73 seconds
Started Aug 06 06:03:19 PM PDT 24
Finished Aug 06 07:37:21 PM PDT 24
Peak memory 2235184 kb
Host smart-c3384fb6-60ad-4149-86bd-503afcb3d414
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=40100782 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_shake_256.40100782 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/11.kmac_alert_test.3926716311
Short name T384
Test name
Test status
Simulation time 16767896 ps
CPU time 0.82 seconds
Started Aug 06 06:03:31 PM PDT 24
Finished Aug 06 06:03:32 PM PDT 24
Peak memory 218568 kb
Host smart-2e4da859-5fde-4cca-a78e-c7b129820d34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926716311 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.3926716311 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_alert_test/latest

Test location /workspace/coverage/default/11.kmac_app.509707107
Short name T550
Test name
Test status
Simulation time 2997404306 ps
CPU time 28.79 seconds
Started Aug 06 06:03:31 PM PDT 24
Finished Aug 06 06:04:00 PM PDT 24
Peak memory 241100 kb
Host smart-088777bb-b76f-49a3-afe8-480dc86dd7fd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509707107 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.509707107 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/11.kmac_app/latest

Test location /workspace/coverage/default/11.kmac_burst_write.2477375041
Short name T927
Test name
Test status
Simulation time 103094798347 ps
CPU time 1186.01 seconds
Started Aug 06 06:03:17 PM PDT 24
Finished Aug 06 06:23:03 PM PDT 24
Peak memory 256388 kb
Host smart-8e557c95-98ec-435c-ba38-88962745b54d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477375041 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.247737504
1 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_burst_write/latest

Test location /workspace/coverage/default/11.kmac_edn_timeout_error.533866470
Short name T374
Test name
Test status
Simulation time 89882666 ps
CPU time 1.25 seconds
Started Aug 06 06:03:30 PM PDT 24
Finished Aug 06 06:03:31 PM PDT 24
Peak memory 218772 kb
Host smart-7a8544c9-4fde-42f5-8886-af4234955237
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=533866470 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.533866470 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/11.kmac_entropy_mode_error.1313562832
Short name T200
Test name
Test status
Simulation time 4412953467 ps
CPU time 32.03 seconds
Started Aug 06 06:03:31 PM PDT 24
Finished Aug 06 06:04:03 PM PDT 24
Peak memory 226960 kb
Host smart-f45b9b62-7ca3-4a3c-afc0-6a650eb45383
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1313562832 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.1313562832 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/11.kmac_entropy_refresh.2995841901
Short name T394
Test name
Test status
Simulation time 7839810630 ps
CPU time 39.8 seconds
Started Aug 06 06:03:31 PM PDT 24
Finished Aug 06 06:04:11 PM PDT 24
Peak memory 243592 kb
Host smart-c4f8e912-b3ed-41b4-9ef2-93c32c9d36fc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995841901 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.2
995841901 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/11.kmac_error.207282419
Short name T290
Test name
Test status
Simulation time 42440103557 ps
CPU time 578.47 seconds
Started Aug 06 06:03:30 PM PDT 24
Finished Aug 06 06:13:09 PM PDT 24
Peak memory 660592 kb
Host smart-1ca29da4-bf29-4b18-be0b-d7200199fffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207282419 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.207282419 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_error/latest

Test location /workspace/coverage/default/11.kmac_key_error.2929492708
Short name T221
Test name
Test status
Simulation time 5227070367 ps
CPU time 6.45 seconds
Started Aug 06 06:03:29 PM PDT 24
Finished Aug 06 06:03:36 PM PDT 24
Peak memory 226900 kb
Host smart-7852b849-b476-4233-b4bd-2bc0e5465f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929492708 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.2929492708 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_key_error/latest

Test location /workspace/coverage/default/11.kmac_lc_escalation.3687630913
Short name T53
Test name
Test status
Simulation time 727391511 ps
CPU time 11.93 seconds
Started Aug 06 06:03:31 PM PDT 24
Finished Aug 06 06:03:43 PM PDT 24
Peak memory 235264 kb
Host smart-f48a5639-a007-46c7-9a9b-76a6dc9f56ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687630913 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.3687630913 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/11.kmac_lc_escalation/latest

Test location /workspace/coverage/default/11.kmac_long_msg_and_output.951184307
Short name T687
Test name
Test status
Simulation time 124181715309 ps
CPU time 1200.64 seconds
Started Aug 06 06:03:19 PM PDT 24
Finished Aug 06 06:23:20 PM PDT 24
Peak memory 1408780 kb
Host smart-cb1329ab-5caa-4f5e-91d8-20cf14f6bc76
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951184307 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_an
d_output.951184307 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/11.kmac_sideload.1059341235
Short name T190
Test name
Test status
Simulation time 13060359582 ps
CPU time 392.63 seconds
Started Aug 06 06:03:19 PM PDT 24
Finished Aug 06 06:09:52 PM PDT 24
Peak memory 517528 kb
Host smart-d51fffe5-ebb4-433c-857c-4262fa62532e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059341235 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.1059341235 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_sideload/latest

Test location /workspace/coverage/default/11.kmac_smoke.3510974019
Short name T30
Test name
Test status
Simulation time 1553027456 ps
CPU time 27.55 seconds
Started Aug 06 06:03:20 PM PDT 24
Finished Aug 06 06:03:48 PM PDT 24
Peak memory 223144 kb
Host smart-dd11ec3b-b6ca-41e7-9c27-1ac82af460ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510974019 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.3510974019 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_smoke/latest

Test location /workspace/coverage/default/11.kmac_stress_all.3981080215
Short name T765
Test name
Test status
Simulation time 58958590375 ps
CPU time 2413.52 seconds
Started Aug 06 06:03:30 PM PDT 24
Finished Aug 06 06:43:44 PM PDT 24
Peak memory 1300176 kb
Host smart-61c71b01-70e8-40bc-be74-000cd8dc1bd6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3981080215 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.3981080215 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_stress_all/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_kmac.3093890350
Short name T219
Test name
Test status
Simulation time 380591608 ps
CPU time 5.96 seconds
Started Aug 06 06:03:32 PM PDT 24
Finished Aug 06 06:03:38 PM PDT 24
Peak memory 227012 kb
Host smart-7c2a0d38-1e05-4091-b1bf-71cfa11fe933
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093890350 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.kmac_test_vectors_kmac.3093890350 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_kmac_xof.1201506472
Short name T250
Test name
Test status
Simulation time 218989457 ps
CPU time 6.22 seconds
Started Aug 06 06:03:32 PM PDT 24
Finished Aug 06 06:03:38 PM PDT 24
Peak memory 219152 kb
Host smart-a8eeb6db-0ca9-4a4b-874a-c92b1a50b6bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201506472 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.kmac_test_vectors_kmac_xof.1201506472 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_224.2547021852
Short name T204
Test name
Test status
Simulation time 20443454949 ps
CPU time 2215.58 seconds
Started Aug 06 06:03:22 PM PDT 24
Finished Aug 06 06:40:18 PM PDT 24
Peak memory 1170464 kb
Host smart-53069e8e-f92a-4678-a174-d32773ff9a94
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2547021852 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_224.2547021852 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_384.446454926
Short name T271
Test name
Test status
Simulation time 187437037966 ps
CPU time 2427.03 seconds
Started Aug 06 06:03:20 PM PDT 24
Finished Aug 06 06:43:47 PM PDT 24
Peak memory 2357156 kb
Host smart-58c9c5cf-c924-4384-a287-ad13d2eb82cf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=446454926 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_384.446454926 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_512.176354075
Short name T898
Test name
Test status
Simulation time 10646776195 ps
CPU time 1346 seconds
Started Aug 06 06:03:31 PM PDT 24
Finished Aug 06 06:25:57 PM PDT 24
Peak memory 705788 kb
Host smart-87787ef1-bbf0-49fd-a1be-01d2cb8edc47
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=176354075 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_512.176354075 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_shake_256.1522093405
Short name T231
Test name
Test status
Simulation time 220518549865 ps
CPU time 5682.21 seconds
Started Aug 06 06:03:31 PM PDT 24
Finished Aug 06 07:38:14 PM PDT 24
Peak memory 2254384 kb
Host smart-ff408a64-9d9e-4aac-8006-ce7dcaaa6f61
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1522093405 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_256.1522093405 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/12.kmac_alert_test.1912296518
Short name T832
Test name
Test status
Simulation time 20958538 ps
CPU time 0.87 seconds
Started Aug 06 06:04:00 PM PDT 24
Finished Aug 06 06:04:01 PM PDT 24
Peak memory 218572 kb
Host smart-2645d9d1-c9d3-430b-ae80-e4f25c8f7f32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912296518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.1912296518 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_alert_test/latest

Test location /workspace/coverage/default/12.kmac_app.2483997269
Short name T902
Test name
Test status
Simulation time 105110964237 ps
CPU time 339.56 seconds
Started Aug 06 06:03:50 PM PDT 24
Finished Aug 06 06:09:29 PM PDT 24
Peak memory 443180 kb
Host smart-1955fb9e-b0da-4edb-95ec-4a8e0d61b2f9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483997269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.2483997269 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/12.kmac_app/latest

Test location /workspace/coverage/default/12.kmac_burst_write.1340790235
Short name T131
Test name
Test status
Simulation time 7823423922 ps
CPU time 183.22 seconds
Started Aug 06 06:03:31 PM PDT 24
Finished Aug 06 06:06:35 PM PDT 24
Peak memory 230132 kb
Host smart-605591d5-cbf3-4024-bf08-db46c365891d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340790235 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.134079023
5 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_burst_write/latest

Test location /workspace/coverage/default/12.kmac_edn_timeout_error.2954539865
Short name T224
Test name
Test status
Simulation time 1425862160 ps
CPU time 41.76 seconds
Started Aug 06 06:03:46 PM PDT 24
Finished Aug 06 06:04:27 PM PDT 24
Peak memory 228364 kb
Host smart-bb13b463-a69e-488c-91c4-fe206bdf450f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2954539865 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.2954539865 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/12.kmac_entropy_mode_error.3878075034
Short name T411
Test name
Test status
Simulation time 37126653 ps
CPU time 1.11 seconds
Started Aug 06 06:03:42 PM PDT 24
Finished Aug 06 06:03:43 PM PDT 24
Peak memory 218860 kb
Host smart-cd9d1661-31db-4995-8551-148a3542c5f7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3878075034 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.3878075034 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/12.kmac_entropy_refresh.204688578
Short name T75
Test name
Test status
Simulation time 13110319705 ps
CPU time 270.77 seconds
Started Aug 06 06:03:44 PM PDT 24
Finished Aug 06 06:08:15 PM PDT 24
Peak memory 437084 kb
Host smart-e49e34bd-b409-45b9-bae7-98fef2a5b0e4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204688578 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.20
4688578 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/12.kmac_key_error.4132266587
Short name T804
Test name
Test status
Simulation time 7266316368 ps
CPU time 8.1 seconds
Started Aug 06 06:03:45 PM PDT 24
Finished Aug 06 06:03:53 PM PDT 24
Peak memory 227016 kb
Host smart-a187257f-f317-4add-8bb0-28d32cb03056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132266587 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.4132266587 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_key_error/latest

Test location /workspace/coverage/default/12.kmac_long_msg_and_output.730780311
Short name T552
Test name
Test status
Simulation time 48941175811 ps
CPU time 1142.53 seconds
Started Aug 06 06:03:32 PM PDT 24
Finished Aug 06 06:22:34 PM PDT 24
Peak memory 1304704 kb
Host smart-274c2708-beef-47e0-82c0-540cecc89444
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730780311 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_an
d_output.730780311 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/12.kmac_sideload.3069531987
Short name T919
Test name
Test status
Simulation time 5236572947 ps
CPU time 165.83 seconds
Started Aug 06 06:03:32 PM PDT 24
Finished Aug 06 06:06:17 PM PDT 24
Peak memory 357600 kb
Host smart-20f1e0dd-500c-40f0-8824-815077788a34
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069531987 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.3069531987 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_sideload/latest

Test location /workspace/coverage/default/12.kmac_smoke.77661886
Short name T483
Test name
Test status
Simulation time 522237882 ps
CPU time 20.45 seconds
Started Aug 06 06:03:32 PM PDT 24
Finished Aug 06 06:03:52 PM PDT 24
Peak memory 227064 kb
Host smart-ad0a5cf2-05b1-4bb3-ad78-29243167c0ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77661886 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.77661886 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_smoke/latest

Test location /workspace/coverage/default/12.kmac_stress_all.1037432915
Short name T275
Test name
Test status
Simulation time 174047460394 ps
CPU time 1108.28 seconds
Started Aug 06 06:03:46 PM PDT 24
Finished Aug 06 06:22:14 PM PDT 24
Peak memory 488596 kb
Host smart-8cb43828-6243-44e3-aea5-868b111bbceb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1037432915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.1037432915 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_stress_all/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_kmac.2724303767
Short name T945
Test name
Test status
Simulation time 737663610 ps
CPU time 6.5 seconds
Started Aug 06 06:03:46 PM PDT 24
Finished Aug 06 06:03:52 PM PDT 24
Peak memory 227128 kb
Host smart-178ccf49-eb9c-4351-ae4e-3b6abfcaf9a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724303767 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.kmac_test_vectors_kmac.2724303767 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_kmac_xof.1635500986
Short name T758
Test name
Test status
Simulation time 865585982 ps
CPU time 7.34 seconds
Started Aug 06 06:03:50 PM PDT 24
Finished Aug 06 06:03:58 PM PDT 24
Peak memory 227072 kb
Host smart-2e219002-194f-4b30-b770-7fb4bce9356e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635500986 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.kmac_test_vectors_kmac_xof.1635500986 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_224.4236039786
Short name T585
Test name
Test status
Simulation time 87242219253 ps
CPU time 3349.18 seconds
Started Aug 06 06:03:44 PM PDT 24
Finished Aug 06 06:59:34 PM PDT 24
Peak memory 3245524 kb
Host smart-7a7e1474-0fdc-4201-a3dd-aff41091939b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4236039786 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_224.4236039786 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_256.3713549599
Short name T881
Test name
Test status
Simulation time 180991831187 ps
CPU time 3475.37 seconds
Started Aug 06 06:03:45 PM PDT 24
Finished Aug 06 07:01:41 PM PDT 24
Peak memory 3001532 kb
Host smart-2d454aeb-90ea-464d-848f-5760be0d63f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3713549599 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_256.3713549599 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_384.2081867763
Short name T436
Test name
Test status
Simulation time 62730676053 ps
CPU time 1757.07 seconds
Started Aug 06 06:03:50 PM PDT 24
Finished Aug 06 06:33:07 PM PDT 24
Peak memory 937772 kb
Host smart-f2199802-0725-4bfa-9d72-7150e75c5dae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2081867763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_384.2081867763 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_512.481929648
Short name T783
Test name
Test status
Simulation time 133501935695 ps
CPU time 1616.09 seconds
Started Aug 06 06:03:45 PM PDT 24
Finished Aug 06 06:30:41 PM PDT 24
Peak memory 1720304 kb
Host smart-bcb50f96-c0a8-4d71-8161-91d215509e38
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=481929648 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_512.481929648 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_shake_128.866158831
Short name T721
Test name
Test status
Simulation time 119808692531 ps
CPU time 6587.74 seconds
Started Aug 06 06:03:45 PM PDT 24
Finished Aug 06 07:53:34 PM PDT 24
Peak memory 2737320 kb
Host smart-f47fe138-8cd6-4900-bf9e-e9909ba1c8dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=866158831 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_128.866158831 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/13.kmac_alert_test.2159914700
Short name T105
Test name
Test status
Simulation time 46180200 ps
CPU time 0.84 seconds
Started Aug 06 06:04:28 PM PDT 24
Finished Aug 06 06:04:29 PM PDT 24
Peak memory 218440 kb
Host smart-a7a82eb3-1e4f-4eab-97b6-294b3396344c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159914700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.2159914700 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_alert_test/latest

Test location /workspace/coverage/default/13.kmac_app.2139770207
Short name T8
Test name
Test status
Simulation time 6925121434 ps
CPU time 91.88 seconds
Started Aug 06 06:04:26 PM PDT 24
Finished Aug 06 06:05:58 PM PDT 24
Peak memory 252520 kb
Host smart-48a5e587-3470-412d-89c0-b8defcee263a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139770207 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.2139770207 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/13.kmac_app/latest

Test location /workspace/coverage/default/13.kmac_burst_write.425602457
Short name T182
Test name
Test status
Simulation time 6752563101 ps
CPU time 682.69 seconds
Started Aug 06 06:04:01 PM PDT 24
Finished Aug 06 06:15:24 PM PDT 24
Peak memory 243500 kb
Host smart-9e545fac-3dac-49d9-9412-84f3c0e99aed
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425602457 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.425602457
+enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_burst_write/latest

Test location /workspace/coverage/default/13.kmac_edn_timeout_error.853307299
Short name T905
Test name
Test status
Simulation time 34488195 ps
CPU time 1.07 seconds
Started Aug 06 06:04:26 PM PDT 24
Finished Aug 06 06:04:27 PM PDT 24
Peak memory 218772 kb
Host smart-cc975020-cecc-446e-aed0-a5ba240debf4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=853307299 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.853307299 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/13.kmac_entropy_mode_error.2500430082
Short name T238
Test name
Test status
Simulation time 144757668 ps
CPU time 1.14 seconds
Started Aug 06 06:04:26 PM PDT 24
Finished Aug 06 06:04:27 PM PDT 24
Peak memory 218732 kb
Host smart-2d3e8f09-acf6-4c1c-8505-b2c9a8b6516f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2500430082 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.2500430082 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/13.kmac_entropy_refresh.304336835
Short name T69
Test name
Test status
Simulation time 74299998850 ps
CPU time 405.45 seconds
Started Aug 06 06:04:28 PM PDT 24
Finished Aug 06 06:11:14 PM PDT 24
Peak memory 478704 kb
Host smart-4e3d1033-612f-43ea-bc6f-f5ffa21652fb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304336835 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.30
4336835 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/13.kmac_error.3087951043
Short name T141
Test name
Test status
Simulation time 83831254562 ps
CPU time 144.31 seconds
Started Aug 06 06:04:26 PM PDT 24
Finished Aug 06 06:06:51 PM PDT 24
Peak memory 337356 kb
Host smart-63712086-f80f-400a-9eda-c20fb98bc5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087951043 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.3087951043 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_error/latest

Test location /workspace/coverage/default/13.kmac_key_error.761646559
Short name T720
Test name
Test status
Simulation time 1848661610 ps
CPU time 7.78 seconds
Started Aug 06 06:04:25 PM PDT 24
Finished Aug 06 06:04:33 PM PDT 24
Peak memory 226828 kb
Host smart-88628239-26f8-427e-853f-b691cb19504d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761646559 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.761646559 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_key_error/latest

Test location /workspace/coverage/default/13.kmac_lc_escalation.2023699026
Short name T396
Test name
Test status
Simulation time 59974994 ps
CPU time 1.37 seconds
Started Aug 06 06:04:27 PM PDT 24
Finished Aug 06 06:04:29 PM PDT 24
Peak memory 226984 kb
Host smart-49bbace9-80ae-46a8-bbf3-fc61aa51204e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023699026 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.2023699026 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/13.kmac_lc_escalation/latest

Test location /workspace/coverage/default/13.kmac_long_msg_and_output.590439211
Short name T928
Test name
Test status
Simulation time 17881535572 ps
CPU time 2278.33 seconds
Started Aug 06 06:04:01 PM PDT 24
Finished Aug 06 06:42:00 PM PDT 24
Peak memory 1257076 kb
Host smart-df574fe8-c615-4d65-baaf-f50065a77efa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590439211 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_an
d_output.590439211 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/13.kmac_sideload.3015168929
Short name T667
Test name
Test status
Simulation time 118679537498 ps
CPU time 499.58 seconds
Started Aug 06 06:04:01 PM PDT 24
Finished Aug 06 06:12:21 PM PDT 24
Peak memory 562216 kb
Host smart-8c243cad-70f5-4e1b-950d-5040d38e0ff8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015168929 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.3015168929 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_sideload/latest

Test location /workspace/coverage/default/13.kmac_smoke.166287396
Short name T484
Test name
Test status
Simulation time 4788896444 ps
CPU time 60.38 seconds
Started Aug 06 06:04:00 PM PDT 24
Finished Aug 06 06:05:00 PM PDT 24
Peak memory 226980 kb
Host smart-4e507246-4377-43a9-aacb-15fac3034341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166287396 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.166287396 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_smoke/latest

Test location /workspace/coverage/default/13.kmac_stress_all.875652042
Short name T950
Test name
Test status
Simulation time 17979935681 ps
CPU time 1348.27 seconds
Started Aug 06 06:04:25 PM PDT 24
Finished Aug 06 06:26:54 PM PDT 24
Peak memory 700004 kb
Host smart-5b66edda-1c86-401a-afc3-fd4f2ae44895
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=875652042 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.875652042 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_stress_all/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_kmac.1599757721
Short name T705
Test name
Test status
Simulation time 723407282 ps
CPU time 6.04 seconds
Started Aug 06 06:04:01 PM PDT 24
Finished Aug 06 06:04:07 PM PDT 24
Peak memory 219832 kb
Host smart-10689ec2-b00f-4cbe-9447-daa6467b998b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599757721 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.kmac_test_vectors_kmac.1599757721 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_kmac_xof.2308737871
Short name T492
Test name
Test status
Simulation time 227301729 ps
CPU time 5.48 seconds
Started Aug 06 06:04:28 PM PDT 24
Finished Aug 06 06:04:33 PM PDT 24
Peak memory 226924 kb
Host smart-7a1c67ef-05a9-40cc-9f38-0df6ae3805e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308737871 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.kmac_test_vectors_kmac_xof.2308737871 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_224.3495649165
Short name T854
Test name
Test status
Simulation time 19932885518 ps
CPU time 2157.42 seconds
Started Aug 06 06:04:02 PM PDT 24
Finished Aug 06 06:40:00 PM PDT 24
Peak memory 1166556 kb
Host smart-89754d6f-2d30-498c-a1f3-12c6e8104013
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3495649165 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_224.3495649165 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_256.66717164
Short name T588
Test name
Test status
Simulation time 77884128186 ps
CPU time 2168.19 seconds
Started Aug 06 06:04:01 PM PDT 24
Finished Aug 06 06:40:10 PM PDT 24
Peak memory 1145800 kb
Host smart-9c14de5f-b626-4409-b732-7649a7af85be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=66717164 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_256.66717164 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_384.829043073
Short name T329
Test name
Test status
Simulation time 292773170227 ps
CPU time 2523.65 seconds
Started Aug 06 06:04:02 PM PDT 24
Finished Aug 06 06:46:06 PM PDT 24
Peak memory 2366328 kb
Host smart-a29f5460-2768-4b4d-b29e-04aed4d7c974
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=829043073 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_384.829043073 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_512.3430054699
Short name T623
Test name
Test status
Simulation time 48913781753 ps
CPU time 1818.12 seconds
Started Aug 06 06:04:01 PM PDT 24
Finished Aug 06 06:34:20 PM PDT 24
Peak memory 1722624 kb
Host smart-dd0d4b84-c5c3-44c1-b64c-0410e3a0467b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3430054699 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_512.3430054699 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_shake_256.520158725
Short name T424
Test name
Test status
Simulation time 207638157359 ps
CPU time 5044.92 seconds
Started Aug 06 06:04:03 PM PDT 24
Finished Aug 06 07:28:09 PM PDT 24
Peak memory 2186432 kb
Host smart-dcc323bd-2d9c-4a21-a835-faf95a1480d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=520158725 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_256.520158725 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/14.kmac_alert_test.2634627880
Short name T824
Test name
Test status
Simulation time 40680212 ps
CPU time 0.82 seconds
Started Aug 06 06:04:44 PM PDT 24
Finished Aug 06 06:04:45 PM PDT 24
Peak memory 218492 kb
Host smart-d17a0d2f-a736-41da-b567-767ff760ac46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634627880 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.2634627880 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_alert_test/latest

Test location /workspace/coverage/default/14.kmac_app.2564208650
Short name T762
Test name
Test status
Simulation time 15729474056 ps
CPU time 235.68 seconds
Started Aug 06 06:04:26 PM PDT 24
Finished Aug 06 06:08:22 PM PDT 24
Peak memory 393660 kb
Host smart-5871c26d-da04-4513-a768-b660967118ed
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564208650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.2564208650 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/14.kmac_app/latest

Test location /workspace/coverage/default/14.kmac_burst_write.3762757318
Short name T700
Test name
Test status
Simulation time 1866332726 ps
CPU time 107.11 seconds
Started Aug 06 06:04:26 PM PDT 24
Finished Aug 06 06:06:13 PM PDT 24
Peak memory 235488 kb
Host smart-2dddce3d-a89e-46fe-9795-96f2502e2d17
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762757318 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.376275731
8 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_burst_write/latest

Test location /workspace/coverage/default/14.kmac_edn_timeout_error.1478742254
Short name T704
Test name
Test status
Simulation time 257675681 ps
CPU time 1.13 seconds
Started Aug 06 06:04:52 PM PDT 24
Finished Aug 06 06:04:53 PM PDT 24
Peak memory 218816 kb
Host smart-b5116a8c-ead4-4494-8f06-329a42028e53
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1478742254 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.1478742254 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/14.kmac_entropy_mode_error.2763588608
Short name T975
Test name
Test status
Simulation time 71829867 ps
CPU time 0.89 seconds
Started Aug 06 06:04:44 PM PDT 24
Finished Aug 06 06:04:45 PM PDT 24
Peak memory 218496 kb
Host smart-7a8f1811-2112-4877-a982-e6a5e6a17d56
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2763588608 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.2763588608 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/14.kmac_entropy_refresh.1926824336
Short name T530
Test name
Test status
Simulation time 18854128824 ps
CPU time 218.67 seconds
Started Aug 06 06:04:27 PM PDT 24
Finished Aug 06 06:08:06 PM PDT 24
Peak memory 379468 kb
Host smart-4db47d4d-8ded-4e0e-99af-d5bf634b9038
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926824336 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.1
926824336 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/14.kmac_error.1798145692
Short name T331
Test name
Test status
Simulation time 11151225924 ps
CPU time 481.94 seconds
Started Aug 06 06:04:28 PM PDT 24
Finished Aug 06 06:12:30 PM PDT 24
Peak memory 394964 kb
Host smart-c2d10fc6-5be5-4fd9-8def-62f537b70192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798145692 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.1798145692 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_error/latest

Test location /workspace/coverage/default/14.kmac_key_error.1712879750
Short name T712
Test name
Test status
Simulation time 499237574 ps
CPU time 5.67 seconds
Started Aug 06 06:04:52 PM PDT 24
Finished Aug 06 06:04:58 PM PDT 24
Peak memory 226840 kb
Host smart-5eba21fd-48df-44e5-a0fd-e2eecc3cf91c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712879750 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.1712879750 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_key_error/latest

Test location /workspace/coverage/default/14.kmac_lc_escalation.3258275761
Short name T366
Test name
Test status
Simulation time 45668382 ps
CPU time 1.37 seconds
Started Aug 06 06:04:44 PM PDT 24
Finished Aug 06 06:04:45 PM PDT 24
Peak memory 226896 kb
Host smart-6c2841f5-8941-42d3-8560-bf7a4e157b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258275761 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.3258275761 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/14.kmac_lc_escalation/latest

Test location /workspace/coverage/default/14.kmac_sideload.2192858308
Short name T308
Test name
Test status
Simulation time 15490977357 ps
CPU time 564.31 seconds
Started Aug 06 06:04:27 PM PDT 24
Finished Aug 06 06:13:52 PM PDT 24
Peak memory 618988 kb
Host smart-a8ca49cc-10b8-4e93-93ba-58d36e3cbcc5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192858308 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.2192858308 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_sideload/latest

Test location /workspace/coverage/default/14.kmac_smoke.2083396293
Short name T957
Test name
Test status
Simulation time 3764177318 ps
CPU time 72.17 seconds
Started Aug 06 06:04:26 PM PDT 24
Finished Aug 06 06:05:38 PM PDT 24
Peak memory 227196 kb
Host smart-73893680-98d1-4992-9ba5-73f623309537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083396293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.2083396293 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_smoke/latest

Test location /workspace/coverage/default/14.kmac_stress_all.4181162013
Short name T375
Test name
Test status
Simulation time 1295085584663 ps
CPU time 2871.16 seconds
Started Aug 06 06:04:43 PM PDT 24
Finished Aug 06 06:52:35 PM PDT 24
Peak memory 1516448 kb
Host smart-bab39965-6827-4cba-9d3c-ee2a376dda84
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4181162013 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.4181162013 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_stress_all/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_kmac.1169837239
Short name T236
Test name
Test status
Simulation time 128802480 ps
CPU time 5.69 seconds
Started Aug 06 06:04:26 PM PDT 24
Finished Aug 06 06:04:32 PM PDT 24
Peak memory 219052 kb
Host smart-51365c1c-8a3a-4c9f-bb9f-8d427684ffd8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169837239 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.kmac_test_vectors_kmac.1169837239 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_kmac_xof.4171214221
Short name T272
Test name
Test status
Simulation time 385223211 ps
CPU time 6.18 seconds
Started Aug 06 06:04:25 PM PDT 24
Finished Aug 06 06:04:31 PM PDT 24
Peak memory 227060 kb
Host smart-5fb84dc8-1d7a-4e7b-baa3-978ae1c43b5c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171214221 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.kmac_test_vectors_kmac_xof.4171214221 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_224.2316569790
Short name T439
Test name
Test status
Simulation time 86175533999 ps
CPU time 2138.92 seconds
Started Aug 06 06:04:25 PM PDT 24
Finished Aug 06 06:40:05 PM PDT 24
Peak memory 1202604 kb
Host smart-eed93516-d950-40db-a479-84f1f70d8ac5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2316569790 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_224.2316569790 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_256.470673211
Short name T240
Test name
Test status
Simulation time 74111577878 ps
CPU time 2214.24 seconds
Started Aug 06 06:04:27 PM PDT 24
Finished Aug 06 06:41:22 PM PDT 24
Peak memory 1098048 kb
Host smart-f19d4530-6135-4b5a-9e06-a93bfa377f53
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=470673211 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_256.470673211 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_384.3399406965
Short name T307
Test name
Test status
Simulation time 134156092801 ps
CPU time 1587.77 seconds
Started Aug 06 06:04:27 PM PDT 24
Finished Aug 06 06:30:55 PM PDT 24
Peak memory 916812 kb
Host smart-ce694b88-50bd-4e11-8f4d-06538e3d9ae8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3399406965 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_384.3399406965 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_512.1061747995
Short name T619
Test name
Test status
Simulation time 140411754819 ps
CPU time 1596.73 seconds
Started Aug 06 06:04:26 PM PDT 24
Finished Aug 06 06:31:03 PM PDT 24
Peak memory 1742704 kb
Host smart-a1539dc4-4b25-49b2-9798-8eebe9ab7b33
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1061747995 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_512.1061747995 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_shake_256.128684983
Short name T726
Test name
Test status
Simulation time 211122137340 ps
CPU time 5181.77 seconds
Started Aug 06 06:04:26 PM PDT 24
Finished Aug 06 07:30:49 PM PDT 24
Peak memory 2229088 kb
Host smart-e8d9bbae-ecf5-419c-adb5-7b188cd490b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=128684983 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_256.128684983 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/15.kmac_alert_test.1988078995
Short name T557
Test name
Test status
Simulation time 97899404 ps
CPU time 0.85 seconds
Started Aug 06 06:05:04 PM PDT 24
Finished Aug 06 06:05:05 PM PDT 24
Peak memory 218560 kb
Host smart-5dfe09ca-4f87-4f60-b449-08060a4329ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988078995 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.1988078995 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_alert_test/latest

Test location /workspace/coverage/default/15.kmac_app.3151641007
Short name T186
Test name
Test status
Simulation time 1451509572 ps
CPU time 42.79 seconds
Started Aug 06 06:04:52 PM PDT 24
Finished Aug 06 06:05:35 PM PDT 24
Peak memory 251452 kb
Host smart-abf3c46f-14c7-406a-a190-b1dd16cb6e90
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151641007 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.3151641007 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/15.kmac_app/latest

Test location /workspace/coverage/default/15.kmac_burst_write.3713859559
Short name T836
Test name
Test status
Simulation time 53719054299 ps
CPU time 1087.52 seconds
Started Aug 06 06:04:43 PM PDT 24
Finished Aug 06 06:22:51 PM PDT 24
Peak memory 256192 kb
Host smart-5e12351e-2bdd-4c3f-a165-4e0c8079022e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713859559 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.371385955
9 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_burst_write/latest

Test location /workspace/coverage/default/15.kmac_edn_timeout_error.1250732531
Short name T406
Test name
Test status
Simulation time 13627490 ps
CPU time 0.86 seconds
Started Aug 06 06:05:01 PM PDT 24
Finished Aug 06 06:05:02 PM PDT 24
Peak memory 218576 kb
Host smart-d9b60544-8a08-4bb4-81d5-ef59d0d2eb2e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1250732531 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.1250732531 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/15.kmac_entropy_mode_error.2070784209
Short name T872
Test name
Test status
Simulation time 1713024233 ps
CPU time 38.73 seconds
Started Aug 06 06:05:06 PM PDT 24
Finished Aug 06 06:05:45 PM PDT 24
Peak memory 227048 kb
Host smart-0922aee7-6df1-4cc9-a5e6-b951b57542d8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2070784209 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.2070784209 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/15.kmac_entropy_refresh.2816935605
Short name T676
Test name
Test status
Simulation time 9386204207 ps
CPU time 233.16 seconds
Started Aug 06 06:04:52 PM PDT 24
Finished Aug 06 06:08:45 PM PDT 24
Peak memory 297128 kb
Host smart-f30f2cbb-800a-407c-b06e-f8bea08d344c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816935605 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.2
816935605 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/15.kmac_error.3608802119
Short name T597
Test name
Test status
Simulation time 7858521572 ps
CPU time 68.66 seconds
Started Aug 06 06:04:54 PM PDT 24
Finished Aug 06 06:06:02 PM PDT 24
Peak memory 292692 kb
Host smart-730dc413-7875-43fc-958c-b511061c1777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608802119 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.3608802119 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_error/latest

Test location /workspace/coverage/default/15.kmac_key_error.2040304258
Short name T666
Test name
Test status
Simulation time 513080659 ps
CPU time 1.55 seconds
Started Aug 06 06:04:53 PM PDT 24
Finished Aug 06 06:04:55 PM PDT 24
Peak memory 226572 kb
Host smart-cec5411a-5ed3-463c-b3d9-50f3bdaa638f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040304258 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.2040304258 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_key_error/latest

Test location /workspace/coverage/default/15.kmac_long_msg_and_output.3911581430
Short name T635
Test name
Test status
Simulation time 23687208146 ps
CPU time 700.59 seconds
Started Aug 06 06:04:44 PM PDT 24
Finished Aug 06 06:16:24 PM PDT 24
Peak memory 562492 kb
Host smart-b140e804-d613-4071-9428-6b1f5542ecb5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911581430 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_a
nd_output.3911581430 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/15.kmac_sideload.2810544351
Short name T257
Test name
Test status
Simulation time 73009063172 ps
CPU time 519.66 seconds
Started Aug 06 06:04:51 PM PDT 24
Finished Aug 06 06:13:31 PM PDT 24
Peak memory 622856 kb
Host smart-b6036b2c-54be-43b8-b6aa-68ad591ce79f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810544351 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.2810544351 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_sideload/latest

Test location /workspace/coverage/default/15.kmac_smoke.782015587
Short name T229
Test name
Test status
Simulation time 5112700845 ps
CPU time 32.16 seconds
Started Aug 06 06:04:43 PM PDT 24
Finished Aug 06 06:05:15 PM PDT 24
Peak memory 227184 kb
Host smart-5b41386a-c6aa-47cd-9ae2-21c92ff93b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782015587 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.782015587 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_smoke/latest

Test location /workspace/coverage/default/15.kmac_stress_all.110392643
Short name T820
Test name
Test status
Simulation time 68152346533 ps
CPU time 2553.09 seconds
Started Aug 06 06:04:54 PM PDT 24
Finished Aug 06 06:47:27 PM PDT 24
Peak memory 1484156 kb
Host smart-2c6d03ed-5b63-479a-a26b-93895b6e8e62
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=110392643 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.110392643 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_stress_all/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_kmac.1469780442
Short name T570
Test name
Test status
Simulation time 325473628 ps
CPU time 6.11 seconds
Started Aug 06 06:04:44 PM PDT 24
Finished Aug 06 06:04:51 PM PDT 24
Peak memory 227052 kb
Host smart-532ed4e0-4b12-490e-8b59-ba672784ee6e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469780442 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.kmac_test_vectors_kmac.1469780442 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_kmac_xof.3016239377
Short name T986
Test name
Test status
Simulation time 606681837 ps
CPU time 5.73 seconds
Started Aug 06 06:04:46 PM PDT 24
Finished Aug 06 06:04:52 PM PDT 24
Peak memory 218944 kb
Host smart-778c75cd-8491-46c0-868b-c24487dbe150
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016239377 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.kmac_test_vectors_kmac_xof.3016239377 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_384.2347731603
Short name T392
Test name
Test status
Simulation time 58677918661 ps
CPU time 1683.81 seconds
Started Aug 06 06:04:44 PM PDT 24
Finished Aug 06 06:32:48 PM PDT 24
Peak memory 915928 kb
Host smart-d04f36c6-b934-4766-a732-878949efa5cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2347731603 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_384.2347731603 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_512.771314952
Short name T265
Test name
Test status
Simulation time 130571047305 ps
CPU time 1491.45 seconds
Started Aug 06 06:04:45 PM PDT 24
Finished Aug 06 06:29:36 PM PDT 24
Peak memory 1692540 kb
Host smart-3e0c12f9-f6f6-4280-b480-a72e69a4ddfc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=771314952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_512.771314952 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/16.kmac_alert_test.1952070465
Short name T717
Test name
Test status
Simulation time 26118532 ps
CPU time 0.89 seconds
Started Aug 06 06:05:20 PM PDT 24
Finished Aug 06 06:05:21 PM PDT 24
Peak memory 218440 kb
Host smart-f8bf7fef-67cf-4f63-aba0-f038bee55024
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952070465 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.1952070465 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_alert_test/latest

Test location /workspace/coverage/default/16.kmac_app.2583652962
Short name T217
Test name
Test status
Simulation time 35474802959 ps
CPU time 266.82 seconds
Started Aug 06 06:05:07 PM PDT 24
Finished Aug 06 06:09:34 PM PDT 24
Peak memory 413520 kb
Host smart-25bf79b1-8100-4863-b961-f3ee46b35a3c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583652962 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.2583652962 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/16.kmac_app/latest

Test location /workspace/coverage/default/16.kmac_burst_write.2745666925
Short name T558
Test name
Test status
Simulation time 8871557990 ps
CPU time 897.02 seconds
Started Aug 06 06:04:55 PM PDT 24
Finished Aug 06 06:19:52 PM PDT 24
Peak memory 243568 kb
Host smart-fa5f846a-650f-408b-88ec-5a89427729df
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745666925 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.274566692
5 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_burst_write/latest

Test location /workspace/coverage/default/16.kmac_edn_timeout_error.2080460283
Short name T420
Test name
Test status
Simulation time 1064702531 ps
CPU time 14.24 seconds
Started Aug 06 06:05:08 PM PDT 24
Finished Aug 06 06:05:22 PM PDT 24
Peak memory 219868 kb
Host smart-4a02fe78-f7a9-4832-8ae2-7265bb72a9c3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2080460283 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.2080460283 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/16.kmac_entropy_mode_error.2025435899
Short name T844
Test name
Test status
Simulation time 33502764 ps
CPU time 1.11 seconds
Started Aug 06 06:05:08 PM PDT 24
Finished Aug 06 06:05:09 PM PDT 24
Peak memory 218756 kb
Host smart-a19aad4b-2777-4367-b40d-903c9f560518
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2025435899 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.2025435899 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/16.kmac_entropy_refresh.675881884
Short name T633
Test name
Test status
Simulation time 872083867 ps
CPU time 44.12 seconds
Started Aug 06 06:05:08 PM PDT 24
Finished Aug 06 06:05:52 PM PDT 24
Peak memory 243452 kb
Host smart-33e18ab7-0714-48a1-85de-8f33aa5723c8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675881884 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.67
5881884 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/16.kmac_error.2853905799
Short name T38
Test name
Test status
Simulation time 66032384135 ps
CPU time 321.21 seconds
Started Aug 06 06:05:08 PM PDT 24
Finished Aug 06 06:10:29 PM PDT 24
Peak memory 335784 kb
Host smart-31969a61-02c2-4c75-9d99-71fc909627f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853905799 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.2853905799 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_error/latest

Test location /workspace/coverage/default/16.kmac_key_error.954253458
Short name T647
Test name
Test status
Simulation time 5929187977 ps
CPU time 10.96 seconds
Started Aug 06 06:05:09 PM PDT 24
Finished Aug 06 06:05:20 PM PDT 24
Peak memory 227028 kb
Host smart-54508cf9-c0c5-45f0-8888-9c1ff824b9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954253458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.954253458 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_key_error/latest

Test location /workspace/coverage/default/16.kmac_lc_escalation.2184191231
Short name T866
Test name
Test status
Simulation time 57970214 ps
CPU time 1.5 seconds
Started Aug 06 06:05:30 PM PDT 24
Finished Aug 06 06:05:31 PM PDT 24
Peak memory 227004 kb
Host smart-7a3458b3-4005-419b-ac26-28f8b3768470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184191231 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.2184191231 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/16.kmac_lc_escalation/latest

Test location /workspace/coverage/default/16.kmac_long_msg_and_output.2739653530
Short name T518
Test name
Test status
Simulation time 828465893 ps
CPU time 20.37 seconds
Started Aug 06 06:04:52 PM PDT 24
Finished Aug 06 06:05:13 PM PDT 24
Peak memory 238900 kb
Host smart-bf157ab5-f5a6-497d-8ba9-45ceb4044253
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739653530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_a
nd_output.2739653530 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/16.kmac_sideload.4206184841
Short name T259
Test name
Test status
Simulation time 48000093753 ps
CPU time 316.95 seconds
Started Aug 06 06:05:04 PM PDT 24
Finished Aug 06 06:10:21 PM PDT 24
Peak memory 480060 kb
Host smart-45e7b8b9-62c0-4569-8d2c-a7ee1854ef2a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206184841 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.4206184841 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_sideload/latest

Test location /workspace/coverage/default/16.kmac_smoke.1440332481
Short name T472
Test name
Test status
Simulation time 307985436 ps
CPU time 6.38 seconds
Started Aug 06 06:05:06 PM PDT 24
Finished Aug 06 06:05:13 PM PDT 24
Peak memory 227024 kb
Host smart-c2d14806-1627-4859-83bd-eb9f34faf9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440332481 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.1440332481 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_smoke/latest

Test location /workspace/coverage/default/16.kmac_stress_all.209371028
Short name T586
Test name
Test status
Simulation time 10544762499 ps
CPU time 159.94 seconds
Started Aug 06 06:05:19 PM PDT 24
Finished Aug 06 06:07:59 PM PDT 24
Peak memory 355428 kb
Host smart-f5e10945-eeca-461a-b566-1c6ba1b87ac1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=209371028 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all.209371028 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_stress_all/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_kmac.1832094539
Short name T600
Test name
Test status
Simulation time 287138876 ps
CPU time 6.87 seconds
Started Aug 06 06:05:08 PM PDT 24
Finished Aug 06 06:05:15 PM PDT 24
Peak memory 227088 kb
Host smart-65f9c92a-57cd-4f10-8510-7147647d2e00
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832094539 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.kmac_test_vectors_kmac.1832094539 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_kmac_xof.1684187033
Short name T701
Test name
Test status
Simulation time 481512279 ps
CPU time 5.72 seconds
Started Aug 06 06:05:09 PM PDT 24
Finished Aug 06 06:05:15 PM PDT 24
Peak memory 219096 kb
Host smart-4541a36e-64ab-4765-8fad-880065f6d9f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684187033 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.kmac_test_vectors_kmac_xof.1684187033 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_256.1557326336
Short name T678
Test name
Test status
Simulation time 103138444912 ps
CPU time 2291.54 seconds
Started Aug 06 06:05:08 PM PDT 24
Finished Aug 06 06:43:20 PM PDT 24
Peak memory 1165016 kb
Host smart-d331be11-c571-42c0-bc61-4ae1c7bd4161
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1557326336 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_256.1557326336 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_384.1783909726
Short name T617
Test name
Test status
Simulation time 995422543187 ps
CPU time 3019.56 seconds
Started Aug 06 06:05:08 PM PDT 24
Finished Aug 06 06:55:28 PM PDT 24
Peak memory 2371892 kb
Host smart-35a6f506-7e55-4e92-a774-4c708d2301ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1783909726 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_384.1783909726 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_512.3996356188
Short name T887
Test name
Test status
Simulation time 241523803482 ps
CPU time 1788.25 seconds
Started Aug 06 06:05:09 PM PDT 24
Finished Aug 06 06:34:57 PM PDT 24
Peak memory 1703308 kb
Host smart-490d0e06-4092-4b03-b447-ac5a4c2a0033
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3996356188 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_512.3996356188 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_shake_256.342193252
Short name T910
Test name
Test status
Simulation time 221928122799 ps
CPU time 5498.45 seconds
Started Aug 06 06:05:08 PM PDT 24
Finished Aug 06 07:36:47 PM PDT 24
Peak memory 2257828 kb
Host smart-205d382a-f2ef-42b5-909a-4fee0f36bb4f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=342193252 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_256.342193252 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/17.kmac_alert_test.157231156
Short name T175
Test name
Test status
Simulation time 31278422 ps
CPU time 0.8 seconds
Started Aug 06 06:05:33 PM PDT 24
Finished Aug 06 06:05:33 PM PDT 24
Peak memory 218492 kb
Host smart-0b3e39dc-a8d6-4306-8aab-3dbaed10e2a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157231156 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.157231156 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/17.kmac_alert_test/latest

Test location /workspace/coverage/default/17.kmac_app.2436722204
Short name T652
Test name
Test status
Simulation time 11255032079 ps
CPU time 208.86 seconds
Started Aug 06 06:05:33 PM PDT 24
Finished Aug 06 06:09:02 PM PDT 24
Peak memory 383640 kb
Host smart-7a27c734-8123-489a-be7f-55907c0f10ab
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436722204 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.2436722204 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/17.kmac_app/latest

Test location /workspace/coverage/default/17.kmac_burst_write.2317751620
Short name T685
Test name
Test status
Simulation time 116939402391 ps
CPU time 1248.55 seconds
Started Aug 06 06:05:20 PM PDT 24
Finished Aug 06 06:26:09 PM PDT 24
Peak memory 258936 kb
Host smart-7412ed77-3e73-4f34-a21f-24ebc3ea1f32
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317751620 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.231775162
0 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_burst_write/latest

Test location /workspace/coverage/default/17.kmac_edn_timeout_error.4173581047
Short name T956
Test name
Test status
Simulation time 72229140 ps
CPU time 1.21 seconds
Started Aug 06 06:05:32 PM PDT 24
Finished Aug 06 06:05:34 PM PDT 24
Peak memory 218764 kb
Host smart-a20cfcfd-5d54-4ddf-aab7-a329385ef7d6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4173581047 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.4173581047 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/17.kmac_entropy_mode_error.720606665
Short name T279
Test name
Test status
Simulation time 93221751 ps
CPU time 0.99 seconds
Started Aug 06 06:05:30 PM PDT 24
Finished Aug 06 06:05:32 PM PDT 24
Peak memory 218552 kb
Host smart-e327b022-ebff-4d8d-993b-594dd267a05a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=720606665 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.720606665 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/17.kmac_entropy_refresh.155435986
Short name T991
Test name
Test status
Simulation time 111459209751 ps
CPU time 217.04 seconds
Started Aug 06 06:05:33 PM PDT 24
Finished Aug 06 06:09:10 PM PDT 24
Peak memory 337660 kb
Host smart-d3429c27-4a73-446a-9cc4-51a1d4daa589
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155435986 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.15
5435986 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/17.kmac_error.1716171093
Short name T784
Test name
Test status
Simulation time 8138288277 ps
CPU time 77.96 seconds
Started Aug 06 06:05:34 PM PDT 24
Finished Aug 06 06:06:52 PM PDT 24
Peak memory 290308 kb
Host smart-d822908e-0952-4a71-88bf-fcc876072cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716171093 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.1716171093 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_error/latest

Test location /workspace/coverage/default/17.kmac_key_error.1888741546
Short name T345
Test name
Test status
Simulation time 6089504921 ps
CPU time 12.25 seconds
Started Aug 06 06:05:35 PM PDT 24
Finished Aug 06 06:05:47 PM PDT 24
Peak memory 226300 kb
Host smart-64931519-940a-406f-a52e-73ba0323e6bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888741546 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.1888741546 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_key_error/latest

Test location /workspace/coverage/default/17.kmac_lc_escalation.1688835521
Short name T888
Test name
Test status
Simulation time 113460669 ps
CPU time 1.45 seconds
Started Aug 06 06:05:35 PM PDT 24
Finished Aug 06 06:05:37 PM PDT 24
Peak memory 226948 kb
Host smart-75a89226-125e-40c1-9998-6b40b9cfe1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688835521 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.1688835521 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/17.kmac_lc_escalation/latest

Test location /workspace/coverage/default/17.kmac_sideload.2185590894
Short name T490
Test name
Test status
Simulation time 6562422398 ps
CPU time 129.03 seconds
Started Aug 06 06:05:21 PM PDT 24
Finished Aug 06 06:07:30 PM PDT 24
Peak memory 269164 kb
Host smart-6ccf7e5f-3c77-4094-ba4d-2c10922a20bb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185590894 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.2185590894 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_sideload/latest

Test location /workspace/coverage/default/17.kmac_smoke.56013524
Short name T18
Test name
Test status
Simulation time 7447539456 ps
CPU time 38.4 seconds
Started Aug 06 06:05:25 PM PDT 24
Finished Aug 06 06:06:03 PM PDT 24
Peak memory 226456 kb
Host smart-3a349fad-a678-4471-abc8-db7e22363e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56013524 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.56013524 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_smoke/latest

Test location /workspace/coverage/default/17.kmac_stress_all.396857892
Short name T858
Test name
Test status
Simulation time 205714958 ps
CPU time 4.75 seconds
Started Aug 06 06:05:36 PM PDT 24
Finished Aug 06 06:05:41 PM PDT 24
Peak memory 226916 kb
Host smart-49ac739e-8e18-4508-a12e-986ae5c3279b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=396857892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.396857892 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_stress_all/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_kmac.3002862878
Short name T799
Test name
Test status
Simulation time 2308465751 ps
CPU time 7.57 seconds
Started Aug 06 06:05:21 PM PDT 24
Finished Aug 06 06:05:29 PM PDT 24
Peak memory 219112 kb
Host smart-1073bf7b-aab7-4e55-8b79-e0ffc51f53b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002862878 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.kmac_test_vectors_kmac.3002862878 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_kmac_xof.311000119
Short name T638
Test name
Test status
Simulation time 841366438 ps
CPU time 6.51 seconds
Started Aug 06 06:05:25 PM PDT 24
Finished Aug 06 06:05:31 PM PDT 24
Peak memory 226260 kb
Host smart-fec0eab3-28de-4d3d-b908-51d0fd8d4d77
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311000119 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.kmac_test_vectors_kmac_xof.311000119 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_256.111587430
Short name T381
Test name
Test status
Simulation time 153102746322 ps
CPU time 3091.45 seconds
Started Aug 06 06:05:30 PM PDT 24
Finished Aug 06 06:57:02 PM PDT 24
Peak memory 3102688 kb
Host smart-3c978df2-9560-4f7a-950e-0fd14767bfe1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=111587430 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_256.111587430 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_384.3754049796
Short name T542
Test name
Test status
Simulation time 193352273559 ps
CPU time 2148.92 seconds
Started Aug 06 06:05:21 PM PDT 24
Finished Aug 06 06:41:11 PM PDT 24
Peak memory 2319576 kb
Host smart-dde2fd3e-acf0-4f8b-8228-7290011c413e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3754049796 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_384.3754049796 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_512.520570673
Short name T402
Test name
Test status
Simulation time 102594053972 ps
CPU time 1766.98 seconds
Started Aug 06 06:05:30 PM PDT 24
Finished Aug 06 06:34:57 PM PDT 24
Peak memory 1763828 kb
Host smart-005f474a-ad5b-4d93-b52f-7bd65ae48698
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=520570673 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_512.520570673 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_shake_128.2742237398
Short name T524
Test name
Test status
Simulation time 122254589264 ps
CPU time 5894.98 seconds
Started Aug 06 06:05:23 PM PDT 24
Finished Aug 06 07:43:39 PM PDT 24
Peak memory 2663108 kb
Host smart-1ded84dc-6700-4ff2-92e9-128987b850d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2742237398 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_128.2742237398 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/18.kmac_alert_test.3382402185
Short name T285
Test name
Test status
Simulation time 18893372 ps
CPU time 0.8 seconds
Started Aug 06 06:05:58 PM PDT 24
Finished Aug 06 06:05:59 PM PDT 24
Peak memory 218528 kb
Host smart-dc664f63-3c7c-41d2-a874-f3264d6adb98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382402185 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.3382402185 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_alert_test/latest

Test location /workspace/coverage/default/18.kmac_app.3135804918
Short name T39
Test name
Test status
Simulation time 5450133260 ps
CPU time 152.64 seconds
Started Aug 06 06:05:45 PM PDT 24
Finished Aug 06 06:08:17 PM PDT 24
Peak memory 275132 kb
Host smart-1745910c-4623-4bbc-a5a9-546b83e0f917
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135804918 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.3135804918 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/18.kmac_app/latest

Test location /workspace/coverage/default/18.kmac_burst_write.21950569
Short name T292
Test name
Test status
Simulation time 23503744531 ps
CPU time 706.03 seconds
Started Aug 06 06:05:55 PM PDT 24
Finished Aug 06 06:17:41 PM PDT 24
Peak memory 243572 kb
Host smart-2141a5bf-d7aa-4435-9a1f-8cbe2b7e3136
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21950569 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.21950569 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_burst_write/latest

Test location /workspace/coverage/default/18.kmac_edn_timeout_error.1929610237
Short name T775
Test name
Test status
Simulation time 20486922 ps
CPU time 0.91 seconds
Started Aug 06 06:05:58 PM PDT 24
Finished Aug 06 06:05:59 PM PDT 24
Peak memory 218432 kb
Host smart-684d77ac-8a9a-4419-a51b-823de789e62a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1929610237 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.1929610237 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/18.kmac_entropy_mode_error.483237327
Short name T918
Test name
Test status
Simulation time 30028409 ps
CPU time 1.01 seconds
Started Aug 06 06:05:58 PM PDT 24
Finished Aug 06 06:05:59 PM PDT 24
Peak memory 218616 kb
Host smart-179a47b1-f8f2-4d87-adc3-1b3a880e585e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=483237327 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.483237327 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/18.kmac_entropy_refresh.3388909109
Short name T626
Test name
Test status
Simulation time 3886092446 ps
CPU time 50.82 seconds
Started Aug 06 06:05:48 PM PDT 24
Finished Aug 06 06:06:39 PM PDT 24
Peak memory 257912 kb
Host smart-3ab07e27-ad92-4b81-bf76-713cebed22d9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388909109 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.3
388909109 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/18.kmac_error.2204732983
Short name T476
Test name
Test status
Simulation time 12047745802 ps
CPU time 245.26 seconds
Started Aug 06 06:05:45 PM PDT 24
Finished Aug 06 06:09:50 PM PDT 24
Peak memory 308920 kb
Host smart-ed871ef8-5672-4f35-9a95-21d7337f5563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204732983 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.2204732983 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_error/latest

Test location /workspace/coverage/default/18.kmac_key_error.872843007
Short name T207
Test name
Test status
Simulation time 1246424805 ps
CPU time 5.66 seconds
Started Aug 06 06:06:03 PM PDT 24
Finished Aug 06 06:06:09 PM PDT 24
Peak memory 226852 kb
Host smart-36f8eee1-72d2-4b10-aa66-489db0f7039f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872843007 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.872843007 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_key_error/latest

Test location /workspace/coverage/default/18.kmac_lc_escalation.1091630615
Short name T102
Test name
Test status
Simulation time 252227279 ps
CPU time 11.75 seconds
Started Aug 06 06:05:57 PM PDT 24
Finished Aug 06 06:06:08 PM PDT 24
Peak memory 227044 kb
Host smart-0d74d8f1-9d14-4374-97cf-b6e93299ae8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091630615 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.1091630615 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/18.kmac_lc_escalation/latest

Test location /workspace/coverage/default/18.kmac_long_msg_and_output.1415098882
Short name T446
Test name
Test status
Simulation time 218294979075 ps
CPU time 3180.31 seconds
Started Aug 06 06:05:33 PM PDT 24
Finished Aug 06 06:58:34 PM PDT 24
Peak memory 2797808 kb
Host smart-8416ab9e-cca7-46a3-a163-4c9e591f15ae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415098882 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_a
nd_output.1415098882 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/18.kmac_sideload.2177321022
Short name T465
Test name
Test status
Simulation time 30795541595 ps
CPU time 451.29 seconds
Started Aug 06 06:05:34 PM PDT 24
Finished Aug 06 06:13:06 PM PDT 24
Peak memory 559380 kb
Host smart-bb3a122f-2d9d-49a8-a4c8-6269e1cb56dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177321022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.2177321022 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_sideload/latest

Test location /workspace/coverage/default/18.kmac_smoke.3994913602
Short name T699
Test name
Test status
Simulation time 6030357528 ps
CPU time 76.5 seconds
Started Aug 06 06:05:35 PM PDT 24
Finished Aug 06 06:06:51 PM PDT 24
Peak memory 227336 kb
Host smart-06e5303d-a165-465f-82d8-38dd0e328619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994913602 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.3994913602 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_smoke/latest

Test location /workspace/coverage/default/18.kmac_stress_all.520662105
Short name T972
Test name
Test status
Simulation time 24502388558 ps
CPU time 1071.96 seconds
Started Aug 06 06:05:57 PM PDT 24
Finished Aug 06 06:23:49 PM PDT 24
Peak memory 1020852 kb
Host smart-eaa232f5-3bcc-4f98-bcfa-7af7ab8e45ff
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=520662105 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all.520662105 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_stress_all/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_kmac.3367359710
Short name T434
Test name
Test status
Simulation time 111992950 ps
CPU time 5.19 seconds
Started Aug 06 06:05:45 PM PDT 24
Finished Aug 06 06:05:50 PM PDT 24
Peak memory 227040 kb
Host smart-071b0c35-01f4-48a9-916d-9680cadff6ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367359710 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.kmac_test_vectors_kmac.3367359710 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_kmac_xof.2369260598
Short name T883
Test name
Test status
Simulation time 388473646 ps
CPU time 5.39 seconds
Started Aug 06 06:05:50 PM PDT 24
Finished Aug 06 06:05:56 PM PDT 24
Peak memory 227016 kb
Host smart-0e2ab513-8948-4e67-a64f-df6260f86646
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369260598 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.kmac_test_vectors_kmac_xof.2369260598 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_224.2890113290
Short name T795
Test name
Test status
Simulation time 85807603823 ps
CPU time 2273.63 seconds
Started Aug 06 06:05:45 PM PDT 24
Finished Aug 06 06:43:39 PM PDT 24
Peak memory 1199820 kb
Host smart-7320da1f-e490-466b-a9bc-6e8c0392a21a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2890113290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_224.2890113290 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_256.106689785
Short name T708
Test name
Test status
Simulation time 56296133992 ps
CPU time 2153.09 seconds
Started Aug 06 06:05:51 PM PDT 24
Finished Aug 06 06:41:45 PM PDT 24
Peak memory 1153452 kb
Host smart-0b3cf597-57fa-4172-9ecb-fa897457abf3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=106689785 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_256.106689785 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_384.1917788841
Short name T634
Test name
Test status
Simulation time 190956251659 ps
CPU time 2424.47 seconds
Started Aug 06 06:05:55 PM PDT 24
Finished Aug 06 06:46:19 PM PDT 24
Peak memory 2392396 kb
Host smart-2aa256de-d4c7-4c54-989a-e6719745fe87
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1917788841 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_384.1917788841 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_512.1486531873
Short name T251
Test name
Test status
Simulation time 502386212976 ps
CPU time 1814.44 seconds
Started Aug 06 06:05:45 PM PDT 24
Finished Aug 06 06:36:00 PM PDT 24
Peak memory 1766080 kb
Host smart-3a43804e-5eab-417f-b0b6-ac1d56fa566f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1486531873 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_512.1486531873 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_shake_256.3263748524
Short name T882
Test name
Test status
Simulation time 139768445885 ps
CPU time 5036.55 seconds
Started Aug 06 06:05:45 PM PDT 24
Finished Aug 06 07:29:43 PM PDT 24
Peak memory 2245068 kb
Host smart-97027734-dc32-43e2-be9c-9e5887fd1d6a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3263748524 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_256.3263748524 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/19.kmac_alert_test.701003095
Short name T416
Test name
Test status
Simulation time 13627607 ps
CPU time 0.81 seconds
Started Aug 06 06:06:27 PM PDT 24
Finished Aug 06 06:06:27 PM PDT 24
Peak memory 218616 kb
Host smart-cd4f17f5-0e63-4e22-9598-089c06767015
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701003095 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.701003095 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/19.kmac_alert_test/latest

Test location /workspace/coverage/default/19.kmac_app.2897157794
Short name T940
Test name
Test status
Simulation time 50522833655 ps
CPU time 240.81 seconds
Started Aug 06 06:06:12 PM PDT 24
Finished Aug 06 06:10:13 PM PDT 24
Peak memory 394320 kb
Host smart-39303bca-a270-4abb-ba02-ae9ee9eb560a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897157794 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.2897157794 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/19.kmac_app/latest

Test location /workspace/coverage/default/19.kmac_burst_write.1763735823
Short name T546
Test name
Test status
Simulation time 11650704219 ps
CPU time 168.06 seconds
Started Aug 06 06:06:14 PM PDT 24
Finished Aug 06 06:09:02 PM PDT 24
Peak memory 238572 kb
Host smart-b5de94b1-c8ea-4103-a16d-ccd4da7daa2b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763735823 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.176373582
3 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_burst_write/latest

Test location /workspace/coverage/default/19.kmac_edn_timeout_error.3864433622
Short name T73
Test name
Test status
Simulation time 132001894 ps
CPU time 0.97 seconds
Started Aug 06 06:06:25 PM PDT 24
Finished Aug 06 06:06:26 PM PDT 24
Peak memory 218668 kb
Host smart-0ad960dc-02ab-46dc-b606-aad58436c676
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3864433622 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.3864433622 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/19.kmac_entropy_mode_error.1634390288
Short name T393
Test name
Test status
Simulation time 38883747 ps
CPU time 0.99 seconds
Started Aug 06 06:06:29 PM PDT 24
Finished Aug 06 06:06:30 PM PDT 24
Peak memory 218480 kb
Host smart-b858ab86-3d8e-461d-8b53-4c9e2fd5e86f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1634390288 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.1634390288 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/19.kmac_entropy_refresh.3690551884
Short name T949
Test name
Test status
Simulation time 74670425178 ps
CPU time 431.08 seconds
Started Aug 06 06:06:27 PM PDT 24
Finished Aug 06 06:13:38 PM PDT 24
Peak memory 507424 kb
Host smart-8ee62869-46fe-46ed-9272-1a936cb49301
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690551884 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.3
690551884 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/19.kmac_error.3300093372
Short name T503
Test name
Test status
Simulation time 1304735040 ps
CPU time 30 seconds
Started Aug 06 06:06:26 PM PDT 24
Finished Aug 06 06:06:56 PM PDT 24
Peak memory 238744 kb
Host smart-c2154ae7-915f-4b4c-88e0-ccd2fcef1c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300093372 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.3300093372 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_error/latest

Test location /workspace/coverage/default/19.kmac_key_error.4242151190
Short name T539
Test name
Test status
Simulation time 11764311224 ps
CPU time 11.43 seconds
Started Aug 06 06:06:26 PM PDT 24
Finished Aug 06 06:06:37 PM PDT 24
Peak memory 227004 kb
Host smart-848b8971-744d-4f9e-ab6c-fd8c92df1fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242151190 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.4242151190 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_key_error/latest

Test location /workspace/coverage/default/19.kmac_lc_escalation.3557888984
Short name T43
Test name
Test status
Simulation time 2964361061 ps
CPU time 47.9 seconds
Started Aug 06 06:06:27 PM PDT 24
Finished Aug 06 06:07:15 PM PDT 24
Peak memory 250608 kb
Host smart-16a7ee85-43ae-4c65-96a7-a063ff7aa1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557888984 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.3557888984 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/19.kmac_lc_escalation/latest

Test location /workspace/coverage/default/19.kmac_long_msg_and_output.2138965673
Short name T256
Test name
Test status
Simulation time 24622777046 ps
CPU time 242.26 seconds
Started Aug 06 06:05:57 PM PDT 24
Finished Aug 06 06:10:00 PM PDT 24
Peak memory 505628 kb
Host smart-79b01f0a-b4a7-416e-aad0-39c9c19e53fa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138965673 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_a
nd_output.2138965673 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/19.kmac_sideload.3681277026
Short name T722
Test name
Test status
Simulation time 5136809934 ps
CPU time 456.3 seconds
Started Aug 06 06:05:58 PM PDT 24
Finished Aug 06 06:13:34 PM PDT 24
Peak memory 374856 kb
Host smart-177f3f10-edcb-47eb-a923-8fac7e30abfa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681277026 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.3681277026 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_sideload/latest

Test location /workspace/coverage/default/19.kmac_stress_all.197091732
Short name T939
Test name
Test status
Simulation time 13137504483 ps
CPU time 516.21 seconds
Started Aug 06 06:06:31 PM PDT 24
Finished Aug 06 06:15:07 PM PDT 24
Peak memory 289472 kb
Host smart-bdd9d87e-76d4-4ee4-847a-c3647cebd8e7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=197091732 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.197091732 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_stress_all/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_kmac.2599567121
Short name T826
Test name
Test status
Simulation time 510948751 ps
CPU time 6.41 seconds
Started Aug 06 06:06:12 PM PDT 24
Finished Aug 06 06:06:19 PM PDT 24
Peak memory 219928 kb
Host smart-ee0f9456-d48c-4093-a484-ae8a3fdca03b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599567121 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.kmac_test_vectors_kmac.2599567121 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_kmac_xof.3283250707
Short name T688
Test name
Test status
Simulation time 201025258 ps
CPU time 5.77 seconds
Started Aug 06 06:06:12 PM PDT 24
Finished Aug 06 06:06:18 PM PDT 24
Peak memory 220000 kb
Host smart-0d7438b8-6160-4971-a97f-f1e017b08489
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283250707 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.kmac_test_vectors_kmac_xof.3283250707 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_224.247214613
Short name T195
Test name
Test status
Simulation time 181424555098 ps
CPU time 2291.45 seconds
Started Aug 06 06:06:12 PM PDT 24
Finished Aug 06 06:44:24 PM PDT 24
Peak memory 1187820 kb
Host smart-7fe045ca-45a7-4343-9940-ac3d98580546
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=247214613 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_224.247214613 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_256.2678327338
Short name T770
Test name
Test status
Simulation time 23361591679 ps
CPU time 2176.65 seconds
Started Aug 06 06:06:12 PM PDT 24
Finished Aug 06 06:42:29 PM PDT 24
Peak memory 1154780 kb
Host smart-8695356a-fc8f-4204-90aa-458beda8c072
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2678327338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_256.2678327338 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_384.3957844246
Short name T780
Test name
Test status
Simulation time 203846781046 ps
CPU time 2176.75 seconds
Started Aug 06 06:06:12 PM PDT 24
Finished Aug 06 06:42:30 PM PDT 24
Peak memory 2356684 kb
Host smart-ee4ab462-20a4-433a-a6bd-7c57434c0122
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3957844246 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_384.3957844246 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_512.3268786600
Short name T599
Test name
Test status
Simulation time 11646779363 ps
CPU time 1211.79 seconds
Started Aug 06 06:06:12 PM PDT 24
Finished Aug 06 06:26:24 PM PDT 24
Peak memory 711636 kb
Host smart-a011923c-41ef-4d6e-a60d-94360a4a901b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3268786600 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_512.3268786600 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_shake_128.143802112
Short name T35
Test name
Test status
Simulation time 61941439812 ps
CPU time 6291.75 seconds
Started Aug 06 06:06:13 PM PDT 24
Finished Aug 06 07:51:06 PM PDT 24
Peak memory 2717204 kb
Host smart-809d42de-fbde-4e84-bdbb-7599bad3bc4b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=143802112 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_128.143802112 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_shake_256.682851735
Short name T637
Test name
Test status
Simulation time 69703522562 ps
CPU time 5189.71 seconds
Started Aug 06 06:06:12 PM PDT 24
Finished Aug 06 07:32:43 PM PDT 24
Peak memory 2215892 kb
Host smart-d0e5536c-7ad9-4915-8236-a6a38509e577
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=682851735 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_256.682851735 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/2.kmac_alert_test.3380256248
Short name T31
Test name
Test status
Simulation time 17359139 ps
CPU time 0.88 seconds
Started Aug 06 06:00:47 PM PDT 24
Finished Aug 06 06:00:48 PM PDT 24
Peak memory 218572 kb
Host smart-7258805d-33bb-4b3d-aec1-092a6769ebbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380256248 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.3380256248 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_alert_test/latest

Test location /workspace/coverage/default/2.kmac_app.4292247480
Short name T825
Test name
Test status
Simulation time 1684017248 ps
CPU time 54.98 seconds
Started Aug 06 06:00:32 PM PDT 24
Finished Aug 06 06:01:27 PM PDT 24
Peak memory 261376 kb
Host smart-79f3d2cc-d6ff-4044-b09d-2a194ec2e9d7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292247480 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.4292247480 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/2.kmac_app/latest

Test location /workspace/coverage/default/2.kmac_app_with_partial_data.4260791124
Short name T828
Test name
Test status
Simulation time 41468068669 ps
CPU time 301.88 seconds
Started Aug 06 06:00:33 PM PDT 24
Finished Aug 06 06:05:35 PM PDT 24
Peak memory 427648 kb
Host smart-89c1e6b8-6f82-4a1d-b102-6e7ed917b812
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260791124 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_par
tial_data.4260791124 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/2.kmac_burst_write.2310581968
Short name T320
Test name
Test status
Simulation time 45250448317 ps
CPU time 1138.26 seconds
Started Aug 06 06:00:33 PM PDT 24
Finished Aug 06 06:19:32 PM PDT 24
Peak memory 257740 kb
Host smart-cc65be04-4a07-4730-bc22-39f98d508896
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310581968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.2310581968
+enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_burst_write/latest

Test location /workspace/coverage/default/2.kmac_edn_timeout_error.1361674245
Short name T954
Test name
Test status
Simulation time 104632421 ps
CPU time 1.02 seconds
Started Aug 06 06:00:47 PM PDT 24
Finished Aug 06 06:00:49 PM PDT 24
Peak memory 218568 kb
Host smart-c448d95c-4448-4dfd-a7e5-69966cadf78f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1361674245 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.1361674245 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_mode_error.1237427961
Short name T309
Test name
Test status
Simulation time 172972054 ps
CPU time 5.31 seconds
Started Aug 06 06:00:46 PM PDT 24
Finished Aug 06 06:00:52 PM PDT 24
Peak memory 224032 kb
Host smart-e80357e5-d5ae-4535-96a8-555a1f6170e6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1237427961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.1237427961 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_refresh.1368817878
Short name T404
Test name
Test status
Simulation time 2488712377 ps
CPU time 157.25 seconds
Started Aug 06 06:00:31 PM PDT 24
Finished Aug 06 06:03:09 PM PDT 24
Peak memory 269976 kb
Host smart-73833312-6ac5-46ff-8fd7-78688c8a8c4a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368817878 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.13
68817878 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/2.kmac_error.2051162957
Short name T767
Test name
Test status
Simulation time 1623850708 ps
CPU time 151.32 seconds
Started Aug 06 06:00:48 PM PDT 24
Finished Aug 06 06:03:19 PM PDT 24
Peak memory 284192 kb
Host smart-62afedd7-55f3-48d4-9dfa-7ae83fb5a3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051162957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.2051162957 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_error/latest

Test location /workspace/coverage/default/2.kmac_key_error.886804925
Short name T232
Test name
Test status
Simulation time 2041331571 ps
CPU time 8.19 seconds
Started Aug 06 06:00:48 PM PDT 24
Finished Aug 06 06:00:56 PM PDT 24
Peak memory 226880 kb
Host smart-bdb5b211-f674-4579-8438-7226c0a8e29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886804925 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.886804925 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_key_error/latest

Test location /workspace/coverage/default/2.kmac_lc_escalation.1191190783
Short name T628
Test name
Test status
Simulation time 65196918 ps
CPU time 1.25 seconds
Started Aug 06 06:00:48 PM PDT 24
Finished Aug 06 06:00:49 PM PDT 24
Peak memory 227024 kb
Host smart-939354a9-589c-4433-8434-b703489fd765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191190783 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.1191190783 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/2.kmac_lc_escalation/latest

Test location /workspace/coverage/default/2.kmac_long_msg_and_output.3927946442
Short name T867
Test name
Test status
Simulation time 67783203351 ps
CPU time 2580.5 seconds
Started Aug 06 06:00:24 PM PDT 24
Finished Aug 06 06:43:25 PM PDT 24
Peak memory 2433324 kb
Host smart-9ad223e4-7694-4670-bf9a-068787773f27
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927946442 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_an
d_output.3927946442 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/2.kmac_mubi.1360381090
Short name T453
Test name
Test status
Simulation time 2082668606 ps
CPU time 21.72 seconds
Started Aug 06 06:00:33 PM PDT 24
Finished Aug 06 06:00:55 PM PDT 24
Peak memory 245316 kb
Host smart-c2ab03ae-b802-49e1-9fd5-3e12b842e6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360381090 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.1360381090 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_mubi/latest

Test location /workspace/coverage/default/2.kmac_sec_cm.4196937907
Short name T90
Test name
Test status
Simulation time 8343905782 ps
CPU time 43.32 seconds
Started Aug 06 06:00:45 PM PDT 24
Finished Aug 06 06:01:29 PM PDT 24
Peak memory 256892 kb
Host smart-fcfb01e3-0c39-4d8c-a2a0-f35c545ddfbf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196937907 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.4196937907 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspace/2.kmac_sec_cm/latest

Test location /workspace/coverage/default/2.kmac_sideload.3656034379
Short name T624
Test name
Test status
Simulation time 6761599523 ps
CPU time 303.22 seconds
Started Aug 06 06:00:29 PM PDT 24
Finished Aug 06 06:05:32 PM PDT 24
Peak memory 327376 kb
Host smart-ffb93f7c-80ba-43dc-a092-52d6c87c7685
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656034379 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.3656034379 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_sideload/latest

Test location /workspace/coverage/default/2.kmac_smoke.3214110550
Short name T168
Test name
Test status
Simulation time 1368972274 ps
CPU time 7.79 seconds
Started Aug 06 06:00:19 PM PDT 24
Finished Aug 06 06:00:27 PM PDT 24
Peak memory 227048 kb
Host smart-1b4b6861-3460-4ec2-b729-985384dd5d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214110550 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.3214110550 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_smoke/latest

Test location /workspace/coverage/default/2.kmac_stress_all.2848737416
Short name T625
Test name
Test status
Simulation time 173622529566 ps
CPU time 1616.54 seconds
Started Aug 06 06:00:46 PM PDT 24
Finished Aug 06 06:27:43 PM PDT 24
Peak memory 861340 kb
Host smart-62b7def4-8efc-49ce-b960-cb8bb35362fe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2848737416 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.2848737416 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_stress_all/latest

Test location /workspace/coverage/default/2.kmac_stress_all_with_rand_reset.3295793729
Short name T116
Test name
Test status
Simulation time 44492011754 ps
CPU time 2042.86 seconds
Started Aug 06 06:00:47 PM PDT 24
Finished Aug 06 06:34:50 PM PDT 24
Peak memory 635484 kb
Host smart-3df0fa36-dbef-42ac-8de6-dc5eda0f3d60
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3295793729 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all_with_rand_reset.3295793729 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_kmac.392610528
Short name T639
Test name
Test status
Simulation time 829999808 ps
CPU time 6.98 seconds
Started Aug 06 06:00:35 PM PDT 24
Finished Aug 06 06:00:42 PM PDT 24
Peak memory 226996 kb
Host smart-ed82b007-ce1b-40aa-a53a-34a64002029e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392610528 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.kmac_test_vectors_kmac.392610528 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_kmac_xof.1167475293
Short name T210
Test name
Test status
Simulation time 1828257073 ps
CPU time 6.14 seconds
Started Aug 06 06:00:35 PM PDT 24
Finished Aug 06 06:00:41 PM PDT 24
Peak memory 219064 kb
Host smart-27a0831d-9494-40ac-9778-b470d5aaae9d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167475293 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.kmac_test_vectors_kmac_xof.1167475293 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_224.432888246
Short name T181
Test name
Test status
Simulation time 140529319909 ps
CPU time 2121.49 seconds
Started Aug 06 06:00:33 PM PDT 24
Finished Aug 06 06:35:55 PM PDT 24
Peak memory 1170816 kb
Host smart-9ae33387-8fb7-4108-a239-11b09fbf7379
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=432888246 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.432888246 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_256.3681802747
Short name T177
Test name
Test status
Simulation time 182827040065 ps
CPU time 3319.97 seconds
Started Aug 06 06:00:33 PM PDT 24
Finished Aug 06 06:55:53 PM PDT 24
Peak memory 2998352 kb
Host smart-08b9ad63-3ac0-4a24-8927-360e34aba242
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3681802747 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.3681802747 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_384.2915309818
Short name T371
Test name
Test status
Simulation time 15290527146 ps
CPU time 1726.89 seconds
Started Aug 06 06:00:34 PM PDT 24
Finished Aug 06 06:29:22 PM PDT 24
Peak memory 920988 kb
Host smart-cb48a4ab-f433-404d-a210-fea225a6c530
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2915309818 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.2915309818 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_512.1560799656
Short name T909
Test name
Test status
Simulation time 11486424483 ps
CPU time 1230.96 seconds
Started Aug 06 06:00:32 PM PDT 24
Finished Aug 06 06:21:03 PM PDT 24
Peak memory 686972 kb
Host smart-4622e49c-1bcb-4b34-814a-13abfeda4a11
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1560799656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.1560799656 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_shake_128.2676045647
Short name T698
Test name
Test status
Simulation time 68315872174 ps
CPU time 6439.26 seconds
Started Aug 06 06:00:33 PM PDT 24
Finished Aug 06 07:47:53 PM PDT 24
Peak memory 2642020 kb
Host smart-c655816b-ac55-4d52-884f-31e86d04234b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2676045647 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.2676045647 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_shake_256.3522862616
Short name T351
Test name
Test status
Simulation time 661139234956 ps
CPU time 5582.52 seconds
Started Aug 06 06:00:34 PM PDT 24
Finished Aug 06 07:33:37 PM PDT 24
Peak memory 2224376 kb
Host smart-f1f43d67-e6ec-4c8c-a97a-398cc4d32236
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3522862616 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.3522862616 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/20.kmac_alert_test.1079836426
Short name T461
Test name
Test status
Simulation time 49714306 ps
CPU time 0.89 seconds
Started Aug 06 06:06:45 PM PDT 24
Finished Aug 06 06:06:46 PM PDT 24
Peak memory 218440 kb
Host smart-d2ee93b3-0f1b-4f14-80b8-deb292f250b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079836426 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.1079836426 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_alert_test/latest

Test location /workspace/coverage/default/20.kmac_app.819723511
Short name T692
Test name
Test status
Simulation time 9461322640 ps
CPU time 300.8 seconds
Started Aug 06 06:06:30 PM PDT 24
Finished Aug 06 06:11:31 PM PDT 24
Peak memory 321516 kb
Host smart-ddebafec-1242-46c9-8839-3a18bc355a97
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819723511 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.819723511 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/20.kmac_app/latest

Test location /workspace/coverage/default/20.kmac_burst_write.2863777202
Short name T897
Test name
Test status
Simulation time 15609889863 ps
CPU time 863.75 seconds
Started Aug 06 06:06:27 PM PDT 24
Finished Aug 06 06:20:51 PM PDT 24
Peak memory 241244 kb
Host smart-7a11f5fb-a1a7-49e3-b3ba-f146768b875f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863777202 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.286377720
2 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_burst_write/latest

Test location /workspace/coverage/default/20.kmac_entropy_refresh.2757424217
Short name T878
Test name
Test status
Simulation time 10223738996 ps
CPU time 169.75 seconds
Started Aug 06 06:06:29 PM PDT 24
Finished Aug 06 06:09:19 PM PDT 24
Peak memory 338804 kb
Host smart-e2ed251e-4fdc-4103-9f1a-5c552bb3bf1c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757424217 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.2
757424217 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/20.kmac_error.3125833227
Short name T657
Test name
Test status
Simulation time 20552148812 ps
CPU time 568.65 seconds
Started Aug 06 06:06:29 PM PDT 24
Finished Aug 06 06:15:58 PM PDT 24
Peak memory 657988 kb
Host smart-6b8b7e78-8a0c-478f-b5ca-bcfd7402f524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125833227 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.3125833227 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_error/latest

Test location /workspace/coverage/default/20.kmac_lc_escalation.3356041702
Short name T15
Test name
Test status
Simulation time 4622455004 ps
CPU time 25.98 seconds
Started Aug 06 06:06:30 PM PDT 24
Finished Aug 06 06:06:56 PM PDT 24
Peak memory 251816 kb
Host smart-a46af032-1e95-48f0-8251-6d581525e5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356041702 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.3356041702 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/20.kmac_lc_escalation/latest

Test location /workspace/coverage/default/20.kmac_long_msg_and_output.1056974167
Short name T589
Test name
Test status
Simulation time 102291495244 ps
CPU time 3346.42 seconds
Started Aug 06 06:06:27 PM PDT 24
Finished Aug 06 07:02:14 PM PDT 24
Peak memory 1671252 kb
Host smart-ec55741b-c379-46b9-b573-ed761fea3118
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056974167 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_a
nd_output.1056974167 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/20.kmac_sideload.1386862146
Short name T537
Test name
Test status
Simulation time 25412544936 ps
CPU time 157.41 seconds
Started Aug 06 06:06:28 PM PDT 24
Finished Aug 06 06:09:05 PM PDT 24
Peak memory 349316 kb
Host smart-b4dd632c-a6ff-4a7a-b783-53f2c9f979de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386862146 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.1386862146 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_sideload/latest

Test location /workspace/coverage/default/20.kmac_smoke.3649944779
Short name T443
Test name
Test status
Simulation time 929130015 ps
CPU time 19.8 seconds
Started Aug 06 06:06:27 PM PDT 24
Finished Aug 06 06:06:47 PM PDT 24
Peak memory 227044 kb
Host smart-f6bcfb52-7e26-4c6e-ad5f-c741aa66de0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649944779 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.3649944779 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_smoke/latest

Test location /workspace/coverage/default/20.kmac_stress_all.2509905433
Short name T792
Test name
Test status
Simulation time 96493703634 ps
CPU time 449.38 seconds
Started Aug 06 06:06:38 PM PDT 24
Finished Aug 06 06:14:08 PM PDT 24
Peak memory 333632 kb
Host smart-135fcc47-64c7-465f-9a5a-82c295f858cc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2509905433 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.2509905433 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_stress_all/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_kmac.2991209819
Short name T889
Test name
Test status
Simulation time 324348967 ps
CPU time 6.61 seconds
Started Aug 06 06:06:28 PM PDT 24
Finished Aug 06 06:06:34 PM PDT 24
Peak memory 219268 kb
Host smart-8569e905-ae2c-409a-8337-af844259c271
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991209819 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.kmac_test_vectors_kmac.2991209819 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_kmac_xof.836271294
Short name T716
Test name
Test status
Simulation time 222568070 ps
CPU time 6.84 seconds
Started Aug 06 06:06:33 PM PDT 24
Finished Aug 06 06:06:40 PM PDT 24
Peak memory 226988 kb
Host smart-733880a6-3717-4493-a733-2972104eaf63
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836271294 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.kmac_test_vectors_kmac_xof.836271294 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_224.2288932939
Short name T658
Test name
Test status
Simulation time 66834725251 ps
CPU time 3099.25 seconds
Started Aug 06 06:06:31 PM PDT 24
Finished Aug 06 06:58:11 PM PDT 24
Peak memory 3220460 kb
Host smart-d21b7a66-0e97-4928-9806-ee6b369e0b57
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2288932939 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_224.2288932939 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_256.3275373432
Short name T395
Test name
Test status
Simulation time 1537070729220 ps
CPU time 3534.1 seconds
Started Aug 06 06:06:31 PM PDT 24
Finished Aug 06 07:05:25 PM PDT 24
Peak memory 3060892 kb
Host smart-eb0fb6d8-8f01-45e5-a811-aff71118280f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3275373432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_256.3275373432 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_384.4009809817
Short name T922
Test name
Test status
Simulation time 198543695026 ps
CPU time 2314.59 seconds
Started Aug 06 06:06:32 PM PDT 24
Finished Aug 06 06:45:07 PM PDT 24
Peak memory 2402244 kb
Host smart-460dee11-bc26-44c7-ad49-4869e8ad8f63
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4009809817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_384.4009809817 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_512.3757124920
Short name T233
Test name
Test status
Simulation time 34150678820 ps
CPU time 1573.27 seconds
Started Aug 06 06:06:28 PM PDT 24
Finished Aug 06 06:32:41 PM PDT 24
Peak memory 1734076 kb
Host smart-2dd66188-90fe-4715-8e83-85d0c2c27948
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3757124920 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_512.3757124920 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_shake_256.1674480197
Short name T363
Test name
Test status
Simulation time 211445496662 ps
CPU time 5551.75 seconds
Started Aug 06 06:06:29 PM PDT 24
Finished Aug 06 07:39:01 PM PDT 24
Peak memory 2251096 kb
Host smart-aca01a2a-fb63-486c-b43c-de23e72fa0b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1674480197 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_256.1674480197 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/21.kmac_alert_test.3394363279
Short name T535
Test name
Test status
Simulation time 22164780 ps
CPU time 0.83 seconds
Started Aug 06 06:07:01 PM PDT 24
Finished Aug 06 06:07:02 PM PDT 24
Peak memory 218576 kb
Host smart-18d2e832-7182-4520-a4a9-57f48e79f9cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394363279 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.3394363279 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_alert_test/latest

Test location /workspace/coverage/default/21.kmac_app.3199287163
Short name T565
Test name
Test status
Simulation time 4858651033 ps
CPU time 123.78 seconds
Started Aug 06 06:07:00 PM PDT 24
Finished Aug 06 06:09:04 PM PDT 24
Peak memory 304900 kb
Host smart-7e39bd65-be21-41f3-935d-97ebc27f04d2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199287163 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.3199287163 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/21.kmac_app/latest

Test location /workspace/coverage/default/21.kmac_burst_write.825204900
Short name T674
Test name
Test status
Simulation time 10369938444 ps
CPU time 600.56 seconds
Started Aug 06 06:06:46 PM PDT 24
Finished Aug 06 06:16:47 PM PDT 24
Peak memory 243496 kb
Host smart-1e71a34d-7742-474f-990e-b93c248a8586
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825204900 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.825204900
+enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_burst_write/latest

Test location /workspace/coverage/default/21.kmac_entropy_refresh.792134035
Short name T68
Test name
Test status
Simulation time 37079721857 ps
CPU time 360.07 seconds
Started Aug 06 06:07:00 PM PDT 24
Finished Aug 06 06:13:00 PM PDT 24
Peak memory 328860 kb
Host smart-f81323f0-22a5-4ba4-b5cc-ec8c87218f44
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792134035 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_entropy_refresh.79
2134035 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/21.kmac_error.3241121202
Short name T640
Test name
Test status
Simulation time 7158780017 ps
CPU time 284.37 seconds
Started Aug 06 06:07:07 PM PDT 24
Finished Aug 06 06:11:52 PM PDT 24
Peak memory 328916 kb
Host smart-05c4d9ce-d6e9-4f21-a014-463e5c8928f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241121202 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_error.3241121202 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_error/latest

Test location /workspace/coverage/default/21.kmac_key_error.2743882557
Short name T6
Test name
Test status
Simulation time 3763457251 ps
CPU time 8.34 seconds
Started Aug 06 06:06:59 PM PDT 24
Finished Aug 06 06:07:07 PM PDT 24
Peak memory 227096 kb
Host smart-8577e199-acf8-4ee3-8c5b-96ea8b7e6190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743882557 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.2743882557 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_key_error/latest

Test location /workspace/coverage/default/21.kmac_lc_escalation.1612460950
Short name T759
Test name
Test status
Simulation time 44185809 ps
CPU time 1.32 seconds
Started Aug 06 06:07:00 PM PDT 24
Finished Aug 06 06:07:01 PM PDT 24
Peak memory 226844 kb
Host smart-df920f7d-05ab-4145-8c9e-7f972fc4f4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612460950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.1612460950 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/21.kmac_lc_escalation/latest

Test location /workspace/coverage/default/21.kmac_sideload.2537087464
Short name T243
Test name
Test status
Simulation time 5485792787 ps
CPU time 155.49 seconds
Started Aug 06 06:06:46 PM PDT 24
Finished Aug 06 06:09:22 PM PDT 24
Peak memory 349032 kb
Host smart-9040f176-7047-4de7-a273-a9c58a65cc59
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537087464 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.2537087464 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_sideload/latest

Test location /workspace/coverage/default/21.kmac_smoke.1634486074
Short name T187
Test name
Test status
Simulation time 5546570175 ps
CPU time 61.04 seconds
Started Aug 06 06:06:46 PM PDT 24
Finished Aug 06 06:07:47 PM PDT 24
Peak memory 227120 kb
Host smart-ad798090-634a-42af-8499-7416d51ad3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634486074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.1634486074 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_smoke/latest

Test location /workspace/coverage/default/21.kmac_stress_all.1133887218
Short name T785
Test name
Test status
Simulation time 237198938717 ps
CPU time 2066.32 seconds
Started Aug 06 06:07:00 PM PDT 24
Finished Aug 06 06:41:26 PM PDT 24
Peak memory 1145656 kb
Host smart-79767051-5aa8-41ca-ad25-a725ea7d0eba
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1133887218 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.1133887218 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_stress_all/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_kmac.3272542382
Short name T122
Test name
Test status
Simulation time 482402954 ps
CPU time 5.88 seconds
Started Aug 06 06:07:04 PM PDT 24
Finished Aug 06 06:07:10 PM PDT 24
Peak memory 219896 kb
Host smart-02809222-aacc-4e70-af7a-2570b13b3368
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272542382 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.kmac_test_vectors_kmac.3272542382 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_kmac_xof.4128509987
Short name T664
Test name
Test status
Simulation time 357717513 ps
CPU time 5.63 seconds
Started Aug 06 06:07:00 PM PDT 24
Finished Aug 06 06:07:05 PM PDT 24
Peak memory 226996 kb
Host smart-f0cf3592-8906-41c0-812f-bede2db575e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128509987 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.kmac_test_vectors_kmac_xof.4128509987 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_256.2614416962
Short name T223
Test name
Test status
Simulation time 19680720763 ps
CPU time 2146.37 seconds
Started Aug 06 06:06:44 PM PDT 24
Finished Aug 06 06:42:31 PM PDT 24
Peak memory 1110960 kb
Host smart-6b289812-2745-40db-adeb-343dbc4c6e32
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2614416962 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_256.2614416962 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_384.3410103483
Short name T663
Test name
Test status
Simulation time 49263974016 ps
CPU time 2477.43 seconds
Started Aug 06 06:07:01 PM PDT 24
Finished Aug 06 06:48:19 PM PDT 24
Peak memory 2383660 kb
Host smart-4370c3be-fb6a-4b78-a8b5-dd03ef51cde5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3410103483 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_384.3410103483 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_512.3056160663
Short name T724
Test name
Test status
Simulation time 43406135393 ps
CPU time 1758.98 seconds
Started Aug 06 06:06:59 PM PDT 24
Finished Aug 06 06:36:18 PM PDT 24
Peak memory 1737600 kb
Host smart-93ff0ace-18d7-436f-bdbc-f1bbb2e68444
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3056160663 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_512.3056160663 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/22.kmac_alert_test.2148569882
Short name T930
Test name
Test status
Simulation time 24860270 ps
CPU time 0.82 seconds
Started Aug 06 06:07:37 PM PDT 24
Finished Aug 06 06:07:38 PM PDT 24
Peak memory 218596 kb
Host smart-22219d78-c9ee-4b4c-9d77-bff9f6861337
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148569882 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.2148569882 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_alert_test/latest

Test location /workspace/coverage/default/22.kmac_app.3750070476
Short name T349
Test name
Test status
Simulation time 19212491008 ps
CPU time 388.67 seconds
Started Aug 06 06:07:19 PM PDT 24
Finished Aug 06 06:13:48 PM PDT 24
Peak memory 340128 kb
Host smart-72c0c0b7-1cdb-4dc5-bff8-822b5b5cd338
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750070476 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.3750070476 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/22.kmac_app/latest

Test location /workspace/coverage/default/22.kmac_burst_write.367025339
Short name T129
Test name
Test status
Simulation time 25508812141 ps
CPU time 1258.64 seconds
Started Aug 06 06:07:04 PM PDT 24
Finished Aug 06 06:28:03 PM PDT 24
Peak memory 262672 kb
Host smart-7458528b-67f9-4773-91d0-59c88aa42422
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367025339 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.367025339
+enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_burst_write/latest

Test location /workspace/coverage/default/22.kmac_entropy_refresh.879361712
Short name T365
Test name
Test status
Simulation time 133456659011 ps
CPU time 309.57 seconds
Started Aug 06 06:07:19 PM PDT 24
Finished Aug 06 06:12:28 PM PDT 24
Peak memory 425872 kb
Host smart-5d095fd2-0c26-41bc-a71f-de1288b36c9c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879361712 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.87
9361712 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/22.kmac_error.1695436731
Short name T668
Test name
Test status
Simulation time 12807403154 ps
CPU time 170.78 seconds
Started Aug 06 06:07:19 PM PDT 24
Finished Aug 06 06:10:10 PM PDT 24
Peak memory 373420 kb
Host smart-685d2091-8fd9-46f7-9cda-3a4c9684cd95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695436731 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.1695436731 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_error/latest

Test location /workspace/coverage/default/22.kmac_key_error.2199291879
Short name T487
Test name
Test status
Simulation time 1669771544 ps
CPU time 9.08 seconds
Started Aug 06 06:07:33 PM PDT 24
Finished Aug 06 06:07:42 PM PDT 24
Peak memory 226896 kb
Host smart-8a8a1c6f-64c7-4288-8ac2-3abceead9f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199291879 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.2199291879 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_key_error/latest

Test location /workspace/coverage/default/22.kmac_lc_escalation.1548589149
Short name T614
Test name
Test status
Simulation time 361165520 ps
CPU time 9.12 seconds
Started Aug 06 06:07:32 PM PDT 24
Finished Aug 06 06:07:42 PM PDT 24
Peak memory 235904 kb
Host smart-1221b32e-99f1-4c40-a7ca-66c542b3f0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548589149 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.1548589149 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/22.kmac_lc_escalation/latest

Test location /workspace/coverage/default/22.kmac_long_msg_and_output.1138181695
Short name T952
Test name
Test status
Simulation time 52423622730 ps
CPU time 2182.52 seconds
Started Aug 06 06:07:00 PM PDT 24
Finished Aug 06 06:43:23 PM PDT 24
Peak memory 2259032 kb
Host smart-87ca3caa-7650-42aa-97f4-9862e83fdcfd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138181695 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_a
nd_output.1138181695 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/22.kmac_sideload.1084274218
Short name T793
Test name
Test status
Simulation time 3433901679 ps
CPU time 276.31 seconds
Started Aug 06 06:07:03 PM PDT 24
Finished Aug 06 06:11:39 PM PDT 24
Peak memory 318032 kb
Host smart-639bacd5-6b0c-409a-8eac-03dd44d3ee7d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084274218 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.1084274218 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_sideload/latest

Test location /workspace/coverage/default/22.kmac_smoke.2941407790
Short name T167
Test name
Test status
Simulation time 336297313 ps
CPU time 7.61 seconds
Started Aug 06 06:06:58 PM PDT 24
Finished Aug 06 06:07:06 PM PDT 24
Peak memory 227040 kb
Host smart-ac733a55-6c23-4582-81a2-e471b6dfc53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941407790 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.2941407790 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_smoke/latest

Test location /workspace/coverage/default/22.kmac_stress_all.4035851495
Short name T696
Test name
Test status
Simulation time 139499505241 ps
CPU time 1040.18 seconds
Started Aug 06 06:07:31 PM PDT 24
Finished Aug 06 06:24:52 PM PDT 24
Peak memory 1059980 kb
Host smart-aadce390-140a-4471-a63e-21b4ba2ff968
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4035851495 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.4035851495 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_stress_all/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_kmac.3911770403
Short name T373
Test name
Test status
Simulation time 236860127 ps
CPU time 5.62 seconds
Started Aug 06 06:07:17 PM PDT 24
Finished Aug 06 06:07:22 PM PDT 24
Peak memory 227072 kb
Host smart-502b2d63-a222-48d6-b93d-57419076dc94
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911770403 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.kmac_test_vectors_kmac.3911770403 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_kmac_xof.3097484524
Short name T206
Test name
Test status
Simulation time 1004708738 ps
CPU time 6.3 seconds
Started Aug 06 06:07:19 PM PDT 24
Finished Aug 06 06:07:26 PM PDT 24
Peak memory 227096 kb
Host smart-a9f22aa8-fd7b-40e1-a054-77f1d397480f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097484524 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.kmac_test_vectors_kmac_xof.3097484524 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_224.4097968601
Short name T861
Test name
Test status
Simulation time 85965267805 ps
CPU time 3535.71 seconds
Started Aug 06 06:07:01 PM PDT 24
Finished Aug 06 07:05:57 PM PDT 24
Peak memory 3204776 kb
Host smart-b84b1f2e-ac8c-410c-a905-cc070e27bfb6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4097968601 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_224.4097968601 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_256.1876683758
Short name T813
Test name
Test status
Simulation time 21306732411 ps
CPU time 2046.75 seconds
Started Aug 06 06:06:59 PM PDT 24
Finished Aug 06 06:41:06 PM PDT 24
Peak memory 1125652 kb
Host smart-af7944bc-d1db-4f39-867e-0efe04a040cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1876683758 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_256.1876683758 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_384.1043969169
Short name T596
Test name
Test status
Simulation time 58990096035 ps
CPU time 1599.61 seconds
Started Aug 06 06:07:18 PM PDT 24
Finished Aug 06 06:33:58 PM PDT 24
Peak memory 921840 kb
Host smart-58932edb-8e07-40a2-a1bc-362ebe9efd82
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1043969169 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_384.1043969169 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_512.2299501954
Short name T124
Test name
Test status
Simulation time 238963531745 ps
CPU time 1632.41 seconds
Started Aug 06 06:07:18 PM PDT 24
Finished Aug 06 06:34:31 PM PDT 24
Peak memory 1741288 kb
Host smart-52b79fc7-7d5a-45f5-9242-bc8eb1954288
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2299501954 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_512.2299501954 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_shake_128.1618759687
Short name T751
Test name
Test status
Simulation time 250072634748 ps
CPU time 6499.73 seconds
Started Aug 06 06:07:20 PM PDT 24
Finished Aug 06 07:55:40 PM PDT 24
Peak memory 2694552 kb
Host smart-cead6777-ab06-4968-a550-3175afca5976
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1618759687 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_128.1618759687 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_shake_256.1042331485
Short name T317
Test name
Test status
Simulation time 65963358471 ps
CPU time 5693 seconds
Started Aug 06 06:07:18 PM PDT 24
Finished Aug 06 07:42:12 PM PDT 24
Peak memory 2245236 kb
Host smart-880b1b55-b187-4e5b-92d1-0767d8b392d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1042331485 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_256.1042331485 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/23.kmac_alert_test.291920516
Short name T802
Test name
Test status
Simulation time 39156440 ps
CPU time 0.75 seconds
Started Aug 06 06:07:48 PM PDT 24
Finished Aug 06 06:07:49 PM PDT 24
Peak memory 218600 kb
Host smart-e6674514-1f1e-4d6b-83de-dd917d508a6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291920516 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.291920516 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/23.kmac_alert_test/latest

Test location /workspace/coverage/default/23.kmac_app.1052376215
Short name T830
Test name
Test status
Simulation time 6095576122 ps
CPU time 190.75 seconds
Started Aug 06 06:07:33 PM PDT 24
Finished Aug 06 06:10:44 PM PDT 24
Peak memory 283304 kb
Host smart-c3759194-e71b-4400-b318-194b91c714b1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052376215 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.1052376215 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/23.kmac_app/latest

Test location /workspace/coverage/default/23.kmac_burst_write.3278157758
Short name T544
Test name
Test status
Simulation time 76401066444 ps
CPU time 528.88 seconds
Started Aug 06 06:07:32 PM PDT 24
Finished Aug 06 06:16:21 PM PDT 24
Peak memory 244148 kb
Host smart-c806563e-2315-4b4e-a103-79ece916cd34
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278157758 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.327815775
8 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_burst_write/latest

Test location /workspace/coverage/default/23.kmac_entropy_refresh.2963382345
Short name T276
Test name
Test status
Simulation time 5813050251 ps
CPU time 154.52 seconds
Started Aug 06 06:07:33 PM PDT 24
Finished Aug 06 06:10:07 PM PDT 24
Peak memory 324612 kb
Host smart-5159a967-6a31-4eef-a213-0ddf5d051361
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963382345 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.2
963382345 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/23.kmac_error.3988000961
Short name T812
Test name
Test status
Simulation time 1935236856 ps
CPU time 161.28 seconds
Started Aug 06 06:07:33 PM PDT 24
Finished Aug 06 06:10:14 PM PDT 24
Peak memory 287852 kb
Host smart-385cf9b3-1061-4fd2-9fb9-c30581096bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988000961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.3988000961 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_error/latest

Test location /workspace/coverage/default/23.kmac_key_error.670679398
Short name T650
Test name
Test status
Simulation time 141922392 ps
CPU time 1.8 seconds
Started Aug 06 06:07:47 PM PDT 24
Finished Aug 06 06:07:49 PM PDT 24
Peak memory 218804 kb
Host smart-416b43ed-f2be-4218-b356-e76b132777e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670679398 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.670679398 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_key_error/latest

Test location /workspace/coverage/default/23.kmac_lc_escalation.1365021533
Short name T24
Test name
Test status
Simulation time 57453969 ps
CPU time 1.24 seconds
Started Aug 06 06:07:47 PM PDT 24
Finished Aug 06 06:07:48 PM PDT 24
Peak memory 226888 kb
Host smart-d1e0b5dd-e9bc-40c8-9ba9-8f5682e86799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365021533 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.1365021533 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/23.kmac_lc_escalation/latest

Test location /workspace/coverage/default/23.kmac_sideload.4077054793
Short name T841
Test name
Test status
Simulation time 79217958750 ps
CPU time 551.19 seconds
Started Aug 06 06:07:31 PM PDT 24
Finished Aug 06 06:16:42 PM PDT 24
Peak memory 644404 kb
Host smart-7a18511c-1d09-4cc3-84fa-003aafee34fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077054793 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.4077054793 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_sideload/latest

Test location /workspace/coverage/default/23.kmac_smoke.3006952214
Short name T538
Test name
Test status
Simulation time 8829318320 ps
CPU time 76.03 seconds
Started Aug 06 06:07:31 PM PDT 24
Finished Aug 06 06:08:47 PM PDT 24
Peak memory 227224 kb
Host smart-a1d71f8c-b430-4bf3-b3d6-ef93538d3482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006952214 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.3006952214 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_smoke/latest

Test location /workspace/coverage/default/23.kmac_stress_all.3726396991
Short name T152
Test name
Test status
Simulation time 5302285400 ps
CPU time 82.54 seconds
Started Aug 06 06:07:47 PM PDT 24
Finished Aug 06 06:09:10 PM PDT 24
Peak memory 252124 kb
Host smart-226376f6-c5be-49ca-b535-734c9f89f823
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3726396991 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.3726396991 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_stress_all/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_kmac.1438275160
Short name T226
Test name
Test status
Simulation time 379182041 ps
CPU time 5.62 seconds
Started Aug 06 06:07:34 PM PDT 24
Finished Aug 06 06:07:39 PM PDT 24
Peak memory 219792 kb
Host smart-f7cad0ff-b519-4e81-8f5b-2198285e36b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438275160 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.kmac_test_vectors_kmac.1438275160 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_kmac_xof.3434905265
Short name T510
Test name
Test status
Simulation time 419830454 ps
CPU time 5.97 seconds
Started Aug 06 06:07:33 PM PDT 24
Finished Aug 06 06:07:39 PM PDT 24
Peak memory 227028 kb
Host smart-cdd89253-ffd9-4d5e-b897-6a7a8816ff1e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434905265 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.kmac_test_vectors_kmac_xof.3434905265 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_224.3030197579
Short name T298
Test name
Test status
Simulation time 262212910173 ps
CPU time 3435.08 seconds
Started Aug 06 06:07:32 PM PDT 24
Finished Aug 06 07:04:48 PM PDT 24
Peak memory 3228820 kb
Host smart-b32244fc-4531-44c6-afd3-9df3674cd56c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3030197579 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_224.3030197579 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_256.4280156643
Short name T299
Test name
Test status
Simulation time 89295134407 ps
CPU time 2143.45 seconds
Started Aug 06 06:07:31 PM PDT 24
Finished Aug 06 06:43:15 PM PDT 24
Peak memory 1155980 kb
Host smart-41a203fc-dc6a-4e1c-9bf3-5078e0432692
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4280156643 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_256.4280156643 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_384.2356125474
Short name T839
Test name
Test status
Simulation time 14881639076 ps
CPU time 1569.91 seconds
Started Aug 06 06:07:32 PM PDT 24
Finished Aug 06 06:33:43 PM PDT 24
Peak memory 914668 kb
Host smart-68a65f7b-0fa8-4c70-929a-5f77bb5f87a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2356125474 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_384.2356125474 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_512.2948536173
Short name T526
Test name
Test status
Simulation time 34436373541 ps
CPU time 1537.13 seconds
Started Aug 06 06:07:39 PM PDT 24
Finished Aug 06 06:33:17 PM PDT 24
Peak memory 1762292 kb
Host smart-8ac76dbc-42b8-4ba5-9ac8-389db4b6fe69
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2948536173 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_512.2948536173 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_shake_128.3816253459
Short name T192
Test name
Test status
Simulation time 62606882899 ps
CPU time 6475.36 seconds
Started Aug 06 06:07:32 PM PDT 24
Finished Aug 06 07:55:29 PM PDT 24
Peak memory 2752672 kb
Host smart-ab7b19b9-4937-48b9-8a60-5c6c581d4dae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3816253459 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_128.3816253459 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/24.kmac_alert_test.3336949513
Short name T924
Test name
Test status
Simulation time 19866932 ps
CPU time 0.89 seconds
Started Aug 06 06:08:00 PM PDT 24
Finished Aug 06 06:08:01 PM PDT 24
Peak memory 218636 kb
Host smart-813485a5-0848-4d7d-8455-e3d6cbdcd00a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336949513 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.3336949513 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_alert_test/latest

Test location /workspace/coverage/default/24.kmac_app.3061268329
Short name T869
Test name
Test status
Simulation time 26309693086 ps
CPU time 202.85 seconds
Started Aug 06 06:08:01 PM PDT 24
Finished Aug 06 06:11:24 PM PDT 24
Peak memory 381384 kb
Host smart-8c0c9ccd-4ead-40e1-b180-3cb21ae61339
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061268329 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.3061268329 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/24.kmac_app/latest

Test location /workspace/coverage/default/24.kmac_burst_write.4239942759
Short name T390
Test name
Test status
Simulation time 20110215460 ps
CPU time 1069.87 seconds
Started Aug 06 06:07:48 PM PDT 24
Finished Aug 06 06:25:38 PM PDT 24
Peak memory 242916 kb
Host smart-936bf916-62cc-48e8-a0c0-7c8010248d27
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239942759 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.423994275
9 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_burst_write/latest

Test location /workspace/coverage/default/24.kmac_entropy_refresh.409669121
Short name T981
Test name
Test status
Simulation time 14621227993 ps
CPU time 143.29 seconds
Started Aug 06 06:08:01 PM PDT 24
Finished Aug 06 06:10:24 PM PDT 24
Peak memory 315048 kb
Host smart-08feb744-058b-4d00-a545-16ed2e975535
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409669121 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.40
9669121 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/24.kmac_error.4070159535
Short name T457
Test name
Test status
Simulation time 57803745528 ps
CPU time 269.69 seconds
Started Aug 06 06:08:00 PM PDT 24
Finished Aug 06 06:12:30 PM PDT 24
Peak memory 432124 kb
Host smart-2803f712-75f3-44c7-9c63-9109a0f59160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070159535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.4070159535 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_error/latest

Test location /workspace/coverage/default/24.kmac_key_error.2027474086
Short name T184
Test name
Test status
Simulation time 2196701269 ps
CPU time 7.83 seconds
Started Aug 06 06:08:02 PM PDT 24
Finished Aug 06 06:08:10 PM PDT 24
Peak memory 227004 kb
Host smart-3e879647-6b24-45df-9008-d4dd73b0a553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027474086 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.2027474086 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_key_error/latest

Test location /workspace/coverage/default/24.kmac_lc_escalation.1092504465
Short name T508
Test name
Test status
Simulation time 169929745 ps
CPU time 1.4 seconds
Started Aug 06 06:08:01 PM PDT 24
Finished Aug 06 06:08:02 PM PDT 24
Peak memory 227116 kb
Host smart-65c270ac-b652-49c6-8b34-ea02f128dcb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092504465 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.1092504465 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/24.kmac_lc_escalation/latest

Test location /workspace/coverage/default/24.kmac_sideload.3239678257
Short name T787
Test name
Test status
Simulation time 19509227469 ps
CPU time 540.3 seconds
Started Aug 06 06:07:48 PM PDT 24
Finished Aug 06 06:16:48 PM PDT 24
Peak memory 647472 kb
Host smart-b14dcf12-f007-4e6e-a75d-6eba8a3bfba9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239678257 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.3239678257 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_sideload/latest

Test location /workspace/coverage/default/24.kmac_smoke.1560169698
Short name T278
Test name
Test status
Simulation time 3619950566 ps
CPU time 69.93 seconds
Started Aug 06 06:07:46 PM PDT 24
Finished Aug 06 06:08:56 PM PDT 24
Peak memory 227108 kb
Host smart-d0f3b4e6-ad30-4f27-8581-29e99ac43495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560169698 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.1560169698 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_smoke/latest

Test location /workspace/coverage/default/24.kmac_stress_all.2584016817
Short name T906
Test name
Test status
Simulation time 9569737034 ps
CPU time 233.5 seconds
Started Aug 06 06:08:00 PM PDT 24
Finished Aug 06 06:11:54 PM PDT 24
Peak memory 251136 kb
Host smart-d6356df1-68eb-4afd-9c15-8501e9bd909f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2584016817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.2584016817 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_stress_all/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_kmac.3468613663
Short name T293
Test name
Test status
Simulation time 759479347 ps
CPU time 6.23 seconds
Started Aug 06 06:08:00 PM PDT 24
Finished Aug 06 06:08:06 PM PDT 24
Peak memory 226996 kb
Host smart-03528f8d-5405-455b-a092-50c6c8996665
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468613663 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.kmac_test_vectors_kmac.3468613663 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_kmac_xof.4231734245
Short name T325
Test name
Test status
Simulation time 109228653 ps
CPU time 5.57 seconds
Started Aug 06 06:08:02 PM PDT 24
Finished Aug 06 06:08:07 PM PDT 24
Peak memory 219920 kb
Host smart-666901b3-f34d-455d-b594-d4a6de9e1ddf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231734245 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.kmac_test_vectors_kmac_xof.4231734245 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_224.3395532208
Short name T423
Test name
Test status
Simulation time 157661830201 ps
CPU time 2247.37 seconds
Started Aug 06 06:07:46 PM PDT 24
Finished Aug 06 06:45:14 PM PDT 24
Peak memory 1218736 kb
Host smart-83a1486f-dc33-4844-9a6f-11528ff81555
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3395532208 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_224.3395532208 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_256.1183812064
Short name T532
Test name
Test status
Simulation time 487734043949 ps
CPU time 3209.83 seconds
Started Aug 06 06:07:48 PM PDT 24
Finished Aug 06 07:01:18 PM PDT 24
Peak memory 3111624 kb
Host smart-52806ccc-4087-4627-becd-4fb298784b9c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1183812064 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_256.1183812064 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_384.79648253
Short name T429
Test name
Test status
Simulation time 252025110299 ps
CPU time 2727.58 seconds
Started Aug 06 06:07:47 PM PDT 24
Finished Aug 06 06:53:15 PM PDT 24
Peak memory 2405872 kb
Host smart-ebfa1c83-d8d4-48c9-baff-ffa6de0388ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=79648253 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_384.79648253 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_512.2312605138
Short name T612
Test name
Test status
Simulation time 215358175868 ps
CPU time 2031.04 seconds
Started Aug 06 06:07:47 PM PDT 24
Finished Aug 06 06:41:38 PM PDT 24
Peak memory 1739992 kb
Host smart-6ef58f49-ea75-4df9-9595-23ce069486c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2312605138 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_512.2312605138 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_shake_256.105936536
Short name T677
Test name
Test status
Simulation time 1039631406290 ps
CPU time 5872.81 seconds
Started Aug 06 06:08:02 PM PDT 24
Finished Aug 06 07:45:56 PM PDT 24
Peak memory 2189224 kb
Host smart-bfc2f635-f921-4256-942c-05638d66a320
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=105936536 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_256.105936536 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/25.kmac_alert_test.985203940
Short name T337
Test name
Test status
Simulation time 55495474 ps
CPU time 0.82 seconds
Started Aug 06 06:08:29 PM PDT 24
Finished Aug 06 06:08:30 PM PDT 24
Peak memory 218608 kb
Host smart-eef3a4f5-3475-4c47-a041-9d1acd881b9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985203940 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.985203940 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/25.kmac_alert_test/latest

Test location /workspace/coverage/default/25.kmac_app.2462672479
Short name T164
Test name
Test status
Simulation time 76199380081 ps
CPU time 165.3 seconds
Started Aug 06 06:08:11 PM PDT 24
Finished Aug 06 06:10:57 PM PDT 24
Peak memory 311492 kb
Host smart-fc5e3973-4404-4348-beb8-8a960fec50d9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462672479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.2462672479 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/25.kmac_app/latest

Test location /workspace/coverage/default/25.kmac_burst_write.2269323319
Short name T288
Test name
Test status
Simulation time 18925684221 ps
CPU time 986.02 seconds
Started Aug 06 06:08:01 PM PDT 24
Finished Aug 06 06:24:27 PM PDT 24
Peak memory 243588 kb
Host smart-d6487f7c-c162-4b54-9384-a7dffd4fb777
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269323319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.226932331
9 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_burst_write/latest

Test location /workspace/coverage/default/25.kmac_entropy_refresh.1162099156
Short name T982
Test name
Test status
Simulation time 1323077982 ps
CPU time 17.14 seconds
Started Aug 06 06:08:12 PM PDT 24
Finished Aug 06 06:08:29 PM PDT 24
Peak memory 228992 kb
Host smart-1f10a7a4-0e55-4adf-ab43-6417b3c257b7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162099156 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.1
162099156 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/25.kmac_error.4167052942
Short name T977
Test name
Test status
Simulation time 13000017162 ps
CPU time 252.59 seconds
Started Aug 06 06:08:23 PM PDT 24
Finished Aug 06 06:12:36 PM PDT 24
Peak memory 325360 kb
Host smart-844b24bf-566e-486b-b47a-e4b96b0f49a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167052942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_error.4167052942 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_error/latest

Test location /workspace/coverage/default/25.kmac_key_error.1193428483
Short name T5
Test name
Test status
Simulation time 2078621125 ps
CPU time 8.7 seconds
Started Aug 06 06:08:25 PM PDT 24
Finished Aug 06 06:08:34 PM PDT 24
Peak memory 226852 kb
Host smart-4de0ec25-a0b8-427f-b3d1-8dba77cd8018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193428483 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.1193428483 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_key_error/latest

Test location /workspace/coverage/default/25.kmac_lc_escalation.2842016465
Short name T452
Test name
Test status
Simulation time 70181345 ps
CPU time 1.49 seconds
Started Aug 06 06:08:25 PM PDT 24
Finished Aug 06 06:08:26 PM PDT 24
Peak memory 226952 kb
Host smart-6ec6bd9b-c221-4304-a7d4-9865b26233fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842016465 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.2842016465 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/25.kmac_lc_escalation/latest

Test location /workspace/coverage/default/25.kmac_long_msg_and_output.3168169051
Short name T611
Test name
Test status
Simulation time 12680051906 ps
CPU time 1713.94 seconds
Started Aug 06 06:08:02 PM PDT 24
Finished Aug 06 06:36:36 PM PDT 24
Peak memory 962312 kb
Host smart-964794a2-b9af-4096-a4e3-6e4732ee16bb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168169051 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_a
nd_output.3168169051 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/25.kmac_sideload.1644772629
Short name T916
Test name
Test status
Simulation time 2001885477 ps
CPU time 147.28 seconds
Started Aug 06 06:08:00 PM PDT 24
Finished Aug 06 06:10:27 PM PDT 24
Peak memory 270780 kb
Host smart-1a35a0b0-e877-450e-b4e3-64ee3479b0ec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644772629 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.1644772629 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_sideload/latest

Test location /workspace/coverage/default/25.kmac_smoke.1475347584
Short name T435
Test name
Test status
Simulation time 3051632459 ps
CPU time 36.94 seconds
Started Aug 06 06:08:00 PM PDT 24
Finished Aug 06 06:08:37 PM PDT 24
Peak memory 227160 kb
Host smart-f98e2e05-0f91-41fc-9660-4a7dcbced86e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475347584 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.1475347584 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_smoke/latest

Test location /workspace/coverage/default/25.kmac_stress_all.2270938498
Short name T680
Test name
Test status
Simulation time 38231056000 ps
CPU time 1229.36 seconds
Started Aug 06 06:08:23 PM PDT 24
Finished Aug 06 06:28:52 PM PDT 24
Peak memory 504248 kb
Host smart-03741243-0361-4d63-8c35-b46069413c23
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2270938498 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.2270938498 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_stress_all/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_kmac.4084824500
Short name T41
Test name
Test status
Simulation time 1039180787 ps
CPU time 6.24 seconds
Started Aug 06 06:08:12 PM PDT 24
Finished Aug 06 06:08:18 PM PDT 24
Peak memory 227024 kb
Host smart-da2fab51-1207-4e82-91e0-8266823b5051
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084824500 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.kmac_test_vectors_kmac.4084824500 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_kmac_xof.2273509463
Short name T413
Test name
Test status
Simulation time 621462010 ps
CPU time 7.24 seconds
Started Aug 06 06:08:16 PM PDT 24
Finished Aug 06 06:08:23 PM PDT 24
Peak memory 220228 kb
Host smart-f94e83d5-6949-421d-8b08-683956f3df77
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273509463 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.kmac_test_vectors_kmac_xof.2273509463 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_224.532762123
Short name T868
Test name
Test status
Simulation time 258626145204 ps
CPU time 3182.26 seconds
Started Aug 06 06:08:13 PM PDT 24
Finished Aug 06 07:01:15 PM PDT 24
Peak memory 3173684 kb
Host smart-77e2b68c-2a5b-4ce8-b961-18520c484870
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=532762123 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_224.532762123 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_256.4055738576
Short name T335
Test name
Test status
Simulation time 61369390531 ps
CPU time 2748.15 seconds
Started Aug 06 06:08:12 PM PDT 24
Finished Aug 06 06:54:01 PM PDT 24
Peak memory 3007108 kb
Host smart-849cce47-7573-460c-861f-55d4f3e843ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4055738576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_256.4055738576 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_384.3258699915
Short name T682
Test name
Test status
Simulation time 130189123103 ps
CPU time 2564.69 seconds
Started Aug 06 06:08:16 PM PDT 24
Finished Aug 06 06:51:01 PM PDT 24
Peak memory 2447780 kb
Host smart-03b81306-26b2-4751-95b9-818c1d99da22
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3258699915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_384.3258699915 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_512.1972527369
Short name T662
Test name
Test status
Simulation time 32962536177 ps
CPU time 1701.6 seconds
Started Aug 06 06:08:15 PM PDT 24
Finished Aug 06 06:36:37 PM PDT 24
Peak memory 1707388 kb
Host smart-c68bf7cd-7be1-49fb-a7f1-7f866d74f04a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1972527369 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_512.1972527369 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_shake_128.3640286839
Short name T553
Test name
Test status
Simulation time 128698140179 ps
CPU time 6273.82 seconds
Started Aug 06 06:08:14 PM PDT 24
Finished Aug 06 07:52:48 PM PDT 24
Peak memory 2685464 kb
Host smart-1ada39ab-ec29-480d-a6f1-8cd2a60030ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3640286839 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_128.3640286839 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_shake_256.344993417
Short name T879
Test name
Test status
Simulation time 109771867649 ps
CPU time 5123.16 seconds
Started Aug 06 06:08:12 PM PDT 24
Finished Aug 06 07:33:35 PM PDT 24
Peak memory 2241984 kb
Host smart-dba3fbf7-32a3-4b79-9f4c-dcb537778349
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=344993417 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_256.344993417 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/26.kmac_alert_test.3775544375
Short name T683
Test name
Test status
Simulation time 49762084 ps
CPU time 0.82 seconds
Started Aug 06 06:08:56 PM PDT 24
Finished Aug 06 06:08:56 PM PDT 24
Peak memory 218488 kb
Host smart-99925be6-90e8-401e-b096-84680cdb51d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775544375 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.3775544375 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_alert_test/latest

Test location /workspace/coverage/default/26.kmac_app.1968289887
Short name T960
Test name
Test status
Simulation time 982502326 ps
CPU time 56.78 seconds
Started Aug 06 06:08:39 PM PDT 24
Finished Aug 06 06:09:36 PM PDT 24
Peak memory 241024 kb
Host smart-c6326a38-d9d7-4457-9b07-7803f0c76cae
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968289887 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.1968289887 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/26.kmac_app/latest

Test location /workspace/coverage/default/26.kmac_burst_write.361470410
Short name T249
Test name
Test status
Simulation time 31856023324 ps
CPU time 1450.77 seconds
Started Aug 06 06:08:23 PM PDT 24
Finished Aug 06 06:32:34 PM PDT 24
Peak memory 266404 kb
Host smart-091e54af-f765-4246-b9a6-03db2c91e606
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361470410 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.361470410
+enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_burst_write/latest

Test location /workspace/coverage/default/26.kmac_entropy_refresh.481064418
Short name T189
Test name
Test status
Simulation time 44888002413 ps
CPU time 267.32 seconds
Started Aug 06 06:08:38 PM PDT 24
Finished Aug 06 06:13:06 PM PDT 24
Peak memory 406396 kb
Host smart-f97b94e5-d8c3-44d2-b4c3-b62ec4b58e49
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481064418 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.48
1064418 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/26.kmac_error.1764695125
Short name T983
Test name
Test status
Simulation time 6467739616 ps
CPU time 219.55 seconds
Started Aug 06 06:08:39 PM PDT 24
Finished Aug 06 06:12:19 PM PDT 24
Peak memory 400424 kb
Host smart-527e957a-840f-4ff3-97cb-9cda1f9cfd5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764695125 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.1764695125 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_error/latest

Test location /workspace/coverage/default/26.kmac_key_error.1627287206
Short name T496
Test name
Test status
Simulation time 3504630865 ps
CPU time 12.91 seconds
Started Aug 06 06:08:37 PM PDT 24
Finished Aug 06 06:08:50 PM PDT 24
Peak memory 227060 kb
Host smart-88a1a8a0-ae07-493c-a3af-c26a55c528d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627287206 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.1627287206 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_key_error/latest

Test location /workspace/coverage/default/26.kmac_lc_escalation.1202762357
Short name T932
Test name
Test status
Simulation time 2496760719 ps
CPU time 14.75 seconds
Started Aug 06 06:08:37 PM PDT 24
Finished Aug 06 06:08:52 PM PDT 24
Peak memory 241508 kb
Host smart-dbc600c6-d579-48bc-9ea6-19b1d9da9a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202762357 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.1202762357 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/26.kmac_lc_escalation/latest

Test location /workspace/coverage/default/26.kmac_long_msg_and_output.779389010
Short name T894
Test name
Test status
Simulation time 139520507639 ps
CPU time 3002.51 seconds
Started Aug 06 06:08:24 PM PDT 24
Finished Aug 06 06:58:27 PM PDT 24
Peak memory 2721072 kb
Host smart-07661785-b2ad-4739-94ee-db500ebe5c51
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779389010 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_an
d_output.779389010 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/26.kmac_sideload.155128688
Short name T339
Test name
Test status
Simulation time 57596063897 ps
CPU time 496.59 seconds
Started Aug 06 06:08:25 PM PDT 24
Finished Aug 06 06:16:41 PM PDT 24
Peak memory 600436 kb
Host smart-5cd213e7-42fa-40aa-8065-69b8a66b3603
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155128688 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.155128688 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_sideload/latest

Test location /workspace/coverage/default/26.kmac_smoke.2083250387
Short name T959
Test name
Test status
Simulation time 1679485656 ps
CPU time 56.2 seconds
Started Aug 06 06:08:25 PM PDT 24
Finished Aug 06 06:09:21 PM PDT 24
Peak memory 226856 kb
Host smart-bebecaf3-d006-4170-b8c2-7b87053d79fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083250387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.2083250387 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_smoke/latest

Test location /workspace/coverage/default/26.kmac_stress_all.2603809561
Short name T283
Test name
Test status
Simulation time 18129374263 ps
CPU time 1482.01 seconds
Started Aug 06 06:09:02 PM PDT 24
Finished Aug 06 06:33:44 PM PDT 24
Peak memory 599588 kb
Host smart-f4494e1d-0afb-48dc-b52d-ebfd878dd401
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2603809561 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.2603809561 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_stress_all/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_kmac.2274541662
Short name T170
Test name
Test status
Simulation time 213707471 ps
CPU time 6.27 seconds
Started Aug 06 06:08:37 PM PDT 24
Finished Aug 06 06:08:43 PM PDT 24
Peak memory 227056 kb
Host smart-6c9a68a1-b63d-4f8c-8126-dbe7e956f5be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274541662 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.kmac_test_vectors_kmac.2274541662 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_kmac_xof.904067380
Short name T247
Test name
Test status
Simulation time 120332948 ps
CPU time 5.75 seconds
Started Aug 06 06:08:38 PM PDT 24
Finished Aug 06 06:08:44 PM PDT 24
Peak memory 219064 kb
Host smart-a7dd4cab-b8c4-49e7-ac09-38294174dc5d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904067380 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 26.kmac_test_vectors_kmac_xof.904067380 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_224.2708911653
Short name T522
Test name
Test status
Simulation time 284338622879 ps
CPU time 3298 seconds
Started Aug 06 06:08:23 PM PDT 24
Finished Aug 06 07:03:22 PM PDT 24
Peak memory 3261676 kb
Host smart-81f0dbc8-69c6-436e-8845-797da697a826
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2708911653 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_224.2708911653 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_384.3170913453
Short name T773
Test name
Test status
Simulation time 286771150181 ps
CPU time 2777.23 seconds
Started Aug 06 06:08:23 PM PDT 24
Finished Aug 06 06:54:40 PM PDT 24
Peak memory 2422500 kb
Host smart-044d129e-c6c9-468d-b028-038fa432a16d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3170913453 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_384.3170913453 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_512.3153475882
Short name T369
Test name
Test status
Simulation time 44506404475 ps
CPU time 1378.48 seconds
Started Aug 06 06:08:23 PM PDT 24
Finished Aug 06 06:31:22 PM PDT 24
Peak memory 720964 kb
Host smart-f0fde3ca-a782-4b48-879b-8ccadead307c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3153475882 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_512.3153475882 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_shake_128.301012130
Short name T803
Test name
Test status
Simulation time 246857453996 ps
CPU time 6180.67 seconds
Started Aug 06 06:08:25 PM PDT 24
Finished Aug 06 07:51:27 PM PDT 24
Peak memory 2668940 kb
Host smart-f3804a4a-621e-4764-818f-e0024d48c45b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=301012130 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_128.301012130 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/27.kmac_alert_test.3205818512
Short name T506
Test name
Test status
Simulation time 20347815 ps
CPU time 0.82 seconds
Started Aug 06 06:09:18 PM PDT 24
Finished Aug 06 06:09:19 PM PDT 24
Peak memory 218516 kb
Host smart-ea060668-7dcf-4adf-9e47-e82c21e3e2c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205818512 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.3205818512 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_alert_test/latest

Test location /workspace/coverage/default/27.kmac_app.3279197030
Short name T798
Test name
Test status
Simulation time 8833125375 ps
CPU time 280.86 seconds
Started Aug 06 06:09:18 PM PDT 24
Finished Aug 06 06:13:59 PM PDT 24
Peak memory 314608 kb
Host smart-30e650e4-ab04-4cc3-8f35-593f76097652
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279197030 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.3279197030 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/27.kmac_app/latest

Test location /workspace/coverage/default/27.kmac_burst_write.3670973770
Short name T937
Test name
Test status
Simulation time 11028001712 ps
CPU time 1053.45 seconds
Started Aug 06 06:08:55 PM PDT 24
Finished Aug 06 06:26:28 PM PDT 24
Peak memory 243332 kb
Host smart-5551d0e6-94a6-451e-9eea-34dd68285848
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670973770 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.367097377
0 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_burst_write/latest

Test location /workspace/coverage/default/27.kmac_entropy_refresh.3732006601
Short name T70
Test name
Test status
Simulation time 12528725551 ps
CPU time 74.58 seconds
Started Aug 06 06:09:17 PM PDT 24
Finished Aug 06 06:10:31 PM PDT 24
Peak memory 260740 kb
Host smart-941dea27-28d9-4f44-a9a0-7b5c828ef4f5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732006601 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.3
732006601 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/27.kmac_error.3636829148
Short name T781
Test name
Test status
Simulation time 6521863703 ps
CPU time 205.6 seconds
Started Aug 06 06:09:16 PM PDT 24
Finished Aug 06 06:12:42 PM PDT 24
Peak memory 310416 kb
Host smart-5df2b5c2-244c-4b3d-b7fb-a40d399abb6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636829148 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.3636829148 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_error/latest

Test location /workspace/coverage/default/27.kmac_key_error.3311459402
Short name T646
Test name
Test status
Simulation time 2144759573 ps
CPU time 5.33 seconds
Started Aug 06 06:09:17 PM PDT 24
Finished Aug 06 06:09:23 PM PDT 24
Peak memory 226824 kb
Host smart-2caab348-d2c5-4fd4-87af-7740ea98caaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311459402 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.3311459402 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_key_error/latest

Test location /workspace/coverage/default/27.kmac_long_msg_and_output.175884767
Short name T756
Test name
Test status
Simulation time 38618613724 ps
CPU time 1091.23 seconds
Started Aug 06 06:08:55 PM PDT 24
Finished Aug 06 06:27:07 PM PDT 24
Peak memory 798656 kb
Host smart-009c59ea-539b-4a21-b572-884fb8ae40e8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175884767 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_an
d_output.175884767 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/27.kmac_sideload.353849026
Short name T670
Test name
Test status
Simulation time 2579123241 ps
CPU time 103.03 seconds
Started Aug 06 06:08:55 PM PDT 24
Finished Aug 06 06:10:38 PM PDT 24
Peak memory 259404 kb
Host smart-1a0859f5-60f6-461e-b9b4-90dfb06f622b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353849026 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.353849026 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_sideload/latest

Test location /workspace/coverage/default/27.kmac_smoke.28015372
Short name T399
Test name
Test status
Simulation time 586694086 ps
CPU time 20.04 seconds
Started Aug 06 06:08:56 PM PDT 24
Finished Aug 06 06:09:16 PM PDT 24
Peak memory 226624 kb
Host smart-1841aa36-4fdb-43e3-818f-866006cca656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28015372 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.28015372 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_smoke/latest

Test location /workspace/coverage/default/27.kmac_stress_all.184069537
Short name T78
Test name
Test status
Simulation time 19907467377 ps
CPU time 614.8 seconds
Started Aug 06 06:09:15 PM PDT 24
Finished Aug 06 06:19:30 PM PDT 24
Peak memory 671856 kb
Host smart-ad87dd00-68b9-4a58-af8c-3853f11f7861
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=184069537 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all.184069537 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_stress_all/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_kmac.263348278
Short name T974
Test name
Test status
Simulation time 1002121910 ps
CPU time 7.31 seconds
Started Aug 06 06:09:18 PM PDT 24
Finished Aug 06 06:09:26 PM PDT 24
Peak memory 227008 kb
Host smart-ac9177c5-e21c-419b-87f1-32ddee226c41
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263348278 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.kmac_test_vectors_kmac.263348278 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_kmac_xof.2363616387
Short name T173
Test name
Test status
Simulation time 798765376 ps
CPU time 6.28 seconds
Started Aug 06 06:09:17 PM PDT 24
Finished Aug 06 06:09:23 PM PDT 24
Peak memory 219944 kb
Host smart-500b7d71-ae70-492f-9700-0d95626d75e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363616387 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.kmac_test_vectors_kmac_xof.2363616387 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_224.3594102831
Short name T943
Test name
Test status
Simulation time 129796183165 ps
CPU time 3077.97 seconds
Started Aug 06 06:08:55 PM PDT 24
Finished Aug 06 07:00:13 PM PDT 24
Peak memory 3195544 kb
Host smart-a07ba7b0-a2be-48b2-af88-c1f037349474
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3594102831 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_224.3594102831 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_256.1371931922
Short name T191
Test name
Test status
Simulation time 91730620006 ps
CPU time 3375.31 seconds
Started Aug 06 06:08:55 PM PDT 24
Finished Aug 06 07:05:11 PM PDT 24
Peak memory 3029660 kb
Host smart-f3819329-231b-44c7-83d1-a348b136b54d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1371931922 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_256.1371931922 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_384.3922648224
Short name T234
Test name
Test status
Simulation time 115237062423 ps
CPU time 2178.69 seconds
Started Aug 06 06:08:55 PM PDT 24
Finished Aug 06 06:45:14 PM PDT 24
Peak memory 2378872 kb
Host smart-20c6ea73-ca36-499d-8aa1-dc5781d73c4f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3922648224 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_384.3922648224 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_512.2839602939
Short name T479
Test name
Test status
Simulation time 123920211303 ps
CPU time 1503.67 seconds
Started Aug 06 06:09:17 PM PDT 24
Finished Aug 06 06:34:21 PM PDT 24
Peak memory 1684364 kb
Host smart-c4e97dbd-9230-458e-ae4c-c1455a71ce46
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2839602939 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_512.2839602939 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_shake_128.427002012
Short name T817
Test name
Test status
Simulation time 125360372139 ps
CPU time 6562.28 seconds
Started Aug 06 06:09:17 PM PDT 24
Finished Aug 06 07:58:40 PM PDT 24
Peak memory 2714384 kb
Host smart-2e61257a-14da-4203-85e9-2b7297c5c907
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=427002012 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_128.427002012 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/28.kmac_alert_test.94821120
Short name T711
Test name
Test status
Simulation time 12516156 ps
CPU time 0.82 seconds
Started Aug 06 06:09:35 PM PDT 24
Finished Aug 06 06:09:36 PM PDT 24
Peak memory 218532 kb
Host smart-c012e434-d292-4007-9b5a-9d9c53a5e434
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94821120 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.94821120 +enable_mas
king=1 +sw_key_masked=0
Directory /workspace/28.kmac_alert_test/latest

Test location /workspace/coverage/default/28.kmac_app.1988820980
Short name T467
Test name
Test status
Simulation time 3360760400 ps
CPU time 56.94 seconds
Started Aug 06 06:09:34 PM PDT 24
Finished Aug 06 06:10:31 PM PDT 24
Peak memory 243500 kb
Host smart-143392a8-33c3-4cf3-b114-33857035474a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988820980 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.1988820980 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/28.kmac_app/latest

Test location /workspace/coverage/default/28.kmac_burst_write.1696680196
Short name T282
Test name
Test status
Simulation time 99647800941 ps
CPU time 616.82 seconds
Started Aug 06 06:09:36 PM PDT 24
Finished Aug 06 06:19:53 PM PDT 24
Peak memory 243516 kb
Host smart-63d1c876-02db-4fd4-a3d5-b1017a050cea
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696680196 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.169668019
6 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_burst_write/latest

Test location /workspace/coverage/default/28.kmac_error.133186006
Short name T971
Test name
Test status
Simulation time 3908696803 ps
CPU time 107.94 seconds
Started Aug 06 06:09:34 PM PDT 24
Finished Aug 06 06:11:22 PM PDT 24
Peak memory 300276 kb
Host smart-30f23c2c-1d48-4188-a35d-a7b81e772432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133186006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.133186006 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_error/latest

Test location /workspace/coverage/default/28.kmac_key_error.3746953064
Short name T901
Test name
Test status
Simulation time 1786938633 ps
CPU time 3.74 seconds
Started Aug 06 06:09:31 PM PDT 24
Finished Aug 06 06:09:35 PM PDT 24
Peak memory 226936 kb
Host smart-49d93b20-06e1-475a-9907-a7bd29a52524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746953064 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.3746953064 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_key_error/latest

Test location /workspace/coverage/default/28.kmac_lc_escalation.1795697460
Short name T863
Test name
Test status
Simulation time 30484664 ps
CPU time 1.4 seconds
Started Aug 06 06:09:35 PM PDT 24
Finished Aug 06 06:09:36 PM PDT 24
Peak memory 226956 kb
Host smart-eb189e84-18b3-495f-aae4-3477ed14e51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795697460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.1795697460 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/28.kmac_lc_escalation/latest

Test location /workspace/coverage/default/28.kmac_sideload.694397979
Short name T707
Test name
Test status
Simulation time 6418757773 ps
CPU time 170.97 seconds
Started Aug 06 06:09:17 PM PDT 24
Finished Aug 06 06:12:08 PM PDT 24
Peak memory 278532 kb
Host smart-62978f6d-ffbb-44af-9d8c-7a5484966953
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694397979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.694397979 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_sideload/latest

Test location /workspace/coverage/default/28.kmac_smoke.3687934861
Short name T805
Test name
Test status
Simulation time 1253585342 ps
CPU time 16.2 seconds
Started Aug 06 06:09:17 PM PDT 24
Finished Aug 06 06:09:33 PM PDT 24
Peak memory 227020 kb
Host smart-1a71870a-85ec-47d4-9730-ba92a1ee3bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687934861 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.3687934861 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_smoke/latest

Test location /workspace/coverage/default/28.kmac_stress_all.3872465244
Short name T571
Test name
Test status
Simulation time 20855536277 ps
CPU time 865.11 seconds
Started Aug 06 06:09:34 PM PDT 24
Finished Aug 06 06:23:59 PM PDT 24
Peak memory 820576 kb
Host smart-0656bd08-0ceb-4bef-a557-6b487aba665f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3872465244 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.3872465244 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_stress_all/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_kmac.388196648
Short name T401
Test name
Test status
Simulation time 508844619 ps
CPU time 6.86 seconds
Started Aug 06 06:09:35 PM PDT 24
Finished Aug 06 06:09:42 PM PDT 24
Peak memory 219044 kb
Host smart-7fab6829-48c3-402f-855b-63056ac0fb23
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388196648 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.kmac_test_vectors_kmac.388196648 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_kmac_xof.3082505859
Short name T388
Test name
Test status
Simulation time 822019821 ps
CPU time 6.64 seconds
Started Aug 06 06:09:33 PM PDT 24
Finished Aug 06 06:09:40 PM PDT 24
Peak memory 226984 kb
Host smart-ec44ce1e-1427-4126-b7d8-a46ae1664330
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082505859 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.kmac_test_vectors_kmac_xof.3082505859 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_224.93592244
Short name T386
Test name
Test status
Simulation time 275662373548 ps
CPU time 3382.86 seconds
Started Aug 06 06:09:35 PM PDT 24
Finished Aug 06 07:05:58 PM PDT 24
Peak memory 3236716 kb
Host smart-f390d694-13fe-4e27-a539-6ffd18cfe4fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=93592244 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_224.93592244 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_256.1102209396
Short name T714
Test name
Test status
Simulation time 40712920645 ps
CPU time 2139.14 seconds
Started Aug 06 06:09:35 PM PDT 24
Finished Aug 06 06:45:14 PM PDT 24
Peak memory 1144336 kb
Host smart-529492c4-437f-4d2c-b73f-3a2a1c92bec5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1102209396 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_256.1102209396 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_384.2530499858
Short name T642
Test name
Test status
Simulation time 344938772290 ps
CPU time 2277.69 seconds
Started Aug 06 06:09:34 PM PDT 24
Finished Aug 06 06:47:32 PM PDT 24
Peak memory 2429376 kb
Host smart-fd7f49cf-2cf4-41d4-aaa7-fe71d3aaf4e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2530499858 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_384.2530499858 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_512.1903144057
Short name T567
Test name
Test status
Simulation time 13424410745 ps
CPU time 1153.07 seconds
Started Aug 06 06:09:33 PM PDT 24
Finished Aug 06 06:28:47 PM PDT 24
Peak memory 713124 kb
Host smart-f03e05a8-b186-4ebe-b0fa-f8f6e5bd7f15
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1903144057 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_512.1903144057 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/29.kmac_alert_test.4017749642
Short name T807
Test name
Test status
Simulation time 36041934 ps
CPU time 0.86 seconds
Started Aug 06 06:09:57 PM PDT 24
Finished Aug 06 06:09:58 PM PDT 24
Peak memory 218568 kb
Host smart-85ebe088-a35f-402f-92da-6069ecbc2d94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017749642 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.4017749642 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_alert_test/latest

Test location /workspace/coverage/default/29.kmac_app.25024838
Short name T754
Test name
Test status
Simulation time 33008294234 ps
CPU time 207.49 seconds
Started Aug 06 06:09:55 PM PDT 24
Finished Aug 06 06:13:23 PM PDT 24
Peak memory 364928 kb
Host smart-8c5460a8-a466-4779-be7e-57d1e428e0d9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25024838 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.25024838 +enable_masking=1
+sw_key_masked=0
Directory /workspace/29.kmac_app/latest

Test location /workspace/coverage/default/29.kmac_burst_write.3453085945
Short name T979
Test name
Test status
Simulation time 21634183175 ps
CPU time 1073.57 seconds
Started Aug 06 06:09:48 PM PDT 24
Finished Aug 06 06:27:41 PM PDT 24
Peak memory 254572 kb
Host smart-19d18cf4-4fc4-46c1-bfd6-5aa6facf43dd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453085945 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.345308594
5 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_burst_write/latest

Test location /workspace/coverage/default/29.kmac_entropy_refresh.4032238590
Short name T831
Test name
Test status
Simulation time 22315128961 ps
CPU time 102.52 seconds
Started Aug 06 06:09:55 PM PDT 24
Finished Aug 06 06:11:38 PM PDT 24
Peak memory 287004 kb
Host smart-28f8a8c0-267f-4982-90af-5a1ad1293fdd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032238590 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.4
032238590 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/29.kmac_error.3505331914
Short name T834
Test name
Test status
Simulation time 15603533705 ps
CPU time 463.65 seconds
Started Aug 06 06:09:58 PM PDT 24
Finished Aug 06 06:17:42 PM PDT 24
Peak memory 590112 kb
Host smart-016df36a-7a1d-49fc-9dcc-a84b45cf121c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505331914 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.3505331914 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_error/latest

Test location /workspace/coverage/default/29.kmac_key_error.3141135642
Short name T163
Test name
Test status
Simulation time 3908900180 ps
CPU time 10.02 seconds
Started Aug 06 06:09:57 PM PDT 24
Finished Aug 06 06:10:08 PM PDT 24
Peak memory 226964 kb
Host smart-8ae7e0ed-2b33-426d-8a60-dc3165af16bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141135642 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.3141135642 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_key_error/latest

Test location /workspace/coverage/default/29.kmac_lc_escalation.562597201
Short name T989
Test name
Test status
Simulation time 694877165 ps
CPU time 1.51 seconds
Started Aug 06 06:09:57 PM PDT 24
Finished Aug 06 06:09:58 PM PDT 24
Peak memory 226944 kb
Host smart-5aaf9dcb-acd5-4fb7-8602-67a4813a29cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562597201 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.562597201 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/29.kmac_lc_escalation/latest

Test location /workspace/coverage/default/29.kmac_long_msg_and_output.722081888
Short name T300
Test name
Test status
Simulation time 33401935122 ps
CPU time 993.69 seconds
Started Aug 06 06:09:46 PM PDT 24
Finished Aug 06 06:26:20 PM PDT 24
Peak memory 699636 kb
Host smart-ede65322-043a-48b0-9a78-bc18f3d7c172
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722081888 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_an
d_output.722081888 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/29.kmac_sideload.907412376
Short name T859
Test name
Test status
Simulation time 105828072481 ps
CPU time 289.86 seconds
Started Aug 06 06:09:53 PM PDT 24
Finished Aug 06 06:14:43 PM PDT 24
Peak memory 425456 kb
Host smart-7c8068d5-4ad7-4b73-83c4-a7cadca23055
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907412376 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.907412376 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_sideload/latest

Test location /workspace/coverage/default/29.kmac_smoke.1066040107
Short name T209
Test name
Test status
Simulation time 194237652 ps
CPU time 4.48 seconds
Started Aug 06 06:09:36 PM PDT 24
Finished Aug 06 06:09:40 PM PDT 24
Peak memory 226824 kb
Host smart-0d9208d9-e488-4ec0-bc71-fa9ac96ea8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066040107 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.1066040107 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_smoke/latest

Test location /workspace/coverage/default/29.kmac_stress_all.3699701458
Short name T468
Test name
Test status
Simulation time 181448145156 ps
CPU time 1654.91 seconds
Started Aug 06 06:09:59 PM PDT 24
Finished Aug 06 06:37:34 PM PDT 24
Peak memory 329396 kb
Host smart-3a760ce7-386c-4226-b0da-11818fbb68dd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3699701458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.3699701458 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_stress_all/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_kmac.4026582795
Short name T405
Test name
Test status
Simulation time 574535735 ps
CPU time 6.45 seconds
Started Aug 06 06:09:54 PM PDT 24
Finished Aug 06 06:10:00 PM PDT 24
Peak memory 219912 kb
Host smart-e2624c11-6e23-43ee-89da-508e684bbbf2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026582795 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.kmac_test_vectors_kmac.4026582795 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_kmac_xof.22790713
Short name T324
Test name
Test status
Simulation time 199056748 ps
CPU time 6.24 seconds
Started Aug 06 06:09:45 PM PDT 24
Finished Aug 06 06:09:51 PM PDT 24
Peak memory 227056 kb
Host smart-cd542c2b-e79d-4ef5-9e5b-0f3e8c792260
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22790713 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.kmac_test_vectors_kmac_xof.22790713 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_256.2888494926
Short name T412
Test name
Test status
Simulation time 65484109460 ps
CPU time 3030.41 seconds
Started Aug 06 06:09:46 PM PDT 24
Finished Aug 06 07:00:17 PM PDT 24
Peak memory 3083180 kb
Host smart-5b9eea10-7947-4962-8c78-57f24b4ff867
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2888494926 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_256.2888494926 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_384.165461311
Short name T267
Test name
Test status
Simulation time 48284807243 ps
CPU time 2519.7 seconds
Started Aug 06 06:09:44 PM PDT 24
Finished Aug 06 06:51:44 PM PDT 24
Peak memory 2422536 kb
Host smart-07fa0265-bc46-4ef2-a8d3-f11d4bf896e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=165461311 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_384.165461311 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_512.2509686999
Short name T827
Test name
Test status
Simulation time 36266241162 ps
CPU time 1642.26 seconds
Started Aug 06 06:09:45 PM PDT 24
Finished Aug 06 06:37:08 PM PDT 24
Peak memory 1717008 kb
Host smart-aa0c0a42-ddb4-44ed-b597-11c79ac98b99
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2509686999 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_512.2509686999 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_shake_128.2067611144
Short name T964
Test name
Test status
Simulation time 62851093032 ps
CPU time 6525.93 seconds
Started Aug 06 06:09:45 PM PDT 24
Finished Aug 06 07:58:32 PM PDT 24
Peak memory 2715168 kb
Host smart-897693a9-c22e-4dfd-bacc-b71bfc6724ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2067611144 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_128.2067611144 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/3.kmac_alert_test.1242977229
Short name T609
Test name
Test status
Simulation time 25101484 ps
CPU time 0.82 seconds
Started Aug 06 06:01:05 PM PDT 24
Finished Aug 06 06:01:07 PM PDT 24
Peak memory 218636 kb
Host smart-b64cec63-b717-478a-87db-51e33efe6bcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242977229 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.1242977229 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_alert_test/latest

Test location /workspace/coverage/default/3.kmac_app.3360756618
Short name T572
Test name
Test status
Simulation time 5225331180 ps
CPU time 134.18 seconds
Started Aug 06 06:01:04 PM PDT 24
Finished Aug 06 06:03:18 PM PDT 24
Peak memory 265228 kb
Host smart-2bfc02b8-ba31-4690-8939-d23d3bbaebfe
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360756618 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.3360756618 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/3.kmac_app/latest

Test location /workspace/coverage/default/3.kmac_app_with_partial_data.700820532
Short name T921
Test name
Test status
Simulation time 41599315154 ps
CPU time 334.94 seconds
Started Aug 06 06:01:03 PM PDT 24
Finished Aug 06 06:06:38 PM PDT 24
Peak memory 318412 kb
Host smart-3797c72e-6a15-4b41-988d-31c5d427d807
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700820532 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_parti
al_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_part
ial_data.700820532 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/3.kmac_burst_write.3128184820
Short name T241
Test name
Test status
Simulation time 69711536364 ps
CPU time 1146.58 seconds
Started Aug 06 06:00:48 PM PDT 24
Finished Aug 06 06:19:54 PM PDT 24
Peak memory 243516 kb
Host smart-33f41393-2f6a-4d87-b9ab-627204666f5e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128184820 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.3128184820
+enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_burst_write/latest

Test location /workspace/coverage/default/3.kmac_edn_timeout_error.3327647544
Short name T615
Test name
Test status
Simulation time 77233892 ps
CPU time 0.93 seconds
Started Aug 06 06:01:03 PM PDT 24
Finished Aug 06 06:01:04 PM PDT 24
Peak memory 218532 kb
Host smart-af890e07-84d9-4c0e-a587-39386d144817
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3327647544 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.3327647544 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_mode_error.4037008446
Short name T347
Test name
Test status
Simulation time 73700222 ps
CPU time 1.1 seconds
Started Aug 06 06:01:05 PM PDT 24
Finished Aug 06 06:01:06 PM PDT 24
Peak memory 218752 kb
Host smart-6581edd1-8597-48b5-9d22-cb699def07f3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4037008446 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.4037008446 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_ready_error.159577595
Short name T13
Test name
Test status
Simulation time 12993089470 ps
CPU time 34.37 seconds
Started Aug 06 06:01:05 PM PDT 24
Finished Aug 06 06:01:39 PM PDT 24
Peak memory 227208 kb
Host smart-0e8a4dec-5d54-4765-90e9-c9253848a210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159577595 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.159577595 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_refresh.317862194
Short name T456
Test name
Test status
Simulation time 487992563 ps
CPU time 10.88 seconds
Started Aug 06 06:01:04 PM PDT 24
Finished Aug 06 06:01:15 PM PDT 24
Peak memory 238796 kb
Host smart-1a97381d-080e-49fa-be7a-2cf495be1fa1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317862194 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.317
862194 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/3.kmac_error.844780495
Short name T731
Test name
Test status
Simulation time 660175013 ps
CPU time 48.55 seconds
Started Aug 06 06:01:02 PM PDT 24
Finished Aug 06 06:01:50 PM PDT 24
Peak memory 251672 kb
Host smart-61f79bcc-4014-44c7-91b7-ba9d458c5d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844780495 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.844780495 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_error/latest

Test location /workspace/coverage/default/3.kmac_key_error.3321656553
Short name T367
Test name
Test status
Simulation time 5871818864 ps
CPU time 10.99 seconds
Started Aug 06 06:01:04 PM PDT 24
Finished Aug 06 06:01:15 PM PDT 24
Peak memory 226980 kb
Host smart-94cbe194-a831-4cab-92f2-f0974359230c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321656553 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.3321656553 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_key_error/latest

Test location /workspace/coverage/default/3.kmac_lc_escalation.3314168850
Short name T962
Test name
Test status
Simulation time 368918784 ps
CPU time 8.73 seconds
Started Aug 06 06:01:04 PM PDT 24
Finished Aug 06 06:01:13 PM PDT 24
Peak memory 226944 kb
Host smart-575643af-b662-4427-8be5-45df42b49b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314168850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.3314168850 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/3.kmac_lc_escalation/latest

Test location /workspace/coverage/default/3.kmac_long_msg_and_output.475938118
Short name T327
Test name
Test status
Simulation time 16423905760 ps
CPU time 2148.97 seconds
Started Aug 06 06:00:47 PM PDT 24
Finished Aug 06 06:36:36 PM PDT 24
Peak memory 1147676 kb
Host smart-e178dfdc-a3e6-434e-99c1-55128700456c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475938118 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_and
_output.475938118 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/3.kmac_mubi.33236147
Short name T56
Test name
Test status
Simulation time 6964274106 ps
CPU time 244.87 seconds
Started Aug 06 06:01:05 PM PDT 24
Finished Aug 06 06:05:10 PM PDT 24
Peak memory 301492 kb
Host smart-518ae655-295e-41af-ba9e-e85a098f6ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33236147 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.33236147 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_mubi/latest

Test location /workspace/coverage/default/3.kmac_sec_cm.115794403
Short name T26
Test name
Test status
Simulation time 27670352609 ps
CPU time 104.5 seconds
Started Aug 06 06:01:04 PM PDT 24
Finished Aug 06 06:02:49 PM PDT 24
Peak memory 269272 kb
Host smart-5b545e60-c2b1-4481-a889-1497e71f7b6d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115794403 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.115794403 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/3.kmac_sec_cm/latest

Test location /workspace/coverage/default/3.kmac_sideload.936281685
Short name T475
Test name
Test status
Simulation time 48148017629 ps
CPU time 414.3 seconds
Started Aug 06 06:00:46 PM PDT 24
Finished Aug 06 06:07:41 PM PDT 24
Peak memory 522464 kb
Host smart-af1e9840-efd8-4240-85ee-9d1e09b67d5f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936281685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.936281685 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_sideload/latest

Test location /workspace/coverage/default/3.kmac_smoke.1915429999
Short name T873
Test name
Test status
Simulation time 1962539817 ps
CPU time 49.2 seconds
Started Aug 06 06:00:47 PM PDT 24
Finished Aug 06 06:01:37 PM PDT 24
Peak memory 224304 kb
Host smart-11af92ac-d72b-4ce9-83db-35e5c3e3f3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915429999 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.1915429999 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_smoke/latest

Test location /workspace/coverage/default/3.kmac_stress_all.1010263777
Short name T606
Test name
Test status
Simulation time 94895494903 ps
CPU time 2387.52 seconds
Started Aug 06 06:01:05 PM PDT 24
Finished Aug 06 06:40:53 PM PDT 24
Peak memory 854644 kb
Host smart-9649d1b4-8137-4356-bc2d-ba611c92f48b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1010263777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.1010263777 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_stress_all/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_kmac.3884022530
Short name T899
Test name
Test status
Simulation time 496445843 ps
CPU time 6.26 seconds
Started Aug 06 06:01:04 PM PDT 24
Finished Aug 06 06:01:10 PM PDT 24
Peak memory 227072 kb
Host smart-ea52588d-3b90-497f-a39e-975393181ead
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884022530 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.kmac_test_vectors_kmac.3884022530 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_kmac_xof.3165868743
Short name T330
Test name
Test status
Simulation time 443099296 ps
CPU time 5.88 seconds
Started Aug 06 06:01:05 PM PDT 24
Finished Aug 06 06:01:11 PM PDT 24
Peak memory 227048 kb
Host smart-0f8b8104-5d5c-45d1-8ac6-19303e6e2f0c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165868743 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.kmac_test_vectors_kmac_xof.3165868743 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_224.4282000902
Short name T422
Test name
Test status
Simulation time 261994660087 ps
CPU time 3147.94 seconds
Started Aug 06 06:01:00 PM PDT 24
Finished Aug 06 06:53:28 PM PDT 24
Peak memory 3216208 kb
Host smart-5bc76f88-b781-4b9e-97df-62af6e6680c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4282000902 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.4282000902 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_256.2119603992
Short name T528
Test name
Test status
Simulation time 582901296368 ps
CPU time 3224.9 seconds
Started Aug 06 06:00:47 PM PDT 24
Finished Aug 06 06:54:32 PM PDT 24
Peak memory 3131472 kb
Host smart-ce9077af-3390-4ce8-9db5-77e4e7eae8cf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2119603992 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.2119603992 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_384.2156140252
Short name T653
Test name
Test status
Simulation time 108309263447 ps
CPU time 1697.83 seconds
Started Aug 06 06:00:47 PM PDT 24
Finished Aug 06 06:29:06 PM PDT 24
Peak memory 932976 kb
Host smart-6127de1b-f5bf-454e-bd8e-afbbc83d2ec6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2156140252 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.2156140252 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_512.235433131
Short name T740
Test name
Test status
Simulation time 406788401497 ps
CPU time 1705.77 seconds
Started Aug 06 06:00:44 PM PDT 24
Finished Aug 06 06:29:10 PM PDT 24
Peak memory 1712148 kb
Host smart-060af7ba-6d41-4951-bc31-e50af0fa5e87
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=235433131 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.235433131 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/30.kmac_alert_test.3627487484
Short name T215
Test name
Test status
Simulation time 18215944 ps
CPU time 0.78 seconds
Started Aug 06 06:10:19 PM PDT 24
Finished Aug 06 06:10:20 PM PDT 24
Peak memory 218504 kb
Host smart-22281725-b31e-4efc-9fff-9787da759f9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627487484 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.3627487484 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_alert_test/latest

Test location /workspace/coverage/default/30.kmac_app.972725808
Short name T695
Test name
Test status
Simulation time 132290390111 ps
CPU time 456.35 seconds
Started Aug 06 06:10:19 PM PDT 24
Finished Aug 06 06:17:56 PM PDT 24
Peak memory 564804 kb
Host smart-4dafa79f-f007-4a5d-84c2-4d330cdce63c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972725808 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.972725808 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/30.kmac_app/latest

Test location /workspace/coverage/default/30.kmac_burst_write.1740470060
Short name T774
Test name
Test status
Simulation time 54901149695 ps
CPU time 1185.58 seconds
Started Aug 06 06:10:09 PM PDT 24
Finished Aug 06 06:29:54 PM PDT 24
Peak memory 261292 kb
Host smart-dcfdf66e-baa3-4676-8f41-1b365892ae32
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740470060 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.174047006
0 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_burst_write/latest

Test location /workspace/coverage/default/30.kmac_entropy_refresh.189519337
Short name T920
Test name
Test status
Simulation time 24215558875 ps
CPU time 279.03 seconds
Started Aug 06 06:10:21 PM PDT 24
Finished Aug 06 06:15:00 PM PDT 24
Peak memory 404256 kb
Host smart-f778978c-05a3-4653-8744-716c7a00548b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189519337 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_entropy_refresh.18
9519337 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/30.kmac_error.1681131276
Short name T455
Test name
Test status
Simulation time 2340845972 ps
CPU time 89.86 seconds
Started Aug 06 06:10:20 PM PDT 24
Finished Aug 06 06:11:50 PM PDT 24
Peak memory 263608 kb
Host smart-63bcb7f5-120f-4379-a6ef-493b3e24f633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681131276 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.1681131276 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_error/latest

Test location /workspace/coverage/default/30.kmac_key_error.776558734
Short name T880
Test name
Test status
Simulation time 3232480965 ps
CPU time 5.85 seconds
Started Aug 06 06:10:18 PM PDT 24
Finished Aug 06 06:10:24 PM PDT 24
Peak memory 227040 kb
Host smart-19a0af2b-4c24-4977-b86c-aa9df8bb336b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776558734 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.776558734 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_key_error/latest

Test location /workspace/coverage/default/30.kmac_lc_escalation.569274196
Short name T52
Test name
Test status
Simulation time 168011966 ps
CPU time 1.27 seconds
Started Aug 06 06:10:19 PM PDT 24
Finished Aug 06 06:10:21 PM PDT 24
Peak memory 227024 kb
Host smart-434d949c-8331-4686-acd0-b69d9e8eb9f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569274196 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.569274196 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/30.kmac_lc_escalation/latest

Test location /workspace/coverage/default/30.kmac_sideload.3070562037
Short name T772
Test name
Test status
Simulation time 4349831680 ps
CPU time 78.57 seconds
Started Aug 06 06:10:09 PM PDT 24
Finished Aug 06 06:11:28 PM PDT 24
Peak memory 253228 kb
Host smart-dfc4ee8c-03a6-4fd6-baaa-0b6a2c5f5bbc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070562037 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.3070562037 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_sideload/latest

Test location /workspace/coverage/default/30.kmac_smoke.4014541183
Short name T749
Test name
Test status
Simulation time 6931746106 ps
CPU time 53.99 seconds
Started Aug 06 06:10:12 PM PDT 24
Finished Aug 06 06:11:06 PM PDT 24
Peak memory 226992 kb
Host smart-18469636-d07e-4af6-8dd1-a371681a6177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014541183 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.4014541183 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_smoke/latest

Test location /workspace/coverage/default/30.kmac_stress_all.3218246514
Short name T17
Test name
Test status
Simulation time 53898010501 ps
CPU time 1873.46 seconds
Started Aug 06 06:10:19 PM PDT 24
Finished Aug 06 06:41:33 PM PDT 24
Peak memory 1157616 kb
Host smart-7777854f-7ae9-4dae-bfac-ce455a6e4e22
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3218246514 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.3218246514 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_stress_all/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_kmac.684186152
Short name T179
Test name
Test status
Simulation time 248716980 ps
CPU time 6.85 seconds
Started Aug 06 06:10:09 PM PDT 24
Finished Aug 06 06:10:16 PM PDT 24
Peak memory 226924 kb
Host smart-001b7107-db90-4a11-a6fd-d51773ca9cd1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684186152 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.kmac_test_vectors_kmac.684186152 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_kmac_xof.3022072874
Short name T659
Test name
Test status
Simulation time 278599060 ps
CPU time 6.4 seconds
Started Aug 06 06:10:19 PM PDT 24
Finished Aug 06 06:10:25 PM PDT 24
Peak memory 227008 kb
Host smart-a850e3ad-4a41-4373-aa14-cc143af3d89f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022072874 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.kmac_test_vectors_kmac_xof.3022072874 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_256.328495281
Short name T890
Test name
Test status
Simulation time 21459335316 ps
CPU time 2090.17 seconds
Started Aug 06 06:10:09 PM PDT 24
Finished Aug 06 06:45:00 PM PDT 24
Peak memory 1130452 kb
Host smart-9469b02a-df6c-4298-82f2-e49afa43ea89
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=328495281 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_256.328495281 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_384.3617782332
Short name T608
Test name
Test status
Simulation time 50537658052 ps
CPU time 2192.65 seconds
Started Aug 06 06:10:12 PM PDT 24
Finished Aug 06 06:46:45 PM PDT 24
Peak memory 2369272 kb
Host smart-23601281-aab5-4474-9ce0-ac967e3ef692
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3617782332 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_384.3617782332 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_512.2119267447
Short name T318
Test name
Test status
Simulation time 136681583532 ps
CPU time 1791.18 seconds
Started Aug 06 06:10:08 PM PDT 24
Finished Aug 06 06:40:00 PM PDT 24
Peak memory 1728724 kb
Host smart-572337cd-506c-4d13-882b-445df64a958a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2119267447 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_512.2119267447 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_shake_128.1223667195
Short name T710
Test name
Test status
Simulation time 66796553180 ps
CPU time 6159.68 seconds
Started Aug 06 06:10:12 PM PDT 24
Finished Aug 06 07:52:52 PM PDT 24
Peak memory 2700476 kb
Host smart-43ae81c7-8494-4420-b705-755cc934e975
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1223667195 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_128.1223667195 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_shake_256.2831125873
Short name T304
Test name
Test status
Simulation time 55698115066 ps
CPU time 5521.47 seconds
Started Aug 06 06:10:10 PM PDT 24
Finished Aug 06 07:42:12 PM PDT 24
Peak memory 2239388 kb
Host smart-0f7d3577-f9ab-4af5-b2f3-b41eaa34785f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2831125873 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_256.2831125873 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/31.kmac_alert_test.2682621581
Short name T853
Test name
Test status
Simulation time 15380283 ps
CPU time 0.83 seconds
Started Aug 06 06:10:52 PM PDT 24
Finished Aug 06 06:10:53 PM PDT 24
Peak memory 218488 kb
Host smart-03957b2a-64e2-4851-99c9-81c0303cb17c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682621581 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.2682621581 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_alert_test/latest

Test location /workspace/coverage/default/31.kmac_app.847127174
Short name T763
Test name
Test status
Simulation time 967890748 ps
CPU time 23.2 seconds
Started Aug 06 06:10:33 PM PDT 24
Finished Aug 06 06:10:57 PM PDT 24
Peak memory 243436 kb
Host smart-ee9181d8-88e8-4b31-9b8b-36872dec1bbb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847127174 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.847127174 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/31.kmac_app/latest

Test location /workspace/coverage/default/31.kmac_burst_write.1374765244
Short name T2
Test name
Test status
Simulation time 25114863356 ps
CPU time 297.63 seconds
Started Aug 06 06:10:21 PM PDT 24
Finished Aug 06 06:15:19 PM PDT 24
Peak memory 236572 kb
Host smart-0528823e-1070-43ac-adf9-eab1981c0cb4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374765244 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_write.137476524
4 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_burst_write/latest

Test location /workspace/coverage/default/31.kmac_entropy_refresh.2170740627
Short name T847
Test name
Test status
Simulation time 4628806830 ps
CPU time 167.21 seconds
Started Aug 06 06:10:33 PM PDT 24
Finished Aug 06 06:13:21 PM PDT 24
Peak memory 283200 kb
Host smart-db07afb3-c34b-450b-ba87-7f1574c9d126
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170740627 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.2
170740627 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/31.kmac_error.422407638
Short name T976
Test name
Test status
Simulation time 57977750888 ps
CPU time 376.77 seconds
Started Aug 06 06:10:51 PM PDT 24
Finished Aug 06 06:17:08 PM PDT 24
Peak memory 500392 kb
Host smart-d48296a8-d385-4903-a0a5-c680f32d29ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422407638 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.422407638 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_error/latest

Test location /workspace/coverage/default/31.kmac_key_error.3186261276
Short name T618
Test name
Test status
Simulation time 7358112394 ps
CPU time 9.38 seconds
Started Aug 06 06:10:51 PM PDT 24
Finished Aug 06 06:11:00 PM PDT 24
Peak memory 227020 kb
Host smart-47434a4f-a994-4029-a31c-d02243346c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186261276 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.3186261276 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_key_error/latest

Test location /workspace/coverage/default/31.kmac_lc_escalation.973993583
Short name T900
Test name
Test status
Simulation time 50189833 ps
CPU time 1.39 seconds
Started Aug 06 06:10:52 PM PDT 24
Finished Aug 06 06:10:54 PM PDT 24
Peak memory 227012 kb
Host smart-10b6e09a-25c4-4f86-98f3-4dac6d1f6b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973993583 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.973993583 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/31.kmac_lc_escalation/latest

Test location /workspace/coverage/default/31.kmac_long_msg_and_output.371818117
Short name T512
Test name
Test status
Simulation time 190185225770 ps
CPU time 2126.39 seconds
Started Aug 06 06:10:20 PM PDT 24
Finished Aug 06 06:45:47 PM PDT 24
Peak memory 2114828 kb
Host smart-0d344f9b-50ef-4d4a-822f-49c0fbf0c906
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371818117 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_an
d_output.371818117 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/31.kmac_sideload.2366435730
Short name T178
Test name
Test status
Simulation time 11888737263 ps
CPU time 399.04 seconds
Started Aug 06 06:10:20 PM PDT 24
Finished Aug 06 06:16:59 PM PDT 24
Peak memory 530280 kb
Host smart-8fd2dbb8-0be1-46d9-8079-af0d89f2ac98
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366435730 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.2366435730 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_sideload/latest

Test location /workspace/coverage/default/31.kmac_smoke.2832467667
Short name T739
Test name
Test status
Simulation time 2227518464 ps
CPU time 45.36 seconds
Started Aug 06 06:10:21 PM PDT 24
Finished Aug 06 06:11:06 PM PDT 24
Peak memory 227112 kb
Host smart-291fd0ca-f3a1-4ded-925c-74d33e12b866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832467667 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.2832467667 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_smoke/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_kmac.3601186326
Short name T246
Test name
Test status
Simulation time 385901455 ps
CPU time 6.08 seconds
Started Aug 06 06:10:34 PM PDT 24
Finished Aug 06 06:10:40 PM PDT 24
Peak memory 219948 kb
Host smart-4e05e17e-2fbc-4686-a9b6-60973d3288ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601186326 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.kmac_test_vectors_kmac.3601186326 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_kmac_xof.2975000058
Short name T690
Test name
Test status
Simulation time 303297816 ps
CPU time 6.2 seconds
Started Aug 06 06:10:33 PM PDT 24
Finished Aug 06 06:10:40 PM PDT 24
Peak memory 219968 kb
Host smart-6e55f7c1-a5d4-4a60-a0fc-7c4ae7181616
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975000058 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.kmac_test_vectors_kmac_xof.2975000058 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_224.82149483
Short name T194
Test name
Test status
Simulation time 27874550311 ps
CPU time 2283.72 seconds
Started Aug 06 06:10:20 PM PDT 24
Finished Aug 06 06:48:24 PM PDT 24
Peak memory 1194288 kb
Host smart-2460c22a-5184-4564-941d-65739d1e78fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=82149483 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_224.82149483 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_512.2093060896
Short name T3
Test name
Test status
Simulation time 16763368807 ps
CPU time 1202.15 seconds
Started Aug 06 06:10:34 PM PDT 24
Finished Aug 06 06:30:37 PM PDT 24
Peak memory 710804 kb
Host smart-4597bdd7-2d03-4c5e-b112-8c5afc4224af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2093060896 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_512.2093060896 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_shake_128.1290535207
Short name T332
Test name
Test status
Simulation time 238676662298 ps
CPU time 6184.51 seconds
Started Aug 06 06:10:35 PM PDT 24
Finished Aug 06 07:53:40 PM PDT 24
Peak memory 2702144 kb
Host smart-4befb284-673b-4f9c-b404-e80acb9c7919
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1290535207 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_128.1290535207 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/32.kmac_alert_test.542106041
Short name T520
Test name
Test status
Simulation time 62123086 ps
CPU time 0.87 seconds
Started Aug 06 06:11:08 PM PDT 24
Finished Aug 06 06:11:09 PM PDT 24
Peak memory 218440 kb
Host smart-8ba80996-382e-4dfa-ad99-f48fa5194de6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542106041 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.542106041 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/32.kmac_alert_test/latest

Test location /workspace/coverage/default/32.kmac_app.4022278908
Short name T777
Test name
Test status
Simulation time 52138383607 ps
CPU time 351.05 seconds
Started Aug 06 06:11:07 PM PDT 24
Finished Aug 06 06:16:58 PM PDT 24
Peak memory 477536 kb
Host smart-1603c1a1-5f25-48b8-9197-73a7154d2dcf
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022278908 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.4022278908 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/32.kmac_app/latest

Test location /workspace/coverage/default/32.kmac_burst_write.4126045464
Short name T382
Test name
Test status
Simulation time 38771048947 ps
CPU time 451.93 seconds
Started Aug 06 06:11:04 PM PDT 24
Finished Aug 06 06:18:36 PM PDT 24
Peak memory 243592 kb
Host smart-ddd809f9-8f50-4a5f-ab1b-cb61a5883fe9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126045464 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.412604546
4 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_burst_write/latest

Test location /workspace/coverage/default/32.kmac_entropy_refresh.4018899918
Short name T665
Test name
Test status
Simulation time 16506201500 ps
CPU time 507.73 seconds
Started Aug 06 06:11:08 PM PDT 24
Finished Aug 06 06:19:36 PM PDT 24
Peak memory 545548 kb
Host smart-26392ddd-06b1-4e7f-b8e2-f741a253b776
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018899918 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.4
018899918 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/32.kmac_error.2814481862
Short name T837
Test name
Test status
Simulation time 843286922 ps
CPU time 42.99 seconds
Started Aug 06 06:11:05 PM PDT 24
Finished Aug 06 06:11:48 PM PDT 24
Peak memory 254596 kb
Host smart-ff8504ca-60ee-4ff3-a17d-4468f26c14c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814481862 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.2814481862 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_error/latest

Test location /workspace/coverage/default/32.kmac_key_error.2721956396
Short name T220
Test name
Test status
Simulation time 12664583636 ps
CPU time 11.16 seconds
Started Aug 06 06:11:08 PM PDT 24
Finished Aug 06 06:11:20 PM PDT 24
Peak memory 226908 kb
Host smart-5876310a-aae3-4d5b-9eb9-196efa871b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721956396 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.2721956396 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_key_error/latest

Test location /workspace/coverage/default/32.kmac_long_msg_and_output.1826273959
Short name T255
Test name
Test status
Simulation time 34358407536 ps
CPU time 286.46 seconds
Started Aug 06 06:10:51 PM PDT 24
Finished Aug 06 06:15:38 PM PDT 24
Peak memory 543936 kb
Host smart-21dea86f-bd55-4bba-adfe-e249a85ab89a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826273959 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_long_msg_a
nd_output.1826273959 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/32.kmac_sideload.1666054715
Short name T201
Test name
Test status
Simulation time 3450240955 ps
CPU time 290.41 seconds
Started Aug 06 06:11:07 PM PDT 24
Finished Aug 06 06:15:58 PM PDT 24
Peak memory 328784 kb
Host smart-505cc769-407b-4a6c-8b2a-32351a852014
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666054715 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.1666054715 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_sideload/latest

Test location /workspace/coverage/default/32.kmac_smoke.4056549806
Short name T377
Test name
Test status
Simulation time 5077720304 ps
CPU time 34.3 seconds
Started Aug 06 06:10:52 PM PDT 24
Finished Aug 06 06:11:27 PM PDT 24
Peak memory 227244 kb
Host smart-91d63eba-f70c-4ce0-a1f1-543a8d1028ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056549806 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.4056549806 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_smoke/latest

Test location /workspace/coverage/default/32.kmac_stress_all.2762791256
Short name T965
Test name
Test status
Simulation time 209567683689 ps
CPU time 768.83 seconds
Started Aug 06 06:11:08 PM PDT 24
Finished Aug 06 06:23:57 PM PDT 24
Peak memory 973748 kb
Host smart-5ff2b4a2-a0c4-43e4-8dc1-93063f02e788
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2762791256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.2762791256 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_stress_all/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_kmac.4085212470
Short name T260
Test name
Test status
Simulation time 467911046 ps
CPU time 6.14 seconds
Started Aug 06 06:11:06 PM PDT 24
Finished Aug 06 06:11:12 PM PDT 24
Peak memory 227120 kb
Host smart-5617814c-41df-41ef-9f83-d747ca9e3d35
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085212470 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.kmac_test_vectors_kmac.4085212470 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_kmac_xof.799637610
Short name T258
Test name
Test status
Simulation time 425462300 ps
CPU time 5.95 seconds
Started Aug 06 06:11:07 PM PDT 24
Finished Aug 06 06:11:13 PM PDT 24
Peak memory 219936 kb
Host smart-12053a16-8965-4208-b44c-6a9f4ffe4f07
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799637610 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.kmac_test_vectors_kmac_xof.799637610 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_224.2245038360
Short name T660
Test name
Test status
Simulation time 20696901626 ps
CPU time 2118.51 seconds
Started Aug 06 06:11:06 PM PDT 24
Finished Aug 06 06:46:25 PM PDT 24
Peak memory 1193228 kb
Host smart-85f8a2e6-64a7-4631-97ff-0bed4d998ae0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2245038360 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_224.2245038360 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_256.3615655379
Short name T248
Test name
Test status
Simulation time 76538070715 ps
CPU time 2127.59 seconds
Started Aug 06 06:11:04 PM PDT 24
Finished Aug 06 06:46:32 PM PDT 24
Peak memory 1128324 kb
Host smart-1820ef93-0de1-4044-8a39-d71f99ba6052
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3615655379 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_256.3615655379 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_384.4199497030
Short name T801
Test name
Test status
Simulation time 15628422831 ps
CPU time 1637.25 seconds
Started Aug 06 06:11:09 PM PDT 24
Finished Aug 06 06:38:27 PM PDT 24
Peak memory 932928 kb
Host smart-c468deb7-688c-49ef-adfc-3be151249a4d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4199497030 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_384.4199497030 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_512.453873407
Short name T89
Test name
Test status
Simulation time 35602565282 ps
CPU time 1534.49 seconds
Started Aug 06 06:11:05 PM PDT 24
Finished Aug 06 06:36:40 PM PDT 24
Peak memory 1738052 kb
Host smart-3ebfcbec-f51d-4078-9a5c-21ec020e589f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=453873407 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_512.453873407 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/33.kmac_alert_test.3136284132
Short name T896
Test name
Test status
Simulation time 63149298 ps
CPU time 0.92 seconds
Started Aug 06 06:11:37 PM PDT 24
Finished Aug 06 06:11:38 PM PDT 24
Peak memory 218604 kb
Host smart-69107fc2-b671-49b4-93ff-0759b3122772
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136284132 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.3136284132 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_alert_test/latest

Test location /workspace/coverage/default/33.kmac_app.2979152932
Short name T907
Test name
Test status
Simulation time 6699568379 ps
CPU time 24.9 seconds
Started Aug 06 06:11:25 PM PDT 24
Finished Aug 06 06:11:50 PM PDT 24
Peak memory 239228 kb
Host smart-e1e330d7-744d-440e-b74c-483213d9700c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979152932 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.2979152932 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/33.kmac_app/latest

Test location /workspace/coverage/default/33.kmac_burst_write.1645117446
Short name T908
Test name
Test status
Simulation time 10081037966 ps
CPU time 599.73 seconds
Started Aug 06 06:11:23 PM PDT 24
Finished Aug 06 06:21:23 PM PDT 24
Peak memory 243544 kb
Host smart-909b7ad7-3d9d-499a-909c-35e42c536039
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645117446 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.164511744
6 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_burst_write/latest

Test location /workspace/coverage/default/33.kmac_entropy_refresh.4147944560
Short name T579
Test name
Test status
Simulation time 38437056255 ps
CPU time 442.84 seconds
Started Aug 06 06:11:24 PM PDT 24
Finished Aug 06 06:18:47 PM PDT 24
Peak memory 535948 kb
Host smart-2b731e54-84c7-4c71-8dd8-beb7192c4d92
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147944560 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.4
147944560 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/33.kmac_error.1101672605
Short name T814
Test name
Test status
Simulation time 2631449805 ps
CPU time 64.89 seconds
Started Aug 06 06:11:36 PM PDT 24
Finished Aug 06 06:12:41 PM PDT 24
Peak memory 259936 kb
Host smart-f9f0dfbc-2366-49d7-af7c-17d1927be880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101672605 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.1101672605 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_error/latest

Test location /workspace/coverage/default/33.kmac_key_error.3154388210
Short name T574
Test name
Test status
Simulation time 495409449 ps
CPU time 4.06 seconds
Started Aug 06 06:11:35 PM PDT 24
Finished Aug 06 06:11:39 PM PDT 24
Peak memory 226940 kb
Host smart-92983ce0-56a1-425f-b0d2-c2f631a40e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154388210 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.3154388210 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_key_error/latest

Test location /workspace/coverage/default/33.kmac_long_msg_and_output.1326379191
Short name T449
Test name
Test status
Simulation time 13349053284 ps
CPU time 495.32 seconds
Started Aug 06 06:11:08 PM PDT 24
Finished Aug 06 06:19:24 PM PDT 24
Peak memory 765172 kb
Host smart-c6ad549d-e672-4ae1-a088-ccf11ba959b3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326379191 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_a
nd_output.1326379191 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/33.kmac_sideload.1646258329
Short name T877
Test name
Test status
Simulation time 7228344301 ps
CPU time 287.1 seconds
Started Aug 06 06:11:08 PM PDT 24
Finished Aug 06 06:15:55 PM PDT 24
Peak memory 310096 kb
Host smart-f56ca69f-386a-43d9-9754-c28f33b20328
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646258329 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.1646258329 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_sideload/latest

Test location /workspace/coverage/default/33.kmac_smoke.3370669197
Short name T237
Test name
Test status
Simulation time 1699587764 ps
CPU time 13.67 seconds
Started Aug 06 06:11:08 PM PDT 24
Finished Aug 06 06:11:21 PM PDT 24
Peak memory 226916 kb
Host smart-c07e619f-813a-4fa7-9434-ff2953e0da54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370669197 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.3370669197 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_smoke/latest

Test location /workspace/coverage/default/33.kmac_stress_all.777597512
Short name T478
Test name
Test status
Simulation time 43245950598 ps
CPU time 1521.82 seconds
Started Aug 06 06:11:36 PM PDT 24
Finished Aug 06 06:36:59 PM PDT 24
Peak memory 450928 kb
Host smart-d0acfd2b-9299-412a-9b42-da786d4ff4d6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=777597512 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.777597512 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_stress_all/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_kmac.1308314014
Short name T833
Test name
Test status
Simulation time 195759060 ps
CPU time 6.27 seconds
Started Aug 06 06:11:24 PM PDT 24
Finished Aug 06 06:11:31 PM PDT 24
Peak memory 219988 kb
Host smart-22f21adb-d238-4cb2-aa87-f0339cb467fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308314014 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.kmac_test_vectors_kmac.1308314014 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_kmac_xof.1988797236
Short name T963
Test name
Test status
Simulation time 1040911414 ps
CPU time 7.36 seconds
Started Aug 06 06:11:24 PM PDT 24
Finished Aug 06 06:11:31 PM PDT 24
Peak memory 227024 kb
Host smart-d6d55767-f18c-467d-a6ee-02fca4be847b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988797236 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.kmac_test_vectors_kmac_xof.1988797236 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_224.729157386
Short name T743
Test name
Test status
Simulation time 65217438725 ps
CPU time 3320.38 seconds
Started Aug 06 06:11:25 PM PDT 24
Finished Aug 06 07:06:46 PM PDT 24
Peak memory 3208936 kb
Host smart-693e7120-12ee-4881-893f-40b6e2e9937d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=729157386 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_224.729157386 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_256.3327891707
Short name T778
Test name
Test status
Simulation time 67434438655 ps
CPU time 3173.93 seconds
Started Aug 06 06:11:24 PM PDT 24
Finished Aug 06 07:04:19 PM PDT 24
Peak memory 3074604 kb
Host smart-40a47542-2546-4f0a-b7d5-6ed4faa3f869
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3327891707 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_256.3327891707 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_384.2638978111
Short name T719
Test name
Test status
Simulation time 49904748641 ps
CPU time 2211.17 seconds
Started Aug 06 06:11:24 PM PDT 24
Finished Aug 06 06:48:16 PM PDT 24
Peak memory 2367368 kb
Host smart-59299f59-72c1-403f-93a5-66b5a0e1b8a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2638978111 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_384.2638978111 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_512.1473663761
Short name T165
Test name
Test status
Simulation time 198012934202 ps
CPU time 1870.44 seconds
Started Aug 06 06:11:24 PM PDT 24
Finished Aug 06 06:42:35 PM PDT 24
Peak memory 1738168 kb
Host smart-5261e06a-9a1f-45d6-9d6b-37dfbcaad791
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1473663761 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_512.1473663761 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/34.kmac_alert_test.2313035399
Short name T794
Test name
Test status
Simulation time 64574364 ps
CPU time 0.8 seconds
Started Aug 06 06:12:02 PM PDT 24
Finished Aug 06 06:12:03 PM PDT 24
Peak memory 218596 kb
Host smart-d0184391-c929-4974-b4f2-ab278a368673
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313035399 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.2313035399 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_alert_test/latest

Test location /workspace/coverage/default/34.kmac_app.863115569
Short name T414
Test name
Test status
Simulation time 1579078900 ps
CPU time 10.71 seconds
Started Aug 06 06:11:59 PM PDT 24
Finished Aug 06 06:12:10 PM PDT 24
Peak memory 226852 kb
Host smart-5c2a8777-82cc-495a-a1d8-b13a23b51cf9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863115569 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.863115569 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/34.kmac_app/latest

Test location /workspace/coverage/default/34.kmac_burst_write.975064594
Short name T746
Test name
Test status
Simulation time 12794651253 ps
CPU time 1348.75 seconds
Started Aug 06 06:11:35 PM PDT 24
Finished Aug 06 06:34:04 PM PDT 24
Peak memory 247164 kb
Host smart-fb72e98e-5165-4b5e-9161-a541e743d48b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975064594 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.975064594
+enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_burst_write/latest

Test location /workspace/coverage/default/34.kmac_entropy_refresh.3941670548
Short name T649
Test name
Test status
Simulation time 26141942943 ps
CPU time 364.2 seconds
Started Aug 06 06:11:59 PM PDT 24
Finished Aug 06 06:18:04 PM PDT 24
Peak memory 494968 kb
Host smart-4d45567a-f46e-4215-a444-db601f386b0e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941670548 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.3
941670548 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/34.kmac_error.2305273151
Short name T575
Test name
Test status
Simulation time 2576080884 ps
CPU time 59.27 seconds
Started Aug 06 06:11:59 PM PDT 24
Finished Aug 06 06:12:59 PM PDT 24
Peak memory 251872 kb
Host smart-ebd284d3-9867-449c-93ec-e3bf4eed4a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305273151 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.2305273151 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_error/latest

Test location /workspace/coverage/default/34.kmac_key_error.2050401765
Short name T769
Test name
Test status
Simulation time 7832464218 ps
CPU time 5.39 seconds
Started Aug 06 06:11:59 PM PDT 24
Finished Aug 06 06:12:04 PM PDT 24
Peak memory 226948 kb
Host smart-3965e20e-4850-48ea-a79e-2dffed1d4398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050401765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.2050401765 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_key_error/latest

Test location /workspace/coverage/default/34.kmac_long_msg_and_output.1207323811
Short name T433
Test name
Test status
Simulation time 70252651479 ps
CPU time 606.73 seconds
Started Aug 06 06:11:37 PM PDT 24
Finished Aug 06 06:21:44 PM PDT 24
Peak memory 876864 kb
Host smart-0336ea23-ef53-4462-a2d8-bf63d2a834b7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207323811 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_a
nd_output.1207323811 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/34.kmac_sideload.3370869358
Short name T942
Test name
Test status
Simulation time 18592039211 ps
CPU time 361.89 seconds
Started Aug 06 06:11:35 PM PDT 24
Finished Aug 06 06:17:37 PM PDT 24
Peak memory 351880 kb
Host smart-6267181d-1ac0-4422-a93f-66c08096a475
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370869358 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.3370869358 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_sideload/latest

Test location /workspace/coverage/default/34.kmac_smoke.1380119108
Short name T561
Test name
Test status
Simulation time 26248165139 ps
CPU time 91.14 seconds
Started Aug 06 06:11:36 PM PDT 24
Finished Aug 06 06:13:07 PM PDT 24
Peak memory 228252 kb
Host smart-bba734fa-ea45-4857-b7bc-897f5426c0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380119108 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.1380119108 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_smoke/latest

Test location /workspace/coverage/default/34.kmac_stress_all.1220051789
Short name T273
Test name
Test status
Simulation time 8124952478 ps
CPU time 124.16 seconds
Started Aug 06 06:12:00 PM PDT 24
Finished Aug 06 06:14:04 PM PDT 24
Peak memory 261564 kb
Host smart-5b78d7d2-3b8d-416d-979b-5da3428da0eb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1220051789 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.1220051789 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_stress_all/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_kmac.2183346041
Short name T328
Test name
Test status
Simulation time 501776151 ps
CPU time 6.79 seconds
Started Aug 06 06:12:00 PM PDT 24
Finished Aug 06 06:12:07 PM PDT 24
Peak memory 227084 kb
Host smart-fbb315e2-43ca-46d4-83cf-3f1359b99e2a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183346041 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.kmac_test_vectors_kmac.2183346041 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_kmac_xof.930066782
Short name T603
Test name
Test status
Simulation time 437407520 ps
CPU time 5.14 seconds
Started Aug 06 06:12:00 PM PDT 24
Finished Aug 06 06:12:05 PM PDT 24
Peak memory 219972 kb
Host smart-8ae09e98-15da-4f54-b702-497bed7ba9c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930066782 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.kmac_test_vectors_kmac_xof.930066782 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_224.937016072
Short name T37
Test name
Test status
Simulation time 66349404173 ps
CPU time 3210.24 seconds
Started Aug 06 06:11:36 PM PDT 24
Finished Aug 06 07:05:06 PM PDT 24
Peak memory 3243572 kb
Host smart-011bf696-1867-4d91-9611-42fb1cd612b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=937016072 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_224.937016072 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_384.985635458
Short name T947
Test name
Test status
Simulation time 61928162798 ps
CPU time 1637.87 seconds
Started Aug 06 06:12:00 PM PDT 24
Finished Aug 06 06:39:18 PM PDT 24
Peak memory 912820 kb
Host smart-cd98e32c-f9a1-4aef-967a-dcb8f68a1a6c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=985635458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_384.985635458 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_512.2739882331
Short name T990
Test name
Test status
Simulation time 70021718072 ps
CPU time 1556.09 seconds
Started Aug 06 06:11:47 PM PDT 24
Finished Aug 06 06:37:43 PM PDT 24
Peak memory 1779772 kb
Host smart-3d377cf6-b3d2-4d94-a24a-f30e4944a877
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2739882331 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_512.2739882331 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_shake_128.4108628424
Short name T870
Test name
Test status
Simulation time 273881286745 ps
CPU time 6257.98 seconds
Started Aug 06 06:11:46 PM PDT 24
Finished Aug 06 07:56:05 PM PDT 24
Peak memory 2710128 kb
Host smart-99888041-397d-47a8-a180-b41499b1903b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4108628424 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_128.4108628424 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_shake_256.156356967
Short name T254
Test name
Test status
Simulation time 222214850760 ps
CPU time 5298.93 seconds
Started Aug 06 06:11:46 PM PDT 24
Finished Aug 06 07:40:06 PM PDT 24
Peak memory 2211184 kb
Host smart-2569189b-fc6e-44e9-a6bd-1c32d002f350
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=156356967 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_256.156356967 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/35.kmac_alert_test.219343111
Short name T336
Test name
Test status
Simulation time 40492237 ps
CPU time 0.78 seconds
Started Aug 06 06:12:26 PM PDT 24
Finished Aug 06 06:12:26 PM PDT 24
Peak memory 218596 kb
Host smart-b7467824-71a0-4c70-8e80-e8a451aaa1cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219343111 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.219343111 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/35.kmac_alert_test/latest

Test location /workspace/coverage/default/35.kmac_app.64948383
Short name T845
Test name
Test status
Simulation time 6469501260 ps
CPU time 177.87 seconds
Started Aug 06 06:12:14 PM PDT 24
Finished Aug 06 06:15:12 PM PDT 24
Peak memory 344848 kb
Host smart-b63ec5f9-2995-4744-8e54-c2b829e08115
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64948383 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.64948383 +enable_masking=1
+sw_key_masked=0
Directory /workspace/35.kmac_app/latest

Test location /workspace/coverage/default/35.kmac_burst_write.3645348404
Short name T741
Test name
Test status
Simulation time 15437924290 ps
CPU time 1394.21 seconds
Started Aug 06 06:12:12 PM PDT 24
Finished Aug 06 06:35:27 PM PDT 24
Peak memory 247076 kb
Host smart-de6e974c-6d64-4b76-8eb6-e9c6509e4f32
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645348404 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.364534840
4 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_burst_write/latest

Test location /workspace/coverage/default/35.kmac_entropy_refresh.649865433
Short name T934
Test name
Test status
Simulation time 4177496697 ps
CPU time 208.66 seconds
Started Aug 06 06:12:13 PM PDT 24
Finished Aug 06 06:15:42 PM PDT 24
Peak memory 299700 kb
Host smart-6064b50b-fd4e-4c6d-80fb-7f9bb7b6e363
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649865433 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.64
9865433 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/35.kmac_error.3246412171
Short name T630
Test name
Test status
Simulation time 18493703870 ps
CPU time 164.47 seconds
Started Aug 06 06:12:12 PM PDT 24
Finished Aug 06 06:14:56 PM PDT 24
Peak memory 352852 kb
Host smart-812f2311-ca50-4f6a-83f3-2e849f8a5425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246412171 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.3246412171 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_error/latest

Test location /workspace/coverage/default/35.kmac_key_error.2347269840
Short name T709
Test name
Test status
Simulation time 1930094145 ps
CPU time 10.14 seconds
Started Aug 06 06:12:27 PM PDT 24
Finished Aug 06 06:12:37 PM PDT 24
Peak memory 226828 kb
Host smart-eb47e728-b5dd-4fcc-8f4e-86301caa7201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347269840 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.2347269840 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_key_error/latest

Test location /workspace/coverage/default/35.kmac_lc_escalation.3128914952
Short name T245
Test name
Test status
Simulation time 46383135 ps
CPU time 1.45 seconds
Started Aug 06 06:12:28 PM PDT 24
Finished Aug 06 06:12:29 PM PDT 24
Peak memory 226996 kb
Host smart-40932312-b09f-4dad-bde5-81abefbaf63d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128914952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.3128914952 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/35.kmac_lc_escalation/latest

Test location /workspace/coverage/default/35.kmac_long_msg_and_output.4187074674
Short name T176
Test name
Test status
Simulation time 7720447104 ps
CPU time 143.41 seconds
Started Aug 06 06:12:13 PM PDT 24
Finished Aug 06 06:14:36 PM PDT 24
Peak memory 292340 kb
Host smart-1b39ac21-0a3c-445f-b806-f4c46bfde985
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187074674 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_a
nd_output.4187074674 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/35.kmac_sideload.3523322168
Short name T364
Test name
Test status
Simulation time 6436003353 ps
CPU time 179.66 seconds
Started Aug 06 06:12:14 PM PDT 24
Finished Aug 06 06:15:14 PM PDT 24
Peak memory 353492 kb
Host smart-9522d540-3b64-4b8c-a292-e2edde80d3c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523322168 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.3523322168 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_sideload/latest

Test location /workspace/coverage/default/35.kmac_smoke.1162093029
Short name T442
Test name
Test status
Simulation time 1175153472 ps
CPU time 14.57 seconds
Started Aug 06 06:12:12 PM PDT 24
Finished Aug 06 06:12:27 PM PDT 24
Peak memory 227036 kb
Host smart-707382a1-3f30-4dcc-82e7-00c62fee32b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162093029 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.1162093029 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_smoke/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_kmac.2947223164
Short name T560
Test name
Test status
Simulation time 634774500 ps
CPU time 7.55 seconds
Started Aug 06 06:12:14 PM PDT 24
Finished Aug 06 06:12:22 PM PDT 24
Peak memory 219864 kb
Host smart-356e389b-c156-40ab-a955-1176f58b1e46
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947223164 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.kmac_test_vectors_kmac.2947223164 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_kmac_xof.3753696506
Short name T408
Test name
Test status
Simulation time 724890250 ps
CPU time 5.94 seconds
Started Aug 06 06:12:12 PM PDT 24
Finished Aug 06 06:12:18 PM PDT 24
Peak memory 227044 kb
Host smart-9bd60086-cc68-4eba-aa42-0f76e633f4e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753696506 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.kmac_test_vectors_kmac_xof.3753696506 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_256.290988810
Short name T205
Test name
Test status
Simulation time 91741189482 ps
CPU time 2213.45 seconds
Started Aug 06 06:12:12 PM PDT 24
Finished Aug 06 06:49:05 PM PDT 24
Peak memory 1151860 kb
Host smart-3555cb87-c8cc-48a3-ad3b-7b12227812cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=290988810 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_256.290988810 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_384.1935810541
Short name T911
Test name
Test status
Simulation time 369794788737 ps
CPU time 2469.25 seconds
Started Aug 06 06:12:13 PM PDT 24
Finished Aug 06 06:53:23 PM PDT 24
Peak memory 2367392 kb
Host smart-c1e0c1f3-8fbf-4f1e-82e0-53f199cd68e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1935810541 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_384.1935810541 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_512.2175871094
Short name T569
Test name
Test status
Simulation time 10888772650 ps
CPU time 1214.89 seconds
Started Aug 06 06:12:14 PM PDT 24
Finished Aug 06 06:32:29 PM PDT 24
Peak memory 708328 kb
Host smart-79a41fe7-c871-49d6-aa5e-dc771711dea7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2175871094 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_512.2175871094 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_shake_128.3714174762
Short name T277
Test name
Test status
Simulation time 244119303432 ps
CPU time 6113.54 seconds
Started Aug 06 06:12:12 PM PDT 24
Finished Aug 06 07:54:06 PM PDT 24
Peak memory 2702648 kb
Host smart-450bf963-b732-4183-8ea9-1102d5985cbb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3714174762 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_shake_128.3714174762 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/36.kmac_alert_test.491827722
Short name T768
Test name
Test status
Simulation time 34556445 ps
CPU time 0.79 seconds
Started Aug 06 06:12:48 PM PDT 24
Finished Aug 06 06:12:49 PM PDT 24
Peak memory 218640 kb
Host smart-0cf98d4d-c9e3-4bab-81a6-75fbac8249e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491827722 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.491827722 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/36.kmac_alert_test/latest

Test location /workspace/coverage/default/36.kmac_app.914359464
Short name T451
Test name
Test status
Simulation time 9729195267 ps
CPU time 212.32 seconds
Started Aug 06 06:12:40 PM PDT 24
Finished Aug 06 06:16:12 PM PDT 24
Peak memory 385612 kb
Host smart-d60a4577-8bd8-4997-848a-61e795487249
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914359464 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.914359464 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/36.kmac_app/latest

Test location /workspace/coverage/default/36.kmac_burst_write.1329491025
Short name T948
Test name
Test status
Simulation time 12179807932 ps
CPU time 689.57 seconds
Started Aug 06 06:12:28 PM PDT 24
Finished Aug 06 06:23:57 PM PDT 24
Peak memory 246336 kb
Host smart-1883acdb-2eaa-4664-afc4-849627d951e9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329491025 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.132949102
5 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_burst_write/latest

Test location /workspace/coverage/default/36.kmac_entropy_refresh.3324445721
Short name T464
Test name
Test status
Simulation time 3914795769 ps
CPU time 160.1 seconds
Started Aug 06 06:12:40 PM PDT 24
Finished Aug 06 06:15:20 PM PDT 24
Peak memory 272920 kb
Host smart-b33180f8-f228-42e5-b93e-3cb649859927
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324445721 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.3
324445721 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/36.kmac_error.3035884895
Short name T450
Test name
Test status
Simulation time 35213393762 ps
CPU time 292.24 seconds
Started Aug 06 06:12:40 PM PDT 24
Finished Aug 06 06:17:33 PM PDT 24
Peak memory 458520 kb
Host smart-972907d1-238e-4979-b527-8e4a10dd0712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035884895 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.3035884895 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_error/latest

Test location /workspace/coverage/default/36.kmac_key_error.877260431
Short name T651
Test name
Test status
Simulation time 4166938975 ps
CPU time 11.33 seconds
Started Aug 06 06:12:38 PM PDT 24
Finished Aug 06 06:12:50 PM PDT 24
Peak memory 227000 kb
Host smart-1b10f927-ba2f-45f1-b742-51f460b071c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877260431 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.877260431 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_key_error/latest

Test location /workspace/coverage/default/36.kmac_lc_escalation.2844831896
Short name T42
Test name
Test status
Simulation time 5687943244 ps
CPU time 49.03 seconds
Started Aug 06 06:12:40 PM PDT 24
Finished Aug 06 06:13:29 PM PDT 24
Peak memory 248416 kb
Host smart-409df664-676a-4758-ad7d-c25b43e0ed41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844831896 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.2844831896 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/36.kmac_lc_escalation/latest

Test location /workspace/coverage/default/36.kmac_long_msg_and_output.4293916582
Short name T352
Test name
Test status
Simulation time 23825519438 ps
CPU time 3032.26 seconds
Started Aug 06 06:12:27 PM PDT 24
Finished Aug 06 07:03:00 PM PDT 24
Peak memory 1601784 kb
Host smart-6df5c97d-f932-44ec-a393-d0564bdc4e53
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293916582 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_a
nd_output.4293916582 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/36.kmac_sideload.1175788462
Short name T342
Test name
Test status
Simulation time 50443733289 ps
CPU time 412.46 seconds
Started Aug 06 06:12:27 PM PDT 24
Finished Aug 06 06:19:20 PM PDT 24
Peak memory 520896 kb
Host smart-a12bb4cb-0561-4f8b-8db5-996f45ace933
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175788462 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.1175788462 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_sideload/latest

Test location /workspace/coverage/default/36.kmac_smoke.2035355522
Short name T289
Test name
Test status
Simulation time 2589095428 ps
CPU time 60.24 seconds
Started Aug 06 06:12:27 PM PDT 24
Finished Aug 06 06:13:27 PM PDT 24
Peak memory 225420 kb
Host smart-8a79bcb8-0a13-4fff-9dca-56b3b121a684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035355522 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.2035355522 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_smoke/latest

Test location /workspace/coverage/default/36.kmac_stress_all.1252863854
Short name T755
Test name
Test status
Simulation time 90978717197 ps
CPU time 3826.52 seconds
Started Aug 06 06:12:49 PM PDT 24
Finished Aug 06 07:16:37 PM PDT 24
Peak memory 2473332 kb
Host smart-5f575a78-5dc5-44c6-8abb-d6836f930011
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1252863854 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all.1252863854 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_stress_all/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_kmac.1044165577
Short name T605
Test name
Test status
Simulation time 516514091 ps
CPU time 7.77 seconds
Started Aug 06 06:12:38 PM PDT 24
Finished Aug 06 06:12:46 PM PDT 24
Peak memory 227072 kb
Host smart-c33430ef-2645-4562-8b3f-6299eedfe83d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044165577 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.kmac_test_vectors_kmac.1044165577 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_kmac_xof.4028224345
Short name T593
Test name
Test status
Simulation time 425507656 ps
CPU time 6.17 seconds
Started Aug 06 06:12:40 PM PDT 24
Finished Aug 06 06:12:46 PM PDT 24
Peak memory 219044 kb
Host smart-d12651cc-5894-42c8-a2f8-954fb5d80cb2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028224345 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.kmac_test_vectors_kmac_xof.4028224345 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_224.784903677
Short name T534
Test name
Test status
Simulation time 45345520138 ps
CPU time 2240.9 seconds
Started Aug 06 06:12:28 PM PDT 24
Finished Aug 06 06:49:49 PM PDT 24
Peak memory 1235736 kb
Host smart-136ac704-eed6-493f-a15a-66b5c0fb8c07
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=784903677 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_224.784903677 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_256.3905683023
Short name T926
Test name
Test status
Simulation time 261151557417 ps
CPU time 3326.02 seconds
Started Aug 06 06:12:29 PM PDT 24
Finished Aug 06 07:07:55 PM PDT 24
Peak memory 3089000 kb
Host smart-5430cce7-6e87-47ad-b911-742cd1ccd9a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3905683023 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_256.3905683023 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_384.4276801533
Short name T738
Test name
Test status
Simulation time 391574568161 ps
CPU time 2339.82 seconds
Started Aug 06 06:12:38 PM PDT 24
Finished Aug 06 06:51:38 PM PDT 24
Peak memory 2360004 kb
Host smart-ffd23925-9d92-4c05-8b35-11c68922a54f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4276801533 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_384.4276801533 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_512.1303852644
Short name T341
Test name
Test status
Simulation time 386856161679 ps
CPU time 1807.32 seconds
Started Aug 06 06:12:40 PM PDT 24
Finished Aug 06 06:42:47 PM PDT 24
Peak memory 1747236 kb
Host smart-5907974e-8e3c-48cd-9570-2b1d478cd8b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1303852644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_512.1303852644 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_shake_128.1692295953
Short name T444
Test name
Test status
Simulation time 66954167193 ps
CPU time 6387.84 seconds
Started Aug 06 06:12:41 PM PDT 24
Finished Aug 06 07:59:10 PM PDT 24
Peak memory 2744620 kb
Host smart-acbead64-135f-43a0-8adc-c9be444d0441
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1692295953 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_shake_128.1692295953 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/37.kmac_alert_test.391892262
Short name T752
Test name
Test status
Simulation time 17165426 ps
CPU time 0.88 seconds
Started Aug 06 06:13:14 PM PDT 24
Finished Aug 06 06:13:15 PM PDT 24
Peak memory 218564 kb
Host smart-3cf58ec1-d8e1-4a23-898c-d5ea5f1c95e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391892262 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.391892262 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/37.kmac_alert_test/latest

Test location /workspace/coverage/default/37.kmac_app.1745871021
Short name T103
Test name
Test status
Simulation time 5971472237 ps
CPU time 91.49 seconds
Started Aug 06 06:13:01 PM PDT 24
Finished Aug 06 06:14:32 PM PDT 24
Peak memory 249888 kb
Host smart-9755310c-7a61-4b91-a64e-1257e08da029
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745871021 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.1745871021 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/37.kmac_app/latest

Test location /workspace/coverage/default/37.kmac_burst_write.1982875633
Short name T104
Test name
Test status
Simulation time 23786188182 ps
CPU time 1364.55 seconds
Started Aug 06 06:12:50 PM PDT 24
Finished Aug 06 06:35:35 PM PDT 24
Peak memory 246892 kb
Host smart-d0f3e330-f3c0-447e-a371-8a4250b83ca4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982875633 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.198287563
3 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_burst_write/latest

Test location /workspace/coverage/default/37.kmac_entropy_refresh.901050552
Short name T415
Test name
Test status
Simulation time 726312715 ps
CPU time 37.44 seconds
Started Aug 06 06:13:00 PM PDT 24
Finished Aug 06 06:13:38 PM PDT 24
Peak memory 234660 kb
Host smart-a603904b-6906-4080-bd46-ff3be0a8191c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901050552 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.90
1050552 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/37.kmac_error.4206773482
Short name T10
Test name
Test status
Simulation time 3716858057 ps
CPU time 116.91 seconds
Started Aug 06 06:13:03 PM PDT 24
Finished Aug 06 06:15:00 PM PDT 24
Peak memory 269700 kb
Host smart-04d801e3-6397-4c71-8b9b-8c2687224b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206773482 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.4206773482 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_error/latest

Test location /workspace/coverage/default/37.kmac_key_error.3104498681
Short name T842
Test name
Test status
Simulation time 2460465889 ps
CPU time 5.05 seconds
Started Aug 06 06:13:04 PM PDT 24
Finished Aug 06 06:13:09 PM PDT 24
Peak memory 227008 kb
Host smart-5c5838ec-547e-46fd-9a57-605fc4d67d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104498681 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.3104498681 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_key_error/latest

Test location /workspace/coverage/default/37.kmac_long_msg_and_output.207798714
Short name T655
Test name
Test status
Simulation time 8439095916 ps
CPU time 321.64 seconds
Started Aug 06 06:12:50 PM PDT 24
Finished Aug 06 06:18:11 PM PDT 24
Peak memory 619532 kb
Host smart-044203b6-07a3-4574-ac10-8fac8628d4df
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207798714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_an
d_output.207798714 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/37.kmac_sideload.2624382550
Short name T923
Test name
Test status
Simulation time 11910401145 ps
CPU time 549.23 seconds
Started Aug 06 06:12:50 PM PDT 24
Finished Aug 06 06:21:59 PM PDT 24
Peak memory 391780 kb
Host smart-00720bd5-5571-4038-9f7d-37f8c9fc332e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624382550 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.2624382550 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_sideload/latest

Test location /workspace/coverage/default/37.kmac_smoke.640767913
Short name T323
Test name
Test status
Simulation time 6577140804 ps
CPU time 36.36 seconds
Started Aug 06 06:12:50 PM PDT 24
Finished Aug 06 06:13:26 PM PDT 24
Peak memory 226996 kb
Host smart-62b2617b-2391-4a41-aa99-e015214a2607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640767913 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.640767913 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_smoke/latest

Test location /workspace/coverage/default/37.kmac_stress_all.1374654911
Short name T60
Test name
Test status
Simulation time 281084934318 ps
CPU time 2079.51 seconds
Started Aug 06 06:13:13 PM PDT 24
Finished Aug 06 06:47:53 PM PDT 24
Peak memory 1647084 kb
Host smart-ad958d77-d368-424a-a3c2-3bf09971e276
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1374654911 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.1374654911 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_stress_all/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_kmac.2344572008
Short name T202
Test name
Test status
Simulation time 135492642 ps
CPU time 6.48 seconds
Started Aug 06 06:13:03 PM PDT 24
Finished Aug 06 06:13:09 PM PDT 24
Peak memory 219044 kb
Host smart-7e96df39-6dba-4f8a-9cc0-bc0eb5ce1c64
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344572008 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.kmac_test_vectors_kmac.2344572008 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_kmac_xof.3105310313
Short name T613
Test name
Test status
Simulation time 308659418 ps
CPU time 7.35 seconds
Started Aug 06 06:13:04 PM PDT 24
Finished Aug 06 06:13:11 PM PDT 24
Peak memory 219112 kb
Host smart-d4b21a78-4146-45da-9669-44ed2e38d0de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105310313 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.kmac_test_vectors_kmac_xof.3105310313 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_224.2192752191
Short name T527
Test name
Test status
Simulation time 154318797479 ps
CPU time 3469.21 seconds
Started Aug 06 06:12:49 PM PDT 24
Finished Aug 06 07:10:39 PM PDT 24
Peak memory 3206848 kb
Host smart-99ec503e-ac22-4541-bfe0-319c3c6faa34
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2192752191 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_224.2192752191 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_256.1284956764
Short name T946
Test name
Test status
Simulation time 62902324664 ps
CPU time 3041.67 seconds
Started Aug 06 06:12:52 PM PDT 24
Finished Aug 06 07:03:34 PM PDT 24
Peak memory 3069688 kb
Host smart-f1439ed0-5194-496b-a6f1-6b6409519cdf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1284956764 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_256.1284956764 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_384.951020911
Short name T185
Test name
Test status
Simulation time 31259845614 ps
CPU time 1633.61 seconds
Started Aug 06 06:12:51 PM PDT 24
Finished Aug 06 06:40:04 PM PDT 24
Peak memory 917776 kb
Host smart-00848579-f95e-4bab-82fe-03eaf1c35101
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=951020911 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_384.951020911 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_512.2773596217
Short name T548
Test name
Test status
Simulation time 44878475493 ps
CPU time 1788.79 seconds
Started Aug 06 06:12:51 PM PDT 24
Finished Aug 06 06:42:41 PM PDT 24
Peak memory 1728060 kb
Host smart-f2a195d5-8495-4f11-ac7a-5d02549992f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2773596217 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_512.2773596217 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/38.kmac_alert_test.2700040031
Short name T482
Test name
Test status
Simulation time 11668094 ps
CPU time 0.79 seconds
Started Aug 06 06:13:49 PM PDT 24
Finished Aug 06 06:13:50 PM PDT 24
Peak memory 218528 kb
Host smart-0ee2e65d-e2bd-4d9d-a33f-ec09f873820c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700040031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.2700040031 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_alert_test/latest

Test location /workspace/coverage/default/38.kmac_app.1293311928
Short name T474
Test name
Test status
Simulation time 6302504860 ps
CPU time 441.62 seconds
Started Aug 06 06:13:48 PM PDT 24
Finished Aug 06 06:21:10 PM PDT 24
Peak memory 381536 kb
Host smart-0b1c7eec-e12a-4404-b83d-8a9b81b388ae
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293311928 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.1293311928 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/38.kmac_app/latest

Test location /workspace/coverage/default/38.kmac_burst_write.767116104
Short name T591
Test name
Test status
Simulation time 4084809578 ps
CPU time 415.54 seconds
Started Aug 06 06:13:13 PM PDT 24
Finished Aug 06 06:20:09 PM PDT 24
Peak memory 233296 kb
Host smart-7925ee4a-ee7c-4ecd-ab12-029a5e0a332d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767116104 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.767116104
+enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_burst_write/latest

Test location /workspace/coverage/default/38.kmac_entropy_refresh.1238125596
Short name T356
Test name
Test status
Simulation time 38266245118 ps
CPU time 194.47 seconds
Started Aug 06 06:13:45 PM PDT 24
Finished Aug 06 06:17:00 PM PDT 24
Peak memory 334316 kb
Host smart-24bde35a-c16d-49e2-b311-36e7dc2de49e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238125596 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.1
238125596 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/38.kmac_error.998898698
Short name T549
Test name
Test status
Simulation time 16622894984 ps
CPU time 92.5 seconds
Started Aug 06 06:13:48 PM PDT 24
Finished Aug 06 06:15:20 PM PDT 24
Peak memory 295916 kb
Host smart-014cad41-5eab-49eb-addd-4917753b0308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998898698 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.998898698 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_error/latest

Test location /workspace/coverage/default/38.kmac_key_error.113485387
Short name T620
Test name
Test status
Simulation time 3175526732 ps
CPU time 6.72 seconds
Started Aug 06 06:13:47 PM PDT 24
Finished Aug 06 06:13:53 PM PDT 24
Peak memory 226956 kb
Host smart-fccbe95d-d8f6-41b6-a0c9-b669148a5b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113485387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.113485387 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_key_error/latest

Test location /workspace/coverage/default/38.kmac_lc_escalation.1351877562
Short name T49
Test name
Test status
Simulation time 151259666 ps
CPU time 1.5 seconds
Started Aug 06 06:13:47 PM PDT 24
Finished Aug 06 06:13:48 PM PDT 24
Peak memory 226952 kb
Host smart-4185a4c9-0164-4719-9692-1739fc4cc614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351877562 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.1351877562 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/38.kmac_lc_escalation/latest

Test location /workspace/coverage/default/38.kmac_long_msg_and_output.506497217
Short name T306
Test name
Test status
Simulation time 64948610949 ps
CPU time 1479.62 seconds
Started Aug 06 06:13:13 PM PDT 24
Finished Aug 06 06:37:53 PM PDT 24
Peak memory 1713552 kb
Host smart-8d92bdf8-68a4-4e81-b101-caaac7527b1e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506497217 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_an
d_output.506497217 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/38.kmac_sideload.4086167730
Short name T968
Test name
Test status
Simulation time 11144545163 ps
CPU time 374 seconds
Started Aug 06 06:13:14 PM PDT 24
Finished Aug 06 06:19:28 PM PDT 24
Peak memory 485936 kb
Host smart-e14a73ec-48b2-4dea-896f-d30ecfbe4aa9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086167730 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.4086167730 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_sideload/latest

Test location /workspace/coverage/default/38.kmac_smoke.2860808824
Short name T350
Test name
Test status
Simulation time 229570903 ps
CPU time 5.17 seconds
Started Aug 06 06:13:13 PM PDT 24
Finished Aug 06 06:13:18 PM PDT 24
Peak memory 226960 kb
Host smart-ba7e5ce5-1abf-4d3e-acaf-eaef2aa18862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860808824 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.2860808824 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_smoke/latest

Test location /workspace/coverage/default/38.kmac_stress_all.1636149244
Short name T59
Test name
Test status
Simulation time 69352866833 ps
CPU time 2266.31 seconds
Started Aug 06 06:13:49 PM PDT 24
Finished Aug 06 06:51:36 PM PDT 24
Peak memory 1161364 kb
Host smart-d0a4c0fa-00d1-4972-a9b0-d076b59cab4f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1636149244 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.1636149244 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_stress_all/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_kmac.3596927830
Short name T857
Test name
Test status
Simulation time 217555711 ps
CPU time 6.56 seconds
Started Aug 06 06:13:31 PM PDT 24
Finished Aug 06 06:13:37 PM PDT 24
Peak memory 227032 kb
Host smart-5d3b451a-b02a-4885-9e31-87eeaaa3d33d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596927830 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.kmac_test_vectors_kmac.3596927830 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_kmac_xof.2071152021
Short name T584
Test name
Test status
Simulation time 351509567 ps
CPU time 6.12 seconds
Started Aug 06 06:13:29 PM PDT 24
Finished Aug 06 06:13:35 PM PDT 24
Peak memory 220016 kb
Host smart-41ad503a-9c27-496c-aba5-1d45cbf17883
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071152021 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.kmac_test_vectors_kmac_xof.2071152021 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_256.1420016393
Short name T587
Test name
Test status
Simulation time 61673330340 ps
CPU time 2934.45 seconds
Started Aug 06 06:13:30 PM PDT 24
Finished Aug 06 07:02:25 PM PDT 24
Peak memory 3029380 kb
Host smart-e8c16913-b8ee-4067-abad-d8dbb6e5899c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1420016393 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_256.1420016393 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_384.1953613941
Short name T566
Test name
Test status
Simulation time 47916585991 ps
CPU time 2429.25 seconds
Started Aug 06 06:13:29 PM PDT 24
Finished Aug 06 06:53:59 PM PDT 24
Peak memory 2409824 kb
Host smart-eadb51cb-da83-4583-9b6d-d8b7b432c5f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1953613941 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_384.1953613941 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_512.1743502351
Short name T169
Test name
Test status
Simulation time 50285742326 ps
CPU time 1672.02 seconds
Started Aug 06 06:13:29 PM PDT 24
Finished Aug 06 06:41:21 PM PDT 24
Peak memory 1691468 kb
Host smart-c0ca2752-e870-4219-998d-877ba5a45b22
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1743502351 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_512.1743502351 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_shake_256.1357663792
Short name T656
Test name
Test status
Simulation time 64093486398 ps
CPU time 4915.07 seconds
Started Aug 06 06:13:28 PM PDT 24
Finished Aug 06 07:35:24 PM PDT 24
Peak memory 2191068 kb
Host smart-0882c0f0-5bc5-4d0b-b3a2-099a2b578cfe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1357663792 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_256.1357663792 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/39.kmac_alert_test.326138902
Short name T684
Test name
Test status
Simulation time 30829344 ps
CPU time 0.88 seconds
Started Aug 06 06:14:00 PM PDT 24
Finished Aug 06 06:14:01 PM PDT 24
Peak memory 218580 kb
Host smart-cff6b4b7-e28c-47b3-9344-b53b30ead39d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326138902 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.326138902 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/39.kmac_alert_test/latest

Test location /workspace/coverage/default/39.kmac_app.2481776169
Short name T497
Test name
Test status
Simulation time 1993267595 ps
CPU time 30.85 seconds
Started Aug 06 06:14:02 PM PDT 24
Finished Aug 06 06:14:33 PM PDT 24
Peak memory 245364 kb
Host smart-6df47f44-6273-4e02-9d9f-d835c3ff3b8d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481776169 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.2481776169 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/39.kmac_app/latest

Test location /workspace/coverage/default/39.kmac_burst_write.2831262135
Short name T348
Test name
Test status
Simulation time 13969886355 ps
CPU time 1614.9 seconds
Started Aug 06 06:14:00 PM PDT 24
Finished Aug 06 06:40:55 PM PDT 24
Peak memory 246976 kb
Host smart-ad8955e9-116d-44f1-8525-d5cdd6ad77c3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831262135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.283126213
5 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_burst_write/latest

Test location /workspace/coverage/default/39.kmac_entropy_refresh.2383422882
Short name T216
Test name
Test status
Simulation time 7867315318 ps
CPU time 336.34 seconds
Started Aug 06 06:14:02 PM PDT 24
Finished Aug 06 06:19:38 PM PDT 24
Peak memory 338844 kb
Host smart-0b002dee-b481-48b8-aecd-dad1a87971b0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383422882 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.2
383422882 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/39.kmac_error.1111158270
Short name T20
Test name
Test status
Simulation time 21035026705 ps
CPU time 264.79 seconds
Started Aug 06 06:14:02 PM PDT 24
Finished Aug 06 06:18:27 PM PDT 24
Peak memory 443620 kb
Host smart-9e4fbf2c-a0bf-41ad-a667-5783d2a4a10c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111158270 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.1111158270 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_error/latest

Test location /workspace/coverage/default/39.kmac_key_error.3130382720
Short name T368
Test name
Test status
Simulation time 7024599052 ps
CPU time 10.5 seconds
Started Aug 06 06:14:02 PM PDT 24
Finished Aug 06 06:14:12 PM PDT 24
Peak memory 227008 kb
Host smart-becdadd0-b5a8-4042-849b-a6da3c15b534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130382720 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.3130382720 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_key_error/latest

Test location /workspace/coverage/default/39.kmac_sideload.897504017
Short name T63
Test name
Test status
Simulation time 33838405440 ps
CPU time 284.24 seconds
Started Aug 06 06:13:48 PM PDT 24
Finished Aug 06 06:18:33 PM PDT 24
Peak memory 428720 kb
Host smart-7f658a43-2831-4592-9442-bcb0b0f2acac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897504017 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.897504017 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_sideload/latest

Test location /workspace/coverage/default/39.kmac_smoke.2185917360
Short name T643
Test name
Test status
Simulation time 3096832891 ps
CPU time 70.28 seconds
Started Aug 06 06:13:48 PM PDT 24
Finished Aug 06 06:14:59 PM PDT 24
Peak memory 227172 kb
Host smart-82729b6e-ce7f-40ff-a3c8-2f8525a4b064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185917360 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.2185917360 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_smoke/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_kmac.1363076775
Short name T540
Test name
Test status
Simulation time 176602374 ps
CPU time 5.99 seconds
Started Aug 06 06:14:02 PM PDT 24
Finished Aug 06 06:14:08 PM PDT 24
Peak memory 219096 kb
Host smart-9e9d6111-878d-47d9-84e0-bfba4e719d71
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363076775 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.kmac_test_vectors_kmac.1363076775 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_kmac_xof.3448877862
Short name T213
Test name
Test status
Simulation time 477803009 ps
CPU time 7.31 seconds
Started Aug 06 06:14:02 PM PDT 24
Finished Aug 06 06:14:09 PM PDT 24
Peak memory 219076 kb
Host smart-d51429c0-5c0a-43d7-b8b2-7d6e59655c97
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448877862 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.kmac_test_vectors_kmac_xof.3448877862 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_256.1723320090
Short name T519
Test name
Test status
Simulation time 182530635707 ps
CPU time 3410.24 seconds
Started Aug 06 06:14:01 PM PDT 24
Finished Aug 06 07:10:52 PM PDT 24
Peak memory 2989800 kb
Host smart-b819837b-7710-4517-a6b5-122496bd7c48
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1723320090 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_256.1723320090 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_384.1265904552
Short name T601
Test name
Test status
Simulation time 57464894549 ps
CPU time 1549.37 seconds
Started Aug 06 06:14:01 PM PDT 24
Finished Aug 06 06:39:50 PM PDT 24
Peak memory 924900 kb
Host smart-9e923154-072d-4ac2-994a-c1ad82f7a296
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1265904552 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_384.1265904552 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_512.2051765542
Short name T980
Test name
Test status
Simulation time 72831848031 ps
CPU time 1656.3 seconds
Started Aug 06 06:14:02 PM PDT 24
Finished Aug 06 06:41:39 PM PDT 24
Peak memory 1732352 kb
Host smart-fdb4636e-f21d-4f4e-b3ce-4710db30d89f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2051765542 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_512.2051765542 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_shake_128.1233313071
Short name T473
Test name
Test status
Simulation time 63041255118 ps
CPU time 6282.17 seconds
Started Aug 06 06:14:02 PM PDT 24
Finished Aug 06 07:58:45 PM PDT 24
Peak memory 2726888 kb
Host smart-10132aa2-baa1-4b6a-bddf-b1652615294f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1233313071 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_128.1233313071 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/4.kmac_alert_test.270407894
Short name T437
Test name
Test status
Simulation time 287889678 ps
CPU time 0.92 seconds
Started Aug 06 06:01:18 PM PDT 24
Finished Aug 06 06:01:19 PM PDT 24
Peak memory 218528 kb
Host smart-c732fd81-673c-4c4c-8ff7-729cf81d8dd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270407894 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.270407894 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/4.kmac_alert_test/latest

Test location /workspace/coverage/default/4.kmac_app.64591852
Short name T622
Test name
Test status
Simulation time 9939168340 ps
CPU time 127.39 seconds
Started Aug 06 06:01:07 PM PDT 24
Finished Aug 06 06:03:14 PM PDT 24
Peak memory 320572 kb
Host smart-275178a0-0640-40d3-996b-dff4c8e7ecb0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64591852 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.64591852 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/4.kmac_app/latest

Test location /workspace/coverage/default/4.kmac_app_with_partial_data.4062922781
Short name T595
Test name
Test status
Simulation time 13335125100 ps
CPU time 110.32 seconds
Started Aug 06 06:01:05 PM PDT 24
Finished Aug 06 06:02:56 PM PDT 24
Peak memory 258448 kb
Host smart-dacda586-9e10-4995-bdc2-42837ec65f11
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062922781 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_par
tial_data.4062922781 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/4.kmac_burst_write.3104145126
Short name T536
Test name
Test status
Simulation time 34796704701 ps
CPU time 830.6 seconds
Started Aug 06 06:01:07 PM PDT 24
Finished Aug 06 06:14:57 PM PDT 24
Peak memory 243488 kb
Host smart-8b11e040-cea7-49df-bb60-f53b792c7435
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104145126 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.3104145126
+enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_burst_write/latest

Test location /workspace/coverage/default/4.kmac_edn_timeout_error.2312745669
Short name T340
Test name
Test status
Simulation time 41164233 ps
CPU time 1.16 seconds
Started Aug 06 06:01:19 PM PDT 24
Finished Aug 06 06:01:20 PM PDT 24
Peak memory 218776 kb
Host smart-065700f1-a4f4-4765-9c74-26eaca87ad22
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2312745669 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.2312745669 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_mode_error.260288259
Short name T106
Test name
Test status
Simulation time 47648623 ps
CPU time 0.89 seconds
Started Aug 06 06:01:16 PM PDT 24
Finished Aug 06 06:01:17 PM PDT 24
Peak memory 218552 kb
Host smart-03fe72b9-e6e0-4f34-8e20-027647463025
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=260288259 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.260288259 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_ready_error.2120460805
Short name T815
Test name
Test status
Simulation time 2710975249 ps
CPU time 15.5 seconds
Started Aug 06 06:01:19 PM PDT 24
Finished Aug 06 06:01:35 PM PDT 24
Peak memory 222512 kb
Host smart-88b8be13-a1cf-4e96-a9d5-8cc5953e0f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120460805 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.2120460805 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_refresh.549740297
Short name T559
Test name
Test status
Simulation time 34328537627 ps
CPU time 394.03 seconds
Started Aug 06 06:01:07 PM PDT 24
Finished Aug 06 06:07:41 PM PDT 24
Peak memory 511068 kb
Host smart-f4699ae5-a74f-492d-bb7a-26d03ebf271c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549740297 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.549
740297 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/4.kmac_error.462089343
Short name T791
Test name
Test status
Simulation time 64993776300 ps
CPU time 491.15 seconds
Started Aug 06 06:01:06 PM PDT 24
Finished Aug 06 06:09:17 PM PDT 24
Peak memory 585244 kb
Host smart-a447f279-a7a2-488c-ad2e-48e9449c0a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462089343 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.462089343 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_error/latest

Test location /workspace/coverage/default/4.kmac_key_error.2802211517
Short name T564
Test name
Test status
Simulation time 507907626 ps
CPU time 1.52 seconds
Started Aug 06 06:01:19 PM PDT 24
Finished Aug 06 06:01:21 PM PDT 24
Peak memory 226384 kb
Host smart-4ea2875f-1c52-4980-a3aa-585bb20fef1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802211517 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.2802211517 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_key_error/latest

Test location /workspace/coverage/default/4.kmac_lc_escalation.3759293111
Short name T47
Test name
Test status
Simulation time 36122550 ps
CPU time 1.22 seconds
Started Aug 06 06:01:18 PM PDT 24
Finished Aug 06 06:01:19 PM PDT 24
Peak memory 227024 kb
Host smart-3a9de8f7-18e5-4c53-b753-7868a2416151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759293111 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.3759293111 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/4.kmac_lc_escalation/latest

Test location /workspace/coverage/default/4.kmac_long_msg_and_output.856897972
Short name T218
Test name
Test status
Simulation time 24178646541 ps
CPU time 632.28 seconds
Started Aug 06 06:01:06 PM PDT 24
Finished Aug 06 06:11:38 PM PDT 24
Peak memory 547856 kb
Host smart-b254b471-4df0-4374-b1a0-fe0123dce4e7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856897972 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_and
_output.856897972 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/4.kmac_mubi.4029930075
Short name T61
Test name
Test status
Simulation time 33315694090 ps
CPU time 340.27 seconds
Started Aug 06 06:01:06 PM PDT 24
Finished Aug 06 06:06:47 PM PDT 24
Peak memory 477596 kb
Host smart-c00ddb64-2f0f-4c11-b3ae-ba7cb31e1787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029930075 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.4029930075 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_mubi/latest

Test location /workspace/coverage/default/4.kmac_sec_cm.237775256
Short name T107
Test name
Test status
Simulation time 9039529728 ps
CPU time 59.44 seconds
Started Aug 06 06:01:17 PM PDT 24
Finished Aug 06 06:02:17 PM PDT 24
Peak memory 282756 kb
Host smart-3e2e5311-a6e8-425b-8e4f-68af3cd5f49b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237775256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.237775256 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/4.kmac_sec_cm/latest

Test location /workspace/coverage/default/4.kmac_sideload.374104237
Short name T903
Test name
Test status
Simulation time 9639502707 ps
CPU time 60.04 seconds
Started Aug 06 06:01:06 PM PDT 24
Finished Aug 06 06:02:06 PM PDT 24
Peak memory 272932 kb
Host smart-c5338a3c-e66b-4fbe-8fc9-ccada5604f1b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374104237 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.374104237 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_sideload/latest

Test location /workspace/coverage/default/4.kmac_smoke.3285141523
Short name T734
Test name
Test status
Simulation time 15916195420 ps
CPU time 78.15 seconds
Started Aug 06 06:01:04 PM PDT 24
Finished Aug 06 06:02:22 PM PDT 24
Peak memory 227548 kb
Host smart-ef45e3d0-987a-4e88-bce9-60e8901310d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285141523 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.3285141523 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_smoke/latest

Test location /workspace/coverage/default/4.kmac_stress_all.3619032068
Short name T969
Test name
Test status
Simulation time 170401116384 ps
CPU time 972.3 seconds
Started Aug 06 06:01:21 PM PDT 24
Finished Aug 06 06:17:34 PM PDT 24
Peak memory 554184 kb
Host smart-22aa0fb1-84d5-4f08-9212-1c7897c6c36a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3619032068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.3619032068 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_stress_all/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_kmac.1944349403
Short name T239
Test name
Test status
Simulation time 134782420 ps
CPU time 6.32 seconds
Started Aug 06 06:01:09 PM PDT 24
Finished Aug 06 06:01:15 PM PDT 24
Peak memory 227136 kb
Host smart-0cacad7d-d1f1-4941-8170-36c4aeec1554
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944349403 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.kmac_test_vectors_kmac.1944349403 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_kmac_xof.2852114938
Short name T430
Test name
Test status
Simulation time 162404907 ps
CPU time 5.68 seconds
Started Aug 06 06:01:09 PM PDT 24
Finished Aug 06 06:01:15 PM PDT 24
Peak memory 219156 kb
Host smart-23f8db71-d9cc-465c-8fde-fa1a59ccddc6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852114938 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.kmac_test_vectors_kmac_xof.2852114938 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_224.4287014144
Short name T268
Test name
Test status
Simulation time 67336053773 ps
CPU time 3269.83 seconds
Started Aug 06 06:01:05 PM PDT 24
Finished Aug 06 06:55:35 PM PDT 24
Peak memory 3212552 kb
Host smart-31749a8d-5b9f-44e8-bbec-5a02351fd108
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4287014144 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.4287014144 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_256.2161495646
Short name T760
Test name
Test status
Simulation time 83687251045 ps
CPU time 3088.07 seconds
Started Aug 06 06:01:06 PM PDT 24
Finished Aug 06 06:52:34 PM PDT 24
Peak memory 3012128 kb
Host smart-b823e61c-daf3-4ec1-a62b-989cc38c9363
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2161495646 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.2161495646 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_384.3254225132
Short name T494
Test name
Test status
Simulation time 30937315271 ps
CPU time 1721.52 seconds
Started Aug 06 06:01:06 PM PDT 24
Finished Aug 06 06:29:48 PM PDT 24
Peak memory 925012 kb
Host smart-ca2e6ef6-3207-4a15-9c51-95e64d28e564
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3254225132 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.3254225132 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_512.2083930581
Short name T958
Test name
Test status
Simulation time 11274113606 ps
CPU time 1361.33 seconds
Started Aug 06 06:01:07 PM PDT 24
Finished Aug 06 06:23:48 PM PDT 24
Peak memory 716808 kb
Host smart-b6649031-2197-498d-bf17-2545232f3a19
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2083930581 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.2083930581 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_shake_128.3477926202
Short name T737
Test name
Test status
Simulation time 61898423011 ps
CPU time 6128.81 seconds
Started Aug 06 06:01:09 PM PDT 24
Finished Aug 06 07:43:18 PM PDT 24
Peak memory 2663232 kb
Host smart-369624da-3053-4600-90d2-d38cf112b39e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3477926202 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.3477926202 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/40.kmac_alert_test.2406231745
Short name T410
Test name
Test status
Simulation time 35957515 ps
CPU time 0.81 seconds
Started Aug 06 06:14:36 PM PDT 24
Finished Aug 06 06:14:37 PM PDT 24
Peak memory 218576 kb
Host smart-161fb969-d23d-42c9-8a05-9e372461331e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406231745 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.2406231745 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_alert_test/latest

Test location /workspace/coverage/default/40.kmac_app.3858090611
Short name T40
Test name
Test status
Simulation time 15897338148 ps
CPU time 201.44 seconds
Started Aug 06 06:14:25 PM PDT 24
Finished Aug 06 06:17:47 PM PDT 24
Peak memory 374712 kb
Host smart-0c799e3b-fea1-4682-8b83-e293bc215ecd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858090611 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.3858090611 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/40.kmac_app/latest

Test location /workspace/coverage/default/40.kmac_burst_write.3034525708
Short name T988
Test name
Test status
Simulation time 220883269338 ps
CPU time 1685.71 seconds
Started Aug 06 06:14:13 PM PDT 24
Finished Aug 06 06:42:19 PM PDT 24
Peak memory 270484 kb
Host smart-67bba087-e3d1-44dd-a1b0-3c04c0e79883
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034525708 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.303452570
8 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_burst_write/latest

Test location /workspace/coverage/default/40.kmac_entropy_refresh.1996152557
Short name T661
Test name
Test status
Simulation time 27280113598 ps
CPU time 248.57 seconds
Started Aug 06 06:14:25 PM PDT 24
Finished Aug 06 06:18:34 PM PDT 24
Peak memory 301868 kb
Host smart-c2b343e1-a444-47c8-8cb9-f84200e5f9a5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996152557 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.1
996152557 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/40.kmac_error.3067750825
Short name T892
Test name
Test status
Simulation time 151620534 ps
CPU time 11.32 seconds
Started Aug 06 06:14:26 PM PDT 24
Finished Aug 06 06:14:37 PM PDT 24
Peak memory 235236 kb
Host smart-584575e8-b40b-4b1c-a0cb-88777c0d4f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067750825 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.3067750825 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_error/latest

Test location /workspace/coverage/default/40.kmac_key_error.2487911182
Short name T876
Test name
Test status
Simulation time 791963419 ps
CPU time 1.43 seconds
Started Aug 06 06:14:26 PM PDT 24
Finished Aug 06 06:14:28 PM PDT 24
Peak memory 226668 kb
Host smart-f6a5e747-867a-4f84-b13a-3f2d94d286ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487911182 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.2487911182 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_key_error/latest

Test location /workspace/coverage/default/40.kmac_lc_escalation.895745010
Short name T67
Test name
Test status
Simulation time 124844127 ps
CPU time 1.28 seconds
Started Aug 06 06:14:32 PM PDT 24
Finished Aug 06 06:14:34 PM PDT 24
Peak memory 226940 kb
Host smart-b57828ea-d2ad-40d9-88b1-5314e4cf3443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895745010 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.895745010 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/40.kmac_lc_escalation/latest

Test location /workspace/coverage/default/40.kmac_long_msg_and_output.1641135208
Short name T757
Test name
Test status
Simulation time 11041851064 ps
CPU time 1108.14 seconds
Started Aug 06 06:14:15 PM PDT 24
Finished Aug 06 06:32:43 PM PDT 24
Peak memory 752944 kb
Host smart-4a94d2cd-f56b-4f8e-aeda-8284a8673724
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641135208 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_a
nd_output.1641135208 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/40.kmac_sideload.2348781379
Short name T253
Test name
Test status
Simulation time 14934765112 ps
CPU time 291.54 seconds
Started Aug 06 06:14:14 PM PDT 24
Finished Aug 06 06:19:06 PM PDT 24
Peak memory 307868 kb
Host smart-5c0fd269-e043-412b-9d43-847202b44636
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348781379 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.2348781379 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_sideload/latest

Test location /workspace/coverage/default/40.kmac_smoke.2977943090
Short name T387
Test name
Test status
Simulation time 1947351640 ps
CPU time 51.19 seconds
Started Aug 06 06:14:13 PM PDT 24
Finished Aug 06 06:15:05 PM PDT 24
Peak memory 227100 kb
Host smart-d460aed9-1adb-4799-8f2b-f8c78bbe65b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977943090 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.2977943090 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_smoke/latest

Test location /workspace/coverage/default/40.kmac_stress_all.3593185566
Short name T211
Test name
Test status
Simulation time 8820298843 ps
CPU time 582.81 seconds
Started Aug 06 06:14:36 PM PDT 24
Finished Aug 06 06:24:19 PM PDT 24
Peak memory 297256 kb
Host smart-6b1a0abe-3e9f-4387-92e5-57b33d7ee35e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3593185566 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.3593185566 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_stress_all/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_kmac.584061040
Short name T333
Test name
Test status
Simulation time 722139141 ps
CPU time 6.99 seconds
Started Aug 06 06:14:15 PM PDT 24
Finished Aug 06 06:14:22 PM PDT 24
Peak memory 226912 kb
Host smart-6155b881-3a5f-4caf-91a2-365dc3c4a823
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584061040 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.kmac_test_vectors_kmac.584061040 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_kmac_xof.610658379
Short name T372
Test name
Test status
Simulation time 470068094 ps
CPU time 5.89 seconds
Started Aug 06 06:14:32 PM PDT 24
Finished Aug 06 06:14:38 PM PDT 24
Peak memory 219808 kb
Host smart-dfc636f4-713c-400b-a38e-5c359a72cd58
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610658379 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.kmac_test_vectors_kmac_xof.610658379 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_224.257893467
Short name T796
Test name
Test status
Simulation time 28045672675 ps
CPU time 2168.91 seconds
Started Aug 06 06:14:14 PM PDT 24
Finished Aug 06 06:50:23 PM PDT 24
Peak memory 1184052 kb
Host smart-cb1f2c21-ef6a-4d36-b209-0574e784f829
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=257893467 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_224.257893467 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_256.4128665780
Short name T310
Test name
Test status
Simulation time 1568927221776 ps
CPU time 3582.83 seconds
Started Aug 06 06:14:13 PM PDT 24
Finished Aug 06 07:13:57 PM PDT 24
Peak memory 3139868 kb
Host smart-ee8d7bd4-8c9c-4932-bc67-f4d690e2d1b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4128665780 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_256.4128665780 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_384.373079469
Short name T671
Test name
Test status
Simulation time 54367459557 ps
CPU time 2371.94 seconds
Started Aug 06 06:14:15 PM PDT 24
Finished Aug 06 06:53:48 PM PDT 24
Peak memory 2324800 kb
Host smart-aba2ed3c-56c9-4d12-98d0-dd2fe0893595
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=373079469 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_384.373079469 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_512.3118502653
Short name T984
Test name
Test status
Simulation time 99348572341 ps
CPU time 1712.92 seconds
Started Aug 06 06:14:13 PM PDT 24
Finished Aug 06 06:42:46 PM PDT 24
Peak memory 1666316 kb
Host smart-510f297e-5635-4bcc-b37c-bae4293a12a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3118502653 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_512.3118502653 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_shake_128.2051502412
Short name T747
Test name
Test status
Simulation time 63788732892 ps
CPU time 6538.25 seconds
Started Aug 06 06:14:15 PM PDT 24
Finished Aug 06 08:03:14 PM PDT 24
Peak memory 2703328 kb
Host smart-d9aed9a4-d3dd-4fb1-ab8a-301758b0d7fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2051502412 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_128.2051502412 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_shake_256.3560367448
Short name T466
Test name
Test status
Simulation time 55078801390 ps
CPU time 5210.81 seconds
Started Aug 06 06:14:12 PM PDT 24
Finished Aug 06 07:41:04 PM PDT 24
Peak memory 2239784 kb
Host smart-e5f0cabb-b79b-476b-a157-8c35a6eae128
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3560367448 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_256.3560367448 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/41.kmac_alert_test.2943964172
Short name T252
Test name
Test status
Simulation time 17343677 ps
CPU time 0.85 seconds
Started Aug 06 06:15:11 PM PDT 24
Finished Aug 06 06:15:12 PM PDT 24
Peak memory 218568 kb
Host smart-edd0c7af-4ef8-4f88-9b65-4b74be388460
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943964172 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.2943964172 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_alert_test/latest

Test location /workspace/coverage/default/41.kmac_app.1775986975
Short name T286
Test name
Test status
Simulation time 709986512 ps
CPU time 8.99 seconds
Started Aug 06 06:14:52 PM PDT 24
Finished Aug 06 06:15:01 PM PDT 24
Peak memory 235248 kb
Host smart-7fefbe6a-e351-4bd4-94d0-b347f74c5524
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775986975 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.1775986975 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/41.kmac_app/latest

Test location /workspace/coverage/default/41.kmac_burst_write.2081636585
Short name T577
Test name
Test status
Simulation time 23432585271 ps
CPU time 673 seconds
Started Aug 06 06:14:36 PM PDT 24
Finished Aug 06 06:25:50 PM PDT 24
Peak memory 243496 kb
Host smart-3f49ee79-3d39-439c-b427-47dca832e43f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081636585 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.208163658
5 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_burst_write/latest

Test location /workspace/coverage/default/41.kmac_entropy_refresh.1194967885
Short name T925
Test name
Test status
Simulation time 13403566452 ps
CPU time 166.58 seconds
Started Aug 06 06:15:00 PM PDT 24
Finished Aug 06 06:17:46 PM PDT 24
Peak memory 275532 kb
Host smart-8037f209-0a6a-427b-aa37-c373bf264834
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194967885 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_entropy_refresh.1
194967885 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/41.kmac_error.1875474632
Short name T22
Test name
Test status
Simulation time 9954213083 ps
CPU time 338.98 seconds
Started Aug 06 06:15:01 PM PDT 24
Finished Aug 06 06:20:40 PM PDT 24
Peak memory 482600 kb
Host smart-7efe62ce-a8a3-4908-ba59-aa077bec6442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875474632 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.1875474632 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_error/latest

Test location /workspace/coverage/default/41.kmac_key_error.283209652
Short name T679
Test name
Test status
Simulation time 3529224501 ps
CPU time 12.54 seconds
Started Aug 06 06:14:59 PM PDT 24
Finished Aug 06 06:15:12 PM PDT 24
Peak memory 227012 kb
Host smart-f37f3fc6-b7a7-4f93-92f6-f206b482d79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283209652 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.283209652 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_key_error/latest

Test location /workspace/coverage/default/41.kmac_lc_escalation.2712247325
Short name T885
Test name
Test status
Simulation time 210897419 ps
CPU time 1.48 seconds
Started Aug 06 06:15:00 PM PDT 24
Finished Aug 06 06:15:02 PM PDT 24
Peak memory 226876 kb
Host smart-c0cc85c2-d8c2-4eeb-b6ac-0f47e53650f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712247325 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.2712247325 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/41.kmac_lc_escalation/latest

Test location /workspace/coverage/default/41.kmac_long_msg_and_output.2448993075
Short name T563
Test name
Test status
Simulation time 16800957987 ps
CPU time 1072.91 seconds
Started Aug 06 06:14:35 PM PDT 24
Finished Aug 06 06:32:29 PM PDT 24
Peak memory 773700 kb
Host smart-a12a9e67-34c3-45b0-91cb-94f846e730f0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448993075 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_a
nd_output.2448993075 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/41.kmac_sideload.2224549589
Short name T514
Test name
Test status
Simulation time 19477231254 ps
CPU time 503.09 seconds
Started Aug 06 06:14:37 PM PDT 24
Finished Aug 06 06:23:00 PM PDT 24
Peak memory 591964 kb
Host smart-840ea7f6-38fb-432d-a496-80285777c63d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224549589 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.2224549589 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_sideload/latest

Test location /workspace/coverage/default/41.kmac_smoke.257790926
Short name T529
Test name
Test status
Simulation time 3891073531 ps
CPU time 38.12 seconds
Started Aug 06 06:14:36 PM PDT 24
Finished Aug 06 06:15:14 PM PDT 24
Peak memory 222048 kb
Host smart-4b6bb5db-4657-40c4-a748-741bb7bc105e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257790926 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.257790926 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_smoke/latest

Test location /workspace/coverage/default/41.kmac_stress_all.4292938243
Short name T354
Test name
Test status
Simulation time 12182821680 ps
CPU time 1076.23 seconds
Started Aug 06 06:15:11 PM PDT 24
Finished Aug 06 06:33:07 PM PDT 24
Peak memory 605612 kb
Host smart-50fc395c-8569-499d-81f3-ebf046e7cf27
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4292938243 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.4292938243 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_stress_all/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_kmac.2853809586
Short name T409
Test name
Test status
Simulation time 91682028 ps
CPU time 6.31 seconds
Started Aug 06 06:14:54 PM PDT 24
Finished Aug 06 06:15:00 PM PDT 24
Peak memory 219928 kb
Host smart-634d75fb-4992-4052-85b1-a7b9c14eae4c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853809586 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.kmac_test_vectors_kmac.2853809586 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_kmac_xof.1129479044
Short name T938
Test name
Test status
Simulation time 847709696 ps
CPU time 6.68 seconds
Started Aug 06 06:14:52 PM PDT 24
Finished Aug 06 06:14:58 PM PDT 24
Peak memory 220004 kb
Host smart-29bd1fb5-fd26-44db-88d5-5d0242386568
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129479044 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.kmac_test_vectors_kmac_xof.1129479044 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_224.1808816983
Short name T359
Test name
Test status
Simulation time 20711235903 ps
CPU time 2194.02 seconds
Started Aug 06 06:14:37 PM PDT 24
Finished Aug 06 06:51:11 PM PDT 24
Peak memory 1198260 kb
Host smart-7aaea07b-33e0-488a-a96b-4ac55d098d70
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1808816983 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_224.1808816983 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_256.2498337868
Short name T403
Test name
Test status
Simulation time 77423327331 ps
CPU time 2168.92 seconds
Started Aug 06 06:14:36 PM PDT 24
Finished Aug 06 06:50:45 PM PDT 24
Peak memory 1150032 kb
Host smart-ea11eb1b-0fae-4610-a74b-2fa9921db7fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2498337868 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_256.2498337868 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_384.201957148
Short name T915
Test name
Test status
Simulation time 168680904257 ps
CPU time 2429.41 seconds
Started Aug 06 06:14:51 PM PDT 24
Finished Aug 06 06:55:21 PM PDT 24
Peak memory 2382168 kb
Host smart-d0d4852b-591b-4ef2-9733-0a54803bffba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=201957148 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_384.201957148 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_512.600767739
Short name T573
Test name
Test status
Simulation time 289033003096 ps
CPU time 1758.84 seconds
Started Aug 06 06:14:53 PM PDT 24
Finished Aug 06 06:44:13 PM PDT 24
Peak memory 1723992 kb
Host smart-8461e103-6bc1-49d7-8228-e4aac53de4bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=600767739 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_512.600767739 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_shake_256.4191650040
Short name T214
Test name
Test status
Simulation time 51554884445 ps
CPU time 5051.1 seconds
Started Aug 06 06:14:52 PM PDT 24
Finished Aug 06 07:39:04 PM PDT 24
Peak memory 2192536 kb
Host smart-59af6bc0-48a9-4613-b688-7a45fb94537c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4191650040 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_256.4191650040 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/42.kmac_alert_test.3502160762
Short name T823
Test name
Test status
Simulation time 32900585 ps
CPU time 0.9 seconds
Started Aug 06 06:15:57 PM PDT 24
Finished Aug 06 06:15:57 PM PDT 24
Peak memory 218528 kb
Host smart-b82e8014-b34c-421f-9118-6f6a7254f74c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502160762 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.3502160762 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_alert_test/latest

Test location /workspace/coverage/default/42.kmac_app.2277601011
Short name T636
Test name
Test status
Simulation time 4580903998 ps
CPU time 194.8 seconds
Started Aug 06 06:15:23 PM PDT 24
Finished Aug 06 06:18:38 PM PDT 24
Peak memory 285068 kb
Host smart-74bc7a95-d090-4bb8-adff-44d59b9f366d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277601011 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.2277601011 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/42.kmac_app/latest

Test location /workspace/coverage/default/42.kmac_burst_write.851722547
Short name T966
Test name
Test status
Simulation time 18376927919 ps
CPU time 231.87 seconds
Started Aug 06 06:15:23 PM PDT 24
Finished Aug 06 06:19:15 PM PDT 24
Peak memory 229676 kb
Host smart-382d4dbc-448c-4417-91dc-696829082dcd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851722547 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.851722547
+enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_burst_write/latest

Test location /workspace/coverage/default/42.kmac_entropy_refresh.3852411847
Short name T76
Test name
Test status
Simulation time 4886766903 ps
CPU time 104.37 seconds
Started Aug 06 06:15:23 PM PDT 24
Finished Aug 06 06:17:07 PM PDT 24
Peak memory 291736 kb
Host smart-5f79b116-3bca-4996-acdb-8ec64f7657ac
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852411847 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.3
852411847 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/42.kmac_error.1072685312
Short name T852
Test name
Test status
Simulation time 70217520564 ps
CPU time 235.8 seconds
Started Aug 06 06:15:22 PM PDT 24
Finished Aug 06 06:19:18 PM PDT 24
Peak memory 438492 kb
Host smart-182aa831-7e2e-4dcf-970f-fb480c3e81fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072685312 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.1072685312 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_error/latest

Test location /workspace/coverage/default/42.kmac_key_error.394929345
Short name T225
Test name
Test status
Simulation time 1089095515 ps
CPU time 2.75 seconds
Started Aug 06 06:15:22 PM PDT 24
Finished Aug 06 06:15:25 PM PDT 24
Peak memory 227148 kb
Host smart-3988b0d9-ca64-459f-9955-46a427175ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394929345 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.394929345 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_key_error/latest

Test location /workspace/coverage/default/42.kmac_lc_escalation.107218677
Short name T733
Test name
Test status
Simulation time 52412604 ps
CPU time 1.38 seconds
Started Aug 06 06:15:36 PM PDT 24
Finished Aug 06 06:15:37 PM PDT 24
Peak memory 226996 kb
Host smart-453bedc4-5da8-4816-a6ee-a5a8c9e10018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107218677 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.107218677 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/42.kmac_lc_escalation/latest

Test location /workspace/coverage/default/42.kmac_long_msg_and_output.2955957870
Short name T904
Test name
Test status
Simulation time 26541567005 ps
CPU time 813.36 seconds
Started Aug 06 06:15:12 PM PDT 24
Finished Aug 06 06:28:46 PM PDT 24
Peak memory 581884 kb
Host smart-3bd81ef3-0c13-43ab-a9f7-255b015ba91a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955957870 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_a
nd_output.2955957870 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/42.kmac_sideload.744276555
Short name T281
Test name
Test status
Simulation time 5046932222 ps
CPU time 35.64 seconds
Started Aug 06 06:15:12 PM PDT 24
Finished Aug 06 06:15:47 PM PDT 24
Peak memory 252356 kb
Host smart-c7c717cb-57f6-4aa7-9397-6126781a0bb2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744276555 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.744276555 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_sideload/latest

Test location /workspace/coverage/default/42.kmac_smoke.130256000
Short name T77
Test name
Test status
Simulation time 716565872 ps
CPU time 25.95 seconds
Started Aug 06 06:15:11 PM PDT 24
Finished Aug 06 06:15:37 PM PDT 24
Peak memory 222044 kb
Host smart-91f97e05-2542-40bf-93cf-c7bcef723585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130256000 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.130256000 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_smoke/latest

Test location /workspace/coverage/default/42.kmac_stress_all.4054735816
Short name T447
Test name
Test status
Simulation time 105216137200 ps
CPU time 900.19 seconds
Started Aug 06 06:15:35 PM PDT 24
Finished Aug 06 06:30:36 PM PDT 24
Peak memory 733080 kb
Host smart-39334b81-0cc6-435e-9de1-6794e7a407af
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4054735816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.4054735816 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_stress_all/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_kmac.430120590
Short name T973
Test name
Test status
Simulation time 221729738 ps
CPU time 5.76 seconds
Started Aug 06 06:15:24 PM PDT 24
Finished Aug 06 06:15:30 PM PDT 24
Peak memory 227000 kb
Host smart-2f55add0-8caa-4493-93e0-258950b15220
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430120590 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.kmac_test_vectors_kmac.430120590 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_kmac_xof.1743675334
Short name T172
Test name
Test status
Simulation time 118976449 ps
CPU time 5.93 seconds
Started Aug 06 06:15:23 PM PDT 24
Finished Aug 06 06:15:29 PM PDT 24
Peak memory 227020 kb
Host smart-7e147bff-595f-4b56-944c-bb94ac1f4750
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743675334 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.kmac_test_vectors_kmac_xof.1743675334 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_384.3804166896
Short name T835
Test name
Test status
Simulation time 31260327015 ps
CPU time 1722.89 seconds
Started Aug 06 06:15:24 PM PDT 24
Finished Aug 06 06:44:07 PM PDT 24
Peak memory 937024 kb
Host smart-3df9a073-cfe4-48a5-aef0-858dd7f693a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3804166896 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_384.3804166896 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_512.3548358676
Short name T929
Test name
Test status
Simulation time 102624641250 ps
CPU time 1869.34 seconds
Started Aug 06 06:15:23 PM PDT 24
Finished Aug 06 06:46:33 PM PDT 24
Peak memory 1728232 kb
Host smart-061f7766-d4f9-45e3-b419-01f17682fd41
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3548358676 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_512.3548358676 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/43.kmac_alert_test.1196503611
Short name T840
Test name
Test status
Simulation time 54040365 ps
CPU time 0.89 seconds
Started Aug 06 06:16:17 PM PDT 24
Finished Aug 06 06:16:17 PM PDT 24
Peak memory 218596 kb
Host smart-7384aaaf-5508-42d8-a56f-4963d559d6bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196503611 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.1196503611 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_alert_test/latest

Test location /workspace/coverage/default/43.kmac_burst_write.2744183654
Short name T706
Test name
Test status
Simulation time 8672190800 ps
CPU time 457.16 seconds
Started Aug 06 06:15:56 PM PDT 24
Finished Aug 06 06:23:33 PM PDT 24
Peak memory 243548 kb
Host smart-37071fea-f9b7-4243-a25b-7010f135ae93
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744183654 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.274418365
4 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_burst_write/latest

Test location /workspace/coverage/default/43.kmac_entropy_refresh.3202186472
Short name T576
Test name
Test status
Simulation time 210823300 ps
CPU time 7.07 seconds
Started Aug 06 06:16:16 PM PDT 24
Finished Aug 06 06:16:23 PM PDT 24
Peak memory 225324 kb
Host smart-7f1581ac-4fce-4fd5-857d-34e02253e49f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202186472 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.3
202186472 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/43.kmac_error.1153599956
Short name T500
Test name
Test status
Simulation time 15365417397 ps
CPU time 530.04 seconds
Started Aug 06 06:16:18 PM PDT 24
Finished Aug 06 06:25:08 PM PDT 24
Peak memory 632236 kb
Host smart-ac17ec32-e8a5-4e9a-8b30-87c32d9ec66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153599956 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.1153599956 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_error/latest

Test location /workspace/coverage/default/43.kmac_key_error.2136399632
Short name T440
Test name
Test status
Simulation time 7366703189 ps
CPU time 7.82 seconds
Started Aug 06 06:16:20 PM PDT 24
Finished Aug 06 06:16:28 PM PDT 24
Peak memory 226996 kb
Host smart-ea102324-56d0-4218-9b9e-9d6b507d48b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136399632 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.2136399632 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_key_error/latest

Test location /workspace/coverage/default/43.kmac_lc_escalation.3994916104
Short name T376
Test name
Test status
Simulation time 167555001 ps
CPU time 1.71 seconds
Started Aug 06 06:16:17 PM PDT 24
Finished Aug 06 06:16:19 PM PDT 24
Peak memory 227024 kb
Host smart-fcd956f2-60c9-45ea-a863-0f085b002fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994916104 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.3994916104 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/43.kmac_lc_escalation/latest

Test location /workspace/coverage/default/43.kmac_long_msg_and_output.556340218
Short name T779
Test name
Test status
Simulation time 47668658741 ps
CPU time 1584.13 seconds
Started Aug 06 06:15:58 PM PDT 24
Finished Aug 06 06:42:22 PM PDT 24
Peak memory 907236 kb
Host smart-deac116d-5463-4f96-afce-0ab9f3b66fd7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556340218 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_an
d_output.556340218 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/43.kmac_sideload.1800570637
Short name T515
Test name
Test status
Simulation time 183935857 ps
CPU time 16.87 seconds
Started Aug 06 06:15:56 PM PDT 24
Finished Aug 06 06:16:13 PM PDT 24
Peak memory 227068 kb
Host smart-4d78b404-4e60-42c7-bc17-3a0f9abf280d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800570637 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.1800570637 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_sideload/latest

Test location /workspace/coverage/default/43.kmac_smoke.4230834012
Short name T274
Test name
Test status
Simulation time 5993989289 ps
CPU time 37.07 seconds
Started Aug 06 06:15:57 PM PDT 24
Finished Aug 06 06:16:34 PM PDT 24
Peak memory 222176 kb
Host smart-eb9e7a7a-263b-4d1d-b2b6-29661ed914cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230834012 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.4230834012 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_smoke/latest

Test location /workspace/coverage/default/43.kmac_stress_all.3799120660
Short name T212
Test name
Test status
Simulation time 16783387978 ps
CPU time 1565.38 seconds
Started Aug 06 06:16:19 PM PDT 24
Finished Aug 06 06:42:24 PM PDT 24
Peak memory 449308 kb
Host smart-c5155e94-6f03-41bd-916f-339552ab74aa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3799120660 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.3799120660 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_stress_all/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_kmac.1747257590
Short name T321
Test name
Test status
Simulation time 620054617 ps
CPU time 6.83 seconds
Started Aug 06 06:15:56 PM PDT 24
Finished Aug 06 06:16:03 PM PDT 24
Peak memory 227056 kb
Host smart-c45ebf1f-ea31-44cb-a071-a4690d016866
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747257590 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.kmac_test_vectors_kmac.1747257590 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_kmac_xof.3512920163
Short name T970
Test name
Test status
Simulation time 120800112 ps
CPU time 5.72 seconds
Started Aug 06 06:15:56 PM PDT 24
Finished Aug 06 06:16:01 PM PDT 24
Peak memory 219084 kb
Host smart-075d73eb-90aa-4e70-b98e-6f516f873e44
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512920163 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.kmac_test_vectors_kmac_xof.3512920163 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_224.462549544
Short name T776
Test name
Test status
Simulation time 109258412610 ps
CPU time 2262.9 seconds
Started Aug 06 06:15:56 PM PDT 24
Finished Aug 06 06:53:40 PM PDT 24
Peak memory 1224748 kb
Host smart-a0d974f5-91a9-4496-879b-98c3969f1f88
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=462549544 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_224.462549544 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_256.2801396746
Short name T821
Test name
Test status
Simulation time 320089164087 ps
CPU time 2308.21 seconds
Started Aug 06 06:15:56 PM PDT 24
Finished Aug 06 06:54:25 PM PDT 24
Peak memory 1144056 kb
Host smart-b1f94fa0-01d5-48fc-9bf6-ff64645d84ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2801396746 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_256.2801396746 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_384.493215684
Short name T689
Test name
Test status
Simulation time 30866984368 ps
CPU time 1679.94 seconds
Started Aug 06 06:15:56 PM PDT 24
Finished Aug 06 06:43:56 PM PDT 24
Peak memory 925268 kb
Host smart-89f9fdc5-36e6-4893-abcd-c07cd6bfc9ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=493215684 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_384.493215684 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_512.1800543200
Short name T303
Test name
Test status
Simulation time 66306129691 ps
CPU time 1499.37 seconds
Started Aug 06 06:15:56 PM PDT 24
Finished Aug 06 06:40:55 PM PDT 24
Peak memory 1698372 kb
Host smart-69c55563-04cb-454a-ae8a-c7b970f8b17e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1800543200 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_512.1800543200 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_shake_128.3669463729
Short name T917
Test name
Test status
Simulation time 251887886901 ps
CPU time 6589.36 seconds
Started Aug 06 06:15:55 PM PDT 24
Finished Aug 06 08:05:45 PM PDT 24
Peak memory 2729528 kb
Host smart-007c127e-a37b-4588-8291-7fb634899d6a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3669463729 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_128.3669463729 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_shake_256.3178919007
Short name T811
Test name
Test status
Simulation time 237406054548 ps
CPU time 5508.39 seconds
Started Aug 06 06:15:56 PM PDT 24
Finished Aug 06 07:47:46 PM PDT 24
Peak memory 2250024 kb
Host smart-81df8f0a-2b2c-44ed-8366-9f071027ad35
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3178919007 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_256.3178919007 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/44.kmac_alert_test.3129149224
Short name T242
Test name
Test status
Simulation time 54310414 ps
CPU time 0.86 seconds
Started Aug 06 06:16:35 PM PDT 24
Finished Aug 06 06:16:36 PM PDT 24
Peak memory 218516 kb
Host smart-648fa270-8a35-4275-9da6-4693cc0efca9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129149224 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.3129149224 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_alert_test/latest

Test location /workspace/coverage/default/44.kmac_app.4247007136
Short name T441
Test name
Test status
Simulation time 10626303979 ps
CPU time 115.55 seconds
Started Aug 06 06:16:36 PM PDT 24
Finished Aug 06 06:18:32 PM PDT 24
Peak memory 304768 kb
Host smart-a13253d4-7dae-4bf1-becf-6d0ba8b09dbf
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247007136 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.4247007136 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/44.kmac_app/latest

Test location /workspace/coverage/default/44.kmac_burst_write.1009275053
Short name T196
Test name
Test status
Simulation time 2252235472 ps
CPU time 27.26 seconds
Started Aug 06 06:16:17 PM PDT 24
Finished Aug 06 06:16:44 PM PDT 24
Peak memory 227108 kb
Host smart-2ca53c61-158a-4728-9def-8777d0e9bf2e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009275053 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.100927505
3 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_burst_write/latest

Test location /workspace/coverage/default/44.kmac_entropy_refresh.3967768420
Short name T297
Test name
Test status
Simulation time 12381652311 ps
CPU time 392.04 seconds
Started Aug 06 06:16:33 PM PDT 24
Finished Aug 06 06:23:05 PM PDT 24
Peak memory 483980 kb
Host smart-87231deb-c3ab-4c7f-9aa5-1cfa55c7b228
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967768420 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.3
967768420 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/44.kmac_error.3482492548
Short name T978
Test name
Test status
Simulation time 2766451779 ps
CPU time 92.95 seconds
Started Aug 06 06:16:36 PM PDT 24
Finished Aug 06 06:18:09 PM PDT 24
Peak memory 291544 kb
Host smart-4d236351-a4c4-4186-b4c3-a62d557c1f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482492548 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_error.3482492548 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_error/latest

Test location /workspace/coverage/default/44.kmac_key_error.1655750487
Short name T545
Test name
Test status
Simulation time 5095127182 ps
CPU time 9.46 seconds
Started Aug 06 06:16:33 PM PDT 24
Finished Aug 06 06:16:43 PM PDT 24
Peak memory 227008 kb
Host smart-ed7e5553-c1e3-40ee-8966-b583d172d0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655750487 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.1655750487 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_key_error/latest

Test location /workspace/coverage/default/44.kmac_lc_escalation.2316081019
Short name T85
Test name
Test status
Simulation time 150360853 ps
CPU time 1.58 seconds
Started Aug 06 06:16:35 PM PDT 24
Finished Aug 06 06:16:36 PM PDT 24
Peak memory 227048 kb
Host smart-0d0b017d-9d4f-440b-aa7e-8ca5ddddda56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316081019 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.2316081019 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/44.kmac_lc_escalation/latest

Test location /workspace/coverage/default/44.kmac_long_msg_and_output.1438042614
Short name T848
Test name
Test status
Simulation time 96973495404 ps
CPU time 3307.1 seconds
Started Aug 06 06:16:18 PM PDT 24
Finished Aug 06 07:11:25 PM PDT 24
Peak memory 1708948 kb
Host smart-509efa8d-9690-44e7-89b9-c3cb50ce79ab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438042614 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_a
nd_output.1438042614 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/44.kmac_sideload.2772804804
Short name T583
Test name
Test status
Simulation time 19917316073 ps
CPU time 339.64 seconds
Started Aug 06 06:16:15 PM PDT 24
Finished Aug 06 06:21:54 PM PDT 24
Peak memory 473184 kb
Host smart-4d5c7125-2081-4c95-a9c9-2c3929d2b2c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772804804 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.2772804804 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_sideload/latest

Test location /workspace/coverage/default/44.kmac_smoke.2863998029
Short name T631
Test name
Test status
Simulation time 405672591 ps
CPU time 9.25 seconds
Started Aug 06 06:16:18 PM PDT 24
Finished Aug 06 06:16:27 PM PDT 24
Peak memory 226908 kb
Host smart-9cf368ca-afb0-4e42-97e3-870231110ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863998029 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.2863998029 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_smoke/latest

Test location /workspace/coverage/default/44.kmac_stress_all.2837517742
Short name T419
Test name
Test status
Simulation time 138728809888 ps
CPU time 525.29 seconds
Started Aug 06 06:16:34 PM PDT 24
Finished Aug 06 06:25:19 PM PDT 24
Peak memory 748928 kb
Host smart-40e0ee15-50c2-4a10-851b-deaca63dccc5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2837517742 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all.2837517742 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_stress_all/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_kmac.48712116
Short name T489
Test name
Test status
Simulation time 174974748 ps
CPU time 6.27 seconds
Started Aug 06 06:16:32 PM PDT 24
Finished Aug 06 06:16:38 PM PDT 24
Peak memory 219004 kb
Host smart-857737e5-c59b-4afb-a654-fb4b6d8965dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48712116 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 44.kmac_test_vectors_kmac.48712116 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_kmac_xof.1715758917
Short name T302
Test name
Test status
Simulation time 364797378 ps
CPU time 7.31 seconds
Started Aug 06 06:16:32 PM PDT 24
Finished Aug 06 06:16:39 PM PDT 24
Peak memory 219940 kb
Host smart-2eeb49ba-05b1-4ef3-b807-6ebaed8f7035
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715758917 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.kmac_test_vectors_kmac_xof.1715758917 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_224.885768770
Short name T941
Test name
Test status
Simulation time 20421149171 ps
CPU time 2200.02 seconds
Started Aug 06 06:16:17 PM PDT 24
Finished Aug 06 06:52:57 PM PDT 24
Peak memory 1207392 kb
Host smart-bc2908c0-4972-4294-8a18-d86d106e59fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=885768770 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_224.885768770 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_256.1117034276
Short name T296
Test name
Test status
Simulation time 212327179230 ps
CPU time 2147.46 seconds
Started Aug 06 06:16:16 PM PDT 24
Finished Aug 06 06:52:04 PM PDT 24
Peak memory 1144408 kb
Host smart-ab8929f6-59cd-4164-a590-a27fd19b4f7f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1117034276 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_256.1117034276 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_384.247693453
Short name T810
Test name
Test status
Simulation time 147428650807 ps
CPU time 2539.89 seconds
Started Aug 06 06:16:17 PM PDT 24
Finished Aug 06 06:58:37 PM PDT 24
Peak memory 2356312 kb
Host smart-a2de0dab-c709-4f24-8bf4-1c34d1e2b19b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=247693453 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_384.247693453 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_512.2866983683
Short name T806
Test name
Test status
Simulation time 42353145111 ps
CPU time 1647.33 seconds
Started Aug 06 06:16:17 PM PDT 24
Finished Aug 06 06:43:44 PM PDT 24
Peak memory 1712876 kb
Host smart-cf30c52c-3bb6-48ca-a327-fb096fecd4c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2866983683 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_512.2866983683 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/45.kmac_alert_test.4133222655
Short name T326
Test name
Test status
Simulation time 25881224 ps
CPU time 0.83 seconds
Started Aug 06 06:16:56 PM PDT 24
Finished Aug 06 06:16:57 PM PDT 24
Peak memory 218616 kb
Host smart-aaa2c573-0e9c-4053-942d-b0e7d86cb46d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133222655 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.4133222655 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_alert_test/latest

Test location /workspace/coverage/default/45.kmac_app.442168638
Short name T673
Test name
Test status
Simulation time 10761523886 ps
CPU time 95.42 seconds
Started Aug 06 06:16:49 PM PDT 24
Finished Aug 06 06:18:24 PM PDT 24
Peak memory 255012 kb
Host smart-9395f57a-4073-409c-b88e-3d82f1984e9d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442168638 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.442168638 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/45.kmac_app/latest

Test location /workspace/coverage/default/45.kmac_burst_write.3054855844
Short name T936
Test name
Test status
Simulation time 8711654577 ps
CPU time 880.35 seconds
Started Aug 06 06:16:34 PM PDT 24
Finished Aug 06 06:31:14 PM PDT 24
Peak memory 242416 kb
Host smart-49d39f5d-c419-448a-b418-61a82ff54a9f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054855844 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.305485584
4 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_burst_write/latest

Test location /workspace/coverage/default/45.kmac_entropy_refresh.580653570
Short name T829
Test name
Test status
Simulation time 10362011811 ps
CPU time 49.82 seconds
Started Aug 06 06:16:46 PM PDT 24
Finished Aug 06 06:17:35 PM PDT 24
Peak memory 256488 kb
Host smart-f9a90222-f35d-41f1-b967-0da28340807d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580653570 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_entropy_refresh.58
0653570 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/45.kmac_error.189572988
Short name T819
Test name
Test status
Simulation time 9734905108 ps
CPU time 351.49 seconds
Started Aug 06 06:16:45 PM PDT 24
Finished Aug 06 06:22:37 PM PDT 24
Peak memory 492608 kb
Host smart-54fdacc4-a6b8-4dc7-ba0c-1fd9e9824968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189572988 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.189572988 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_error/latest

Test location /workspace/coverage/default/45.kmac_key_error.3806986193
Short name T771
Test name
Test status
Simulation time 5689687432 ps
CPU time 10.68 seconds
Started Aug 06 06:16:49 PM PDT 24
Finished Aug 06 06:16:59 PM PDT 24
Peak memory 227008 kb
Host smart-495bf114-0ed3-4740-ae70-dd5d3f2beb60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806986193 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.3806986193 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_key_error/latest

Test location /workspace/coverage/default/45.kmac_lc_escalation.3135278402
Short name T383
Test name
Test status
Simulation time 74466523 ps
CPU time 1.25 seconds
Started Aug 06 06:16:44 PM PDT 24
Finished Aug 06 06:16:46 PM PDT 24
Peak memory 226972 kb
Host smart-dc57cbea-ad3c-490f-8472-8e3bcd3d0a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135278402 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.3135278402 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/45.kmac_lc_escalation/latest

Test location /workspace/coverage/default/45.kmac_long_msg_and_output.3196628284
Short name T291
Test name
Test status
Simulation time 198939557080 ps
CPU time 2630.83 seconds
Started Aug 06 06:16:36 PM PDT 24
Finished Aug 06 07:00:27 PM PDT 24
Peak memory 2528752 kb
Host smart-e65fd798-9ab2-4ab9-ba75-a9055c595703
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196628284 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_a
nd_output.3196628284 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/45.kmac_sideload.1019021148
Short name T562
Test name
Test status
Simulation time 15326824233 ps
CPU time 397.2 seconds
Started Aug 06 06:16:33 PM PDT 24
Finished Aug 06 06:23:10 PM PDT 24
Peak memory 563256 kb
Host smart-2f622b1c-f3fd-4246-a56d-b863b569dd53
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019021148 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.1019021148 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_sideload/latest

Test location /workspace/coverage/default/45.kmac_smoke.948380851
Short name T935
Test name
Test status
Simulation time 2824774109 ps
CPU time 33.53 seconds
Started Aug 06 06:16:33 PM PDT 24
Finished Aug 06 06:17:07 PM PDT 24
Peak memory 227200 kb
Host smart-e170eabe-2b8f-4b0e-b1db-25344972ae9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948380851 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.948380851 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_smoke/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_kmac.380873411
Short name T675
Test name
Test status
Simulation time 404050683 ps
CPU time 5.73 seconds
Started Aug 06 06:16:44 PM PDT 24
Finished Aug 06 06:16:50 PM PDT 24
Peak memory 227052 kb
Host smart-37af224d-bc11-4ec0-a0df-d913b6be3cbb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380873411 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.kmac_test_vectors_kmac.380873411 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_kmac_xof.3469066890
Short name T471
Test name
Test status
Simulation time 104746758 ps
CPU time 5.3 seconds
Started Aug 06 06:16:48 PM PDT 24
Finished Aug 06 06:16:54 PM PDT 24
Peak memory 219912 kb
Host smart-9feda687-ce01-4a2f-b752-4af3c472270e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469066890 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.kmac_test_vectors_kmac_xof.3469066890 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_256.854203219
Short name T884
Test name
Test status
Simulation time 108949193152 ps
CPU time 1934.04 seconds
Started Aug 06 06:16:35 PM PDT 24
Finished Aug 06 06:48:49 PM PDT 24
Peak memory 1098536 kb
Host smart-4b44a712-4646-41ef-afe9-dae091542094
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=854203219 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_256.854203219 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_384.1613135762
Short name T718
Test name
Test status
Simulation time 59710849779 ps
CPU time 1581.88 seconds
Started Aug 06 06:16:34 PM PDT 24
Finished Aug 06 06:42:56 PM PDT 24
Peak memory 912056 kb
Host smart-70292717-4458-4deb-8d2e-e93d7da983c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1613135762 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_384.1613135762 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_512.1987425297
Short name T322
Test name
Test status
Simulation time 11131351227 ps
CPU time 1214.01 seconds
Started Aug 06 06:16:45 PM PDT 24
Finished Aug 06 06:36:59 PM PDT 24
Peak memory 713064 kb
Host smart-4b836961-872a-4d78-9fb2-3a490b254dc7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1987425297 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_512.1987425297 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/46.kmac_alert_test.4061979751
Short name T797
Test name
Test status
Simulation time 52461542 ps
CPU time 0.84 seconds
Started Aug 06 06:17:22 PM PDT 24
Finished Aug 06 06:17:23 PM PDT 24
Peak memory 218568 kb
Host smart-6c6f08df-b63f-4172-a815-c84723a282da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061979751 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.4061979751 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_alert_test/latest

Test location /workspace/coverage/default/46.kmac_app.764070307
Short name T730
Test name
Test status
Simulation time 9725040787 ps
CPU time 144.94 seconds
Started Aug 06 06:17:21 PM PDT 24
Finished Aug 06 06:19:46 PM PDT 24
Peak memory 328808 kb
Host smart-5b85bb64-509c-4c76-b1cd-f2fd770c4f78
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764070307 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.764070307 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/46.kmac_app/latest

Test location /workspace/coverage/default/46.kmac_burst_write.3666825956
Short name T843
Test name
Test status
Simulation time 253746732651 ps
CPU time 1583.4 seconds
Started Aug 06 06:17:06 PM PDT 24
Finished Aug 06 06:43:29 PM PDT 24
Peak memory 272852 kb
Host smart-b5ead665-e6f0-4480-97f3-a00c968c4fa4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666825956 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.366682595
6 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_burst_write/latest

Test location /workspace/coverage/default/46.kmac_entropy_refresh.3507069810
Short name T727
Test name
Test status
Simulation time 11659344852 ps
CPU time 214.51 seconds
Started Aug 06 06:17:20 PM PDT 24
Finished Aug 06 06:20:55 PM PDT 24
Peak memory 289764 kb
Host smart-8e608d03-1d7a-4586-bbb0-48a9d5951efb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507069810 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_entropy_refresh.3
507069810 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/46.kmac_error.225684951
Short name T488
Test name
Test status
Simulation time 2355097230 ps
CPU time 75.53 seconds
Started Aug 06 06:17:21 PM PDT 24
Finished Aug 06 06:18:37 PM PDT 24
Peak memory 300876 kb
Host smart-bfede39d-5ab0-4e16-800a-d9dd5a1e6c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225684951 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.225684951 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_error/latest

Test location /workspace/coverage/default/46.kmac_key_error.2763426653
Short name T616
Test name
Test status
Simulation time 1525323304 ps
CPU time 9.95 seconds
Started Aug 06 06:17:21 PM PDT 24
Finished Aug 06 06:17:31 PM PDT 24
Peak memory 226812 kb
Host smart-80838a80-e4b6-4ad9-ad59-edfd73c46982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763426653 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.2763426653 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_key_error/latest

Test location /workspace/coverage/default/46.kmac_lc_escalation.2835381928
Short name T477
Test name
Test status
Simulation time 187986773 ps
CPU time 1.8 seconds
Started Aug 06 06:17:22 PM PDT 24
Finished Aug 06 06:17:24 PM PDT 24
Peak memory 226820 kb
Host smart-37bf2fa5-486c-444c-bdb2-608ebf36ec4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835381928 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.2835381928 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/46.kmac_lc_escalation/latest

Test location /workspace/coverage/default/46.kmac_long_msg_and_output.161897336
Short name T458
Test name
Test status
Simulation time 109783596391 ps
CPU time 3056.87 seconds
Started Aug 06 06:16:55 PM PDT 24
Finished Aug 06 07:07:53 PM PDT 24
Peak memory 2675928 kb
Host smart-63316959-c5d2-4f7f-bbf4-2191cf6e2d8d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161897336 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_an
d_output.161897336 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/46.kmac_sideload.3963844347
Short name T955
Test name
Test status
Simulation time 57577532445 ps
CPU time 383.34 seconds
Started Aug 06 06:17:07 PM PDT 24
Finished Aug 06 06:23:31 PM PDT 24
Peak memory 544408 kb
Host smart-4523c1e3-1763-4530-be98-b89b68781e32
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963844347 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.3963844347 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_sideload/latest

Test location /workspace/coverage/default/46.kmac_smoke.368480280
Short name T745
Test name
Test status
Simulation time 3533349977 ps
CPU time 44.19 seconds
Started Aug 06 06:16:54 PM PDT 24
Finished Aug 06 06:17:38 PM PDT 24
Peak memory 223228 kb
Host smart-ec3488fc-6379-48e8-b4f3-8eaba4ea252c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368480280 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.368480280 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_smoke/latest

Test location /workspace/coverage/default/46.kmac_stress_all.3777578955
Short name T874
Test name
Test status
Simulation time 36394498181 ps
CPU time 1200.13 seconds
Started Aug 06 06:17:34 PM PDT 24
Finished Aug 06 06:37:35 PM PDT 24
Peak memory 1242496 kb
Host smart-568dc5b2-7f7a-4a6f-bb87-f3f76660bc57
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3777578955 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.3777578955 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_stress_all/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_kmac.2741557552
Short name T228
Test name
Test status
Simulation time 501182172 ps
CPU time 6.64 seconds
Started Aug 06 06:17:11 PM PDT 24
Finished Aug 06 06:17:17 PM PDT 24
Peak memory 227020 kb
Host smart-bf3a9b67-6fd6-42cf-9325-56be28d28bc7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741557552 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.kmac_test_vectors_kmac.2741557552 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_kmac_xof.1827802550
Short name T951
Test name
Test status
Simulation time 849473074 ps
CPU time 9.04 seconds
Started Aug 06 06:17:11 PM PDT 24
Finished Aug 06 06:17:20 PM PDT 24
Peak memory 219908 kb
Host smart-fe34d289-cec6-4693-a473-f9a4e6571117
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827802550 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.kmac_test_vectors_kmac_xof.1827802550 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_224.3914273284
Short name T871
Test name
Test status
Simulation time 272702133343 ps
CPU time 3475.24 seconds
Started Aug 06 06:17:07 PM PDT 24
Finished Aug 06 07:15:03 PM PDT 24
Peak memory 3220008 kb
Host smart-505f2585-bd8b-4db5-aff9-91ea16599154
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3914273284 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_224.3914273284 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_256.664910064
Short name T933
Test name
Test status
Simulation time 76497286251 ps
CPU time 2090.97 seconds
Started Aug 06 06:17:11 PM PDT 24
Finished Aug 06 06:52:02 PM PDT 24
Peak memory 1135820 kb
Host smart-cab42bba-b437-4c02-9daa-4c4b17969a2a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=664910064 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_256.664910064 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_384.4252533754
Short name T470
Test name
Test status
Simulation time 102076213914 ps
CPU time 2190.89 seconds
Started Aug 06 06:17:06 PM PDT 24
Finished Aug 06 06:53:38 PM PDT 24
Peak memory 2362464 kb
Host smart-e5fdc45a-162a-468f-ab28-c9108d108de8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4252533754 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_384.4252533754 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_512.2928893346
Short name T533
Test name
Test status
Simulation time 42758146261 ps
CPU time 1184.26 seconds
Started Aug 06 06:17:08 PM PDT 24
Finished Aug 06 06:36:52 PM PDT 24
Peak memory 701664 kb
Host smart-ed2bf277-a026-4afa-b222-663dd3b96f67
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2928893346 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_512.2928893346 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_shake_256.2690826393
Short name T555
Test name
Test status
Simulation time 204122275676 ps
CPU time 5809.19 seconds
Started Aug 06 06:17:08 PM PDT 24
Finished Aug 06 07:53:58 PM PDT 24
Peak memory 2283760 kb
Host smart-03f13904-9812-431d-a277-c2a6748f4252
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2690826393 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_256.2690826393 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/47.kmac_alert_test.443831003
Short name T931
Test name
Test status
Simulation time 41916879 ps
CPU time 0.86 seconds
Started Aug 06 06:17:58 PM PDT 24
Finished Aug 06 06:17:59 PM PDT 24
Peak memory 218580 kb
Host smart-787b12cb-0a48-44dd-b1b6-df13323b3202
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443831003 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.443831003 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/47.kmac_alert_test/latest

Test location /workspace/coverage/default/47.kmac_app.1748614961
Short name T629
Test name
Test status
Simulation time 9598720110 ps
CPU time 143.85 seconds
Started Aug 06 06:17:45 PM PDT 24
Finished Aug 06 06:20:09 PM PDT 24
Peak memory 330240 kb
Host smart-718b9903-94ea-4028-b81b-a9058c21f3b7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748614961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.1748614961 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/47.kmac_app/latest

Test location /workspace/coverage/default/47.kmac_burst_write.1971821722
Short name T397
Test name
Test status
Simulation time 20614748259 ps
CPU time 524.95 seconds
Started Aug 06 06:17:32 PM PDT 24
Finished Aug 06 06:26:17 PM PDT 24
Peak memory 234972 kb
Host smart-18d20f55-7054-40c4-9a5e-aec102519a87
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971821722 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.197182172
2 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_burst_write/latest

Test location /workspace/coverage/default/47.kmac_entropy_refresh.4242661136
Short name T71
Test name
Test status
Simulation time 10198890421 ps
CPU time 50.07 seconds
Started Aug 06 06:17:44 PM PDT 24
Finished Aug 06 06:18:34 PM PDT 24
Peak memory 255016 kb
Host smart-4ff56d46-910d-4b16-a393-d8acdf4481f5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242661136 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.4
242661136 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/47.kmac_error.278958758
Short name T426
Test name
Test status
Simulation time 971434599 ps
CPU time 63.6 seconds
Started Aug 06 06:17:45 PM PDT 24
Finished Aug 06 06:18:49 PM PDT 24
Peak memory 252700 kb
Host smart-8caa10d9-56ac-4822-9f93-34cafa9dbb64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278958758 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.278958758 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_error/latest

Test location /workspace/coverage/default/47.kmac_key_error.2861235771
Short name T491
Test name
Test status
Simulation time 4558236211 ps
CPU time 13.77 seconds
Started Aug 06 06:17:44 PM PDT 24
Finished Aug 06 06:17:58 PM PDT 24
Peak memory 227072 kb
Host smart-c5620817-c88f-43a2-abf6-fdfdb4620d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861235771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.2861235771 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_key_error/latest

Test location /workspace/coverage/default/47.kmac_lc_escalation.2605624169
Short name T766
Test name
Test status
Simulation time 90605454 ps
CPU time 1.25 seconds
Started Aug 06 06:17:45 PM PDT 24
Finished Aug 06 06:17:46 PM PDT 24
Peak memory 226992 kb
Host smart-4a94d5f9-3835-421f-bef5-526025eb968c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605624169 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.2605624169 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/47.kmac_lc_escalation/latest

Test location /workspace/coverage/default/47.kmac_long_msg_and_output.1328033273
Short name T580
Test name
Test status
Simulation time 26856153669 ps
CPU time 860.52 seconds
Started Aug 06 06:17:32 PM PDT 24
Finished Aug 06 06:31:53 PM PDT 24
Peak memory 626116 kb
Host smart-17b8585c-600d-4878-ae67-ddb4a2aa0bd3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328033273 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_a
nd_output.1328033273 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/47.kmac_sideload.3527646077
Short name T654
Test name
Test status
Simulation time 9725273103 ps
CPU time 38.6 seconds
Started Aug 06 06:17:33 PM PDT 24
Finished Aug 06 06:18:12 PM PDT 24
Peak memory 259816 kb
Host smart-54554613-63c5-4e46-8998-9369d4386ad4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527646077 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.3527646077 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_sideload/latest

Test location /workspace/coverage/default/47.kmac_smoke.2308072856
Short name T789
Test name
Test status
Simulation time 4459236982 ps
CPU time 25.1 seconds
Started Aug 06 06:17:22 PM PDT 24
Finished Aug 06 06:17:47 PM PDT 24
Peak memory 227220 kb
Host smart-55251bc5-97e5-4b38-9a33-05ebca35631f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308072856 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.2308072856 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_smoke/latest

Test location /workspace/coverage/default/47.kmac_stress_all.3357533779
Short name T953
Test name
Test status
Simulation time 550061785050 ps
CPU time 1731.55 seconds
Started Aug 06 06:17:45 PM PDT 24
Finished Aug 06 06:46:37 PM PDT 24
Peak memory 1620992 kb
Host smart-406168af-04a3-4242-8833-682294dd9de0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3357533779 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.3357533779 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_stress_all/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_kmac.607089596
Short name T398
Test name
Test status
Simulation time 1307397064 ps
CPU time 6.33 seconds
Started Aug 06 06:17:44 PM PDT 24
Finished Aug 06 06:17:50 PM PDT 24
Peak memory 227076 kb
Host smart-42a84d0e-8072-4658-84b0-5c25d5e4af0a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607089596 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.kmac_test_vectors_kmac.607089596 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_kmac_xof.3194102135
Short name T315
Test name
Test status
Simulation time 1045283559 ps
CPU time 6.29 seconds
Started Aug 06 06:17:46 PM PDT 24
Finished Aug 06 06:17:52 PM PDT 24
Peak memory 227064 kb
Host smart-042fa257-2bb0-44c4-9af7-238c120e8a41
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194102135 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.kmac_test_vectors_kmac_xof.3194102135 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_224.487164888
Short name T378
Test name
Test status
Simulation time 269589070733 ps
CPU time 3344.76 seconds
Started Aug 06 06:17:33 PM PDT 24
Finished Aug 06 07:13:18 PM PDT 24
Peak memory 3180788 kb
Host smart-83ce042b-6763-44b3-89f5-524677ae6692
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=487164888 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_224.487164888 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_256.387703564
Short name T235
Test name
Test status
Simulation time 110269981763 ps
CPU time 2036.68 seconds
Started Aug 06 06:17:33 PM PDT 24
Finished Aug 06 06:51:30 PM PDT 24
Peak memory 1112052 kb
Host smart-e98e7090-367b-4eb1-9cca-217d673f6746
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=387703564 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_256.387703564 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_384.1039289168
Short name T36
Test name
Test status
Simulation time 282787029057 ps
CPU time 2384.29 seconds
Started Aug 06 06:17:33 PM PDT 24
Finished Aug 06 06:57:18 PM PDT 24
Peak memory 2423248 kb
Host smart-7640b5b2-5db5-4b40-ab64-ce00f72b9b0a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1039289168 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_384.1039289168 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_512.1980649851
Short name T750
Test name
Test status
Simulation time 32939563645 ps
CPU time 1227.36 seconds
Started Aug 06 06:18:33 PM PDT 24
Finished Aug 06 06:39:01 PM PDT 24
Peak memory 1683732 kb
Host smart-944e18c3-ab0d-4b53-b746-94777176ddaf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1980649851 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_512.1980649851 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_shake_128.1877043531
Short name T391
Test name
Test status
Simulation time 236996448384 ps
CPU time 6137.66 seconds
Started Aug 06 06:17:33 PM PDT 24
Finished Aug 06 07:59:51 PM PDT 24
Peak memory 2646284 kb
Host smart-9dbb5526-0e41-4a19-9a80-9a182d3838b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1877043531 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_shake_128.1877043531 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/48.kmac_alert_test.2484809514
Short name T203
Test name
Test status
Simulation time 16058378 ps
CPU time 0.87 seconds
Started Aug 06 06:18:41 PM PDT 24
Finished Aug 06 06:18:42 PM PDT 24
Peak memory 218556 kb
Host smart-c1edc790-10e3-45d7-8345-02d59df430f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484809514 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.2484809514 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_alert_test/latest

Test location /workspace/coverage/default/48.kmac_app.1069594013
Short name T985
Test name
Test status
Simulation time 132029616989 ps
CPU time 395.5 seconds
Started Aug 06 06:18:22 PM PDT 24
Finished Aug 06 06:24:58 PM PDT 24
Peak memory 504608 kb
Host smart-a471e520-fb83-4931-9b1c-babbb83e924c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069594013 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.1069594013 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/48.kmac_app/latest

Test location /workspace/coverage/default/48.kmac_burst_write.2598783259
Short name T130
Test name
Test status
Simulation time 19230318780 ps
CPU time 900.22 seconds
Started Aug 06 06:18:09 PM PDT 24
Finished Aug 06 06:33:09 PM PDT 24
Peak memory 252376 kb
Host smart-2730eb48-2e8f-442a-80b0-ded23b328cf9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598783259 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.259878325
9 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_burst_write/latest

Test location /workspace/coverage/default/48.kmac_entropy_refresh.3764353952
Short name T151
Test name
Test status
Simulation time 1101295818 ps
CPU time 36.5 seconds
Started Aug 06 06:18:23 PM PDT 24
Finished Aug 06 06:19:00 PM PDT 24
Peak memory 243516 kb
Host smart-5d696668-fe85-4f37-bc44-3a8ee675489f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764353952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.3
764353952 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/48.kmac_error.2699420219
Short name T851
Test name
Test status
Simulation time 9392139037 ps
CPU time 344.01 seconds
Started Aug 06 06:18:24 PM PDT 24
Finished Aug 06 06:24:08 PM PDT 24
Peak memory 495564 kb
Host smart-75acd654-42ab-4533-8e76-963459238d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699420219 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.2699420219 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_error/latest

Test location /workspace/coverage/default/48.kmac_key_error.3844818191
Short name T319
Test name
Test status
Simulation time 4159770728 ps
CPU time 10.36 seconds
Started Aug 06 06:18:22 PM PDT 24
Finished Aug 06 06:18:32 PM PDT 24
Peak memory 227004 kb
Host smart-799a6b85-632a-4222-8989-79968327f2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844818191 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.3844818191 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_key_error/latest

Test location /workspace/coverage/default/48.kmac_lc_escalation.3882340991
Short name T50
Test name
Test status
Simulation time 70911123 ps
CPU time 1.79 seconds
Started Aug 06 06:18:23 PM PDT 24
Finished Aug 06 06:18:25 PM PDT 24
Peak memory 227108 kb
Host smart-54a1dc3f-127e-4ad3-a03c-c06d5216fed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882340991 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.3882340991 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/48.kmac_lc_escalation/latest

Test location /workspace/coverage/default/48.kmac_sideload.3970095952
Short name T621
Test name
Test status
Simulation time 6338213489 ps
CPU time 278.68 seconds
Started Aug 06 06:18:08 PM PDT 24
Finished Aug 06 06:22:47 PM PDT 24
Peak memory 312932 kb
Host smart-482a5659-5027-43ae-a7c0-c99fe1765652
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970095952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.3970095952 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_sideload/latest

Test location /workspace/coverage/default/48.kmac_smoke.2798033069
Short name T694
Test name
Test status
Simulation time 2493288856 ps
CPU time 54.36 seconds
Started Aug 06 06:17:58 PM PDT 24
Finished Aug 06 06:18:52 PM PDT 24
Peak memory 227172 kb
Host smart-c2d663e0-c047-482b-b6f4-6dfc96b6bdbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798033069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.2798033069 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_smoke/latest

Test location /workspace/coverage/default/48.kmac_stress_all.2618368335
Short name T686
Test name
Test status
Simulation time 85013510305 ps
CPU time 919.26 seconds
Started Aug 06 06:18:40 PM PDT 24
Finished Aug 06 06:34:00 PM PDT 24
Peak memory 504572 kb
Host smart-367efa14-eb0f-46aa-a27d-2e29982ebed9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2618368335 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.2618368335 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_stress_all/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_kmac.1034668309
Short name T400
Test name
Test status
Simulation time 3233409488 ps
CPU time 7.26 seconds
Started Aug 06 06:18:24 PM PDT 24
Finished Aug 06 06:18:31 PM PDT 24
Peak memory 227148 kb
Host smart-4020f564-f785-4678-a870-1b5aeda16700
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034668309 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.kmac_test_vectors_kmac.1034668309 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_kmac_xof.2178445616
Short name T864
Test name
Test status
Simulation time 369439399 ps
CPU time 6.27 seconds
Started Aug 06 06:18:23 PM PDT 24
Finished Aug 06 06:18:29 PM PDT 24
Peak memory 227048 kb
Host smart-09c6ef19-3084-402a-b517-04178edd5554
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178445616 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.kmac_test_vectors_kmac_xof.2178445616 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_256.3204464953
Short name T860
Test name
Test status
Simulation time 85103144429 ps
CPU time 3132.36 seconds
Started Aug 06 06:18:09 PM PDT 24
Finished Aug 06 07:10:22 PM PDT 24
Peak memory 2999276 kb
Host smart-ad3a0f27-ee15-44d6-8c93-365d5276205e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3204464953 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_256.3204464953 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_384.957546259
Short name T753
Test name
Test status
Simulation time 70006982763 ps
CPU time 1544.82 seconds
Started Aug 06 06:18:11 PM PDT 24
Finished Aug 06 06:43:56 PM PDT 24
Peak memory 906608 kb
Host smart-09596cd9-d3f5-408c-b831-7a270498f2fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=957546259 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_384.957546259 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_512.1798954900
Short name T531
Test name
Test status
Simulation time 52270325649 ps
CPU time 1130.08 seconds
Started Aug 06 06:18:11 PM PDT 24
Finished Aug 06 06:37:01 PM PDT 24
Peak memory 704052 kb
Host smart-7287126b-ed6b-47de-91df-38f347b7b6e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1798954900 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_512.1798954900 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_shake_256.1397032755
Short name T314
Test name
Test status
Simulation time 54975650512 ps
CPU time 5125.53 seconds
Started Aug 06 06:18:21 PM PDT 24
Finished Aug 06 07:43:47 PM PDT 24
Peak memory 2230656 kb
Host smart-cb1b0b4c-9e56-4ed0-871d-7cd4e57a24ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1397032755 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_256.1397032755 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/49.kmac_alert_test.3480151850
Short name T448
Test name
Test status
Simulation time 19456935 ps
CPU time 0.86 seconds
Started Aug 06 06:19:07 PM PDT 24
Finished Aug 06 06:19:08 PM PDT 24
Peak memory 218548 kb
Host smart-e1948cf1-340e-4df4-9a3c-f06d9911c20a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480151850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.3480151850 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_alert_test/latest

Test location /workspace/coverage/default/49.kmac_app.172937596
Short name T703
Test name
Test status
Simulation time 3334406196 ps
CPU time 83.93 seconds
Started Aug 06 06:19:07 PM PDT 24
Finished Aug 06 06:20:31 PM PDT 24
Peak memory 284840 kb
Host smart-bb33319e-ec31-494a-b4cc-6d601d1b2de3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172937596 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.172937596 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/49.kmac_app/latest

Test location /workspace/coverage/default/49.kmac_burst_write.2120789481
Short name T505
Test name
Test status
Simulation time 88225846902 ps
CPU time 1304.05 seconds
Started Aug 06 06:18:40 PM PDT 24
Finished Aug 06 06:40:24 PM PDT 24
Peak memory 261348 kb
Host smart-86675fe7-1210-4d18-a3a9-4e5fc3e5af21
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120789481 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.212078948
1 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_burst_write/latest

Test location /workspace/coverage/default/49.kmac_entropy_refresh.218137662
Short name T150
Test name
Test status
Simulation time 15795468943 ps
CPU time 122.8 seconds
Started Aug 06 06:19:06 PM PDT 24
Finished Aug 06 06:21:09 PM PDT 24
Peak memory 312528 kb
Host smart-bba45d6f-6521-48a9-829c-181656a8ea13
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218137662 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.21
8137662 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/49.kmac_key_error.3787249526
Short name T270
Test name
Test status
Simulation time 739061753 ps
CPU time 3.93 seconds
Started Aug 06 06:19:08 PM PDT 24
Finished Aug 06 06:19:12 PM PDT 24
Peak memory 226916 kb
Host smart-5819f988-8090-4bab-b974-1041b87dc3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787249526 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.3787249526 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_key_error/latest

Test location /workspace/coverage/default/49.kmac_lc_escalation.540904379
Short name T967
Test name
Test status
Simulation time 42852196 ps
CPU time 1.76 seconds
Started Aug 06 06:19:05 PM PDT 24
Finished Aug 06 06:19:07 PM PDT 24
Peak memory 226916 kb
Host smart-f3686835-4295-46d1-84e5-76d3b5404454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540904379 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.540904379 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/49.kmac_lc_escalation/latest

Test location /workspace/coverage/default/49.kmac_long_msg_and_output.2179108021
Short name T261
Test name
Test status
Simulation time 197412215354 ps
CPU time 2591.45 seconds
Started Aug 06 06:18:40 PM PDT 24
Finished Aug 06 07:01:52 PM PDT 24
Peak memory 2458216 kb
Host smart-8af8da42-3a4d-4b81-a77f-ba482b3c2acf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179108021 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_a
nd_output.2179108021 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/49.kmac_sideload.2778892850
Short name T230
Test name
Test status
Simulation time 11193270694 ps
CPU time 307.89 seconds
Started Aug 06 06:18:41 PM PDT 24
Finished Aug 06 06:23:49 PM PDT 24
Peak memory 455700 kb
Host smart-eff7b0a5-b2a7-46b3-b4ce-7dcc9d2819e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778892850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.2778892850 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_sideload/latest

Test location /workspace/coverage/default/49.kmac_smoke.4092348437
Short name T454
Test name
Test status
Simulation time 6238905507 ps
CPU time 15.03 seconds
Started Aug 06 06:18:41 PM PDT 24
Finished Aug 06 06:18:56 PM PDT 24
Peak memory 227128 kb
Host smart-e5811278-d93e-4c43-9fd0-98f4ef34abe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092348437 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.4092348437 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_smoke/latest

Test location /workspace/coverage/default/49.kmac_stress_all.2163616482
Short name T594
Test name
Test status
Simulation time 3883600678 ps
CPU time 97.21 seconds
Started Aug 06 06:19:05 PM PDT 24
Finished Aug 06 06:20:43 PM PDT 24
Peak memory 282324 kb
Host smart-0d3c52b6-3162-4a10-b600-4391315e5b2b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2163616482 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.2163616482 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_stress_all/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_kmac.2835567677
Short name T610
Test name
Test status
Simulation time 486130959 ps
CPU time 6.07 seconds
Started Aug 06 06:19:06 PM PDT 24
Finished Aug 06 06:19:12 PM PDT 24
Peak memory 227068 kb
Host smart-0418d77a-7012-46b3-8750-c2f922ee8452
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835567677 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.kmac_test_vectors_kmac.2835567677 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_kmac_xof.487639260
Short name T353
Test name
Test status
Simulation time 201123258 ps
CPU time 6.73 seconds
Started Aug 06 06:19:07 PM PDT 24
Finished Aug 06 06:19:14 PM PDT 24
Peak memory 227084 kb
Host smart-aaad7362-d24f-489c-a9d7-33dcc3d6192d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487639260 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 49.kmac_test_vectors_kmac_xof.487639260 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_224.3389796973
Short name T697
Test name
Test status
Simulation time 66728855788 ps
CPU time 3028.88 seconds
Started Aug 06 06:18:43 PM PDT 24
Finished Aug 06 07:09:12 PM PDT 24
Peak memory 3200720 kb
Host smart-bee27d2a-b631-4c44-a60b-5299b79cf84c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3389796973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_224.3389796973 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_256.2411912099
Short name T174
Test name
Test status
Simulation time 64018455127 ps
CPU time 2906.41 seconds
Started Aug 06 06:18:41 PM PDT 24
Finished Aug 06 07:07:08 PM PDT 24
Peak memory 3006452 kb
Host smart-649758bd-fd7d-4c91-8bb5-ecc83d6f1388
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2411912099 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_256.2411912099 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_384.2016408183
Short name T438
Test name
Test status
Simulation time 105974161869 ps
CPU time 2249.14 seconds
Started Aug 06 06:18:40 PM PDT 24
Finished Aug 06 06:56:10 PM PDT 24
Peak memory 2409612 kb
Host smart-5a5b8c77-281e-4d8e-a1f1-1de85f60cf69
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2016408183 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_384.2016408183 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_512.3305575550
Short name T425
Test name
Test status
Simulation time 22159069397 ps
CPU time 1110.62 seconds
Started Aug 06 06:18:40 PM PDT 24
Finished Aug 06 06:37:11 PM PDT 24
Peak memory 695112 kb
Host smart-0277f315-a3f9-40ce-a7aa-e94ea349ef7d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3305575550 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_512.3305575550 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_shake_128.2679254971
Short name T713
Test name
Test status
Simulation time 120901606252 ps
CPU time 6302.18 seconds
Started Aug 06 06:18:41 PM PDT 24
Finished Aug 06 08:03:44 PM PDT 24
Peak memory 2636948 kb
Host smart-de076eb4-0aef-4f6c-8b17-1c05d7635152
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2679254971 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_128.2679254971 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_shake_256.1793094155
Short name T669
Test name
Test status
Simulation time 528970400334 ps
CPU time 5639.05 seconds
Started Aug 06 06:19:06 PM PDT 24
Finished Aug 06 07:53:05 PM PDT 24
Peak memory 2252752 kb
Host smart-690a75ca-03ae-42bb-8f6c-2852996b722d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1793094155 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_256.1793094155 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/5.kmac_alert_test.3664873944
Short name T850
Test name
Test status
Simulation time 73183680 ps
CPU time 0.81 seconds
Started Aug 06 06:01:48 PM PDT 24
Finished Aug 06 06:01:49 PM PDT 24
Peak memory 218564 kb
Host smart-0688da25-2e7f-44b4-8e1d-b4e60b636a8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664873944 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.3664873944 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_alert_test/latest

Test location /workspace/coverage/default/5.kmac_app.3114557693
Short name T592
Test name
Test status
Simulation time 104035877859 ps
CPU time 350.35 seconds
Started Aug 06 06:01:34 PM PDT 24
Finished Aug 06 06:07:24 PM PDT 24
Peak memory 467872 kb
Host smart-a7db6642-fd23-45e6-8ee1-edf3ba018a4a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114557693 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.3114557693 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/5.kmac_app/latest

Test location /workspace/coverage/default/5.kmac_burst_write.445235831
Short name T838
Test name
Test status
Simulation time 6633268104 ps
CPU time 260.01 seconds
Started Aug 06 06:01:20 PM PDT 24
Finished Aug 06 06:05:41 PM PDT 24
Peak memory 235772 kb
Host smart-35b988a7-5e33-402d-a35d-9f681b649f81
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445235831 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.445235831 +
enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_burst_write/latest

Test location /workspace/coverage/default/5.kmac_edn_timeout_error.2686236296
Short name T346
Test name
Test status
Simulation time 759974353 ps
CPU time 18.23 seconds
Started Aug 06 06:01:32 PM PDT 24
Finished Aug 06 06:01:50 PM PDT 24
Peak memory 222024 kb
Host smart-8d5a855b-92fa-4583-b1f7-f2ec60f131f0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2686236296 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.2686236296 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_mode_error.2221455325
Short name T83
Test name
Test status
Simulation time 78571170 ps
CPU time 1.14 seconds
Started Aug 06 06:01:32 PM PDT 24
Finished Aug 06 06:01:34 PM PDT 24
Peak memory 218752 kb
Host smart-2ce70e48-5777-4170-b333-7b7d6468d27b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2221455325 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.2221455325 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_ready_error.1412560813
Short name T370
Test name
Test status
Simulation time 322502354 ps
CPU time 6.44 seconds
Started Aug 06 06:01:32 PM PDT 24
Finished Aug 06 06:01:39 PM PDT 24
Peak memory 222112 kb
Host smart-79372bb0-8fb6-4d4b-9a65-b3d74af35ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412560813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.1412560813 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_refresh.2478844728
Short name T693
Test name
Test status
Simulation time 6251377253 ps
CPU time 240.48 seconds
Started Aug 06 06:01:33 PM PDT 24
Finished Aug 06 06:05:34 PM PDT 24
Peak memory 298084 kb
Host smart-6f06ed1b-a574-4576-8b28-e455c5d49496
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478844728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.24
78844728 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/5.kmac_error.1622018691
Short name T23
Test name
Test status
Simulation time 57146050767 ps
CPU time 197 seconds
Started Aug 06 06:01:33 PM PDT 24
Finished Aug 06 06:04:50 PM PDT 24
Peak memory 350020 kb
Host smart-91dc58ef-1c46-499f-a205-bd6be896bce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622018691 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.1622018691 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_error/latest

Test location /workspace/coverage/default/5.kmac_key_error.2752925742
Short name T357
Test name
Test status
Simulation time 2383256149 ps
CPU time 8.69 seconds
Started Aug 06 06:01:33 PM PDT 24
Finished Aug 06 06:01:41 PM PDT 24
Peak memory 226972 kb
Host smart-da8ea30a-7a64-4f77-b177-9d30764ebf3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752925742 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.2752925742 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_key_error/latest

Test location /workspace/coverage/default/5.kmac_lc_escalation.3355342253
Short name T987
Test name
Test status
Simulation time 39576918 ps
CPU time 1.31 seconds
Started Aug 06 06:01:33 PM PDT 24
Finished Aug 06 06:01:34 PM PDT 24
Peak memory 227020 kb
Host smart-27587c98-4d12-4feb-ad7e-91a87eceb1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355342253 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.3355342253 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/5.kmac_lc_escalation/latest

Test location /workspace/coverage/default/5.kmac_long_msg_and_output.1259359771
Short name T495
Test name
Test status
Simulation time 90032565095 ps
CPU time 1445.72 seconds
Started Aug 06 06:01:20 PM PDT 24
Finished Aug 06 06:25:27 PM PDT 24
Peak memory 861128 kb
Host smart-e58d7e1f-02a8-4225-a484-ad5721538231
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259359771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_an
d_output.1259359771 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/5.kmac_mubi.3214751671
Short name T742
Test name
Test status
Simulation time 6968465005 ps
CPU time 96.71 seconds
Started Aug 06 06:01:33 PM PDT 24
Finished Aug 06 06:03:10 PM PDT 24
Peak memory 257664 kb
Host smart-db215c64-0a83-414f-a80d-719fa97fa76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214751671 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.3214751671 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_mubi/latest

Test location /workspace/coverage/default/5.kmac_sideload.1164466032
Short name T295
Test name
Test status
Simulation time 102563672039 ps
CPU time 373.8 seconds
Started Aug 06 06:01:21 PM PDT 24
Finished Aug 06 06:07:35 PM PDT 24
Peak memory 492544 kb
Host smart-e2b0335b-75fb-4d34-be7a-f78bd3ddc57e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164466032 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.1164466032 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_sideload/latest

Test location /workspace/coverage/default/5.kmac_smoke.1145471566
Short name T123
Test name
Test status
Simulation time 3267182595 ps
CPU time 35.78 seconds
Started Aug 06 06:01:21 PM PDT 24
Finished Aug 06 06:01:57 PM PDT 24
Peak memory 223408 kb
Host smart-335f38e9-af49-4976-9825-7d451f2067c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145471566 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.1145471566 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_smoke/latest

Test location /workspace/coverage/default/5.kmac_stress_all.1583467454
Short name T507
Test name
Test status
Simulation time 620145583604 ps
CPU time 1905.29 seconds
Started Aug 06 06:01:47 PM PDT 24
Finished Aug 06 06:33:33 PM PDT 24
Peak memory 973708 kb
Host smart-72defa28-b3f5-4550-a705-ffdba2188e12
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1583467454 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.1583467454 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_stress_all/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_kmac.3311051015
Short name T171
Test name
Test status
Simulation time 781864387 ps
CPU time 6.59 seconds
Started Aug 06 06:01:34 PM PDT 24
Finished Aug 06 06:01:41 PM PDT 24
Peak memory 227008 kb
Host smart-7118409a-b4cb-471a-affa-aa1c73cde7eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311051015 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.kmac_test_vectors_kmac.3311051015 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_kmac_xof.945060339
Short name T418
Test name
Test status
Simulation time 263597451 ps
CPU time 6.63 seconds
Started Aug 06 06:01:31 PM PDT 24
Finished Aug 06 06:01:37 PM PDT 24
Peak memory 220008 kb
Host smart-896ab6f9-08c2-4d12-887a-d4c0dd56974d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945060339 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.kmac_test_vectors_kmac_xof.945060339 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_224.3949668572
Short name T311
Test name
Test status
Simulation time 268411611969 ps
CPU time 3183.36 seconds
Started Aug 06 06:01:19 PM PDT 24
Finished Aug 06 06:54:22 PM PDT 24
Peak memory 3172320 kb
Host smart-83e5f27f-a38f-4546-89ec-1a19863d90db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3949668572 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_224.3949668572 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_256.4181956852
Short name T421
Test name
Test status
Simulation time 95863719219 ps
CPU time 3494.23 seconds
Started Aug 06 06:01:18 PM PDT 24
Finished Aug 06 06:59:33 PM PDT 24
Peak memory 3008988 kb
Host smart-3d97c4d0-7270-4007-bece-422661b5cdeb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4181956852 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_256.4181956852 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_384.3306451779
Short name T846
Test name
Test status
Simulation time 50971283759 ps
CPU time 2447.25 seconds
Started Aug 06 06:01:20 PM PDT 24
Finished Aug 06 06:42:08 PM PDT 24
Peak memory 2447908 kb
Host smart-4ad28204-ede9-4d14-a370-9ea561290a52
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3306451779 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_384.3306451779 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_512.64127129
Short name T582
Test name
Test status
Simulation time 140181576435 ps
CPU time 1576.81 seconds
Started Aug 06 06:01:17 PM PDT 24
Finished Aug 06 06:27:34 PM PDT 24
Peak memory 1750756 kb
Host smart-ebf7c9e3-d113-44c3-90d4-4e97458b571f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=64127129 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_512.64127129 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/6.kmac_alert_test.299567871
Short name T523
Test name
Test status
Simulation time 133069041 ps
CPU time 0.85 seconds
Started Aug 06 06:02:08 PM PDT 24
Finished Aug 06 06:02:09 PM PDT 24
Peak memory 218576 kb
Host smart-dd80ee03-c86d-4459-a5aa-4f571d3d7f76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299567871 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.299567871 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/6.kmac_alert_test/latest

Test location /workspace/coverage/default/6.kmac_app.3385576486
Short name T602
Test name
Test status
Simulation time 19705386705 ps
CPU time 256.01 seconds
Started Aug 06 06:02:07 PM PDT 24
Finished Aug 06 06:06:23 PM PDT 24
Peak memory 420448 kb
Host smart-791caeff-9cd2-471f-8027-5df7e121bab2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385576486 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.3385576486 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/6.kmac_app/latest

Test location /workspace/coverage/default/6.kmac_app_with_partial_data.1478016026
Short name T481
Test name
Test status
Simulation time 22392185055 ps
CPU time 238.66 seconds
Started Aug 06 06:02:07 PM PDT 24
Finished Aug 06 06:06:06 PM PDT 24
Peak memory 299496 kb
Host smart-05191a63-e70e-4e67-9ffb-cc98dbf1db98
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478016026 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_par
tial_data.1478016026 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/6.kmac_burst_write.647738946
Short name T312
Test name
Test status
Simulation time 209220079 ps
CPU time 2.38 seconds
Started Aug 06 06:01:48 PM PDT 24
Finished Aug 06 06:01:51 PM PDT 24
Peak memory 227016 kb
Host smart-2912c1c3-b616-4d06-9972-421a2e06ce8b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647738946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.647738946 +
enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_burst_write/latest

Test location /workspace/coverage/default/6.kmac_edn_timeout_error.3668297074
Short name T556
Test name
Test status
Simulation time 21416810 ps
CPU time 1.14 seconds
Started Aug 06 06:02:06 PM PDT 24
Finished Aug 06 06:02:07 PM PDT 24
Peak memory 218744 kb
Host smart-dff302ba-e754-418f-88d2-f5f38ced7cfc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3668297074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.3668297074 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_mode_error.3514853865
Short name T551
Test name
Test status
Simulation time 28995427 ps
CPU time 1.05 seconds
Started Aug 06 06:02:09 PM PDT 24
Finished Aug 06 06:02:10 PM PDT 24
Peak memory 218496 kb
Host smart-ba6cef08-4729-4031-87c4-cc7bd899810c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3514853865 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.3514853865 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_ready_error.1853391935
Short name T800
Test name
Test status
Simulation time 3320507370 ps
CPU time 37.47 seconds
Started Aug 06 06:02:08 PM PDT 24
Finished Aug 06 06:02:46 PM PDT 24
Peak memory 223708 kb
Host smart-d9856da3-6cf2-4736-bf60-2c8d9dd4bdff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853391935 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.1853391935 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_refresh.2866252788
Short name T380
Test name
Test status
Simulation time 55141564766 ps
CPU time 353.29 seconds
Started Aug 06 06:02:08 PM PDT 24
Finished Aug 06 06:08:01 PM PDT 24
Peak memory 469756 kb
Host smart-72b4163c-277c-49e1-a072-42726c284ec1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866252788 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.28
66252788 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/6.kmac_error.2745887823
Short name T269
Test name
Test status
Simulation time 13972692151 ps
CPU time 50.23 seconds
Started Aug 06 06:02:09 PM PDT 24
Finished Aug 06 06:02:59 PM PDT 24
Peak memory 269776 kb
Host smart-b8d44e21-f4d0-4338-b6db-66da1ba23cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745887823 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.2745887823 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_error/latest

Test location /workspace/coverage/default/6.kmac_key_error.2713300877
Short name T199
Test name
Test status
Simulation time 3124912208 ps
CPU time 5.28 seconds
Started Aug 06 06:02:07 PM PDT 24
Finished Aug 06 06:02:13 PM PDT 24
Peak memory 226920 kb
Host smart-404cc1b5-b709-43d0-b228-fd036cbd9b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713300877 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.2713300877 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_key_error/latest

Test location /workspace/coverage/default/6.kmac_lc_escalation.2672905793
Short name T48
Test name
Test status
Simulation time 134312552 ps
CPU time 1.28 seconds
Started Aug 06 06:02:09 PM PDT 24
Finished Aug 06 06:02:10 PM PDT 24
Peak memory 226936 kb
Host smart-3a723a4a-8583-41eb-9326-7a7d66c8569c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672905793 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.2672905793 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/6.kmac_lc_escalation/latest

Test location /workspace/coverage/default/6.kmac_long_msg_and_output.2959282555
Short name T486
Test name
Test status
Simulation time 17538040310 ps
CPU time 2394.67 seconds
Started Aug 06 06:01:47 PM PDT 24
Finished Aug 06 06:41:42 PM PDT 24
Peak memory 1210144 kb
Host smart-059a0363-ef28-415e-8b1f-78e9f052123b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959282555 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_an
d_output.2959282555 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/6.kmac_mubi.1498347156
Short name T463
Test name
Test status
Simulation time 28554617210 ps
CPU time 382.9 seconds
Started Aug 06 06:02:07 PM PDT 24
Finished Aug 06 06:08:30 PM PDT 24
Peak memory 339736 kb
Host smart-2342cf64-5a33-4408-8edc-e7b69c1214ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498347156 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.1498347156 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_mubi/latest

Test location /workspace/coverage/default/6.kmac_sideload.3017959039
Short name T355
Test name
Test status
Simulation time 15184667908 ps
CPU time 515.3 seconds
Started Aug 06 06:01:47 PM PDT 24
Finished Aug 06 06:10:22 PM PDT 24
Peak memory 609484 kb
Host smart-c8958d2a-b4d4-40ba-a8b5-29543a28a396
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017959039 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.3017959039 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_sideload/latest

Test location /workspace/coverage/default/6.kmac_smoke.1779583921
Short name T338
Test name
Test status
Simulation time 2910992222 ps
CPU time 38.58 seconds
Started Aug 06 06:01:46 PM PDT 24
Finished Aug 06 06:02:25 PM PDT 24
Peak memory 223408 kb
Host smart-1d42c807-c82f-4c34-9edb-69c7d7686135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779583921 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.1779583921 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_smoke/latest

Test location /workspace/coverage/default/6.kmac_stress_all.3725296207
Short name T581
Test name
Test status
Simulation time 2247768460 ps
CPU time 65.42 seconds
Started Aug 06 06:02:06 PM PDT 24
Finished Aug 06 06:03:12 PM PDT 24
Peak memory 272792 kb
Host smart-6cc158b4-2c92-4b58-af4d-7ffb23310e2f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3725296207 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.3725296207 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_stress_all/latest

Test location /workspace/coverage/default/6.kmac_stress_all_with_rand_reset.2935667793
Short name T115
Test name
Test status
Simulation time 772331354424 ps
CPU time 2338.02 seconds
Started Aug 06 06:02:09 PM PDT 24
Finished Aug 06 06:41:08 PM PDT 24
Peak memory 637136 kb
Host smart-80c61bb9-a24d-423e-8be8-9f1c9fa269bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2935667793 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all_with_rand_reset.2935667793 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_kmac.415458340
Short name T865
Test name
Test status
Simulation time 114737474 ps
CPU time 5.86 seconds
Started Aug 06 06:01:48 PM PDT 24
Finished Aug 06 06:01:54 PM PDT 24
Peak memory 219096 kb
Host smart-819a0d17-9958-4ab0-adf5-5054c735ca0e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415458340 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.kmac_test_vectors_kmac.415458340 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_kmac_xof.83992642
Short name T604
Test name
Test status
Simulation time 331992381 ps
CPU time 5.34 seconds
Started Aug 06 06:02:06 PM PDT 24
Finished Aug 06 06:02:12 PM PDT 24
Peak memory 227116 kb
Host smart-2b89117c-2553-4cf0-99bc-0c90e604ecbc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83992642 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.kmac_test_vectors_kmac_xof.83992642 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_224.2445981433
Short name T358
Test name
Test status
Simulation time 23325751554 ps
CPU time 2281.46 seconds
Started Aug 06 06:01:47 PM PDT 24
Finished Aug 06 06:39:49 PM PDT 24
Peak memory 1215976 kb
Host smart-03831c16-c474-4721-8804-1491c8c7ddbf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2445981433 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_224.2445981433 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_256.3017948120
Short name T516
Test name
Test status
Simulation time 135458530009 ps
CPU time 2171.22 seconds
Started Aug 06 06:01:46 PM PDT 24
Finished Aug 06 06:37:58 PM PDT 24
Peak memory 1110968 kb
Host smart-c94edfcf-12e4-4a2a-b0ce-25a2770cc8e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3017948120 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_256.3017948120 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_384.2566594112
Short name T280
Test name
Test status
Simulation time 575373638760 ps
CPU time 2924.96 seconds
Started Aug 06 06:01:47 PM PDT 24
Finished Aug 06 06:50:32 PM PDT 24
Peak memory 2469860 kb
Host smart-a221b4ab-c8c4-4c34-b224-33097a80f12f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2566594112 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_384.2566594112 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_512.1828918454
Short name T294
Test name
Test status
Simulation time 280088748786 ps
CPU time 1613.55 seconds
Started Aug 06 06:01:47 PM PDT 24
Finished Aug 06 06:28:41 PM PDT 24
Peak memory 1739920 kb
Host smart-531927e3-6363-480d-8eab-dde4e9cd96c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1828918454 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_512.1828918454 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/7.kmac_alert_test.2959390379
Short name T607
Test name
Test status
Simulation time 20311764 ps
CPU time 0.83 seconds
Started Aug 06 06:02:21 PM PDT 24
Finished Aug 06 06:02:22 PM PDT 24
Peak memory 218616 kb
Host smart-a72e21be-b159-4c70-ac6b-d77b4830848f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959390379 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.2959390379 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_alert_test/latest

Test location /workspace/coverage/default/7.kmac_app.570808783
Short name T432
Test name
Test status
Simulation time 38853099424 ps
CPU time 292.78 seconds
Started Aug 06 06:02:22 PM PDT 24
Finished Aug 06 06:07:15 PM PDT 24
Peak memory 440060 kb
Host smart-ad5f60e0-d845-46a9-82c0-dffdfcb8664e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570808783 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.570808783 +enable_masking=1
+sw_key_masked=0
Directory /workspace/7.kmac_app/latest

Test location /workspace/coverage/default/7.kmac_app_with_partial_data.2921780095
Short name T788
Test name
Test status
Simulation time 14661029751 ps
CPU time 193.26 seconds
Started Aug 06 06:02:19 PM PDT 24
Finished Aug 06 06:05:33 PM PDT 24
Peak memory 359044 kb
Host smart-1648adf5-1b61-4892-bf52-679cbf5c3f54
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921780095 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_par
tial_data.2921780095 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/7.kmac_burst_write.4192432749
Short name T34
Test name
Test status
Simulation time 87301867829 ps
CPU time 1172.68 seconds
Started Aug 06 06:02:05 PM PDT 24
Finished Aug 06 06:21:37 PM PDT 24
Peak memory 258192 kb
Host smart-95cca600-b51f-42b0-a85b-c58f59e7fdc2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192432749 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.4192432749
+enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_burst_write/latest

Test location /workspace/coverage/default/7.kmac_edn_timeout_error.3631460075
Short name T469
Test name
Test status
Simulation time 503376988 ps
CPU time 34.22 seconds
Started Aug 06 06:02:20 PM PDT 24
Finished Aug 06 06:02:54 PM PDT 24
Peak memory 227656 kb
Host smart-6f4939a8-4470-4a63-80df-f71ca1307cf3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3631460075 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.3631460075 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_mode_error.3577567591
Short name T19
Test name
Test status
Simulation time 1642202113 ps
CPU time 48.72 seconds
Started Aug 06 06:02:20 PM PDT 24
Finished Aug 06 06:03:09 PM PDT 24
Peak memory 227424 kb
Host smart-e0a2f08f-d91f-4ab9-8f3c-ff7147f3d9c6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3577567591 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.3577567591 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_ready_error.245266367
Short name T725
Test name
Test status
Simulation time 663620841 ps
CPU time 7.3 seconds
Started Aug 06 06:02:21 PM PDT 24
Finished Aug 06 06:02:28 PM PDT 24
Peak memory 225920 kb
Host smart-b6eec9de-508f-40ee-ad69-a1b585a98b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245266367 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.245266367 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_refresh.142340359
Short name T80
Test name
Test status
Simulation time 6378457729 ps
CPU time 117.53 seconds
Started Aug 06 06:02:21 PM PDT 24
Finished Aug 06 06:04:18 PM PDT 24
Peak memory 306276 kb
Host smart-24a1b090-f21c-498d-a3a8-45f705270ba2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142340359 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.142
340359 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/7.kmac_error.297631697
Short name T140
Test name
Test status
Simulation time 22427499406 ps
CPU time 255.43 seconds
Started Aug 06 06:02:22 PM PDT 24
Finished Aug 06 06:06:38 PM PDT 24
Peak memory 324748 kb
Host smart-7df563cc-a0b2-4ec6-afca-7da350e0e51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297631697 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.297631697 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_error/latest

Test location /workspace/coverage/default/7.kmac_key_error.1144611357
Short name T301
Test name
Test status
Simulation time 434182820 ps
CPU time 3.47 seconds
Started Aug 06 06:02:20 PM PDT 24
Finished Aug 06 06:02:24 PM PDT 24
Peak memory 226784 kb
Host smart-24811953-f0eb-4f0c-bba7-a7b503717839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144611357 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.1144611357 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_key_error/latest

Test location /workspace/coverage/default/7.kmac_lc_escalation.1969165293
Short name T87
Test name
Test status
Simulation time 119082420 ps
CPU time 1.57 seconds
Started Aug 06 06:02:21 PM PDT 24
Finished Aug 06 06:02:23 PM PDT 24
Peak memory 227028 kb
Host smart-19c29eab-5604-44cb-b119-ce57d6a2aef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969165293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.1969165293 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/7.kmac_lc_escalation/latest

Test location /workspace/coverage/default/7.kmac_mubi.3074055853
Short name T57
Test name
Test status
Simulation time 54256542513 ps
CPU time 164.99 seconds
Started Aug 06 06:02:21 PM PDT 24
Finished Aug 06 06:05:06 PM PDT 24
Peak memory 274536 kb
Host smart-a649e751-8740-49f7-86d1-9a3091d67d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074055853 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.3074055853 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_mubi/latest

Test location /workspace/coverage/default/7.kmac_sideload.3037216530
Short name T183
Test name
Test status
Simulation time 4718370588 ps
CPU time 368.45 seconds
Started Aug 06 06:02:08 PM PDT 24
Finished Aug 06 06:08:16 PM PDT 24
Peak memory 346260 kb
Host smart-65b54170-80f1-4c6f-9287-6077b1910c16
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037216530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.3037216530 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_sideload/latest

Test location /workspace/coverage/default/7.kmac_smoke.1796422507
Short name T517
Test name
Test status
Simulation time 8670776114 ps
CPU time 55.97 seconds
Started Aug 06 06:02:09 PM PDT 24
Finished Aug 06 06:03:05 PM PDT 24
Peak memory 224116 kb
Host smart-3cfcdd70-8591-4111-806f-944a40b0cb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796422507 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.1796422507 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_smoke/latest

Test location /workspace/coverage/default/7.kmac_stress_all.127792648
Short name T82
Test name
Test status
Simulation time 787025543819 ps
CPU time 1482.79 seconds
Started Aug 06 06:02:23 PM PDT 24
Finished Aug 06 06:27:06 PM PDT 24
Peak memory 831484 kb
Host smart-cd052a6c-e982-44c7-b6d0-5c07c3a95719
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=127792648 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.127792648 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_stress_all/latest

Test location /workspace/coverage/default/7.kmac_stress_all_with_rand_reset.2696995261
Short name T117
Test name
Test status
Simulation time 89492767833 ps
CPU time 778.3 seconds
Started Aug 06 06:02:21 PM PDT 24
Finished Aug 06 06:15:20 PM PDT 24
Peak memory 432296 kb
Host smart-4f949c99-71d7-4ff2-a1d3-05c7915bb306
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2696995261 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all_with_rand_reset.2696995261 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_kmac.1350672756
Short name T284
Test name
Test status
Simulation time 163980603 ps
CPU time 5.68 seconds
Started Aug 06 06:02:22 PM PDT 24
Finished Aug 06 06:02:27 PM PDT 24
Peak memory 227136 kb
Host smart-e5e28abc-8cc2-47b3-9f7b-15c85d4ff328
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350672756 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.kmac_test_vectors_kmac.1350672756 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_kmac_xof.3875961490
Short name T856
Test name
Test status
Simulation time 242368075 ps
CPU time 6.6 seconds
Started Aug 06 06:02:21 PM PDT 24
Finished Aug 06 06:02:28 PM PDT 24
Peak memory 226984 kb
Host smart-e37f9591-7067-48f8-b0a6-80bcc72e8ed5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875961490 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.kmac_test_vectors_kmac_xof.3875961490 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_224.3487745326
Short name T816
Test name
Test status
Simulation time 262017107219 ps
CPU time 3050.34 seconds
Started Aug 06 06:02:08 PM PDT 24
Finished Aug 06 06:52:59 PM PDT 24
Peak memory 3219264 kb
Host smart-bc0bfa2b-c060-4fae-9fbc-7dc7c45ace2d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3487745326 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_224.3487745326 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_256.3683454461
Short name T729
Test name
Test status
Simulation time 143597955338 ps
CPU time 2400.5 seconds
Started Aug 06 06:02:08 PM PDT 24
Finished Aug 06 06:42:08 PM PDT 24
Peak memory 1138724 kb
Host smart-65c09ab8-93b3-470e-a57d-403cf379b2df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3683454461 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_256.3683454461 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_384.4216772401
Short name T681
Test name
Test status
Simulation time 27875274216 ps
CPU time 1573.78 seconds
Started Aug 06 06:02:07 PM PDT 24
Finished Aug 06 06:28:22 PM PDT 24
Peak memory 924004 kb
Host smart-9960595f-05ae-4d3e-9df7-0640c854b885
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4216772401 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_384.4216772401 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_512.3120761453
Short name T208
Test name
Test status
Simulation time 52888740377 ps
CPU time 1335.64 seconds
Started Aug 06 06:02:07 PM PDT 24
Finished Aug 06 06:24:23 PM PDT 24
Peak memory 693756 kb
Host smart-f3588acc-c2d5-4b61-82c4-fbf611d2e995
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3120761453 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_512.3120761453 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_shake_128.611212749
Short name T691
Test name
Test status
Simulation time 64706283366 ps
CPU time 6365.29 seconds
Started Aug 06 06:02:07 PM PDT 24
Finished Aug 06 07:48:13 PM PDT 24
Peak memory 2705272 kb
Host smart-bfe8a326-4c5f-407f-ba80-f548efb5d603
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=611212749 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_128.611212749 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/8.kmac_alert_test.1035234576
Short name T480
Test name
Test status
Simulation time 14184217 ps
CPU time 0.8 seconds
Started Aug 06 06:02:41 PM PDT 24
Finished Aug 06 06:02:43 PM PDT 24
Peak memory 218576 kb
Host smart-1fd03acf-1264-4fcc-a652-16cfb38a50df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035234576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.1035234576 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_alert_test/latest

Test location /workspace/coverage/default/8.kmac_app.3206339937
Short name T641
Test name
Test status
Simulation time 9092048351 ps
CPU time 265.87 seconds
Started Aug 06 06:02:36 PM PDT 24
Finished Aug 06 06:07:02 PM PDT 24
Peak memory 440060 kb
Host smart-c1a471be-1e5f-40b2-b43d-b6be126ee886
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206339937 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.3206339937 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/8.kmac_app/latest

Test location /workspace/coverage/default/8.kmac_app_with_partial_data.399390760
Short name T525
Test name
Test status
Simulation time 37284046658 ps
CPU time 206.41 seconds
Started Aug 06 06:02:36 PM PDT 24
Finished Aug 06 06:06:02 PM PDT 24
Peak memory 360120 kb
Host smart-7f05c47e-77bb-4cfa-8389-50779aaedd36
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399390760 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_parti
al_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_part
ial_data.399390760 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/8.kmac_burst_write.2219739624
Short name T648
Test name
Test status
Simulation time 1224565837 ps
CPU time 70.34 seconds
Started Aug 06 06:02:23 PM PDT 24
Finished Aug 06 06:03:34 PM PDT 24
Peak memory 226996 kb
Host smart-98725eb2-b0d1-482e-816f-f89708ff8f90
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219739624 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.2219739624
+enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_burst_write/latest

Test location /workspace/coverage/default/8.kmac_edn_timeout_error.1050932068
Short name T227
Test name
Test status
Simulation time 19597292 ps
CPU time 1.07 seconds
Started Aug 06 06:02:35 PM PDT 24
Finished Aug 06 06:02:36 PM PDT 24
Peak memory 218788 kb
Host smart-4952add5-2464-49c1-b32d-849e330474f0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1050932068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.1050932068 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_mode_error.3220535474
Short name T728
Test name
Test status
Simulation time 1242318536 ps
CPU time 14.09 seconds
Started Aug 06 06:02:36 PM PDT 24
Finished Aug 06 06:02:50 PM PDT 24
Peak memory 225360 kb
Host smart-c3eaa9ea-4d59-48fa-bd34-7f27614fa673
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3220535474 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.3220535474 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_ready_error.2383658166
Short name T11
Test name
Test status
Simulation time 2157701865 ps
CPU time 20.41 seconds
Started Aug 06 06:02:35 PM PDT 24
Finished Aug 06 06:02:56 PM PDT 24
Peak memory 221640 kb
Host smart-067c2357-ac38-4e3a-a8b7-4fe48b7022b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383658166 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.2383658166 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_refresh.3000034301
Short name T81
Test name
Test status
Simulation time 11674469070 ps
CPU time 298.22 seconds
Started Aug 06 06:02:34 PM PDT 24
Finished Aug 06 06:07:32 PM PDT 24
Peak memory 319700 kb
Host smart-20588b8b-c118-4300-ac45-2bc491b6cb78
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000034301 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.30
00034301 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/8.kmac_error.4174274346
Short name T445
Test name
Test status
Simulation time 15590333325 ps
CPU time 273.91 seconds
Started Aug 06 06:02:35 PM PDT 24
Finished Aug 06 06:07:09 PM PDT 24
Peak memory 436792 kb
Host smart-03fa3b3c-0e5f-4d33-8ff1-ad43441961a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174274346 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.4174274346 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_error/latest

Test location /workspace/coverage/default/8.kmac_key_error.3654475836
Short name T389
Test name
Test status
Simulation time 1337996451 ps
CPU time 4.74 seconds
Started Aug 06 06:02:37 PM PDT 24
Finished Aug 06 06:02:42 PM PDT 24
Peak memory 226804 kb
Host smart-e5a90da4-a19e-4184-b49e-e5cb2c37504d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654475836 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.3654475836 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_key_error/latest

Test location /workspace/coverage/default/8.kmac_lc_escalation.1231689000
Short name T51
Test name
Test status
Simulation time 29699030 ps
CPU time 1.43 seconds
Started Aug 06 06:02:37 PM PDT 24
Finished Aug 06 06:02:39 PM PDT 24
Peak memory 226964 kb
Host smart-258589f7-a4b8-4ecf-94c4-0ae258ec4efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231689000 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.1231689000 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/8.kmac_lc_escalation/latest

Test location /workspace/coverage/default/8.kmac_long_msg_and_output.2591017788
Short name T379
Test name
Test status
Simulation time 28638820994 ps
CPU time 932.97 seconds
Started Aug 06 06:02:22 PM PDT 24
Finished Aug 06 06:17:56 PM PDT 24
Peak memory 1189552 kb
Host smart-03b6ab45-e450-4cf2-80d6-09b3b7d12aae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591017788 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_an
d_output.2591017788 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/8.kmac_mubi.3721190655
Short name T822
Test name
Test status
Simulation time 13977070319 ps
CPU time 369.9 seconds
Started Aug 06 06:02:34 PM PDT 24
Finished Aug 06 06:08:44 PM PDT 24
Peak memory 478440 kb
Host smart-16622d6b-8559-453a-8ecc-ebaec4273317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721190655 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.3721190655 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_mubi/latest

Test location /workspace/coverage/default/8.kmac_sideload.3997658335
Short name T761
Test name
Test status
Simulation time 3780418070 ps
CPU time 302.52 seconds
Started Aug 06 06:02:22 PM PDT 24
Finished Aug 06 06:07:24 PM PDT 24
Peak memory 326024 kb
Host smart-7a18c911-cd2a-4a20-9a70-1b89f77d838c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997658335 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.3997658335 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_sideload/latest

Test location /workspace/coverage/default/8.kmac_smoke.1214283107
Short name T790
Test name
Test status
Simulation time 1746122016 ps
CPU time 8.86 seconds
Started Aug 06 06:02:19 PM PDT 24
Finished Aug 06 06:02:28 PM PDT 24
Peak memory 227056 kb
Host smart-eac7c7e7-a1af-4a6a-abcf-df00a19d6659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214283107 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.1214283107 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_smoke/latest

Test location /workspace/coverage/default/8.kmac_stress_all.1753602074
Short name T287
Test name
Test status
Simulation time 79425556764 ps
CPU time 915.47 seconds
Started Aug 06 06:02:41 PM PDT 24
Finished Aug 06 06:17:57 PM PDT 24
Peak memory 358344 kb
Host smart-4496f6a3-bf06-4751-958f-c46c2b29704e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1753602074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.1753602074 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_stress_all/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_kmac.3081468871
Short name T362
Test name
Test status
Simulation time 246975088 ps
CPU time 7.07 seconds
Started Aug 06 06:02:34 PM PDT 24
Finished Aug 06 06:02:42 PM PDT 24
Peak memory 227004 kb
Host smart-bb1e4e98-1399-4016-8057-886d495ec878
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081468871 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.kmac_test_vectors_kmac.3081468871 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_kmac_xof.1355840981
Short name T541
Test name
Test status
Simulation time 410938314 ps
CPU time 5.76 seconds
Started Aug 06 06:02:35 PM PDT 24
Finished Aug 06 06:02:41 PM PDT 24
Peak memory 227052 kb
Host smart-bf40efe2-24be-4603-90f8-70de4457e041
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355840981 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.kmac_test_vectors_kmac_xof.1355840981 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_224.932716004
Short name T427
Test name
Test status
Simulation time 597526291629 ps
CPU time 3440.6 seconds
Started Aug 06 06:02:23 PM PDT 24
Finished Aug 06 06:59:44 PM PDT 24
Peak memory 3248096 kb
Host smart-4a1d638a-2235-49a7-888c-078a3ff73181
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=932716004 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_224.932716004 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_256.274688340
Short name T316
Test name
Test status
Simulation time 163410294501 ps
CPU time 2220.99 seconds
Started Aug 06 06:02:22 PM PDT 24
Finished Aug 06 06:39:24 PM PDT 24
Peak memory 1166312 kb
Host smart-6191cb5f-03a9-4dc0-920c-051d0f35487d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=274688340 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_256.274688340 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_384.592892181
Short name T886
Test name
Test status
Simulation time 62800791445 ps
CPU time 2426.62 seconds
Started Aug 06 06:02:35 PM PDT 24
Finished Aug 06 06:43:02 PM PDT 24
Peak memory 2401724 kb
Host smart-0ef2fd5b-e8cc-4eb3-a398-0e4e2c1d71ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=592892181 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_384.592892181 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_512.1813079208
Short name T361
Test name
Test status
Simulation time 43681793424 ps
CPU time 1169.93 seconds
Started Aug 06 06:02:36 PM PDT 24
Finished Aug 06 06:22:06 PM PDT 24
Peak memory 700348 kb
Host smart-81b28071-df79-404a-b04a-d5a8ad8db9e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1813079208 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_512.1813079208 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/9.kmac_alert_test.70715804
Short name T913
Test name
Test status
Simulation time 22956869 ps
CPU time 0.82 seconds
Started Aug 06 06:03:03 PM PDT 24
Finished Aug 06 06:03:04 PM PDT 24
Peak memory 218616 kb
Host smart-926a8b39-1c7d-4a6f-be1b-c5917e86e59f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70715804 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.70715804 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/9.kmac_alert_test/latest

Test location /workspace/coverage/default/9.kmac_app.854769173
Short name T598
Test name
Test status
Simulation time 98909874682 ps
CPU time 530.85 seconds
Started Aug 06 06:02:48 PM PDT 24
Finished Aug 06 06:11:39 PM PDT 24
Peak memory 578396 kb
Host smart-67a11485-3e85-44bf-852e-c645f0ca5451
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854769173 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.854769173 +enable_masking=1
+sw_key_masked=0
Directory /workspace/9.kmac_app/latest

Test location /workspace/coverage/default/9.kmac_app_with_partial_data.3470936920
Short name T732
Test name
Test status
Simulation time 23776980455 ps
CPU time 406.05 seconds
Started Aug 06 06:02:49 PM PDT 24
Finished Aug 06 06:09:36 PM PDT 24
Peak memory 342800 kb
Host smart-8b059dcb-87db-492c-bd61-a9e4af2e1d6f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470936920 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_par
tial_data.3470936920 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/9.kmac_burst_write.165250906
Short name T511
Test name
Test status
Simulation time 27562902667 ps
CPU time 1434.22 seconds
Started Aug 06 06:02:37 PM PDT 24
Finished Aug 06 06:26:32 PM PDT 24
Peak memory 266152 kb
Host smart-494066e1-dbba-4b0f-b444-f1b20873211d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165250906 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.165250906 +
enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_burst_write/latest

Test location /workspace/coverage/default/9.kmac_edn_timeout_error.2453415927
Short name T748
Test name
Test status
Simulation time 1199798716 ps
CPU time 28.43 seconds
Started Aug 06 06:02:50 PM PDT 24
Finished Aug 06 06:03:19 PM PDT 24
Peak memory 233212 kb
Host smart-39148d1c-5e24-478a-95c8-2d63681ea842
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2453415927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.2453415927 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_mode_error.2197633914
Short name T33
Test name
Test status
Simulation time 18880415 ps
CPU time 0.91 seconds
Started Aug 06 06:03:02 PM PDT 24
Finished Aug 06 06:03:03 PM PDT 24
Peak memory 218572 kb
Host smart-a09b69a8-7f53-4d38-a4ab-c7922d6f66c1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2197633914 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.2197633914 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_ready_error.1954362122
Short name T914
Test name
Test status
Simulation time 3531725402 ps
CPU time 39.32 seconds
Started Aug 06 06:03:03 PM PDT 24
Finished Aug 06 06:03:43 PM PDT 24
Peak memory 227188 kb
Host smart-122eac3c-7ab9-4025-b77c-ca2b554ac77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954362122 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.1954362122 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_refresh.1085318198
Short name T521
Test name
Test status
Simulation time 4110301841 ps
CPU time 163.04 seconds
Started Aug 06 06:02:48 PM PDT 24
Finished Aug 06 06:05:32 PM PDT 24
Peak memory 278040 kb
Host smart-13b06973-cb14-4290-a713-4ad004b33c07
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085318198 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.10
85318198 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/9.kmac_error.226552236
Short name T493
Test name
Test status
Simulation time 9983238200 ps
CPU time 356.2 seconds
Started Aug 06 06:02:50 PM PDT 24
Finished Aug 06 06:08:47 PM PDT 24
Peak memory 487608 kb
Host smart-7888438e-9af0-4e1d-a1b3-1deda7bdb692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226552236 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.226552236 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_error/latest

Test location /workspace/coverage/default/9.kmac_key_error.1807645636
Short name T385
Test name
Test status
Simulation time 4560464018 ps
CPU time 9.44 seconds
Started Aug 06 06:02:50 PM PDT 24
Finished Aug 06 06:02:59 PM PDT 24
Peak memory 227024 kb
Host smart-e5703d6d-486b-4c35-8d9a-e2f86a9fd732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807645636 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.1807645636 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_key_error/latest

Test location /workspace/coverage/default/9.kmac_lc_escalation.964594695
Short name T54
Test name
Test status
Simulation time 1167701421 ps
CPU time 8.93 seconds
Started Aug 06 06:03:01 PM PDT 24
Finished Aug 06 06:03:10 PM PDT 24
Peak memory 242708 kb
Host smart-f73d6037-42d7-443c-a404-35591c4aaa7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964594695 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.964594695 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_lc_escalation/latest

Test location /workspace/coverage/default/9.kmac_long_msg_and_output.2554568272
Short name T632
Test name
Test status
Simulation time 87927409203 ps
CPU time 954.19 seconds
Started Aug 06 06:02:42 PM PDT 24
Finished Aug 06 06:18:36 PM PDT 24
Peak memory 1198972 kb
Host smart-41f95e98-f472-4955-be50-1fa8ac8f29f2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554568272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_an
d_output.2554568272 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/9.kmac_mubi.590306229
Short name T313
Test name
Test status
Simulation time 30775480011 ps
CPU time 196.02 seconds
Started Aug 06 06:02:51 PM PDT 24
Finished Aug 06 06:06:07 PM PDT 24
Peak memory 385800 kb
Host smart-fd5a69b0-2f1c-4502-aecc-776d621605da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590306229 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.590306229 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_mubi/latest

Test location /workspace/coverage/default/9.kmac_sideload.629295514
Short name T862
Test name
Test status
Simulation time 12513016581 ps
CPU time 120.86 seconds
Started Aug 06 06:02:42 PM PDT 24
Finished Aug 06 06:04:43 PM PDT 24
Peak memory 267128 kb
Host smart-2a295c46-08fc-4432-a8bd-100d327b4906
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629295514 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.629295514 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_sideload/latest

Test location /workspace/coverage/default/9.kmac_smoke.1970683105
Short name T590
Test name
Test status
Simulation time 12862415708 ps
CPU time 53.95 seconds
Started Aug 06 06:02:36 PM PDT 24
Finished Aug 06 06:03:30 PM PDT 24
Peak memory 227140 kb
Host smart-e8506fbd-7cba-42f7-89c5-a8290cfa3079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970683105 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.1970683105 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_smoke/latest

Test location /workspace/coverage/default/9.kmac_stress_all.2484660957
Short name T735
Test name
Test status
Simulation time 1525530290 ps
CPU time 120.8 seconds
Started Aug 06 06:03:03 PM PDT 24
Finished Aug 06 06:05:04 PM PDT 24
Peak memory 271900 kb
Host smart-bed02521-5386-4957-bfa7-7fb2fd2d15ea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2484660957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.2484660957 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_stress_all/latest

Test location /workspace/coverage/default/9.kmac_stress_all_with_rand_reset.1170598871
Short name T45
Test name
Test status
Simulation time 151791053842 ps
CPU time 3513.79 seconds
Started Aug 06 06:03:00 PM PDT 24
Finished Aug 06 07:01:34 PM PDT 24
Peak memory 857744 kb
Host smart-a6676745-17c2-4bee-8f87-508b6a176038
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1170598871 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all_with_rand_reset.1170598871 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_kmac.743868153
Short name T744
Test name
Test status
Simulation time 726496330 ps
CPU time 6 seconds
Started Aug 06 06:02:49 PM PDT 24
Finished Aug 06 06:02:55 PM PDT 24
Peak memory 227024 kb
Host smart-570aa56a-b44b-4fa8-9804-4b5e9c4a48ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743868153 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.kmac_test_vectors_kmac.743868153 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_kmac_xof.2890154363
Short name T499
Test name
Test status
Simulation time 428294965 ps
CPU time 5.57 seconds
Started Aug 06 06:02:49 PM PDT 24
Finished Aug 06 06:02:55 PM PDT 24
Peak memory 219092 kb
Host smart-0d2258ab-5365-4548-acec-97f94cf04888
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890154363 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.kmac_test_vectors_kmac_xof.2890154363 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_224.1577752287
Short name T645
Test name
Test status
Simulation time 95593540369 ps
CPU time 2268.04 seconds
Started Aug 06 06:02:41 PM PDT 24
Finished Aug 06 06:40:29 PM PDT 24
Peak memory 1185052 kb
Host smart-fb017092-2501-4dbe-801b-07169d590f2e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1577752287 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_224.1577752287 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_256.2892357000
Short name T188
Test name
Test status
Simulation time 91240392781 ps
CPU time 2036.65 seconds
Started Aug 06 06:02:49 PM PDT 24
Finished Aug 06 06:36:47 PM PDT 24
Peak memory 1132384 kb
Host smart-110297b6-4215-4ae9-8763-5bb0d8649cb2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2892357000 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_256.2892357000 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_384.4035436627
Short name T504
Test name
Test status
Simulation time 68613357237 ps
CPU time 1714.93 seconds
Started Aug 06 06:02:50 PM PDT 24
Finished Aug 06 06:31:25 PM PDT 24
Peak memory 928356 kb
Host smart-6a464759-24a0-4909-a4bb-f5f55addd593
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4035436627 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_384.4035436627 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_512.4154548824
Short name T460
Test name
Test status
Simulation time 199797465625 ps
CPU time 1931.43 seconds
Started Aug 06 06:02:49 PM PDT 24
Finished Aug 06 06:35:01 PM PDT 24
Peak memory 1753168 kb
Host smart-6a6cfbfb-1031-45fd-93ce-4cfc7228c07c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4154548824 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_512.4154548824 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_shake_128.1957132706
Short name T222
Test name
Test status
Simulation time 274780965925 ps
CPU time 6549.19 seconds
Started Aug 06 06:02:49 PM PDT 24
Finished Aug 06 07:52:00 PM PDT 24
Peak memory 2734804 kb
Host smart-f78f2267-1fec-4662-bea6-0828fa0dc7ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1957132706 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_128.1957132706 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_shake_256.2966051279
Short name T543
Test name
Test status
Simulation time 57689820363 ps
CPU time 5472 seconds
Started Aug 06 06:02:49 PM PDT 24
Finished Aug 06 07:34:02 PM PDT 24
Peak memory 2257728 kb
Host smart-0c82031f-5ab8-4d59-b7fc-53bc916f8540
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2966051279 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_256.2966051279 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_shake_256/latest
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