Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	61972729	1			T1	30203		T3	111108		T6	11653
all_values[1]	61972729	1			T1	30203		T3	111108		T6	11653
all_values[2]	61972729	1			T1	30203		T3	111108		T6	11653

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

534865

1

T1

1089

T3

29

T6

1602

auto[1]

185383322

1

T1

89520

T3

333295

T6

33357

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

185076033

1

T1

89748

T3

332199

T6

34431

auto[1]

842154

1

T1

861

T3

1125

T6

528

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	175974	1			T3	7		T6	714		T34	1
all_values[0]	auto[0]	auto[1]	1804	1			T3	8		T6	12		T34	2
all_values[0]	auto[1]	auto[0]	61516037	1			T1	29916		T3	110726		T6	10763
all_values[0]	auto[1]	auto[1]	278914	1			T1	287		T3	367		T6	164
all_values[1]	auto[0]	auto[0]	179929	1			T1	175		T3	1		T6	475
all_values[1]	auto[0]	auto[1]	1447	1			T1	1		T3	2		T6	4
all_values[1]	auto[1]	auto[0]	61512082	1			T1	29741		T3	110732		T6	11002
all_values[1]	auto[1]	auto[1]	279271	1			T1	286		T3	373		T6	172
all_values[2]	auto[0]	auto[0]	174187	1			T1	906		T3	5		T6	394
all_values[2]	auto[0]	auto[1]	1524	1			T1	7		T3	6		T6	3
all_values[2]	auto[1]	auto[0]	61517824	1			T1	29010		T3	110728		T6	11083
all_values[2]	auto[1]	auto[1]	279194	1			T1	280		T3	369		T6	173