Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
173518 |
1 |
|
|
T1 |
384 |
|
T3 |
2 |
|
T6 |
260 |
auto[1] |
215036 |
1 |
|
|
T3 |
490 |
|
T6 |
36 |
|
T34 |
4528 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
96836 |
1 |
|
|
T1 |
74 |
|
T3 |
134 |
|
T6 |
67 |
lower_val |
96371 |
1 |
|
|
T1 |
102 |
|
T3 |
97 |
|
T6 |
76 |
zero_val |
1453 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T6 |
4 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
140144 |
1 |
|
|
T1 |
198 |
|
T3 |
108 |
|
T6 |
138 |
lower_val |
140546 |
1 |
|
|
T1 |
186 |
|
T3 |
128 |
|
T6 |
138 |
zero_val |
107864 |
1 |
|
|
T3 |
256 |
|
T6 |
20 |
|
T34 |
2292 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
21365 |
1 |
|
|
T1 |
28 |
|
T6 |
27 |
|
T8 |
1 |
higher_val |
higher_val |
auto[1] |
13705 |
1 |
|
|
T3 |
33 |
|
T6 |
1 |
|
T34 |
274 |
higher_val |
lower_val |
auto[0] |
21417 |
1 |
|
|
T1 |
46 |
|
T6 |
30 |
|
T38 |
24 |
higher_val |
lower_val |
auto[1] |
13652 |
1 |
|
|
T3 |
32 |
|
T6 |
2 |
|
T34 |
277 |
higher_val |
zero_val |
auto[0] |
85 |
1 |
|
|
T6 |
1 |
|
T39 |
1 |
|
T62 |
1 |
higher_val |
zero_val |
auto[1] |
26612 |
1 |
|
|
T3 |
69 |
|
T6 |
6 |
|
T34 |
521 |
lower_val |
higher_val |
auto[0] |
21472 |
1 |
|
|
T1 |
63 |
|
T6 |
32 |
|
T38 |
14 |
lower_val |
higher_val |
auto[1] |
13266 |
1 |
|
|
T3 |
17 |
|
T6 |
1 |
|
T34 |
281 |
lower_val |
lower_val |
auto[0] |
21515 |
1 |
|
|
T1 |
39 |
|
T6 |
34 |
|
T38 |
22 |
lower_val |
lower_val |
auto[1] |
13385 |
1 |
|
|
T3 |
28 |
|
T6 |
2 |
|
T34 |
300 |
lower_val |
zero_val |
auto[0] |
92 |
1 |
|
|
T3 |
1 |
|
T6 |
1 |
|
T36 |
1 |
lower_val |
zero_val |
auto[1] |
26641 |
1 |
|
|
T3 |
51 |
|
T6 |
6 |
|
T34 |
618 |
zero_val |
higher_val |
auto[0] |
423 |
1 |
|
|
T6 |
3 |
|
T34 |
1 |
|
T8 |
1 |
zero_val |
higher_val |
auto[1] |
84 |
1 |
|
|
T6 |
1 |
|
T36 |
1 |
|
T17 |
2 |
zero_val |
lower_val |
auto[0] |
416 |
1 |
|
|
T1 |
1 |
|
T37 |
1 |
|
T38 |
1 |
zero_val |
lower_val |
auto[1] |
115 |
1 |
|
|
T34 |
2 |
|
T17 |
1 |
|
T186 |
1 |
zero_val |
zero_val |
auto[0] |
253 |
1 |
|
|
T3 |
1 |
|
T36 |
1 |
|
T20 |
1 |
zero_val |
zero_val |
auto[1] |
162 |
1 |
|
|
T34 |
4 |
|
T36 |
1 |
|
T187 |
2 |