Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	5435	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	6245	1			T34	38		T36	24		T38	17
len_5001_7500	11110	1			T3	33		T34	36		T36	24
len_2501_5000	6645	1			T3	34		T34	36		T36	24
len_1025_2500	3961	1			T3	20		T34	22		T36	14
len_769_1024	5967	1			T1	57		T3	4		T6	18
len_513_768	6435	1			T1	36		T3	3		T6	19
len_257_512	11725	1			T1	53		T3	4		T6	13
len_0_256	129700	1			T1	46		T3	148		T6	65
len_keccak_block_sizes[72]	502	1			T3	2		T34	3		T36	2
len_keccak_block_sizes[104]	390	1			T34	3		T36	2		T45	2
len_keccak_block_sizes[136]	302	1			T34	3		T45	2		T41	1
len_keccak_block_sizes[144]	208	1			T6	1		T34	3		T44	1
len_keccak_block_sizes[168]	133	1			T34	3		T37	1		T188	3
len_1	536	1			T3	2		T34	3		T36	2
len_0	930	1			T3	2		T34	3		T36	2