Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	61972729	1			T1	30203		T3	111108		T6	11653
all_pins[1]	61972729	1			T1	30203		T3	111108		T6	11653
all_pins[2]	61972729	1			T1	30203		T3	111108		T6	11653

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	185329739	1			T1	90222		T3	332957		T6	34768
values[0x1]	588448	1			T1	387		T3	367		T6	191
transitions[0x0=>0x1]	586391	1			T1	387		T3	367		T6	191
transitions[0x1=>0x0]	586413	1			T1	387		T3	367		T6	191

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	61693815	1			T1	29916		T3	110741		T6	11489
all_pins[0]	values[0x1]	278914	1			T1	287		T3	367		T6	164
all_pins[0]	transitions[0x0=>0x1]	278907	1			T1	287		T3	367		T6	164
all_pins[0]	transitions[0x1=>0x0]	5439	1			T1	100		T6	27		T37	54
all_pins[1]	values[0x0]	61967283	1			T1	30103		T3	111108		T6	11626
all_pins[1]	values[0x1]	5446	1			T1	100		T6	27		T37	54
all_pins[1]	transitions[0x0=>0x1]	5224	1			T1	100		T6	27		T37	54
all_pins[1]	transitions[0x1=>0x0]	303866	1			T15	6345		T22	767		T43	643
all_pins[2]	values[0x0]	61668641	1			T1	30203		T3	111108		T6	11653
all_pins[2]	values[0x1]	304088	1			T15	6363		T22	767		T43	643
all_pins[2]	transitions[0x0=>0x1]	302260	1			T15	6314		T22	767		T43	643
all_pins[2]	transitions[0x1=>0x0]	277108	1			T1	287		T3	367		T6	164