Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8034734 |
1 |
|
|
T1 |
31597 |
|
T3 |
3936 |
|
T6 |
14796 |
auto[1] |
8034661 |
1 |
|
|
T1 |
31597 |
|
T3 |
3936 |
|
T6 |
14796 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
15945379 |
1 |
|
|
T1 |
62918 |
|
T3 |
7872 |
|
T6 |
29426 |
triple_byte_access |
41362 |
1 |
|
|
T1 |
116 |
|
T6 |
58 |
|
T34 |
620 |
halfword_access |
41372 |
1 |
|
|
T1 |
74 |
|
T6 |
60 |
|
T34 |
632 |
byte_access |
41282 |
1 |
|
|
T1 |
86 |
|
T6 |
48 |
|
T34 |
620 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
7972726 |
1 |
|
|
T1 |
31459 |
|
T3 |
3936 |
|
T6 |
14713 |
auto[0] |
triple_byte_access |
20681 |
1 |
|
|
T1 |
58 |
|
T6 |
29 |
|
T34 |
310 |
auto[0] |
halfword_access |
20686 |
1 |
|
|
T1 |
37 |
|
T6 |
30 |
|
T34 |
316 |
auto[0] |
byte_access |
20641 |
1 |
|
|
T1 |
43 |
|
T6 |
24 |
|
T34 |
310 |
auto[1] |
word_access |
7972653 |
1 |
|
|
T1 |
31459 |
|
T3 |
3936 |
|
T6 |
14713 |
auto[1] |
triple_byte_access |
20681 |
1 |
|
|
T1 |
58 |
|
T6 |
29 |
|
T34 |
310 |
auto[1] |
halfword_access |
20686 |
1 |
|
|
T1 |
37 |
|
T6 |
30 |
|
T34 |
316 |
auto[1] |
byte_access |
20641 |
1 |
|
|
T1 |
43 |
|
T6 |
24 |
|
T34 |
310 |