Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	81286884	1			T1	11705		T2	908		T3	212980
all_values[1]	81286884	1			T1	11705		T2	908		T3	212980
all_values[2]	81286884	1			T1	11705		T2	908		T3	212980

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

522706

1

T2

23

T3

7

T33

6

auto[1]

243337946

1

T1

35115

T2

2701

T3

638933

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

242669358

1

T1

34773

T2

2340

T3

637176

auto[1]

1191294

1

T1

342

T2

384

T3

1764

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	157804	1			T34	6		T11	1		T7	1037
all_values[0]	auto[0]	auto[1]	2021	1			T34	6		T7	14		T41	4
all_values[0]	auto[1]	auto[0]	80731982	1			T1	11591		T2	780		T3	212392
all_values[0]	auto[1]	auto[1]	395077	1			T1	114		T2	128		T3	588
all_values[1]	auto[0]	auto[0]	189909	1			T2	12		T34	3		T36	5
all_values[1]	auto[0]	auto[1]	1521	1			T2	3		T34	4		T36	2
all_values[1]	auto[1]	auto[0]	80699877	1			T1	11591		T2	768		T3	212392
all_values[1]	auto[1]	auto[1]	395577	1			T1	114		T2	125		T3	588
all_values[2]	auto[0]	auto[0]	170069	1			T2	7		T3	5		T33	5
all_values[2]	auto[0]	auto[1]	1382	1			T2	1		T3	2		T33	1
all_values[2]	auto[1]	auto[0]	80719717	1			T1	11591		T2	773		T3	212387
all_values[2]	auto[1]	auto[1]	395716	1			T1	114		T2	127		T3	586