Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
267054 |
1 |
|
|
T1 |
168 |
|
T2 |
170 |
|
T3 |
780 |
auto[1] |
275114 |
1 |
|
|
T33 |
16 |
|
T34 |
778 |
|
T46 |
4672 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
136093 |
1 |
|
|
T1 |
36 |
|
T2 |
64 |
|
T3 |
192 |
lower_val |
133884 |
1 |
|
|
T1 |
46 |
|
T2 |
32 |
|
T3 |
177 |
zero_val |
1580 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
202754 |
1 |
|
|
T1 |
78 |
|
T2 |
94 |
|
T3 |
366 |
lower_val |
201854 |
1 |
|
|
T1 |
90 |
|
T2 |
76 |
|
T3 |
414 |
zero_val |
137560 |
1 |
|
|
T33 |
6 |
|
T34 |
384 |
|
T46 |
2274 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
34057 |
1 |
|
|
T1 |
17 |
|
T2 |
35 |
|
T3 |
102 |
higher_val |
higher_val |
auto[1] |
17240 |
1 |
|
|
T34 |
50 |
|
T46 |
293 |
|
T41 |
41 |
higher_val |
lower_val |
auto[0] |
33178 |
1 |
|
|
T1 |
19 |
|
T2 |
29 |
|
T3 |
90 |
higher_val |
lower_val |
auto[1] |
17380 |
1 |
|
|
T33 |
3 |
|
T34 |
52 |
|
T46 |
353 |
higher_val |
zero_val |
auto[0] |
82 |
1 |
|
|
T46 |
1 |
|
T77 |
1 |
|
T152 |
1 |
higher_val |
zero_val |
auto[1] |
34156 |
1 |
|
|
T33 |
2 |
|
T34 |
98 |
|
T46 |
588 |
lower_val |
higher_val |
auto[0] |
33121 |
1 |
|
|
T1 |
22 |
|
T2 |
18 |
|
T3 |
79 |
lower_val |
higher_val |
auto[1] |
17036 |
1 |
|
|
T33 |
1 |
|
T34 |
52 |
|
T46 |
291 |
lower_val |
lower_val |
auto[0] |
32689 |
1 |
|
|
T1 |
24 |
|
T2 |
14 |
|
T3 |
98 |
lower_val |
lower_val |
auto[1] |
17132 |
1 |
|
|
T33 |
1 |
|
T34 |
40 |
|
T46 |
294 |
lower_val |
zero_val |
auto[0] |
78 |
1 |
|
|
T8 |
1 |
|
T54 |
1 |
|
T104 |
1 |
lower_val |
zero_val |
auto[1] |
33828 |
1 |
|
|
T34 |
92 |
|
T46 |
599 |
|
T41 |
74 |
zero_val |
higher_val |
auto[0] |
463 |
1 |
|
|
T33 |
1 |
|
T36 |
1 |
|
T38 |
1 |
zero_val |
higher_val |
auto[1] |
103 |
1 |
|
|
T77 |
1 |
|
T15 |
2 |
|
T20 |
2 |
zero_val |
lower_val |
auto[0] |
501 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
zero_val |
lower_val |
auto[1] |
91 |
1 |
|
|
T15 |
1 |
|
T54 |
1 |
|
T190 |
1 |
zero_val |
zero_val |
auto[0] |
260 |
1 |
|
|
T46 |
1 |
|
T8 |
1 |
|
T77 |
1 |
zero_val |
zero_val |
auto[1] |
162 |
1 |
|
|
T34 |
2 |
|
T46 |
2 |
|
T77 |
1 |