Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	7746	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	7773	1			T3	17		T34	17		T36	24
len_5001_7500	13017	1			T3	17		T34	17		T36	24
len_2501_5000	8160	1			T3	17		T34	17		T36	24
len_1025_2500	4832	1			T3	10		T34	10		T36	14
len_769_1024	5888	1			T1	15		T3	2		T34	2
len_513_768	6470	1			T1	16		T3	2		T34	2
len_257_512	13899	1			T1	25		T3	2		T34	2
len_0_256	196669	1			T1	21		T2	85		T3	290
len_keccak_block_sizes[72]	629	1			T3	2		T34	2		T36	2
len_keccak_block_sizes[104]	525	1			T3	2		T34	2		T36	2
len_keccak_block_sizes[136]	430	1			T3	2		T34	2		T46	3
len_keccak_block_sizes[144]	326	1			T3	2		T34	2		T46	3
len_keccak_block_sizes[168]	225	1			T1	2		T46	3		T66	3
len_1	664	1			T3	2		T34	2		T36	2
len_0	1065	1			T3	2		T34	2		T36	2