Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	81286884	1			T1	11705		T2	908		T3	212980
all_pins[1]	81286884	1			T1	11705		T2	908		T3	212980
all_pins[2]	81286884	1			T1	11705		T2	908		T3	212980

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	243184792	1			T1	34282		T2	2596		T3	638352
values[0x1]	675860	1			T1	833		T2	128		T3	588
transitions[0x0=>0x1]	673841	1			T1	832		T2	128		T3	588
transitions[0x1=>0x0]	673861	1			T1	833		T2	128		T3	588

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	80891807	1			T1	11591		T2	780		T3	212392
all_pins[0]	values[0x1]	395077	1			T1	114		T2	128		T3	588
all_pins[0]	transitions[0x0=>0x1]	395064	1			T1	114		T2	128		T3	588
all_pins[0]	transitions[0x1=>0x0]	5582	1			T8	30		T19	35		T146	60
all_pins[1]	values[0x0]	81281289	1			T1	11705		T2	908		T3	212980
all_pins[1]	values[0x1]	5595	1			T8	30		T19	35		T146	60
all_pins[1]	transitions[0x0=>0x1]	5267	1			T8	30		T19	35		T146	60
all_pins[1]	transitions[0x1=>0x0]	274860	1			T1	719		T7	908		T15	1019
all_pins[2]	values[0x0]	81011696	1			T1	10986		T2	908		T3	212980
all_pins[2]	values[0x1]	275188	1			T1	719		T7	908		T15	1019
all_pins[2]	transitions[0x0=>0x1]	273510	1			T1	718		T7	907		T15	1012
all_pins[2]	transitions[0x1=>0x0]	393419	1			T1	114		T2	128		T3	588