Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	608	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5217	1			T1	8		T7	12		T8	13
len_601_800	12103	1			T1	20		T7	28		T8	37
len_401_600	8036	1			T1	16		T7	22		T8	23
len_201_400	15565	1			T1	8		T7	6		T8	6
len_65_200	51996	1			T1	3		T2	44		T46	685
len_min_for_xof_require_squeeze	699	1			T2	1		T46	9		T66	10
len_keccak_block_sizes[72]	485	1			T46	9		T66	5		T63	5
len_keccak_block_sizes[104]	482	1			T2	1		T46	9		T66	5
len_keccak_block_sizes[136]	475	1			T46	9		T66	5		T63	5
len_keccak_block_sizes[144]	266	1			T2	1		T66	5		T63	5
len_keccak_block_sizes[168]	276	1			T66	5		T63	5		T64	5
len_datapath_width	13832	1			T2	3		T33	3		T38	3
len_2_63	162222	1			T1	6		T2	38		T3	390
len_1	53	1			T152	1		T191	1		T131	2