Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9560639 |
1 |
|
|
T1 |
12753 |
|
T2 |
3280 |
|
T3 |
2730 |
auto[1] |
9560575 |
1 |
|
|
T1 |
12753 |
|
T2 |
3280 |
|
T3 |
2730 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
18938672 |
1 |
|
|
T1 |
25386 |
|
T2 |
6452 |
|
T3 |
5460 |
triple_byte_access |
60610 |
1 |
|
|
T1 |
42 |
|
T2 |
30 |
|
T46 |
558 |
halfword_access |
61382 |
1 |
|
|
T1 |
36 |
|
T2 |
34 |
|
T46 |
558 |
byte_access |
60550 |
1 |
|
|
T1 |
42 |
|
T2 |
44 |
|
T46 |
558 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
9469368 |
1 |
|
|
T1 |
12693 |
|
T2 |
3226 |
|
T3 |
2730 |
auto[0] |
triple_byte_access |
30305 |
1 |
|
|
T1 |
21 |
|
T2 |
15 |
|
T46 |
279 |
auto[0] |
halfword_access |
30691 |
1 |
|
|
T1 |
18 |
|
T2 |
17 |
|
T46 |
279 |
auto[0] |
byte_access |
30275 |
1 |
|
|
T1 |
21 |
|
T2 |
22 |
|
T46 |
279 |
auto[1] |
word_access |
9469304 |
1 |
|
|
T1 |
12693 |
|
T2 |
3226 |
|
T3 |
2730 |
auto[1] |
triple_byte_access |
30305 |
1 |
|
|
T1 |
21 |
|
T2 |
15 |
|
T46 |
279 |
auto[1] |
halfword_access |
30691 |
1 |
|
|
T1 |
18 |
|
T2 |
17 |
|
T46 |
279 |
auto[1] |
byte_access |
30275 |
1 |
|
|
T1 |
21 |
|
T2 |
22 |
|
T46 |
279 |