Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	79957376	1			T1	84193		T2	24417		T3	178
all_values[1]	79957376	1			T1	84193		T2	24417		T3	178
all_values[2]	79957376	1			T1	84193		T2	24417		T3	178

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

456758

1

T1

621

T2

123

T3

64

auto[1]

239415370

1

T1

251958

T2

73128

T3

470

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

238724145

1

T1

251400

T2

72561

T3

471

auto[1]

1147983

1

T1

1179

T2

690

T3

63

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	133627	1			T1	39		T2	59		T31	2060
all_values[0]	auto[0]	auto[1]	1792	1			T1	10		T2	2		T31	2
all_values[0]	auto[1]	auto[0]	79441088	1			T1	83761		T2	24128		T3	157
all_values[0]	auto[1]	auto[1]	380869	1			T1	383		T2	228		T3	21
all_values[1]	auto[0]	auto[0]	141415	1			T1	219		T3	13		T14	5174
all_values[1]	auto[0]	auto[1]	1401	1			T1	5		T3	1		T14	7
all_values[1]	auto[1]	auto[0]	79433300	1			T1	83581		T2	24187		T3	144
all_values[1]	auto[1]	auto[1]	381260	1			T1	388		T2	230		T3	20
all_values[2]	auto[0]	auto[0]	177051	1			T1	340		T2	60		T3	44
all_values[2]	auto[0]	auto[1]	1472	1			T1	8		T2	2		T3	6
all_values[2]	auto[1]	auto[0]	79397664	1			T1	83460		T2	24127		T3	113
all_values[2]	auto[1]	auto[1]	381189	1			T1	385		T2	228		T3	15