Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
217196 |
1 |
|
|
T1 |
180 |
|
T2 |
370 |
|
T3 |
30 |
auto[1] |
307884 |
1 |
|
|
T1 |
368 |
|
T14 |
276 |
|
T34 |
618 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
131185 |
1 |
|
|
T1 |
123 |
|
T2 |
107 |
|
T3 |
7 |
lower_val |
130061 |
1 |
|
|
T1 |
113 |
|
T2 |
78 |
|
T3 |
4 |
zero_val |
1599 |
1 |
|
|
T1 |
7 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
185876 |
1 |
|
|
T1 |
192 |
|
T2 |
208 |
|
T3 |
18 |
lower_val |
184388 |
1 |
|
|
T1 |
186 |
|
T2 |
162 |
|
T3 |
12 |
zero_val |
154816 |
1 |
|
|
T1 |
170 |
|
T14 |
126 |
|
T34 |
308 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
27133 |
1 |
|
|
T1 |
22 |
|
T2 |
69 |
|
T3 |
6 |
higher_val |
higher_val |
auto[1] |
19134 |
1 |
|
|
T1 |
24 |
|
T14 |
11 |
|
T34 |
39 |
higher_val |
lower_val |
auto[0] |
26612 |
1 |
|
|
T1 |
12 |
|
T2 |
38 |
|
T3 |
1 |
higher_val |
lower_val |
auto[1] |
19537 |
1 |
|
|
T1 |
31 |
|
T14 |
25 |
|
T34 |
51 |
higher_val |
zero_val |
auto[0] |
88 |
1 |
|
|
T14 |
2 |
|
T48 |
1 |
|
T189 |
1 |
higher_val |
zero_val |
auto[1] |
38681 |
1 |
|
|
T1 |
34 |
|
T14 |
32 |
|
T34 |
74 |
lower_val |
higher_val |
auto[0] |
26887 |
1 |
|
|
T1 |
32 |
|
T2 |
42 |
|
T3 |
2 |
lower_val |
higher_val |
auto[1] |
19169 |
1 |
|
|
T1 |
19 |
|
T14 |
21 |
|
T34 |
43 |
lower_val |
lower_val |
auto[0] |
26641 |
1 |
|
|
T1 |
20 |
|
T2 |
36 |
|
T3 |
2 |
lower_val |
lower_val |
auto[1] |
18981 |
1 |
|
|
T1 |
12 |
|
T14 |
20 |
|
T34 |
38 |
lower_val |
zero_val |
auto[0] |
69 |
1 |
|
|
T14 |
1 |
|
T39 |
1 |
|
T190 |
1 |
lower_val |
zero_val |
auto[1] |
38314 |
1 |
|
|
T1 |
30 |
|
T14 |
32 |
|
T34 |
83 |
zero_val |
higher_val |
auto[0] |
461 |
1 |
|
|
T3 |
1 |
|
T14 |
4 |
|
T35 |
1 |
zero_val |
higher_val |
auto[1] |
114 |
1 |
|
|
T174 |
1 |
|
T191 |
1 |
|
T104 |
2 |
zero_val |
lower_val |
auto[0] |
482 |
1 |
|
|
T1 |
3 |
|
T2 |
1 |
|
T7 |
1 |
zero_val |
lower_val |
auto[1] |
124 |
1 |
|
|
T1 |
4 |
|
T14 |
2 |
|
T39 |
1 |
zero_val |
zero_val |
auto[0] |
247 |
1 |
|
|
T14 |
1 |
|
T64 |
1 |
|
T41 |
1 |
zero_val |
zero_val |
auto[1] |
171 |
1 |
|
|
T39 |
1 |
|
T190 |
1 |
|
T192 |
1 |