Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	79957376	1			T1	84193		T2	24417		T3	178
all_pins[1]	79957376	1			T1	84193		T2	24417		T3	178
all_pins[2]	79957376	1			T1	84193		T2	24417		T3	178

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	239189849	1			T1	252083		T2	73023		T3	513
values[0x1]	682279	1			T1	496		T2	228		T3	21
transitions[0x0=>0x1]	680186	1			T1	496		T2	228		T3	21
transitions[0x1=>0x0]	680208	1			T1	496		T2	228		T3	21

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	79576507	1			T1	83810		T2	24189		T3	157
all_pins[0]	values[0x1]	380869	1			T1	383		T2	228		T3	21
all_pins[0]	transitions[0x0=>0x1]	380853	1			T1	383		T2	228		T3	21
all_pins[0]	transitions[0x1=>0x0]	5828	1			T1	113		T7	37		T31	94
all_pins[1]	values[0x0]	79951532	1			T1	84080		T2	24417		T3	178
all_pins[1]	values[0x1]	5844	1			T1	113		T7	37		T31	94
all_pins[1]	transitions[0x0=>0x1]	5530	1			T1	113		T7	37		T31	94
all_pins[1]	transitions[0x1=>0x0]	295252	1			T7	646		T14	1514		T19	514
all_pins[2]	values[0x0]	79661810	1			T1	84193		T2	24417		T3	178
all_pins[2]	values[0x1]	295566	1			T7	646		T14	1518		T19	514
all_pins[2]	transitions[0x0=>0x1]	293803	1			T7	646		T14	1507		T19	514
all_pins[2]	transitions[0x1=>0x0]	379128	1			T1	383		T2	228		T3	21