Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9436604 |
1 |
|
|
T1 |
42027 |
|
T2 |
26606 |
|
T3 |
456 |
auto[1] |
9436550 |
1 |
|
|
T1 |
42027 |
|
T2 |
26606 |
|
T3 |
456 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
18698767 |
1 |
|
|
T1 |
83674 |
|
T2 |
53000 |
|
T3 |
890 |
triple_byte_access |
57863 |
1 |
|
|
T1 |
140 |
|
T2 |
74 |
|
T3 |
8 |
halfword_access |
58236 |
1 |
|
|
T1 |
136 |
|
T2 |
78 |
|
T3 |
6 |
byte_access |
58288 |
1 |
|
|
T1 |
104 |
|
T2 |
60 |
|
T3 |
8 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
9349410 |
1 |
|
|
T1 |
41837 |
|
T2 |
26500 |
|
T3 |
445 |
auto[0] |
triple_byte_access |
28932 |
1 |
|
|
T1 |
70 |
|
T2 |
37 |
|
T3 |
4 |
auto[0] |
halfword_access |
29118 |
1 |
|
|
T1 |
68 |
|
T2 |
39 |
|
T3 |
3 |
auto[0] |
byte_access |
29144 |
1 |
|
|
T1 |
52 |
|
T2 |
30 |
|
T3 |
4 |
auto[1] |
word_access |
9349357 |
1 |
|
|
T1 |
41837 |
|
T2 |
26500 |
|
T3 |
445 |
auto[1] |
triple_byte_access |
28931 |
1 |
|
|
T1 |
70 |
|
T2 |
37 |
|
T3 |
4 |
auto[1] |
halfword_access |
29118 |
1 |
|
|
T1 |
68 |
|
T2 |
39 |
|
T3 |
3 |
auto[1] |
byte_access |
29144 |
1 |
|
|
T1 |
52 |
|
T2 |
30 |
|
T3 |
4 |