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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.15 97.91 92.65 99.89 76.06 95.59 99.05 97.88


Total test records in report: 1202
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T132 /workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.3581400014 Aug 09 07:18:19 PM PDT 24 Aug 09 07:18:22 PM PDT 24 144967538 ps
T133 /workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.2415010038 Aug 09 07:18:19 PM PDT 24 Aug 09 07:18:23 PM PDT 24 179664147 ps
T148 /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.2502252773 Aug 09 07:18:11 PM PDT 24 Aug 09 07:18:14 PM PDT 24 71726633 ps
T170 /workspace/coverage/cover_reg_top/47.kmac_intr_test.982103223 Aug 09 07:18:29 PM PDT 24 Aug 09 07:18:30 PM PDT 24 28552123 ps
T88 /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.1778014053 Aug 09 07:18:10 PM PDT 24 Aug 09 07:18:11 PM PDT 24 26250071 ps
T149 /workspace/coverage/cover_reg_top/17.kmac_tl_errors.914714391 Aug 09 07:18:17 PM PDT 24 Aug 09 07:18:20 PM PDT 24 48300289 ps
T160 /workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.2776965682 Aug 09 07:18:01 PM PDT 24 Aug 09 07:18:04 PM PDT 24 199060094 ps
T89 /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.3018868096 Aug 09 07:17:48 PM PDT 24 Aug 09 07:17:50 PM PDT 24 24656996 ps
T1045 /workspace/coverage/cover_reg_top/15.kmac_csr_rw.3704073637 Aug 09 07:18:19 PM PDT 24 Aug 09 07:18:20 PM PDT 24 15969971 ps
T1046 /workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.1026757075 Aug 09 07:18:10 PM PDT 24 Aug 09 07:18:13 PM PDT 24 112776485 ps
T1047 /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.948731761 Aug 09 07:18:03 PM PDT 24 Aug 09 07:18:19 PM PDT 24 296659834 ps
T169 /workspace/coverage/cover_reg_top/6.kmac_intr_test.2870390623 Aug 09 07:18:00 PM PDT 24 Aug 09 07:18:01 PM PDT 24 35206644 ps
T164 /workspace/coverage/cover_reg_top/12.kmac_intr_test.3866637730 Aug 09 07:18:09 PM PDT 24 Aug 09 07:18:10 PM PDT 24 15249438 ps
T165 /workspace/coverage/cover_reg_top/11.kmac_intr_test.1887037597 Aug 09 07:18:12 PM PDT 24 Aug 09 07:18:13 PM PDT 24 51040566 ps
T161 /workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.2217022451 Aug 09 07:17:44 PM PDT 24 Aug 09 07:17:45 PM PDT 24 48992096 ps
T92 /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.957633711 Aug 09 07:17:47 PM PDT 24 Aug 09 07:17:49 PM PDT 24 542429755 ps
T166 /workspace/coverage/cover_reg_top/17.kmac_intr_test.3245462247 Aug 09 07:18:27 PM PDT 24 Aug 09 07:18:28 PM PDT 24 17923130 ps
T1048 /workspace/coverage/cover_reg_top/11.kmac_tl_errors.3209680590 Aug 09 07:18:12 PM PDT 24 Aug 09 07:18:15 PM PDT 24 49098866 ps
T1049 /workspace/coverage/cover_reg_top/4.kmac_tl_errors.541046484 Aug 09 07:18:00 PM PDT 24 Aug 09 07:18:02 PM PDT 24 27669065 ps
T1050 /workspace/coverage/cover_reg_top/12.kmac_tl_errors.1816210536 Aug 09 07:18:10 PM PDT 24 Aug 09 07:18:14 PM PDT 24 416133787 ps
T1051 /workspace/coverage/cover_reg_top/4.kmac_mem_walk.3617127620 Aug 09 07:18:00 PM PDT 24 Aug 09 07:18:01 PM PDT 24 42557682 ps
T1052 /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.651399343 Aug 09 07:18:18 PM PDT 24 Aug 09 07:18:21 PM PDT 24 129035887 ps
T90 /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.2724085756 Aug 09 07:18:16 PM PDT 24 Aug 09 07:18:18 PM PDT 24 62770411 ps
T91 /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.1860937332 Aug 09 07:17:43 PM PDT 24 Aug 09 07:17:45 PM PDT 24 34603624 ps
T1053 /workspace/coverage/cover_reg_top/3.kmac_intr_test.2116477370 Aug 09 07:18:04 PM PDT 24 Aug 09 07:18:05 PM PDT 24 27748151 ps
T1054 /workspace/coverage/cover_reg_top/0.kmac_mem_walk.1232942123 Aug 09 07:17:39 PM PDT 24 Aug 09 07:17:40 PM PDT 24 37480876 ps
T1055 /workspace/coverage/cover_reg_top/7.kmac_intr_test.3837295497 Aug 09 07:18:05 PM PDT 24 Aug 09 07:18:05 PM PDT 24 16901586 ps
T1056 /workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.1971487881 Aug 09 07:18:03 PM PDT 24 Aug 09 07:18:06 PM PDT 24 60933015 ps
T1057 /workspace/coverage/cover_reg_top/33.kmac_intr_test.2278822458 Aug 09 07:18:29 PM PDT 24 Aug 09 07:18:30 PM PDT 24 14873187 ps
T93 /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.975374248 Aug 09 07:18:27 PM PDT 24 Aug 09 07:18:29 PM PDT 24 111858603 ps
T162 /workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.2534547305 Aug 09 07:18:00 PM PDT 24 Aug 09 07:18:01 PM PDT 24 132882824 ps
T163 /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.1479221681 Aug 09 07:18:25 PM PDT 24 Aug 09 07:18:28 PM PDT 24 286939599 ps
T178 /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.2856907141 Aug 09 07:18:26 PM PDT 24 Aug 09 07:18:31 PM PDT 24 231781616 ps
T1058 /workspace/coverage/cover_reg_top/45.kmac_intr_test.336388459 Aug 09 07:18:27 PM PDT 24 Aug 09 07:18:28 PM PDT 24 38926380 ps
T1059 /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.1631401025 Aug 09 07:17:46 PM PDT 24 Aug 09 07:17:49 PM PDT 24 1326496568 ps
T101 /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.3792639576 Aug 09 07:18:03 PM PDT 24 Aug 09 07:18:04 PM PDT 24 163985650 ps
T1060 /workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.3898108373 Aug 09 07:18:02 PM PDT 24 Aug 09 07:18:03 PM PDT 24 30791062 ps
T102 /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.4262389491 Aug 09 07:18:20 PM PDT 24 Aug 09 07:18:22 PM PDT 24 72345887 ps
T1061 /workspace/coverage/cover_reg_top/48.kmac_intr_test.1443141040 Aug 09 07:18:36 PM PDT 24 Aug 09 07:18:37 PM PDT 24 107331276 ps
T1062 /workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.3179210680 Aug 09 07:18:26 PM PDT 24 Aug 09 07:18:29 PM PDT 24 361368874 ps
T1063 /workspace/coverage/cover_reg_top/16.kmac_intr_test.222381716 Aug 09 07:18:20 PM PDT 24 Aug 09 07:18:21 PM PDT 24 25313629 ps
T1064 /workspace/coverage/cover_reg_top/14.kmac_intr_test.1331522410 Aug 09 07:18:18 PM PDT 24 Aug 09 07:18:19 PM PDT 24 22905907 ps
T1065 /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.3608354028 Aug 09 07:18:18 PM PDT 24 Aug 09 07:18:21 PM PDT 24 139159678 ps
T188 /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.2498808745 Aug 09 07:17:38 PM PDT 24 Aug 09 07:17:39 PM PDT 24 29033542 ps
T1066 /workspace/coverage/cover_reg_top/17.kmac_csr_rw.2260044140 Aug 09 07:18:34 PM PDT 24 Aug 09 07:18:35 PM PDT 24 17365909 ps
T1067 /workspace/coverage/cover_reg_top/0.kmac_tl_errors.1967869594 Aug 09 07:17:43 PM PDT 24 Aug 09 07:17:46 PM PDT 24 72981485 ps
T167 /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.2650209703 Aug 09 07:17:43 PM PDT 24 Aug 09 07:17:44 PM PDT 24 79336088 ps
T1068 /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.144580219 Aug 09 07:18:07 PM PDT 24 Aug 09 07:18:08 PM PDT 24 31269794 ps
T1069 /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.871331544 Aug 09 07:18:06 PM PDT 24 Aug 09 07:18:09 PM PDT 24 105174918 ps
T179 /workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.1295813474 Aug 09 07:17:59 PM PDT 24 Aug 09 07:18:05 PM PDT 24 428784856 ps
T98 /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.3047630073 Aug 09 07:18:20 PM PDT 24 Aug 09 07:18:21 PM PDT 24 50063566 ps
T1070 /workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.3634076031 Aug 09 07:18:04 PM PDT 24 Aug 09 07:18:07 PM PDT 24 126471146 ps
T1071 /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.3909800657 Aug 09 07:17:43 PM PDT 24 Aug 09 07:17:45 PM PDT 24 36481869 ps
T1072 /workspace/coverage/cover_reg_top/12.kmac_csr_rw.1823805164 Aug 09 07:18:13 PM PDT 24 Aug 09 07:18:14 PM PDT 24 27210920 ps
T1073 /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.4078624805 Aug 09 07:18:12 PM PDT 24 Aug 09 07:18:13 PM PDT 24 51175039 ps
T99 /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.2320769287 Aug 09 07:18:11 PM PDT 24 Aug 09 07:18:12 PM PDT 24 69974833 ps
T1074 /workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.1605246537 Aug 09 07:18:10 PM PDT 24 Aug 09 07:18:12 PM PDT 24 24217724 ps
T1075 /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.303674569 Aug 09 07:17:45 PM PDT 24 Aug 09 07:17:57 PM PDT 24 3004461204 ps
T1076 /workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.1360350140 Aug 09 07:18:03 PM PDT 24 Aug 09 07:18:05 PM PDT 24 609271384 ps
T1077 /workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.1142450852 Aug 09 07:18:24 PM PDT 24 Aug 09 07:18:26 PM PDT 24 46630470 ps
T1078 /workspace/coverage/cover_reg_top/14.kmac_csr_rw.1227191551 Aug 09 07:18:19 PM PDT 24 Aug 09 07:18:20 PM PDT 24 43883908 ps
T94 /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.319671146 Aug 09 07:18:27 PM PDT 24 Aug 09 07:18:30 PM PDT 24 149629061 ps
T1079 /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.129817034 Aug 09 07:17:48 PM PDT 24 Aug 09 07:17:58 PM PDT 24 509915416 ps
T1080 /workspace/coverage/cover_reg_top/10.kmac_csr_rw.1249865416 Aug 09 07:18:09 PM PDT 24 Aug 09 07:18:10 PM PDT 24 98637579 ps
T1081 /workspace/coverage/cover_reg_top/27.kmac_intr_test.1216417734 Aug 09 07:18:29 PM PDT 24 Aug 09 07:18:30 PM PDT 24 13588152 ps
T1082 /workspace/coverage/cover_reg_top/14.kmac_tl_errors.4258391931 Aug 09 07:18:18 PM PDT 24 Aug 09 07:18:21 PM PDT 24 304353274 ps
T1083 /workspace/coverage/cover_reg_top/34.kmac_intr_test.3821280546 Aug 09 07:18:25 PM PDT 24 Aug 09 07:18:25 PM PDT 24 124554825 ps
T1084 /workspace/coverage/cover_reg_top/35.kmac_intr_test.2438556658 Aug 09 07:18:26 PM PDT 24 Aug 09 07:18:28 PM PDT 24 40799880 ps
T1085 /workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.1146957615 Aug 09 07:18:11 PM PDT 24 Aug 09 07:18:12 PM PDT 24 114730374 ps
T100 /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.1493079459 Aug 09 07:18:26 PM PDT 24 Aug 09 07:18:28 PM PDT 24 71934335 ps
T1086 /workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.1606529794 Aug 09 07:17:59 PM PDT 24 Aug 09 07:18:07 PM PDT 24 137754979 ps
T176 /workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.3481867852 Aug 09 07:18:02 PM PDT 24 Aug 09 07:18:05 PM PDT 24 473267565 ps
T1087 /workspace/coverage/cover_reg_top/10.kmac_intr_test.4060181762 Aug 09 07:18:12 PM PDT 24 Aug 09 07:18:13 PM PDT 24 48281394 ps
T95 /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.2320204361 Aug 09 07:18:05 PM PDT 24 Aug 09 07:18:07 PM PDT 24 63232139 ps
T96 /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.3935498022 Aug 09 07:18:01 PM PDT 24 Aug 09 07:18:02 PM PDT 24 59865100 ps
T1088 /workspace/coverage/cover_reg_top/37.kmac_intr_test.1739326518 Aug 09 07:18:30 PM PDT 24 Aug 09 07:18:31 PM PDT 24 47376738 ps
T1089 /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.2870404761 Aug 09 07:18:01 PM PDT 24 Aug 09 07:18:03 PM PDT 24 101532392 ps
T1090 /workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.1983285223 Aug 09 07:18:02 PM PDT 24 Aug 09 07:18:04 PM PDT 24 50550181 ps
T1091 /workspace/coverage/cover_reg_top/29.kmac_intr_test.994637154 Aug 09 07:18:29 PM PDT 24 Aug 09 07:18:30 PM PDT 24 35934177 ps
T1092 /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.2014527178 Aug 09 07:18:25 PM PDT 24 Aug 09 07:18:27 PM PDT 24 198025888 ps
T1093 /workspace/coverage/cover_reg_top/0.kmac_intr_test.2116294730 Aug 09 07:17:37 PM PDT 24 Aug 09 07:17:37 PM PDT 24 27223308 ps
T1094 /workspace/coverage/cover_reg_top/39.kmac_intr_test.4248517259 Aug 09 07:18:30 PM PDT 24 Aug 09 07:18:31 PM PDT 24 16829186 ps
T180 /workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.3221796391 Aug 09 07:18:01 PM PDT 24 Aug 09 07:18:08 PM PDT 24 4658209269 ps
T1095 /workspace/coverage/cover_reg_top/16.kmac_csr_rw.4078238000 Aug 09 07:18:17 PM PDT 24 Aug 09 07:18:19 PM PDT 24 161027930 ps
T1096 /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.2184031758 Aug 09 07:18:02 PM PDT 24 Aug 09 07:18:05 PM PDT 24 139238192 ps
T1097 /workspace/coverage/cover_reg_top/21.kmac_intr_test.2302292586 Aug 09 07:18:27 PM PDT 24 Aug 09 07:18:28 PM PDT 24 31693082 ps
T1098 /workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.1943087368 Aug 09 07:18:18 PM PDT 24 Aug 09 07:18:20 PM PDT 24 82733445 ps
T1099 /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.725926356 Aug 09 07:18:09 PM PDT 24 Aug 09 07:18:12 PM PDT 24 104172436 ps
T1100 /workspace/coverage/cover_reg_top/11.kmac_csr_rw.2022829156 Aug 09 07:18:10 PM PDT 24 Aug 09 07:18:11 PM PDT 24 15578486 ps
T1101 /workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.652593646 Aug 09 07:18:25 PM PDT 24 Aug 09 07:18:26 PM PDT 24 110215902 ps
T1102 /workspace/coverage/cover_reg_top/9.kmac_tl_errors.2283647363 Aug 09 07:18:07 PM PDT 24 Aug 09 07:18:09 PM PDT 24 59600876 ps
T1103 /workspace/coverage/cover_reg_top/41.kmac_intr_test.1010113335 Aug 09 07:18:27 PM PDT 24 Aug 09 07:18:28 PM PDT 24 22551125 ps
T1104 /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.4045629549 Aug 09 07:17:35 PM PDT 24 Aug 09 07:17:37 PM PDT 24 40430917 ps
T1105 /workspace/coverage/cover_reg_top/5.kmac_csr_rw.3320099529 Aug 09 07:18:01 PM PDT 24 Aug 09 07:18:02 PM PDT 24 39946751 ps
T1106 /workspace/coverage/cover_reg_top/18.kmac_tl_errors.3771023270 Aug 09 07:18:28 PM PDT 24 Aug 09 07:18:30 PM PDT 24 217741112 ps
T1107 /workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.628464062 Aug 09 07:18:03 PM PDT 24 Aug 09 07:18:05 PM PDT 24 76115162 ps
T1108 /workspace/coverage/cover_reg_top/30.kmac_intr_test.1995119332 Aug 09 07:18:36 PM PDT 24 Aug 09 07:18:37 PM PDT 24 46995478 ps
T1109 /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.2304807690 Aug 09 07:18:01 PM PDT 24 Aug 09 07:18:02 PM PDT 24 45268151 ps
T1110 /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.328815544 Aug 09 07:18:18 PM PDT 24 Aug 09 07:18:21 PM PDT 24 137059825 ps
T1111 /workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.3665898943 Aug 09 07:18:22 PM PDT 24 Aug 09 07:18:24 PM PDT 24 39162254 ps
T177 /workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.2010536819 Aug 09 07:18:26 PM PDT 24 Aug 09 07:18:30 PM PDT 24 111462831 ps
T1112 /workspace/coverage/cover_reg_top/42.kmac_intr_test.3473913018 Aug 09 07:18:29 PM PDT 24 Aug 09 07:18:30 PM PDT 24 93956692 ps
T1113 /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.1357345072 Aug 09 07:18:16 PM PDT 24 Aug 09 07:18:18 PM PDT 24 172316857 ps
T1114 /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.3154088354 Aug 09 07:17:43 PM PDT 24 Aug 09 07:17:45 PM PDT 24 132285543 ps
T1115 /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.1185375639 Aug 09 07:18:07 PM PDT 24 Aug 09 07:18:09 PM PDT 24 446214316 ps
T1116 /workspace/coverage/cover_reg_top/19.kmac_intr_test.3222820618 Aug 09 07:18:27 PM PDT 24 Aug 09 07:18:28 PM PDT 24 175747145 ps
T1117 /workspace/coverage/cover_reg_top/5.kmac_intr_test.1682012013 Aug 09 07:18:00 PM PDT 24 Aug 09 07:18:01 PM PDT 24 22945938 ps
T1118 /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.1290085345 Aug 09 07:18:12 PM PDT 24 Aug 09 07:18:14 PM PDT 24 194730865 ps
T1119 /workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.4280454471 Aug 09 07:17:46 PM PDT 24 Aug 09 07:17:47 PM PDT 24 66669886 ps
T1120 /workspace/coverage/cover_reg_top/23.kmac_intr_test.2546440153 Aug 09 07:18:26 PM PDT 24 Aug 09 07:18:27 PM PDT 24 55039407 ps
T1121 /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.1816266916 Aug 09 07:18:18 PM PDT 24 Aug 09 07:18:20 PM PDT 24 40473195 ps
T1122 /workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.2535647380 Aug 09 07:17:46 PM PDT 24 Aug 09 07:17:48 PM PDT 24 141390298 ps
T185 /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.3304602725 Aug 09 07:18:19 PM PDT 24 Aug 09 07:18:24 PM PDT 24 226542478 ps
T1123 /workspace/coverage/cover_reg_top/44.kmac_intr_test.2241033194 Aug 09 07:18:29 PM PDT 24 Aug 09 07:18:30 PM PDT 24 16367264 ps
T1124 /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.2570186098 Aug 09 07:17:38 PM PDT 24 Aug 09 07:17:40 PM PDT 24 146225316 ps
T1125 /workspace/coverage/cover_reg_top/38.kmac_intr_test.1758478611 Aug 09 07:18:26 PM PDT 24 Aug 09 07:18:27 PM PDT 24 16331155 ps
T1126 /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.158608853 Aug 09 07:18:18 PM PDT 24 Aug 09 07:18:20 PM PDT 24 46423056 ps
T1127 /workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.4240764399 Aug 09 07:18:25 PM PDT 24 Aug 09 07:18:28 PM PDT 24 267116732 ps
T1128 /workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.2142127645 Aug 09 07:17:46 PM PDT 24 Aug 09 07:17:51 PM PDT 24 2608966912 ps
T1129 /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.2119274328 Aug 09 07:18:20 PM PDT 24 Aug 09 07:18:22 PM PDT 24 61201997 ps
T97 /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.2566470270 Aug 09 07:18:11 PM PDT 24 Aug 09 07:18:13 PM PDT 24 26453410 ps
T1130 /workspace/coverage/cover_reg_top/2.kmac_mem_walk.3467508754 Aug 09 07:17:44 PM PDT 24 Aug 09 07:17:45 PM PDT 24 13524983 ps
T1131 /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.2203888592 Aug 09 07:18:14 PM PDT 24 Aug 09 07:18:16 PM PDT 24 90529286 ps
T1132 /workspace/coverage/cover_reg_top/1.kmac_csr_rw.235540788 Aug 09 07:17:44 PM PDT 24 Aug 09 07:17:45 PM PDT 24 22473628 ps
T1133 /workspace/coverage/cover_reg_top/9.kmac_intr_test.3331180212 Aug 09 07:18:03 PM PDT 24 Aug 09 07:18:04 PM PDT 24 47068251 ps
T1134 /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.1106244087 Aug 09 07:18:16 PM PDT 24 Aug 09 07:18:19 PM PDT 24 170779855 ps
T1135 /workspace/coverage/cover_reg_top/13.kmac_intr_test.3618763921 Aug 09 07:18:27 PM PDT 24 Aug 09 07:18:29 PM PDT 24 42302460 ps
T1136 /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.530457576 Aug 09 07:17:43 PM PDT 24 Aug 09 07:17:44 PM PDT 24 69531022 ps
T1137 /workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.944790403 Aug 09 07:17:48 PM PDT 24 Aug 09 07:17:50 PM PDT 24 42623956 ps
T1138 /workspace/coverage/cover_reg_top/6.kmac_tl_errors.3303345541 Aug 09 07:17:58 PM PDT 24 Aug 09 07:18:02 PM PDT 24 587369599 ps
T1139 /workspace/coverage/cover_reg_top/13.kmac_tl_errors.4007273147 Aug 09 07:18:10 PM PDT 24 Aug 09 07:18:14 PM PDT 24 488731822 ps
T1140 /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.26953164 Aug 09 07:18:18 PM PDT 24 Aug 09 07:18:21 PM PDT 24 197038978 ps
T1141 /workspace/coverage/cover_reg_top/16.kmac_tl_errors.2653281830 Aug 09 07:18:27 PM PDT 24 Aug 09 07:18:31 PM PDT 24 52384971 ps
T1142 /workspace/coverage/cover_reg_top/18.kmac_csr_rw.1554782444 Aug 09 07:18:25 PM PDT 24 Aug 09 07:18:26 PM PDT 24 33432679 ps
T1143 /workspace/coverage/cover_reg_top/6.kmac_csr_rw.3144087868 Aug 09 07:18:01 PM PDT 24 Aug 09 07:18:02 PM PDT 24 72408621 ps
T1144 /workspace/coverage/cover_reg_top/31.kmac_intr_test.1389947156 Aug 09 07:18:29 PM PDT 24 Aug 09 07:18:30 PM PDT 24 20623533 ps
T1145 /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.3087802809 Aug 09 07:18:27 PM PDT 24 Aug 09 07:18:29 PM PDT 24 77170509 ps
T1146 /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.2455506033 Aug 09 07:18:01 PM PDT 24 Aug 09 07:18:11 PM PDT 24 1522930954 ps
T1147 /workspace/coverage/cover_reg_top/20.kmac_intr_test.1996801409 Aug 09 07:18:27 PM PDT 24 Aug 09 07:18:28 PM PDT 24 61253331 ps
T182 /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.857362039 Aug 09 07:18:08 PM PDT 24 Aug 09 07:18:13 PM PDT 24 898959259 ps
T1148 /workspace/coverage/cover_reg_top/49.kmac_intr_test.3867991920 Aug 09 07:18:27 PM PDT 24 Aug 09 07:18:28 PM PDT 24 17397569 ps
T1149 /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.2134711796 Aug 09 07:17:43 PM PDT 24 Aug 09 07:17:46 PM PDT 24 102222642 ps
T186 /workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.1612081234 Aug 09 07:18:09 PM PDT 24 Aug 09 07:18:13 PM PDT 24 592128563 ps
T1150 /workspace/coverage/cover_reg_top/18.kmac_intr_test.1279872257 Aug 09 07:18:25 PM PDT 24 Aug 09 07:18:26 PM PDT 24 12441489 ps
T1151 /workspace/coverage/cover_reg_top/22.kmac_intr_test.706407682 Aug 09 07:18:29 PM PDT 24 Aug 09 07:18:30 PM PDT 24 22171205 ps
T181 /workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.1608202341 Aug 09 07:17:38 PM PDT 24 Aug 09 07:17:43 PM PDT 24 931951257 ps
T1152 /workspace/coverage/cover_reg_top/25.kmac_intr_test.3981987117 Aug 09 07:18:29 PM PDT 24 Aug 09 07:18:30 PM PDT 24 48795592 ps
T1153 /workspace/coverage/cover_reg_top/15.kmac_tl_errors.2780683145 Aug 09 07:18:18 PM PDT 24 Aug 09 07:18:21 PM PDT 24 101498925 ps
T1154 /workspace/coverage/cover_reg_top/2.kmac_tl_errors.2752197381 Aug 09 07:17:45 PM PDT 24 Aug 09 07:17:47 PM PDT 24 119126387 ps
T1155 /workspace/coverage/cover_reg_top/3.kmac_mem_walk.3241677651 Aug 09 07:17:46 PM PDT 24 Aug 09 07:17:47 PM PDT 24 37114731 ps
T1156 /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.583608549 Aug 09 07:17:43 PM PDT 24 Aug 09 07:17:49 PM PDT 24 279050626 ps
T1157 /workspace/coverage/cover_reg_top/0.kmac_csr_rw.3986583390 Aug 09 07:17:34 PM PDT 24 Aug 09 07:17:36 PM PDT 24 48555626 ps
T1158 /workspace/coverage/cover_reg_top/8.kmac_csr_rw.3358961075 Aug 09 07:18:04 PM PDT 24 Aug 09 07:18:05 PM PDT 24 22902458 ps
T1159 /workspace/coverage/cover_reg_top/1.kmac_tl_errors.1988416415 Aug 09 07:17:43 PM PDT 24 Aug 09 07:17:46 PM PDT 24 110464420 ps
T1160 /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.206316735 Aug 09 07:18:05 PM PDT 24 Aug 09 07:18:06 PM PDT 24 34177246 ps
T1161 /workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.1410483384 Aug 09 07:17:58 PM PDT 24 Aug 09 07:18:01 PM PDT 24 451047702 ps
T1162 /workspace/coverage/cover_reg_top/19.kmac_csr_rw.2987545833 Aug 09 07:18:27 PM PDT 24 Aug 09 07:18:29 PM PDT 24 20555055 ps
T1163 /workspace/coverage/cover_reg_top/4.kmac_intr_test.1414234022 Aug 09 07:18:00 PM PDT 24 Aug 09 07:18:01 PM PDT 24 20495216 ps
T175 /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.2019995065 Aug 09 07:18:18 PM PDT 24 Aug 09 07:18:21 PM PDT 24 252834399 ps
T1164 /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.3237140084 Aug 09 07:18:18 PM PDT 24 Aug 09 07:18:19 PM PDT 24 210381692 ps
T1165 /workspace/coverage/cover_reg_top/2.kmac_csr_rw.195197110 Aug 09 07:17:45 PM PDT 24 Aug 09 07:17:46 PM PDT 24 40913781 ps
T151 /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.12375428 Aug 09 07:17:45 PM PDT 24 Aug 09 07:17:47 PM PDT 24 19715236 ps
T1166 /workspace/coverage/cover_reg_top/1.kmac_intr_test.1506188186 Aug 09 07:17:45 PM PDT 24 Aug 09 07:17:46 PM PDT 24 19760968 ps
T1167 /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.2022369317 Aug 09 07:18:26 PM PDT 24 Aug 09 07:18:28 PM PDT 24 56390103 ps
T1168 /workspace/coverage/cover_reg_top/9.kmac_csr_rw.676232511 Aug 09 07:18:05 PM PDT 24 Aug 09 07:18:06 PM PDT 24 33100634 ps
T1169 /workspace/coverage/cover_reg_top/7.kmac_tl_errors.2473194368 Aug 09 07:18:04 PM PDT 24 Aug 09 07:18:08 PM PDT 24 1908075553 ps
T1170 /workspace/coverage/cover_reg_top/8.kmac_tl_errors.2988227454 Aug 09 07:18:05 PM PDT 24 Aug 09 07:18:09 PM PDT 24 59786792 ps
T1171 /workspace/coverage/cover_reg_top/26.kmac_intr_test.3101747879 Aug 09 07:18:25 PM PDT 24 Aug 09 07:18:26 PM PDT 24 42625400 ps
T1172 /workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.542033598 Aug 09 07:17:59 PM PDT 24 Aug 09 07:18:10 PM PDT 24 743547894 ps
T1173 /workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.3733285891 Aug 09 07:17:45 PM PDT 24 Aug 09 07:17:48 PM PDT 24 123126075 ps
T1174 /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.2550884790 Aug 09 07:18:00 PM PDT 24 Aug 09 07:18:01 PM PDT 24 35387565 ps
T1175 /workspace/coverage/cover_reg_top/24.kmac_intr_test.823222181 Aug 09 07:18:36 PM PDT 24 Aug 09 07:18:37 PM PDT 24 39405212 ps
T1176 /workspace/coverage/cover_reg_top/15.kmac_intr_test.805663768 Aug 09 07:18:19 PM PDT 24 Aug 09 07:18:20 PM PDT 24 19143029 ps
T1177 /workspace/coverage/cover_reg_top/13.kmac_csr_rw.3385267108 Aug 09 07:18:22 PM PDT 24 Aug 09 07:18:24 PM PDT 24 30240615 ps
T1178 /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.2302635163 Aug 09 07:18:04 PM PDT 24 Aug 09 07:18:07 PM PDT 24 107845265 ps
T1179 /workspace/coverage/cover_reg_top/3.kmac_tl_errors.3554555637 Aug 09 07:17:45 PM PDT 24 Aug 09 07:17:46 PM PDT 24 47985295 ps
T1180 /workspace/coverage/cover_reg_top/1.kmac_mem_walk.1185566731 Aug 09 07:17:49 PM PDT 24 Aug 09 07:17:50 PM PDT 24 84987491 ps
T1181 /workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.3160979617 Aug 09 07:18:04 PM PDT 24 Aug 09 07:18:08 PM PDT 24 177893081 ps
T1182 /workspace/coverage/cover_reg_top/7.kmac_csr_rw.1184503057 Aug 09 07:18:02 PM PDT 24 Aug 09 07:18:03 PM PDT 24 31416029 ps
T1183 /workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.2895863224 Aug 09 07:17:46 PM PDT 24 Aug 09 07:17:57 PM PDT 24 775026846 ps
T1184 /workspace/coverage/cover_reg_top/8.kmac_intr_test.4282629740 Aug 09 07:18:05 PM PDT 24 Aug 09 07:18:06 PM PDT 24 52015162 ps
T152 /workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.3432789627 Aug 09 07:18:02 PM PDT 24 Aug 09 07:18:04 PM PDT 24 74289117 ps
T1185 /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.1700076642 Aug 09 07:18:03 PM PDT 24 Aug 09 07:18:09 PM PDT 24 230327724 ps
T1186 /workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.2432472178 Aug 09 07:18:27 PM PDT 24 Aug 09 07:18:30 PM PDT 24 263415412 ps
T1187 /workspace/coverage/cover_reg_top/4.kmac_csr_rw.613256220 Aug 09 07:17:58 PM PDT 24 Aug 09 07:18:00 PM PDT 24 28189111 ps
T1188 /workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.2558956986 Aug 09 07:18:03 PM PDT 24 Aug 09 07:18:05 PM PDT 24 24255960 ps
T1189 /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.2991681572 Aug 09 07:17:43 PM PDT 24 Aug 09 07:17:59 PM PDT 24 1171455901 ps
T1190 /workspace/coverage/cover_reg_top/28.kmac_intr_test.1367702525 Aug 09 07:18:26 PM PDT 24 Aug 09 07:18:27 PM PDT 24 14057693 ps
T1191 /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.3477830453 Aug 09 07:18:22 PM PDT 24 Aug 09 07:18:24 PM PDT 24 594431859 ps
T1192 /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.2568828531 Aug 09 07:17:58 PM PDT 24 Aug 09 07:18:01 PM PDT 24 127907498 ps
T1193 /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.1858166289 Aug 09 07:17:35 PM PDT 24 Aug 09 07:17:37 PM PDT 24 106736840 ps
T1194 /workspace/coverage/cover_reg_top/43.kmac_intr_test.469989306 Aug 09 07:18:26 PM PDT 24 Aug 09 07:18:26 PM PDT 24 14775387 ps
T1195 /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.3655086577 Aug 09 07:18:22 PM PDT 24 Aug 09 07:18:24 PM PDT 24 176729301 ps
T1196 /workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.172399159 Aug 09 07:17:59 PM PDT 24 Aug 09 07:18:02 PM PDT 24 348907799 ps
T1197 /workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.2617123746 Aug 09 07:17:44 PM PDT 24 Aug 09 07:17:46 PM PDT 24 1030970633 ps
T183 /workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.498519814 Aug 09 07:17:44 PM PDT 24 Aug 09 07:17:49 PM PDT 24 1645862320 ps
T1198 /workspace/coverage/cover_reg_top/46.kmac_intr_test.1485508538 Aug 09 07:18:36 PM PDT 24 Aug 09 07:18:37 PM PDT 24 21834325 ps
T1199 /workspace/coverage/cover_reg_top/40.kmac_intr_test.3065820834 Aug 09 07:18:26 PM PDT 24 Aug 09 07:18:27 PM PDT 24 22089294 ps
T184 /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.739619575 Aug 09 07:18:10 PM PDT 24 Aug 09 07:18:15 PM PDT 24 745291596 ps
T1200 /workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.2986504208 Aug 09 07:18:01 PM PDT 24 Aug 09 07:18:04 PM PDT 24 489366164 ps
T1201 /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.3420983566 Aug 09 07:18:11 PM PDT 24 Aug 09 07:18:13 PM PDT 24 307000670 ps
T1202 /workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.3510041512 Aug 09 07:17:47 PM PDT 24 Aug 09 07:17:48 PM PDT 24 31789905 ps

Test location /workspace/coverage/default/49.kmac_stress_all.3708249302
Short name T14
Test name
Test status
Simulation time 11860461787 ps
CPU time 1053.08 seconds
Started Aug 09 06:05:07 PM PDT 24
Finished Aug 09 06:22:40 PM PDT 24
Peak memory 339072 kb
Host smart-423f654e-f38e-41e7-b501-5a11ee22c4d1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3708249302 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.3708249302 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.125682054
Short name T131
Test name
Test status
Simulation time 843040502 ps
CPU time 2.96 seconds
Started Aug 09 07:17:59 PM PDT 24
Finished Aug 09 07:18:02 PM PDT 24
Peak memory 216556 kb
Host smart-030347d7-4f6b-4fb1-9bc8-a54742895b8f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125682054 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.125682
054 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/2.kmac_sec_cm.2249926457
Short name T27
Test name
Test status
Simulation time 3450764224 ps
CPU time 44.93 seconds
Started Aug 09 05:53:35 PM PDT 24
Finished Aug 09 05:54:20 PM PDT 24
Peak memory 257012 kb
Host smart-afaedfa8-3cfe-4527-aa2e-37aed4b8069a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249926457 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.2249926457 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspace/2.kmac_sec_cm/latest

Test location /workspace/coverage/default/3.kmac_stress_all_with_rand_reset.2938009377
Short name T16
Test name
Test status
Simulation time 77473574129 ps
CPU time 382.09 seconds
Started Aug 09 05:53:47 PM PDT 24
Finished Aug 09 06:00:09 PM PDT 24
Peak memory 418684 kb
Host smart-6d43529c-49db-4301-aec5-52be23f94358
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2938009377 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all_with_rand_reset.2938009377 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.kmac_lc_escalation.2134694217
Short name T49
Test name
Test status
Simulation time 117338154 ps
CPU time 1.29 seconds
Started Aug 09 05:53:54 PM PDT 24
Finished Aug 09 05:53:56 PM PDT 24
Peak memory 226836 kb
Host smart-503a2c5c-4676-4a36-830f-1c2ee7f1241e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134694217 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.2134694217 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/6.kmac_lc_escalation/latest

Test location /workspace/coverage/default/11.kmac_key_error.1827508198
Short name T5
Test name
Test status
Simulation time 168377383 ps
CPU time 1.32 seconds
Started Aug 09 05:54:02 PM PDT 24
Finished Aug 09 05:54:04 PM PDT 24
Peak memory 226528 kb
Host smart-d9d25d2c-4409-4b1f-8192-5a3a65280932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827508198 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.1827508198 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_key_error/latest

Test location /workspace/coverage/default/12.kmac_error.2915476417
Short name T19
Test name
Test status
Simulation time 20664492380 ps
CPU time 432.78 seconds
Started Aug 09 05:54:09 PM PDT 24
Finished Aug 09 06:01:22 PM PDT 24
Peak memory 377896 kb
Host smart-544c3878-ae15-4a7a-bd6e-4985297d9cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915476417 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.2915476417 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_error/latest

Test location /workspace/coverage/default/0.kmac_lc_escalation.2469657667
Short name T51
Test name
Test status
Simulation time 29172873 ps
CPU time 1.32 seconds
Started Aug 09 05:53:25 PM PDT 24
Finished Aug 09 05:53:26 PM PDT 24
Peak memory 226872 kb
Host smart-bac964bd-5f6e-4ddb-9134-e1b00c5dbd21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469657667 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.2469657667 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/0.kmac_lc_escalation/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.975374248
Short name T93
Test name
Test status
Simulation time 111858603 ps
CPU time 1.18 seconds
Started Aug 09 07:18:27 PM PDT 24
Finished Aug 09 07:18:29 PM PDT 24
Peak memory 217792 kb
Host smart-ee96946d-1666-4763-be8a-ccf1d7d2de2a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975374248 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_
errors.975374248 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/default/1.kmac_entropy_ready_error.1036719798
Short name T173
Test name
Test status
Simulation time 13706387559 ps
CPU time 70.89 seconds
Started Aug 09 05:53:32 PM PDT 24
Finished Aug 09 05:54:43 PM PDT 24
Peak memory 224548 kb
Host smart-f5a80555-ea43-4eb9-98cc-9bfab8e55fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036719798 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.1036719798 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_ready_error/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_intr_test.2116477370
Short name T1053
Test name
Test status
Simulation time 27748151 ps
CPU time 0.81 seconds
Started Aug 09 07:18:04 PM PDT 24
Finished Aug 09 07:18:05 PM PDT 24
Peak memory 216356 kb
Host smart-a1ebfd97-e5ce-423c-95cb-a683482db700
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116477370 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.2116477370 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_intr_test/latest

Test location /workspace/coverage/default/0.kmac_edn_timeout_error.3205802756
Short name T40
Test name
Test status
Simulation time 67713863 ps
CPU time 1.27 seconds
Started Aug 09 05:53:23 PM PDT 24
Finished Aug 09 05:53:25 PM PDT 24
Peak memory 218552 kb
Host smart-c3bf7808-d4a3-4b99-885f-98baf5621673
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3205802756 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.3205802756 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/10.kmac_lc_escalation.3781008527
Short name T10
Test name
Test status
Simulation time 59155841 ps
CPU time 1.31 seconds
Started Aug 09 05:54:10 PM PDT 24
Finished Aug 09 05:54:11 PM PDT 24
Peak memory 226956 kb
Host smart-8d60727a-95f7-4233-a674-b795cc9ab32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781008527 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.3781008527 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/10.kmac_lc_escalation/latest

Test location /workspace/coverage/default/37.kmac_lc_escalation.3880615048
Short name T45
Test name
Test status
Simulation time 1499065925 ps
CPU time 13.8 seconds
Started Aug 09 06:00:01 PM PDT 24
Finished Aug 09 06:00:19 PM PDT 24
Peak memory 236308 kb
Host smart-0bbeaf3d-472a-4e19-8276-9bec61c2f436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880615048 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.3880615048 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/37.kmac_lc_escalation/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_shake_256.3177507789
Short name T190
Test name
Test status
Simulation time 599438376174 ps
CPU time 10082.6 seconds
Started Aug 09 06:01:19 PM PDT 24
Finished Aug 09 08:49:23 PM PDT 24
Peak memory 6320264 kb
Host smart-e3a034a7-90f7-49cb-bfa2-3c15aa5767cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3177507789 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_256.3177507789 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/1.kmac_entropy_mode_error.1034516155
Short name T79
Test name
Test status
Simulation time 37238445 ps
CPU time 1.01 seconds
Started Aug 09 05:53:39 PM PDT 24
Finished Aug 09 05:53:40 PM PDT 24
Peak memory 220528 kb
Host smart-b23036c9-19a7-4d24-8a9a-2a3fa7430053
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1034516155 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.1034516155 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/28.kmac_entropy_refresh.79179650
Short name T72
Test name
Test status
Simulation time 7652192537 ps
CPU time 337.91 seconds
Started Aug 09 05:56:56 PM PDT 24
Finished Aug 09 06:02:34 PM PDT 24
Peak memory 327076 kb
Host smart-9c96a069-06b5-435a-9c36-26305dcf195a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79179650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_entropy_refresh.791
79650 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/19.kmac_lc_escalation.1198597408
Short name T81
Test name
Test status
Simulation time 71631233 ps
CPU time 1.82 seconds
Started Aug 09 05:55:16 PM PDT 24
Finished Aug 09 05:55:18 PM PDT 24
Peak memory 226996 kb
Host smart-f5f0467e-3e54-4a99-b6ce-53d2b28f9c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198597408 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.1198597408 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/19.kmac_lc_escalation/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.3047630073
Short name T98
Test name
Test status
Simulation time 50063566 ps
CPU time 1.16 seconds
Started Aug 09 07:18:20 PM PDT 24
Finished Aug 09 07:18:21 PM PDT 24
Peak memory 217012 kb
Host smart-9377911a-6ca1-46ec-bc65-7aef8644f107
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047630073 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg
_errors.3047630073 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.12375428
Short name T151
Test name
Test status
Simulation time 19715236 ps
CPU time 1.2 seconds
Started Aug 09 07:17:45 PM PDT 24
Finished Aug 09 07:17:47 PM PDT 24
Peak memory 216524 kb
Host smart-619bc1be-ce91-4735-bf59-02f5ffa82a30
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12375428 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partial_
access.12375428 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_mem_partial_access/latest

Test location /workspace/coverage/default/14.kmac_lc_escalation.3302172932
Short name T866
Test name
Test status
Simulation time 38937972 ps
CPU time 1.26 seconds
Started Aug 09 05:54:32 PM PDT 24
Finished Aug 09 05:54:33 PM PDT 24
Peak memory 226800 kb
Host smart-177e1c4f-e60b-4e5e-968b-57525128fcf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302172932 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.3302172932 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/14.kmac_lc_escalation/latest

Test location /workspace/coverage/default/15.kmac_lc_escalation.1302394105
Short name T830
Test name
Test status
Simulation time 76450967 ps
CPU time 1.58 seconds
Started Aug 09 05:54:40 PM PDT 24
Finished Aug 09 05:54:42 PM PDT 24
Peak memory 226868 kb
Host smart-f5f5c4b3-bcd5-4d48-b951-fde457084180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302394105 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.1302394105 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/15.kmac_lc_escalation/latest

Test location /workspace/coverage/default/0.kmac_alert_test.4126936749
Short name T318
Test name
Test status
Simulation time 21253455 ps
CPU time 0.87 seconds
Started Aug 09 05:53:22 PM PDT 24
Finished Aug 09 05:53:23 PM PDT 24
Peak memory 218468 kb
Host smart-146c055a-ab2e-4fde-8882-78c628365808
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126936749 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.4126936749 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.857362039
Short name T182
Test name
Test status
Simulation time 898959259 ps
CPU time 4.44 seconds
Started Aug 09 07:18:08 PM PDT 24
Finished Aug 09 07:18:13 PM PDT 24
Peak memory 216440 kb
Host smart-e2432d74-27a3-4e64-ad69-960d2b6f2d7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857362039 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.85736
2039 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/36.kmac_intr_test.3313181148
Short name T134
Test name
Test status
Simulation time 68487510 ps
CPU time 0.91 seconds
Started Aug 09 07:18:26 PM PDT 24
Finished Aug 09 07:18:28 PM PDT 24
Peak memory 216328 kb
Host smart-d39897fa-fece-492f-aa44-1006114435b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313181148 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.3313181148 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_intr_test/latest

Test location /workspace/coverage/default/1.kmac_error.2486868147
Short name T43
Test name
Test status
Simulation time 2340462560 ps
CPU time 204.16 seconds
Started Aug 09 05:53:30 PM PDT 24
Finished Aug 09 05:56:54 PM PDT 24
Peak memory 310192 kb
Host smart-76e6e679-b9fc-4a05-aa4c-3d51366240a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486868147 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.2486868147 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_error/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.498519814
Short name T183
Test name
Test status
Simulation time 1645862320 ps
CPU time 4.83 seconds
Started Aug 09 07:17:44 PM PDT 24
Finished Aug 09 07:17:49 PM PDT 24
Peak memory 216500 kb
Host smart-81a4ccb6-6821-4d9a-a762-0863037f8492
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498519814 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.498519
814 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/12.kmac_app.1801545845
Short name T174
Test name
Test status
Simulation time 40399595966 ps
CPU time 296.08 seconds
Started Aug 09 05:54:14 PM PDT 24
Finished Aug 09 05:59:10 PM PDT 24
Peak memory 421676 kb
Host smart-b78c2f24-14a1-43c2-b971-c2fb3ce6b2de
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801545845 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.1801545845 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/12.kmac_app/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.1493079459
Short name T100
Test name
Test status
Simulation time 71934335 ps
CPU time 2.51 seconds
Started Aug 09 07:18:26 PM PDT 24
Finished Aug 09 07:18:28 PM PDT 24
Peak memory 220504 kb
Host smart-c274721c-df99-4bd7-b3ab-68efb8a05d36
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493079459 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kma
c_shadow_reg_errors_with_csr_rw.1493079459 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/2.kmac_key_error.1817564059
Short name T107
Test name
Test status
Simulation time 3201518609 ps
CPU time 10.34 seconds
Started Aug 09 05:53:35 PM PDT 24
Finished Aug 09 05:53:45 PM PDT 24
Peak memory 226816 kb
Host smart-55be966b-7de1-4f37-8a3f-20fd1152a673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817564059 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.1817564059 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_key_error/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.2566470270
Short name T97
Test name
Test status
Simulation time 26453410 ps
CPU time 1.66 seconds
Started Aug 09 07:18:11 PM PDT 24
Finished Aug 09 07:18:13 PM PDT 24
Peak memory 216564 kb
Host smart-72b374cf-dd3a-49c5-ac4e-88a1de5002a2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566470270 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kma
c_shadow_reg_errors_with_csr_rw.2566470270 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/13.kmac_entropy_refresh.2991413026
Short name T578
Test name
Test status
Simulation time 36406661848 ps
CPU time 492.13 seconds
Started Aug 09 05:54:21 PM PDT 24
Finished Aug 09 06:02:33 PM PDT 24
Peak memory 548860 kb
Host smart-2e32a588-567e-4715-b175-dbfd8d7d7516
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991413026 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.2
991413026 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_entropy_refresh/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.1608202341
Short name T181
Test name
Test status
Simulation time 931951257 ps
CPU time 4.6 seconds
Started Aug 09 07:17:38 PM PDT 24
Finished Aug 09 07:17:43 PM PDT 24
Peak memory 216516 kb
Host smart-5d34fc5d-df56-4c3a-a3f8-31323c49fec5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608202341 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.16082
02341 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.2415010038
Short name T133
Test name
Test status
Simulation time 179664147 ps
CPU time 4.04 seconds
Started Aug 09 07:18:19 PM PDT 24
Finished Aug 09 07:18:23 PM PDT 24
Peak memory 216568 kb
Host smart-e41ba6f6-3a09-4451-a43a-3f7ccc708362
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415010038 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.2415
010038 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.kmac_stress_all.3827074887
Short name T1
Test name
Test status
Simulation time 29238389861 ps
CPU time 1429.17 seconds
Started Aug 09 05:53:23 PM PDT 24
Finished Aug 09 06:17:13 PM PDT 24
Peak memory 624768 kb
Host smart-61b4a00c-84d5-402e-ab0f-2f33e7d023fb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3827074887 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.3827074887 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.2498808745
Short name T188
Test name
Test status
Simulation time 29033542 ps
CPU time 1.03 seconds
Started Aug 09 07:17:38 PM PDT 24
Finished Aug 09 07:17:39 PM PDT 24
Peak memory 216636 kb
Host smart-3a3fc392-5f33-462a-8e7a-a84414b80eab
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498808745 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_
errors.2498808745 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/default/11.kmac_error.3328509538
Short name T896
Test name
Test status
Simulation time 2249210326 ps
CPU time 20.72 seconds
Started Aug 09 05:54:13 PM PDT 24
Finished Aug 09 05:54:34 PM PDT 24
Peak memory 243376 kb
Host smart-c1d1863b-0f02-4074-bad8-b59b737e4e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328509538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.3328509538 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_error/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.2142127645
Short name T1128
Test name
Test status
Simulation time 2608966912 ps
CPU time 5.27 seconds
Started Aug 09 07:17:46 PM PDT 24
Finished Aug 09 07:17:51 PM PDT 24
Peak memory 216532 kb
Host smart-c31506e2-47b1-4098-ad70-369f8cef224a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142127645 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.2142127
645 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.303674569
Short name T1075
Test name
Test status
Simulation time 3004461204 ps
CPU time 11.38 seconds
Started Aug 09 07:17:45 PM PDT 24
Finished Aug 09 07:17:57 PM PDT 24
Peak memory 216572 kb
Host smart-1c00b53a-2ed7-4755-b430-d84d5ff74461
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303674569 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.30367456
9 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.1858166289
Short name T1193
Test name
Test status
Simulation time 106736840 ps
CPU time 1.19 seconds
Started Aug 09 07:17:35 PM PDT 24
Finished Aug 09 07:17:37 PM PDT 24
Peak memory 216432 kb
Host smart-eaf5a700-7a10-4785-860d-49bd07f2f2f5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858166289 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.1858166
289 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.1631401025
Short name T1059
Test name
Test status
Simulation time 1326496568 ps
CPU time 3.11 seconds
Started Aug 09 07:17:46 PM PDT 24
Finished Aug 09 07:17:49 PM PDT 24
Peak memory 222720 kb
Host smart-68528373-f0d5-464f-afdb-10bf1d21d3db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631401025 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.kmac_csr_mem_rw_with_rand_reset.1631401025 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_rw.3986583390
Short name T1157
Test name
Test status
Simulation time 48555626 ps
CPU time 1.26 seconds
Started Aug 09 07:17:34 PM PDT 24
Finished Aug 09 07:17:36 PM PDT 24
Peak memory 216444 kb
Host smart-224d323a-b2da-42fb-87de-09f26782d731
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986583390 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.3986583390 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_intr_test.2116294730
Short name T1093
Test name
Test status
Simulation time 27223308 ps
CPU time 0.77 seconds
Started Aug 09 07:17:37 PM PDT 24
Finished Aug 09 07:17:37 PM PDT 24
Peak memory 216312 kb
Host smart-ba944a6c-59c7-409f-bd1d-dab53d48affa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116294730 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.2116294730 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.4045629549
Short name T1104
Test name
Test status
Simulation time 40430917 ps
CPU time 1.41 seconds
Started Aug 09 07:17:35 PM PDT 24
Finished Aug 09 07:17:37 PM PDT 24
Peak memory 216544 kb
Host smart-71c4f1c7-7ff3-4e89-a050-3f62315a0658
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045629549 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partia
l_access.4045629549 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_mem_walk.1232942123
Short name T1054
Test name
Test status
Simulation time 37480876 ps
CPU time 0.76 seconds
Started Aug 09 07:17:39 PM PDT 24
Finished Aug 09 07:17:40 PM PDT 24
Peak memory 216364 kb
Host smart-b29326bf-a3c9-478c-859c-dd1c20f25cd9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232942123 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.1232942123
+enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.2535647380
Short name T1122
Test name
Test status
Simulation time 141390298 ps
CPU time 2.24 seconds
Started Aug 09 07:17:46 PM PDT 24
Finished Aug 09 07:17:48 PM PDT 24
Peak memory 216528 kb
Host smart-fe9b7ff6-e063-4bec-b4e8-66e649c1a01c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535647380 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr
_outstanding.2535647380 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.2570186098
Short name T1124
Test name
Test status
Simulation time 146225316 ps
CPU time 1.71 seconds
Started Aug 09 07:17:38 PM PDT 24
Finished Aug 09 07:17:40 PM PDT 24
Peak memory 220272 kb
Host smart-5c4776b5-2597-4d09-a990-0b92e83bdfa8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570186098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac
_shadow_reg_errors_with_csr_rw.2570186098 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_tl_errors.1967869594
Short name T1067
Test name
Test status
Simulation time 72981485 ps
CPU time 2.41 seconds
Started Aug 09 07:17:43 PM PDT 24
Finished Aug 09 07:17:46 PM PDT 24
Peak memory 216728 kb
Host smart-fd2a166c-ef0f-4bf4-ae40-3e800cf387c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967869594 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.1967869594 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.129817034
Short name T1079
Test name
Test status
Simulation time 509915416 ps
CPU time 9.18 seconds
Started Aug 09 07:17:48 PM PDT 24
Finished Aug 09 07:17:58 PM PDT 24
Peak memory 216460 kb
Host smart-f635bc8e-ebf5-46ea-a445-990652139c35
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129817034 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.12981703
4 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.2991681572
Short name T1189
Test name
Test status
Simulation time 1171455901 ps
CPU time 16.01 seconds
Started Aug 09 07:17:43 PM PDT 24
Finished Aug 09 07:17:59 PM PDT 24
Peak memory 216356 kb
Host smart-c7267c8e-434c-4111-836d-b4efcbb329a4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991681572 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.2991681
572 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.530457576
Short name T1136
Test name
Test status
Simulation time 69531022 ps
CPU time 0.99 seconds
Started Aug 09 07:17:43 PM PDT 24
Finished Aug 09 07:17:44 PM PDT 24
Peak memory 216296 kb
Host smart-0b2af35e-8706-46dd-8375-375045d58f4e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530457576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.53045757
6 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.4280454471
Short name T1119
Test name
Test status
Simulation time 66669886 ps
CPU time 1.46 seconds
Started Aug 09 07:17:46 PM PDT 24
Finished Aug 09 07:17:47 PM PDT 24
Peak memory 217620 kb
Host smart-fa246e31-d4b9-4a8b-935c-6bef5267bfcb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280454471 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.kmac_csr_mem_rw_with_rand_reset.4280454471 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_rw.235540788
Short name T1132
Test name
Test status
Simulation time 22473628 ps
CPU time 0.95 seconds
Started Aug 09 07:17:44 PM PDT 24
Finished Aug 09 07:17:45 PM PDT 24
Peak memory 216260 kb
Host smart-37492e7b-6670-447a-8b2d-b9b792e679a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235540788 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.235540788 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_intr_test.1506188186
Short name T1166
Test name
Test status
Simulation time 19760968 ps
CPU time 0.78 seconds
Started Aug 09 07:17:45 PM PDT 24
Finished Aug 09 07:17:46 PM PDT 24
Peak memory 216324 kb
Host smart-6edc3902-c7cc-4a7c-98b8-4f5e2a5e4073
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506188186 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.1506188186 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_mem_walk.1185566731
Short name T1180
Test name
Test status
Simulation time 84987491 ps
CPU time 0.78 seconds
Started Aug 09 07:17:49 PM PDT 24
Finished Aug 09 07:17:50 PM PDT 24
Peak memory 216360 kb
Host smart-fdcad5f1-46a5-4da2-9d98-ac9c9f8c006b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185566731 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.1185566731
+enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.944790403
Short name T1137
Test name
Test status
Simulation time 42623956 ps
CPU time 2.22 seconds
Started Aug 09 07:17:48 PM PDT 24
Finished Aug 09 07:17:50 PM PDT 24
Peak memory 216620 kb
Host smart-d949babf-7763-4890-8a77-85a353860f41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944790403 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr_
outstanding.944790403 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.3909800657
Short name T1071
Test name
Test status
Simulation time 36481869 ps
CPU time 1.28 seconds
Started Aug 09 07:17:43 PM PDT 24
Finished Aug 09 07:17:45 PM PDT 24
Peak memory 217220 kb
Host smart-17ff5ff8-b6c6-4936-bc3d-7910ecd40d11
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909800657 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_
errors.3909800657 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.957633711
Short name T92
Test name
Test status
Simulation time 542429755 ps
CPU time 2.04 seconds
Started Aug 09 07:17:47 PM PDT 24
Finished Aug 09 07:17:49 PM PDT 24
Peak memory 219576 kb
Host smart-4f742588-0fee-4178-96a1-c3b31d9a8010
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957633711 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_
shadow_reg_errors_with_csr_rw.957633711 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_tl_errors.1988416415
Short name T1159
Test name
Test status
Simulation time 110464420 ps
CPU time 2.89 seconds
Started Aug 09 07:17:43 PM PDT 24
Finished Aug 09 07:17:46 PM PDT 24
Peak memory 216636 kb
Host smart-7613a28e-757d-4343-9847-7f0096630988
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988416415 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.1988416415 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.1146957615
Short name T1085
Test name
Test status
Simulation time 114730374 ps
CPU time 1.55 seconds
Started Aug 09 07:18:11 PM PDT 24
Finished Aug 09 07:18:12 PM PDT 24
Peak memory 217560 kb
Host smart-e5df524c-1846-4264-bc36-3997cbbc91ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146957615 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.kmac_csr_mem_rw_with_rand_reset.1146957615 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_csr_rw.1249865416
Short name T1080
Test name
Test status
Simulation time 98637579 ps
CPU time 1.17 seconds
Started Aug 09 07:18:09 PM PDT 24
Finished Aug 09 07:18:10 PM PDT 24
Peak memory 216496 kb
Host smart-3b2bcec2-1bb0-4808-a4b5-53c069d96e0c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249865416 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.1249865416 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_intr_test.4060181762
Short name T1087
Test name
Test status
Simulation time 48281394 ps
CPU time 0.82 seconds
Started Aug 09 07:18:12 PM PDT 24
Finished Aug 09 07:18:13 PM PDT 24
Peak memory 216328 kb
Host smart-1aafbdc6-75de-4394-9442-636c72f5731e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060181762 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.4060181762 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.1106244087
Short name T1134
Test name
Test status
Simulation time 170779855 ps
CPU time 2.58 seconds
Started Aug 09 07:18:16 PM PDT 24
Finished Aug 09 07:18:19 PM PDT 24
Peak memory 216552 kb
Host smart-a6892b5c-8974-42b9-8c45-31cad6880914
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106244087 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_cs
r_outstanding.1106244087 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.2724085756
Short name T90
Test name
Test status
Simulation time 62770411 ps
CPU time 1.58 seconds
Started Aug 09 07:18:16 PM PDT 24
Finished Aug 09 07:18:18 PM PDT 24
Peak memory 217844 kb
Host smart-ca78471f-d45f-4eae-b00d-1ea4c36a6e6a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724085756 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg
_errors.2724085756 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.1357345072
Short name T1113
Test name
Test status
Simulation time 172316857 ps
CPU time 2.39 seconds
Started Aug 09 07:18:16 PM PDT 24
Finished Aug 09 07:18:18 PM PDT 24
Peak memory 216492 kb
Host smart-e5d7322a-941c-47a5-b71e-b3960b12cba6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357345072 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kma
c_shadow_reg_errors_with_csr_rw.1357345072 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_tl_errors.2950624839
Short name T138
Test name
Test status
Simulation time 31124125 ps
CPU time 2.08 seconds
Started Aug 09 07:18:16 PM PDT 24
Finished Aug 09 07:18:18 PM PDT 24
Peak memory 216668 kb
Host smart-744f4d48-b15d-4fce-9602-e3be508fd9df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950624839 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.2950624839 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.1185375639
Short name T1115
Test name
Test status
Simulation time 446214316 ps
CPU time 2.23 seconds
Started Aug 09 07:18:07 PM PDT 24
Finished Aug 09 07:18:09 PM PDT 24
Peak memory 217864 kb
Host smart-c72178e9-08ba-4b6d-a516-b9f2d9666969
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185375639 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.kmac_csr_mem_rw_with_rand_reset.1185375639 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_csr_rw.2022829156
Short name T1100
Test name
Test status
Simulation time 15578486 ps
CPU time 0.98 seconds
Started Aug 09 07:18:10 PM PDT 24
Finished Aug 09 07:18:11 PM PDT 24
Peak memory 216264 kb
Host smart-42261792-c718-4e26-95de-96e2277e7668
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022829156 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.2022829156 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_intr_test.1887037597
Short name T165
Test name
Test status
Simulation time 51040566 ps
CPU time 0.8 seconds
Started Aug 09 07:18:12 PM PDT 24
Finished Aug 09 07:18:13 PM PDT 24
Peak memory 216340 kb
Host smart-5c55ba42-b23b-4d73-9b15-249cf07c1d04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887037597 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.1887037597 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.1605246537
Short name T1074
Test name
Test status
Simulation time 24217724 ps
CPU time 1.45 seconds
Started Aug 09 07:18:10 PM PDT 24
Finished Aug 09 07:18:12 PM PDT 24
Peak memory 216544 kb
Host smart-dbe20e20-de73-4ad6-8f18-fedd734a6d1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605246537 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_cs
r_outstanding.1605246537 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.2320769287
Short name T99
Test name
Test status
Simulation time 69974833 ps
CPU time 1.07 seconds
Started Aug 09 07:18:11 PM PDT 24
Finished Aug 09 07:18:12 PM PDT 24
Peak memory 216792 kb
Host smart-b4809664-a44b-481e-96a6-d6b1c2d5a95d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320769287 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg
_errors.2320769287 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.3420983566
Short name T1201
Test name
Test status
Simulation time 307000670 ps
CPU time 2.03 seconds
Started Aug 09 07:18:11 PM PDT 24
Finished Aug 09 07:18:13 PM PDT 24
Peak memory 216740 kb
Host smart-45c27b6b-bda0-4be9-8a81-2b087913b931
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420983566 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kma
c_shadow_reg_errors_with_csr_rw.3420983566 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_tl_errors.3209680590
Short name T1048
Test name
Test status
Simulation time 49098866 ps
CPU time 3.21 seconds
Started Aug 09 07:18:12 PM PDT 24
Finished Aug 09 07:18:15 PM PDT 24
Peak memory 216708 kb
Host smart-6e085714-f537-4006-9572-33dd8f9d68c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209680590 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.3209680590 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.739619575
Short name T184
Test name
Test status
Simulation time 745291596 ps
CPU time 4.82 seconds
Started Aug 09 07:18:10 PM PDT 24
Finished Aug 09 07:18:15 PM PDT 24
Peak memory 216508 kb
Host smart-0028ba00-bd33-48e4-a548-dabfc05196f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739619575 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.73961
9575 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.1026757075
Short name T1046
Test name
Test status
Simulation time 112776485 ps
CPU time 2.16 seconds
Started Aug 09 07:18:10 PM PDT 24
Finished Aug 09 07:18:13 PM PDT 24
Peak memory 222160 kb
Host smart-e00d6cfd-e42b-4d1e-a6b7-8ba4da423603
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026757075 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.kmac_csr_mem_rw_with_rand_reset.1026757075 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_csr_rw.1823805164
Short name T1072
Test name
Test status
Simulation time 27210920 ps
CPU time 0.99 seconds
Started Aug 09 07:18:13 PM PDT 24
Finished Aug 09 07:18:14 PM PDT 24
Peak memory 216276 kb
Host smart-f17fab85-92ee-4e69-a87e-b26ba812da3f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823805164 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.1823805164 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_intr_test.3866637730
Short name T164
Test name
Test status
Simulation time 15249438 ps
CPU time 0.84 seconds
Started Aug 09 07:18:09 PM PDT 24
Finished Aug 09 07:18:10 PM PDT 24
Peak memory 216376 kb
Host smart-44cf1fe7-815f-46d3-80b6-5f88b62e9036
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866637730 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.3866637730 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.2203888592
Short name T1131
Test name
Test status
Simulation time 90529286 ps
CPU time 2.48 seconds
Started Aug 09 07:18:14 PM PDT 24
Finished Aug 09 07:18:16 PM PDT 24
Peak memory 216580 kb
Host smart-4f4e4862-a445-42aa-9360-8a00a1e206be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203888592 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_cs
r_outstanding.2203888592 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.4078624805
Short name T1073
Test name
Test status
Simulation time 51175039 ps
CPU time 0.84 seconds
Started Aug 09 07:18:12 PM PDT 24
Finished Aug 09 07:18:13 PM PDT 24
Peak memory 216296 kb
Host smart-ef8d5f32-56c0-4fa5-8474-f7c139409346
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078624805 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg
_errors.4078624805 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.725926356
Short name T1099
Test name
Test status
Simulation time 104172436 ps
CPU time 3.06 seconds
Started Aug 09 07:18:09 PM PDT 24
Finished Aug 09 07:18:12 PM PDT 24
Peak memory 220104 kb
Host smart-b77b1c3b-740b-4b7f-aede-568a1ef25855
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725926356 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac
_shadow_reg_errors_with_csr_rw.725926356 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_tl_errors.1816210536
Short name T1050
Test name
Test status
Simulation time 416133787 ps
CPU time 3.03 seconds
Started Aug 09 07:18:10 PM PDT 24
Finished Aug 09 07:18:14 PM PDT 24
Peak memory 216724 kb
Host smart-9522b3be-ee24-41a5-bbd3-ff928a58e2ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816210536 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.1816210536 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.1612081234
Short name T186
Test name
Test status
Simulation time 592128563 ps
CPU time 4.44 seconds
Started Aug 09 07:18:09 PM PDT 24
Finished Aug 09 07:18:13 PM PDT 24
Peak memory 216484 kb
Host smart-a989ead2-fb16-45c6-a14e-e3a4808f17fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612081234 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.1612
081234 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.3665898943
Short name T1111
Test name
Test status
Simulation time 39162254 ps
CPU time 2.26 seconds
Started Aug 09 07:18:22 PM PDT 24
Finished Aug 09 07:18:24 PM PDT 24
Peak memory 221572 kb
Host smart-101ab6c0-1f36-4eec-86d2-41d063b6323e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665898943 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.kmac_csr_mem_rw_with_rand_reset.3665898943 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_csr_rw.3385267108
Short name T1177
Test name
Test status
Simulation time 30240615 ps
CPU time 1.18 seconds
Started Aug 09 07:18:22 PM PDT 24
Finished Aug 09 07:18:24 PM PDT 24
Peak memory 216436 kb
Host smart-8caf52f6-0284-4ba9-8376-66b1d925bc60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385267108 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.3385267108 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_intr_test.3618763921
Short name T1135
Test name
Test status
Simulation time 42302460 ps
CPU time 0.76 seconds
Started Aug 09 07:18:27 PM PDT 24
Finished Aug 09 07:18:29 PM PDT 24
Peak memory 216164 kb
Host smart-d8fcdff9-eb22-468a-8c2a-234488497878
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618763921 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.3618763921 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.3477830453
Short name T1191
Test name
Test status
Simulation time 594431859 ps
CPU time 2.49 seconds
Started Aug 09 07:18:22 PM PDT 24
Finished Aug 09 07:18:24 PM PDT 24
Peak memory 216472 kb
Host smart-4697e80c-d63a-4d56-ab58-15f0aacbfa56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477830453 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_cs
r_outstanding.3477830453 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.1778014053
Short name T88
Test name
Test status
Simulation time 26250071 ps
CPU time 1.17 seconds
Started Aug 09 07:18:10 PM PDT 24
Finished Aug 09 07:18:11 PM PDT 24
Peak memory 216788 kb
Host smart-03f95a02-fbe9-407d-9e27-c3799f26bc20
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778014053 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg
_errors.1778014053 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_tl_errors.4007273147
Short name T1139
Test name
Test status
Simulation time 488731822 ps
CPU time 3.84 seconds
Started Aug 09 07:18:10 PM PDT 24
Finished Aug 09 07:18:14 PM PDT 24
Peak memory 216668 kb
Host smart-73b1c728-ea9e-4567-87e1-cb01fa2944f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007273147 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.4007273147 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.1943087368
Short name T1098
Test name
Test status
Simulation time 82733445 ps
CPU time 1.56 seconds
Started Aug 09 07:18:18 PM PDT 24
Finished Aug 09 07:18:20 PM PDT 24
Peak memory 217672 kb
Host smart-749b04e2-eb94-48b3-9ee8-dbca904fcfbb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943087368 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.kmac_csr_mem_rw_with_rand_reset.1943087368 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_csr_rw.1227191551
Short name T1078
Test name
Test status
Simulation time 43883908 ps
CPU time 1 seconds
Started Aug 09 07:18:19 PM PDT 24
Finished Aug 09 07:18:20 PM PDT 24
Peak memory 216276 kb
Host smart-428976ea-c46a-4019-98b7-34575791792f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227191551 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.1227191551 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_intr_test.1331522410
Short name T1064
Test name
Test status
Simulation time 22905907 ps
CPU time 0.81 seconds
Started Aug 09 07:18:18 PM PDT 24
Finished Aug 09 07:18:19 PM PDT 24
Peak memory 216000 kb
Host smart-dbdd4bec-04a6-4084-bf41-67359a04710e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331522410 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.1331522410 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.1816266916
Short name T1121
Test name
Test status
Simulation time 40473195 ps
CPU time 2.22 seconds
Started Aug 09 07:18:18 PM PDT 24
Finished Aug 09 07:18:20 PM PDT 24
Peak memory 216492 kb
Host smart-d6879c61-1b78-4aaa-8663-c975b1aa3d00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816266916 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_cs
r_outstanding.1816266916 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.3237140084
Short name T1164
Test name
Test status
Simulation time 210381692 ps
CPU time 1.15 seconds
Started Aug 09 07:18:18 PM PDT 24
Finished Aug 09 07:18:19 PM PDT 24
Peak memory 216784 kb
Host smart-b9712b8d-990b-4072-870f-9e73847d222e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237140084 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg
_errors.3237140084 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.3087802809
Short name T1145
Test name
Test status
Simulation time 77170509 ps
CPU time 1.7 seconds
Started Aug 09 07:18:27 PM PDT 24
Finished Aug 09 07:18:29 PM PDT 24
Peak memory 216672 kb
Host smart-42740c21-b1ba-4a86-8137-bbc97cae0ee3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087802809 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kma
c_shadow_reg_errors_with_csr_rw.3087802809 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_tl_errors.4258391931
Short name T1082
Test name
Test status
Simulation time 304353274 ps
CPU time 2.68 seconds
Started Aug 09 07:18:18 PM PDT 24
Finished Aug 09 07:18:21 PM PDT 24
Peak memory 216712 kb
Host smart-5de344ef-28c9-4ffa-96f9-22fe7fe6e6fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258391931 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.4258391931 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.2019995065
Short name T175
Test name
Test status
Simulation time 252834399 ps
CPU time 2.86 seconds
Started Aug 09 07:18:18 PM PDT 24
Finished Aug 09 07:18:21 PM PDT 24
Peak memory 216556 kb
Host smart-f4c580cc-4f28-432e-9950-01032afed3a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019995065 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.2019
995065 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.651399343
Short name T1052
Test name
Test status
Simulation time 129035887 ps
CPU time 2.39 seconds
Started Aug 09 07:18:18 PM PDT 24
Finished Aug 09 07:18:21 PM PDT 24
Peak memory 221180 kb
Host smart-40aa2c5b-1131-4a00-942d-fe3ed8a7616f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651399343 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.kmac_csr_mem_rw_with_rand_reset.651399343 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_csr_rw.3704073637
Short name T1045
Test name
Test status
Simulation time 15969971 ps
CPU time 1.19 seconds
Started Aug 09 07:18:19 PM PDT 24
Finished Aug 09 07:18:20 PM PDT 24
Peak memory 216472 kb
Host smart-6b185dac-ff88-4ba6-9b18-cb25792c9f3f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704073637 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.3704073637 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_intr_test.805663768
Short name T1176
Test name
Test status
Simulation time 19143029 ps
CPU time 0.78 seconds
Started Aug 09 07:18:19 PM PDT 24
Finished Aug 09 07:18:20 PM PDT 24
Peak memory 216328 kb
Host smart-fa59cdbc-a0fb-4eb8-a37d-95e2c6762394
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805663768 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.805663768 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/15.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.26953164
Short name T1140
Test name
Test status
Simulation time 197038978 ps
CPU time 2.42 seconds
Started Aug 09 07:18:18 PM PDT 24
Finished Aug 09 07:18:21 PM PDT 24
Peak memory 216520 kb
Host smart-d9823629-47b3-4cf8-a7da-6603218ec2ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26953164 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_csr_
outstanding.26953164 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.2022369317
Short name T1167
Test name
Test status
Simulation time 56390103 ps
CPU time 1.11 seconds
Started Aug 09 07:18:26 PM PDT 24
Finished Aug 09 07:18:28 PM PDT 24
Peak memory 216404 kb
Host smart-5bb86e62-eae9-44df-b2f8-dc92493c182a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022369317 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg
_errors.2022369317 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.2119274328
Short name T1129
Test name
Test status
Simulation time 61201997 ps
CPU time 1.72 seconds
Started Aug 09 07:18:20 PM PDT 24
Finished Aug 09 07:18:22 PM PDT 24
Peak memory 220048 kb
Host smart-e9383e07-bf02-40bd-b89a-337e6753f72a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119274328 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kma
c_shadow_reg_errors_with_csr_rw.2119274328 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_tl_errors.2780683145
Short name T1153
Test name
Test status
Simulation time 101498925 ps
CPU time 3.01 seconds
Started Aug 09 07:18:18 PM PDT 24
Finished Aug 09 07:18:21 PM PDT 24
Peak memory 216728 kb
Host smart-8edf68ec-6a17-4c9d-9277-d060209e7ef6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780683145 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.2780683145 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.3581400014
Short name T132
Test name
Test status
Simulation time 144967538 ps
CPU time 2.95 seconds
Started Aug 09 07:18:19 PM PDT 24
Finished Aug 09 07:18:22 PM PDT 24
Peak memory 216504 kb
Host smart-d106e4cf-7606-4dbb-8f50-c75866078bf3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581400014 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.3581
400014 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.158608853
Short name T1126
Test name
Test status
Simulation time 46423056 ps
CPU time 1.72 seconds
Started Aug 09 07:18:18 PM PDT 24
Finished Aug 09 07:18:20 PM PDT 24
Peak memory 217584 kb
Host smart-8e62c857-b1b1-46bd-8805-f61b6c5ee5b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158608853 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.kmac_csr_mem_rw_with_rand_reset.158608853 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_csr_rw.4078238000
Short name T1095
Test name
Test status
Simulation time 161027930 ps
CPU time 0.97 seconds
Started Aug 09 07:18:17 PM PDT 24
Finished Aug 09 07:18:19 PM PDT 24
Peak memory 216232 kb
Host smart-d75a68b0-f355-47ca-8e5c-22c2dd532aa3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078238000 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.4078238000 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_intr_test.222381716
Short name T1063
Test name
Test status
Simulation time 25313629 ps
CPU time 0.84 seconds
Started Aug 09 07:18:20 PM PDT 24
Finished Aug 09 07:18:21 PM PDT 24
Peak memory 216396 kb
Host smart-e64eafb2-6c77-4914-b9e7-e9fb1d4456f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222381716 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.222381716 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/16.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.328815544
Short name T1110
Test name
Test status
Simulation time 137059825 ps
CPU time 2.18 seconds
Started Aug 09 07:18:18 PM PDT 24
Finished Aug 09 07:18:21 PM PDT 24
Peak memory 216620 kb
Host smart-4e193757-727f-4d7c-b423-b7231d54d6e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328815544 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_csr
_outstanding.328815544 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.4262389491
Short name T102
Test name
Test status
Simulation time 72345887 ps
CPU time 1.72 seconds
Started Aug 09 07:18:20 PM PDT 24
Finished Aug 09 07:18:22 PM PDT 24
Peak memory 216512 kb
Host smart-13c5033d-738b-4a14-ad2e-36b6fb9bfcb3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262389491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kma
c_shadow_reg_errors_with_csr_rw.4262389491 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_tl_errors.2653281830
Short name T1141
Test name
Test status
Simulation time 52384971 ps
CPU time 3 seconds
Started Aug 09 07:18:27 PM PDT 24
Finished Aug 09 07:18:31 PM PDT 24
Peak memory 216532 kb
Host smart-08744e6d-6436-4b43-ab5a-3eb84a5ed02b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653281830 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.2653281830 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.3304602725
Short name T185
Test name
Test status
Simulation time 226542478 ps
CPU time 4.7 seconds
Started Aug 09 07:18:19 PM PDT 24
Finished Aug 09 07:18:24 PM PDT 24
Peak memory 216512 kb
Host smart-5e263081-4be2-490e-a247-1be6bbbe1904
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304602725 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.3304
602725 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.2014527178
Short name T1092
Test name
Test status
Simulation time 198025888 ps
CPU time 2.79 seconds
Started Aug 09 07:18:25 PM PDT 24
Finished Aug 09 07:18:27 PM PDT 24
Peak memory 221604 kb
Host smart-6e64c23f-3508-469e-a700-c230341c59eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014527178 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.kmac_csr_mem_rw_with_rand_reset.2014527178 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_csr_rw.2260044140
Short name T1066
Test name
Test status
Simulation time 17365909 ps
CPU time 1.07 seconds
Started Aug 09 07:18:34 PM PDT 24
Finished Aug 09 07:18:35 PM PDT 24
Peak memory 216352 kb
Host smart-a9de8039-7373-4405-b6ad-5eddcf7057ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260044140 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.2260044140 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_intr_test.3245462247
Short name T166
Test name
Test status
Simulation time 17923130 ps
CPU time 0.91 seconds
Started Aug 09 07:18:27 PM PDT 24
Finished Aug 09 07:18:28 PM PDT 24
Peak memory 216116 kb
Host smart-210df4f3-2eb1-40d3-a8cc-ae47ba9f657b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245462247 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.3245462247 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.3179210680
Short name T1062
Test name
Test status
Simulation time 361368874 ps
CPU time 2.83 seconds
Started Aug 09 07:18:26 PM PDT 24
Finished Aug 09 07:18:29 PM PDT 24
Peak memory 216524 kb
Host smart-2e7c3a4a-0a12-4fb8-94a9-612369bb9290
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179210680 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_cs
r_outstanding.3179210680 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.3655086577
Short name T1195
Test name
Test status
Simulation time 176729301 ps
CPU time 1.17 seconds
Started Aug 09 07:18:22 PM PDT 24
Finished Aug 09 07:18:24 PM PDT 24
Peak memory 216816 kb
Host smart-e1f0242f-9202-46ff-a6f5-c9ea91c025da
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655086577 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg
_errors.3655086577 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.3608354028
Short name T1065
Test name
Test status
Simulation time 139159678 ps
CPU time 2.07 seconds
Started Aug 09 07:18:18 PM PDT 24
Finished Aug 09 07:18:21 PM PDT 24
Peak memory 216460 kb
Host smart-3933eb0c-f90b-45f4-b223-2ea9d6873070
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608354028 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kma
c_shadow_reg_errors_with_csr_rw.3608354028 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_tl_errors.914714391
Short name T149
Test name
Test status
Simulation time 48300289 ps
CPU time 2.75 seconds
Started Aug 09 07:18:17 PM PDT 24
Finished Aug 09 07:18:20 PM PDT 24
Peak memory 216692 kb
Host smart-7267b850-7a8b-458b-a371-e6c1e10494c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914714391 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.914714391 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/17.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.2856907141
Short name T178
Test name
Test status
Simulation time 231781616 ps
CPU time 5.15 seconds
Started Aug 09 07:18:26 PM PDT 24
Finished Aug 09 07:18:31 PM PDT 24
Peak memory 216516 kb
Host smart-f6639731-d7a1-4fb2-96f7-e8e32086f241
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856907141 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.2856
907141 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.1479221681
Short name T163
Test name
Test status
Simulation time 286939599 ps
CPU time 2.36 seconds
Started Aug 09 07:18:25 PM PDT 24
Finished Aug 09 07:18:28 PM PDT 24
Peak memory 222364 kb
Host smart-f10ab055-2fca-4375-aeee-ae691af35f33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479221681 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.kmac_csr_mem_rw_with_rand_reset.1479221681 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_csr_rw.1554782444
Short name T1142
Test name
Test status
Simulation time 33432679 ps
CPU time 1.22 seconds
Started Aug 09 07:18:25 PM PDT 24
Finished Aug 09 07:18:26 PM PDT 24
Peak memory 216468 kb
Host smart-64b956af-3fcd-4648-9a66-2d713624af9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554782444 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.1554782444 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_intr_test.1279872257
Short name T1150
Test name
Test status
Simulation time 12441489 ps
CPU time 0.82 seconds
Started Aug 09 07:18:25 PM PDT 24
Finished Aug 09 07:18:26 PM PDT 24
Peak memory 216320 kb
Host smart-793c9bf9-f37e-489c-a5cc-c497648703f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279872257 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.1279872257 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.1142450852
Short name T1077
Test name
Test status
Simulation time 46630470 ps
CPU time 1.48 seconds
Started Aug 09 07:18:24 PM PDT 24
Finished Aug 09 07:18:26 PM PDT 24
Peak memory 216612 kb
Host smart-4f9f667e-eb09-42d5-8bd2-a9cf40f21307
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142450852 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_cs
r_outstanding.1142450852 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_tl_errors.3771023270
Short name T1106
Test name
Test status
Simulation time 217741112 ps
CPU time 1.78 seconds
Started Aug 09 07:18:28 PM PDT 24
Finished Aug 09 07:18:30 PM PDT 24
Peak memory 216704 kb
Host smart-55b14541-6252-4ec4-b538-87a58588915a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771023270 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.3771023270 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.4240764399
Short name T1127
Test name
Test status
Simulation time 267116732 ps
CPU time 2.89 seconds
Started Aug 09 07:18:25 PM PDT 24
Finished Aug 09 07:18:28 PM PDT 24
Peak memory 216572 kb
Host smart-6d8ef950-19b0-4f21-9c84-5ce9e061d5b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240764399 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.4240
764399 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.2432472178
Short name T1186
Test name
Test status
Simulation time 263415412 ps
CPU time 2.57 seconds
Started Aug 09 07:18:27 PM PDT 24
Finished Aug 09 07:18:30 PM PDT 24
Peak memory 222700 kb
Host smart-4211cc15-ca66-4e0e-a6d3-d8bdad4dc795
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432472178 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.kmac_csr_mem_rw_with_rand_reset.2432472178 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_csr_rw.2987545833
Short name T1162
Test name
Test status
Simulation time 20555055 ps
CPU time 0.99 seconds
Started Aug 09 07:18:27 PM PDT 24
Finished Aug 09 07:18:29 PM PDT 24
Peak memory 216272 kb
Host smart-99dd4352-d885-4784-826b-5bdc9306e71c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987545833 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.2987545833 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_intr_test.3222820618
Short name T1116
Test name
Test status
Simulation time 175747145 ps
CPU time 0.84 seconds
Started Aug 09 07:18:27 PM PDT 24
Finished Aug 09 07:18:28 PM PDT 24
Peak memory 216304 kb
Host smart-f981738a-9855-453c-9968-b7399384ca6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222820618 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.3222820618 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.652593646
Short name T1101
Test name
Test status
Simulation time 110215902 ps
CPU time 1.63 seconds
Started Aug 09 07:18:25 PM PDT 24
Finished Aug 09 07:18:26 PM PDT 24
Peak memory 216560 kb
Host smart-f28b2191-c51f-4769-b7f6-cab0a4d87fb5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652593646 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_csr
_outstanding.652593646 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.2400363137
Short name T87
Test name
Test status
Simulation time 27867374 ps
CPU time 0.99 seconds
Started Aug 09 07:18:28 PM PDT 24
Finished Aug 09 07:18:29 PM PDT 24
Peak memory 216592 kb
Host smart-8963d049-1d38-4748-90ae-55922f165f0e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400363137 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg
_errors.2400363137 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.319671146
Short name T94
Test name
Test status
Simulation time 149629061 ps
CPU time 3.09 seconds
Started Aug 09 07:18:27 PM PDT 24
Finished Aug 09 07:18:30 PM PDT 24
Peak memory 220432 kb
Host smart-901bcbfc-3ee6-4869-8aa5-b760414ea59a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319671146 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac
_shadow_reg_errors_with_csr_rw.319671146 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_tl_errors.3484414233
Short name T140
Test name
Test status
Simulation time 122388327 ps
CPU time 2.45 seconds
Started Aug 09 07:18:25 PM PDT 24
Finished Aug 09 07:18:28 PM PDT 24
Peak memory 216684 kb
Host smart-9bab5eb6-34e7-4087-9f95-703e5bb6af29
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484414233 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.3484414233 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.2010536819
Short name T177
Test name
Test status
Simulation time 111462831 ps
CPU time 4.05 seconds
Started Aug 09 07:18:26 PM PDT 24
Finished Aug 09 07:18:30 PM PDT 24
Peak memory 216496 kb
Host smart-4f5f62c2-6850-41fd-a2e4-62d35d5bf3b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010536819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.2010
536819 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.583608549
Short name T1156
Test name
Test status
Simulation time 279050626 ps
CPU time 5.43 seconds
Started Aug 09 07:17:43 PM PDT 24
Finished Aug 09 07:17:49 PM PDT 24
Peak memory 216468 kb
Host smart-5cee686f-5fb5-4fb8-94a7-871f5655f306
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583608549 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.58360854
9 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.2895863224
Short name T1183
Test name
Test status
Simulation time 775026846 ps
CPU time 11 seconds
Started Aug 09 07:17:46 PM PDT 24
Finished Aug 09 07:17:57 PM PDT 24
Peak memory 216508 kb
Host smart-34ce7c02-76b4-46f9-8060-0673834aa973
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895863224 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.2895863
224 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.3510041512
Short name T1202
Test name
Test status
Simulation time 31789905 ps
CPU time 1.21 seconds
Started Aug 09 07:17:47 PM PDT 24
Finished Aug 09 07:17:48 PM PDT 24
Peak memory 216480 kb
Host smart-1c01b1e1-b6dc-412a-9559-c75d915570e6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510041512 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.3510041
512 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.2217022451
Short name T161
Test name
Test status
Simulation time 48992096 ps
CPU time 1.6 seconds
Started Aug 09 07:17:44 PM PDT 24
Finished Aug 09 07:17:45 PM PDT 24
Peak memory 219612 kb
Host smart-45ee3646-1a39-48a5-b0cd-5aa4bb8adc8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217022451 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.kmac_csr_mem_rw_with_rand_reset.2217022451 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_rw.195197110
Short name T1165
Test name
Test status
Simulation time 40913781 ps
CPU time 0.98 seconds
Started Aug 09 07:17:45 PM PDT 24
Finished Aug 09 07:17:46 PM PDT 24
Peak memory 216244 kb
Host smart-19fa73f5-313b-48c2-a1dd-64f8ef652d2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195197110 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.195197110 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_intr_test.3662760448
Short name T135
Test name
Test status
Simulation time 32063532 ps
CPU time 0.81 seconds
Started Aug 09 07:17:47 PM PDT 24
Finished Aug 09 07:17:47 PM PDT 24
Peak memory 216360 kb
Host smart-d32eb320-6b0f-4f19-9e34-dc695be29db0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662760448 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.3662760448 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.2502298076
Short name T150
Test name
Test status
Simulation time 20100311 ps
CPU time 1.16 seconds
Started Aug 09 07:17:45 PM PDT 24
Finished Aug 09 07:17:47 PM PDT 24
Peak memory 216472 kb
Host smart-18f6bb4d-f9b9-4d99-bd16-d5c2d74711e2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502298076 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partia
l_access.2502298076 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_mem_walk.3467508754
Short name T1130
Test name
Test status
Simulation time 13524983 ps
CPU time 0.78 seconds
Started Aug 09 07:17:44 PM PDT 24
Finished Aug 09 07:17:45 PM PDT 24
Peak memory 216336 kb
Host smart-9ca884c8-1d87-4fc8-8c10-0b0d7e24b5f3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467508754 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.3467508754
+enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.2617123746
Short name T1197
Test name
Test status
Simulation time 1030970633 ps
CPU time 2.69 seconds
Started Aug 09 07:17:44 PM PDT 24
Finished Aug 09 07:17:46 PM PDT 24
Peak memory 216520 kb
Host smart-0d54a1f5-8389-4b90-862b-ea248809bf91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617123746 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr
_outstanding.2617123746 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.2650209703
Short name T167
Test name
Test status
Simulation time 79336088 ps
CPU time 0.99 seconds
Started Aug 09 07:17:43 PM PDT 24
Finished Aug 09 07:17:44 PM PDT 24
Peak memory 216608 kb
Host smart-0d03ea9a-69f6-4912-8737-f88b9d0cb92b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650209703 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_
errors.2650209703 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.2134711796
Short name T1149
Test name
Test status
Simulation time 102222642 ps
CPU time 2.65 seconds
Started Aug 09 07:17:43 PM PDT 24
Finished Aug 09 07:17:46 PM PDT 24
Peak memory 219984 kb
Host smart-50618c24-26d9-4b40-9aaf-f3e62251801d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134711796 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac
_shadow_reg_errors_with_csr_rw.2134711796 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_tl_errors.2752197381
Short name T1154
Test name
Test status
Simulation time 119126387 ps
CPU time 2.06 seconds
Started Aug 09 07:17:45 PM PDT 24
Finished Aug 09 07:17:47 PM PDT 24
Peak memory 216692 kb
Host smart-5e7bb1cb-fd7f-4003-a9cf-2f495cc9554c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752197381 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.2752197381 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.3733285891
Short name T1173
Test name
Test status
Simulation time 123126075 ps
CPU time 2.57 seconds
Started Aug 09 07:17:45 PM PDT 24
Finished Aug 09 07:17:48 PM PDT 24
Peak memory 216528 kb
Host smart-69d0ff01-9d6d-4a08-a909-a2f7dbdd3278
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733285891 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.37332
85891 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.kmac_intr_test.1996801409
Short name T1147
Test name
Test status
Simulation time 61253331 ps
CPU time 0.85 seconds
Started Aug 09 07:18:27 PM PDT 24
Finished Aug 09 07:18:28 PM PDT 24
Peak memory 216336 kb
Host smart-72b4dce5-02f5-4fb8-baf2-68f1e327fd5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996801409 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.1996801409 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.kmac_intr_test.2302292586
Short name T1097
Test name
Test status
Simulation time 31693082 ps
CPU time 0.8 seconds
Started Aug 09 07:18:27 PM PDT 24
Finished Aug 09 07:18:28 PM PDT 24
Peak memory 216280 kb
Host smart-02278cbb-5b64-47a0-9059-0fd1b007cfc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302292586 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.2302292586 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.kmac_intr_test.706407682
Short name T1151
Test name
Test status
Simulation time 22171205 ps
CPU time 0.83 seconds
Started Aug 09 07:18:29 PM PDT 24
Finished Aug 09 07:18:30 PM PDT 24
Peak memory 216112 kb
Host smart-33e754d7-f078-4208-9cd4-a978e9c33b54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706407682 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.706407682 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/22.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.kmac_intr_test.2546440153
Short name T1120
Test name
Test status
Simulation time 55039407 ps
CPU time 0.76 seconds
Started Aug 09 07:18:26 PM PDT 24
Finished Aug 09 07:18:27 PM PDT 24
Peak memory 216324 kb
Host smart-335657fe-c5fe-4289-bd93-38a9a560645c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546440153 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.2546440153 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.kmac_intr_test.823222181
Short name T1175
Test name
Test status
Simulation time 39405212 ps
CPU time 0.76 seconds
Started Aug 09 07:18:36 PM PDT 24
Finished Aug 09 07:18:37 PM PDT 24
Peak memory 216060 kb
Host smart-9f764420-6e70-4c4c-b4d7-be229ded1011
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823222181 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.823222181 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/24.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.kmac_intr_test.3981987117
Short name T1152
Test name
Test status
Simulation time 48795592 ps
CPU time 0.82 seconds
Started Aug 09 07:18:29 PM PDT 24
Finished Aug 09 07:18:30 PM PDT 24
Peak memory 216228 kb
Host smart-6792d287-6c1e-474d-b96d-53097e9443c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981987117 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.3981987117 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.kmac_intr_test.3101747879
Short name T1171
Test name
Test status
Simulation time 42625400 ps
CPU time 0.81 seconds
Started Aug 09 07:18:25 PM PDT 24
Finished Aug 09 07:18:26 PM PDT 24
Peak memory 216224 kb
Host smart-99bbef27-3e46-4702-9a96-61c0273250c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101747879 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.3101747879 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.kmac_intr_test.1216417734
Short name T1081
Test name
Test status
Simulation time 13588152 ps
CPU time 0.82 seconds
Started Aug 09 07:18:29 PM PDT 24
Finished Aug 09 07:18:30 PM PDT 24
Peak memory 216344 kb
Host smart-0fa5bf70-42fb-4edb-91e2-42abe945c382
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216417734 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.1216417734 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.kmac_intr_test.1367702525
Short name T1190
Test name
Test status
Simulation time 14057693 ps
CPU time 0.83 seconds
Started Aug 09 07:18:26 PM PDT 24
Finished Aug 09 07:18:27 PM PDT 24
Peak memory 216068 kb
Host smart-2eb53873-19e4-4c34-809b-ce3ea575c533
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367702525 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.1367702525 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.kmac_intr_test.994637154
Short name T1091
Test name
Test status
Simulation time 35934177 ps
CPU time 0.81 seconds
Started Aug 09 07:18:29 PM PDT 24
Finished Aug 09 07:18:30 PM PDT 24
Peak memory 216324 kb
Host smart-e3421a2c-229e-4548-8314-66887b5109ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994637154 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.994637154 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/29.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.1606529794
Short name T1086
Test name
Test status
Simulation time 137754979 ps
CPU time 7.77 seconds
Started Aug 09 07:17:59 PM PDT 24
Finished Aug 09 07:18:07 PM PDT 24
Peak memory 216424 kb
Host smart-fb381985-790b-47b8-b69f-375989d7b1e2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606529794 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.1606529
794 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.948731761
Short name T1047
Test name
Test status
Simulation time 296659834 ps
CPU time 15.93 seconds
Started Aug 09 07:18:03 PM PDT 24
Finished Aug 09 07:18:19 PM PDT 24
Peak memory 216416 kb
Host smart-40d76a09-f7d4-4a11-bdd0-d8cd9ea2ec56
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948731761 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.94873176
1 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.3898108373
Short name T1060
Test name
Test status
Simulation time 30791062 ps
CPU time 1.13 seconds
Started Aug 09 07:18:02 PM PDT 24
Finished Aug 09 07:18:03 PM PDT 24
Peak memory 216728 kb
Host smart-d7980f84-3117-4f0e-b4a6-5ef158cbfead
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898108373 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.3898108
373 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.1983285223
Short name T1090
Test name
Test status
Simulation time 50550181 ps
CPU time 1.83 seconds
Started Aug 09 07:18:02 PM PDT 24
Finished Aug 09 07:18:04 PM PDT 24
Peak memory 220568 kb
Host smart-e390d8d3-28bf-4d7d-bedc-b4efa1cfecd8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983285223 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.kmac_csr_mem_rw_with_rand_reset.1983285223 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_rw.4262756250
Short name T187
Test name
Test status
Simulation time 95522613 ps
CPU time 1 seconds
Started Aug 09 07:18:01 PM PDT 24
Finished Aug 09 07:18:02 PM PDT 24
Peak memory 216232 kb
Host smart-80e9d953-6c0d-4410-b431-9c0b7105a84a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262756250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.4262756250 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.3154088354
Short name T1114
Test name
Test status
Simulation time 132285543 ps
CPU time 1.63 seconds
Started Aug 09 07:17:43 PM PDT 24
Finished Aug 09 07:17:45 PM PDT 24
Peak memory 216456 kb
Host smart-eeb63df4-635c-4ea5-b5cf-7f9af08ed2a8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154088354 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partia
l_access.3154088354 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_mem_walk.3241677651
Short name T1155
Test name
Test status
Simulation time 37114731 ps
CPU time 0.75 seconds
Started Aug 09 07:17:46 PM PDT 24
Finished Aug 09 07:17:47 PM PDT 24
Peak memory 216108 kb
Host smart-d3f9ae83-8053-415d-8888-467f1317db56
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241677651 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.3241677651
+enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.2986504208
Short name T1200
Test name
Test status
Simulation time 489366164 ps
CPU time 2.7 seconds
Started Aug 09 07:18:01 PM PDT 24
Finished Aug 09 07:18:04 PM PDT 24
Peak memory 216536 kb
Host smart-60081a11-475f-45f5-a672-9ced203ed103
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986504208 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr
_outstanding.2986504208 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.3018868096
Short name T89
Test name
Test status
Simulation time 24656996 ps
CPU time 1.07 seconds
Started Aug 09 07:17:48 PM PDT 24
Finished Aug 09 07:17:50 PM PDT 24
Peak memory 216788 kb
Host smart-bed516e1-1984-4949-b247-63110ac8ebe5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018868096 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_
errors.3018868096 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.1860937332
Short name T91
Test name
Test status
Simulation time 34603624 ps
CPU time 1.57 seconds
Started Aug 09 07:17:43 PM PDT 24
Finished Aug 09 07:17:45 PM PDT 24
Peak memory 216564 kb
Host smart-6210077a-7b91-42f9-a5d3-678c85dcdfdf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860937332 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac
_shadow_reg_errors_with_csr_rw.1860937332 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_tl_errors.3554555637
Short name T1179
Test name
Test status
Simulation time 47985295 ps
CPU time 1.69 seconds
Started Aug 09 07:17:45 PM PDT 24
Finished Aug 09 07:17:46 PM PDT 24
Peak memory 216660 kb
Host smart-20cac8cb-912a-4a98-98c2-ca6c49381c85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554555637 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.3554555637 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.1295813474
Short name T179
Test name
Test status
Simulation time 428784856 ps
CPU time 6.02 seconds
Started Aug 09 07:17:59 PM PDT 24
Finished Aug 09 07:18:05 PM PDT 24
Peak memory 216440 kb
Host smart-790a9ee4-47f7-4cbd-8a39-b319830c1980
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295813474 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.12958
13474 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.kmac_intr_test.1995119332
Short name T1108
Test name
Test status
Simulation time 46995478 ps
CPU time 0.8 seconds
Started Aug 09 07:18:36 PM PDT 24
Finished Aug 09 07:18:37 PM PDT 24
Peak memory 216168 kb
Host smart-f5214a01-51d1-4d45-9c0c-1b72ec576029
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995119332 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.1995119332 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.kmac_intr_test.1389947156
Short name T1144
Test name
Test status
Simulation time 20623533 ps
CPU time 0.83 seconds
Started Aug 09 07:18:29 PM PDT 24
Finished Aug 09 07:18:30 PM PDT 24
Peak memory 216340 kb
Host smart-c1101fbe-93cf-41c2-8a9c-66368b46a208
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389947156 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.1389947156 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.kmac_intr_test.618721487
Short name T136
Test name
Test status
Simulation time 35006986 ps
CPU time 0.83 seconds
Started Aug 09 07:18:26 PM PDT 24
Finished Aug 09 07:18:26 PM PDT 24
Peak memory 216340 kb
Host smart-c3bbe3a1-0c4b-4779-9893-406e3dfcc25f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618721487 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.618721487 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/32.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.kmac_intr_test.2278822458
Short name T1057
Test name
Test status
Simulation time 14873187 ps
CPU time 0.85 seconds
Started Aug 09 07:18:29 PM PDT 24
Finished Aug 09 07:18:30 PM PDT 24
Peak memory 216284 kb
Host smart-199763e1-7c78-426b-a9d6-10b72f6ad99e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278822458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.2278822458 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.kmac_intr_test.3821280546
Short name T1083
Test name
Test status
Simulation time 124554825 ps
CPU time 0.83 seconds
Started Aug 09 07:18:25 PM PDT 24
Finished Aug 09 07:18:25 PM PDT 24
Peak memory 216352 kb
Host smart-e9c9b673-6bae-4602-99d7-792b75b1747a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821280546 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.3821280546 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.kmac_intr_test.2438556658
Short name T1084
Test name
Test status
Simulation time 40799880 ps
CPU time 0.87 seconds
Started Aug 09 07:18:26 PM PDT 24
Finished Aug 09 07:18:28 PM PDT 24
Peak memory 216328 kb
Host smart-e0762e2a-5854-4ea8-a393-960f99b4b29e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438556658 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.2438556658 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.kmac_intr_test.1739326518
Short name T1088
Test name
Test status
Simulation time 47376738 ps
CPU time 0.78 seconds
Started Aug 09 07:18:30 PM PDT 24
Finished Aug 09 07:18:31 PM PDT 24
Peak memory 216348 kb
Host smart-a1c4fd0e-af98-4c70-b369-beb7075ee1ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739326518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.1739326518 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.kmac_intr_test.1758478611
Short name T1125
Test name
Test status
Simulation time 16331155 ps
CPU time 0.85 seconds
Started Aug 09 07:18:26 PM PDT 24
Finished Aug 09 07:18:27 PM PDT 24
Peak memory 216372 kb
Host smart-e585642f-cf86-4701-a041-886fe58f78d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758478611 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.1758478611 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.kmac_intr_test.4248517259
Short name T1094
Test name
Test status
Simulation time 16829186 ps
CPU time 0.81 seconds
Started Aug 09 07:18:30 PM PDT 24
Finished Aug 09 07:18:31 PM PDT 24
Peak memory 216296 kb
Host smart-5de04600-d0d9-411d-ad3e-730ca05e1944
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248517259 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.4248517259 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.2455506033
Short name T1146
Test name
Test status
Simulation time 1522930954 ps
CPU time 9.47 seconds
Started Aug 09 07:18:01 PM PDT 24
Finished Aug 09 07:18:11 PM PDT 24
Peak memory 216464 kb
Host smart-cbbe83ab-03b5-47a0-85f0-3579547fcc2e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455506033 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.2455506
033 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.542033598
Short name T1172
Test name
Test status
Simulation time 743547894 ps
CPU time 10.84 seconds
Started Aug 09 07:17:59 PM PDT 24
Finished Aug 09 07:18:10 PM PDT 24
Peak memory 216464 kb
Host smart-ee479eb2-1805-4d45-93e3-591f080d1597
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542033598 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.54203359
8 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.2534547305
Short name T162
Test name
Test status
Simulation time 132882824 ps
CPU time 1.2 seconds
Started Aug 09 07:18:00 PM PDT 24
Finished Aug 09 07:18:01 PM PDT 24
Peak memory 216492 kb
Host smart-d8ea96d7-cb31-48f8-ad69-621847c40c8e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534547305 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.2534547
305 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.2776965682
Short name T160
Test name
Test status
Simulation time 199060094 ps
CPU time 2.22 seconds
Started Aug 09 07:18:01 PM PDT 24
Finished Aug 09 07:18:04 PM PDT 24
Peak memory 219496 kb
Host smart-1f10eea5-2d16-428e-bc8e-fdbc15fc8cdf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776965682 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.kmac_csr_mem_rw_with_rand_reset.2776965682 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_rw.613256220
Short name T1187
Test name
Test status
Simulation time 28189111 ps
CPU time 1.15 seconds
Started Aug 09 07:17:58 PM PDT 24
Finished Aug 09 07:18:00 PM PDT 24
Peak memory 216524 kb
Host smart-ea92b6ec-c1e1-494f-a833-d5c3b3f4707d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613256220 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.613256220 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_intr_test.1414234022
Short name T1163
Test name
Test status
Simulation time 20495216 ps
CPU time 0.83 seconds
Started Aug 09 07:18:00 PM PDT 24
Finished Aug 09 07:18:01 PM PDT 24
Peak memory 216284 kb
Host smart-d1dbb941-df30-4611-8254-886482693b6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414234022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.1414234022 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.3432789627
Short name T152
Test name
Test status
Simulation time 74289117 ps
CPU time 1.26 seconds
Started Aug 09 07:18:02 PM PDT 24
Finished Aug 09 07:18:04 PM PDT 24
Peak memory 216476 kb
Host smart-43faed68-21a9-4084-afa1-cbd356a0d80c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432789627 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partia
l_access.3432789627 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_mem_walk.3617127620
Short name T1051
Test name
Test status
Simulation time 42557682 ps
CPU time 0.77 seconds
Started Aug 09 07:18:00 PM PDT 24
Finished Aug 09 07:18:01 PM PDT 24
Peak memory 216188 kb
Host smart-5e6dc3ca-284d-478b-a156-249eb89796e1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617127620 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.3617127620
+enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.2943661903
Short name T1044
Test name
Test status
Simulation time 346835457 ps
CPU time 2.54 seconds
Started Aug 09 07:17:59 PM PDT 24
Finished Aug 09 07:18:01 PM PDT 24
Peak memory 216556 kb
Host smart-0bba0971-1ae7-486a-bb9e-8ede662dae74
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943661903 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr
_outstanding.2943661903 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.2304807690
Short name T1109
Test name
Test status
Simulation time 45268151 ps
CPU time 0.99 seconds
Started Aug 09 07:18:01 PM PDT 24
Finished Aug 09 07:18:02 PM PDT 24
Peak memory 216624 kb
Host smart-8925752c-c02c-4251-be5a-fc698a7219e9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304807690 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_
errors.2304807690 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.2870404761
Short name T1089
Test name
Test status
Simulation time 101532392 ps
CPU time 1.52 seconds
Started Aug 09 07:18:01 PM PDT 24
Finished Aug 09 07:18:03 PM PDT 24
Peak memory 216808 kb
Host smart-6ae89df5-2d17-4ce2-a020-f5c74e6e9518
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870404761 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac
_shadow_reg_errors_with_csr_rw.2870404761 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_tl_errors.541046484
Short name T1049
Test name
Test status
Simulation time 27669065 ps
CPU time 1.82 seconds
Started Aug 09 07:18:00 PM PDT 24
Finished Aug 09 07:18:02 PM PDT 24
Peak memory 216644 kb
Host smart-d39e94f0-1f41-4550-9c9c-e2e8f69e5f47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541046484 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.541046484 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/4.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.3221796391
Short name T180
Test name
Test status
Simulation time 4658209269 ps
CPU time 6.71 seconds
Started Aug 09 07:18:01 PM PDT 24
Finished Aug 09 07:18:08 PM PDT 24
Peak memory 216640 kb
Host smart-fa6e1e45-3b5b-48b5-bf04-b9adf8360923
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221796391 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.32217
96391 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.kmac_intr_test.3065820834
Short name T1199
Test name
Test status
Simulation time 22089294 ps
CPU time 0.85 seconds
Started Aug 09 07:18:26 PM PDT 24
Finished Aug 09 07:18:27 PM PDT 24
Peak memory 216308 kb
Host smart-aeef29ef-ad21-4a83-b7ab-b78f5e278bf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065820834 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.3065820834 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.kmac_intr_test.1010113335
Short name T1103
Test name
Test status
Simulation time 22551125 ps
CPU time 0.83 seconds
Started Aug 09 07:18:27 PM PDT 24
Finished Aug 09 07:18:28 PM PDT 24
Peak memory 216356 kb
Host smart-007e7f30-c4a4-48d5-bdb9-5aef46ced280
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010113335 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.1010113335 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.kmac_intr_test.3473913018
Short name T1112
Test name
Test status
Simulation time 93956692 ps
CPU time 0.8 seconds
Started Aug 09 07:18:29 PM PDT 24
Finished Aug 09 07:18:30 PM PDT 24
Peak memory 216296 kb
Host smart-d40e00c1-ba1b-4987-8f79-94b795527560
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473913018 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.3473913018 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.kmac_intr_test.469989306
Short name T1194
Test name
Test status
Simulation time 14775387 ps
CPU time 0.87 seconds
Started Aug 09 07:18:26 PM PDT 24
Finished Aug 09 07:18:26 PM PDT 24
Peak memory 216348 kb
Host smart-1fdd1370-0f09-4d95-9a83-a3b8f469ba06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469989306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.469989306 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/43.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.kmac_intr_test.2241033194
Short name T1123
Test name
Test status
Simulation time 16367264 ps
CPU time 0.84 seconds
Started Aug 09 07:18:29 PM PDT 24
Finished Aug 09 07:18:30 PM PDT 24
Peak memory 216344 kb
Host smart-ff724427-c9b1-46bb-ae21-9a8a3a4ca7ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241033194 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.2241033194 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.kmac_intr_test.336388459
Short name T1058
Test name
Test status
Simulation time 38926380 ps
CPU time 0.8 seconds
Started Aug 09 07:18:27 PM PDT 24
Finished Aug 09 07:18:28 PM PDT 24
Peak memory 216332 kb
Host smart-9e23e743-5723-4a0e-8e38-0b866ecbbce8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336388459 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.336388459 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/45.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.kmac_intr_test.1485508538
Short name T1198
Test name
Test status
Simulation time 21834325 ps
CPU time 0.8 seconds
Started Aug 09 07:18:36 PM PDT 24
Finished Aug 09 07:18:37 PM PDT 24
Peak memory 216172 kb
Host smart-0371819c-5fc6-433d-8df6-e0704891a46b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485508538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.1485508538 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.kmac_intr_test.982103223
Short name T170
Test name
Test status
Simulation time 28552123 ps
CPU time 0.81 seconds
Started Aug 09 07:18:29 PM PDT 24
Finished Aug 09 07:18:30 PM PDT 24
Peak memory 216312 kb
Host smart-4629a08d-aea3-4eed-ae4b-627efa7941b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982103223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.982103223 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/47.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.kmac_intr_test.1443141040
Short name T1061
Test name
Test status
Simulation time 107331276 ps
CPU time 0.79 seconds
Started Aug 09 07:18:36 PM PDT 24
Finished Aug 09 07:18:37 PM PDT 24
Peak memory 216168 kb
Host smart-8260a95c-1697-47b8-9956-320f81ae44d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443141040 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.1443141040 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.kmac_intr_test.3867991920
Short name T1148
Test name
Test status
Simulation time 17397569 ps
CPU time 0.79 seconds
Started Aug 09 07:18:27 PM PDT 24
Finished Aug 09 07:18:28 PM PDT 24
Peak memory 216248 kb
Host smart-0e613fa4-9f74-4754-bdf4-00066347a2e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867991920 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.3867991920 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.1360350140
Short name T1076
Test name
Test status
Simulation time 609271384 ps
CPU time 1.77 seconds
Started Aug 09 07:18:03 PM PDT 24
Finished Aug 09 07:18:05 PM PDT 24
Peak memory 218660 kb
Host smart-096103b6-a4eb-4d5b-907d-18b018b4ff15
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360350140 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.kmac_csr_mem_rw_with_rand_reset.1360350140 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_csr_rw.3320099529
Short name T1105
Test name
Test status
Simulation time 39946751 ps
CPU time 0.99 seconds
Started Aug 09 07:18:01 PM PDT 24
Finished Aug 09 07:18:02 PM PDT 24
Peak memory 216276 kb
Host smart-420d1ba2-4d98-42bf-809e-d446d13e0d44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320099529 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.3320099529 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_intr_test.1682012013
Short name T1117
Test name
Test status
Simulation time 22945938 ps
CPU time 0.8 seconds
Started Aug 09 07:18:00 PM PDT 24
Finished Aug 09 07:18:01 PM PDT 24
Peak memory 216352 kb
Host smart-cdaa7b12-9e6c-4317-a1fd-017c959a3391
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682012013 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.1682012013 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.172399159
Short name T1196
Test name
Test status
Simulation time 348907799 ps
CPU time 2.7 seconds
Started Aug 09 07:17:59 PM PDT 24
Finished Aug 09 07:18:02 PM PDT 24
Peak memory 216528 kb
Host smart-54838cd4-3847-4484-ada3-49716471ffec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172399159 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr_
outstanding.172399159 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.3935498022
Short name T96
Test name
Test status
Simulation time 59865100 ps
CPU time 0.94 seconds
Started Aug 09 07:18:01 PM PDT 24
Finished Aug 09 07:18:02 PM PDT 24
Peak memory 216572 kb
Host smart-9bfb5b50-b68d-4a62-9b1d-94a9f7323ffe
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935498022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_
errors.3935498022 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.2568828531
Short name T1192
Test name
Test status
Simulation time 127907498 ps
CPU time 2.98 seconds
Started Aug 09 07:17:58 PM PDT 24
Finished Aug 09 07:18:01 PM PDT 24
Peak memory 219448 kb
Host smart-96ad0b05-5009-40f9-8244-7caa1698041d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568828531 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac
_shadow_reg_errors_with_csr_rw.2568828531 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_tl_errors.3455274847
Short name T137
Test name
Test status
Simulation time 150734178 ps
CPU time 4.8 seconds
Started Aug 09 07:18:00 PM PDT 24
Finished Aug 09 07:18:05 PM PDT 24
Peak memory 216640 kb
Host smart-949a1e74-26db-44ee-b2cd-26ce5e30917e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455274847 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.3455274847 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.963147578
Short name T139
Test name
Test status
Simulation time 162396105 ps
CPU time 1.72 seconds
Started Aug 09 07:18:07 PM PDT 24
Finished Aug 09 07:18:09 PM PDT 24
Peak memory 217580 kb
Host smart-91009062-bf24-400c-9a4e-683fceee60a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963147578 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.kmac_csr_mem_rw_with_rand_reset.963147578 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_csr_rw.3144087868
Short name T1143
Test name
Test status
Simulation time 72408621 ps
CPU time 1.05 seconds
Started Aug 09 07:18:01 PM PDT 24
Finished Aug 09 07:18:02 PM PDT 24
Peak memory 216220 kb
Host smart-75d9b9c3-d984-4f5c-b972-2a6e50897295
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144087868 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.3144087868 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_intr_test.2870390623
Short name T169
Test name
Test status
Simulation time 35206644 ps
CPU time 0.79 seconds
Started Aug 09 07:18:00 PM PDT 24
Finished Aug 09 07:18:01 PM PDT 24
Peak memory 216256 kb
Host smart-5b644c84-6b85-4c1d-ae11-5e03b9fabfbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870390623 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.2870390623 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.3665354241
Short name T159
Test name
Test status
Simulation time 363955251 ps
CPU time 1.85 seconds
Started Aug 09 07:18:01 PM PDT 24
Finished Aug 09 07:18:03 PM PDT 24
Peak memory 216528 kb
Host smart-ff6e32ee-1b46-464b-889f-ef88ee64d4a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665354241 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr
_outstanding.3665354241 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.2550884790
Short name T1174
Test name
Test status
Simulation time 35387565 ps
CPU time 1.22 seconds
Started Aug 09 07:18:00 PM PDT 24
Finished Aug 09 07:18:01 PM PDT 24
Peak memory 216784 kb
Host smart-4aa4e671-5d56-49a9-9249-66fc99fc926f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550884790 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_
errors.2550884790 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.2184031758
Short name T1096
Test name
Test status
Simulation time 139238192 ps
CPU time 3.24 seconds
Started Aug 09 07:18:02 PM PDT 24
Finished Aug 09 07:18:05 PM PDT 24
Peak memory 219388 kb
Host smart-e8abf5fb-1b81-4929-98fd-44905e93894b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184031758 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac
_shadow_reg_errors_with_csr_rw.2184031758 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_tl_errors.3303345541
Short name T1138
Test name
Test status
Simulation time 587369599 ps
CPU time 4.11 seconds
Started Aug 09 07:17:58 PM PDT 24
Finished Aug 09 07:18:02 PM PDT 24
Peak memory 216628 kb
Host smart-2ea1ba34-5b6c-4d05-9824-a321a66bee25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303345541 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.3303345541 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.1410483384
Short name T1161
Test name
Test status
Simulation time 451047702 ps
CPU time 2.58 seconds
Started Aug 09 07:17:58 PM PDT 24
Finished Aug 09 07:18:01 PM PDT 24
Peak memory 216492 kb
Host smart-e2c17122-a137-456c-8238-ddbb9d18484b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410483384 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.14104
83384 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.628464062
Short name T1107
Test name
Test status
Simulation time 76115162 ps
CPU time 1.58 seconds
Started Aug 09 07:18:03 PM PDT 24
Finished Aug 09 07:18:05 PM PDT 24
Peak memory 218908 kb
Host smart-e83fc6ef-7436-48a2-9ca4-33a4d8a90b55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628464062 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.kmac_csr_mem_rw_with_rand_reset.628464062 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_csr_rw.1184503057
Short name T1182
Test name
Test status
Simulation time 31416029 ps
CPU time 1.19 seconds
Started Aug 09 07:18:02 PM PDT 24
Finished Aug 09 07:18:03 PM PDT 24
Peak memory 216468 kb
Host smart-f51f794e-0b9e-4911-a1dd-ab5f5dd5e619
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184503057 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.1184503057 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_intr_test.3837295497
Short name T1055
Test name
Test status
Simulation time 16901586 ps
CPU time 0.8 seconds
Started Aug 09 07:18:05 PM PDT 24
Finished Aug 09 07:18:05 PM PDT 24
Peak memory 216316 kb
Host smart-14e9cebe-af38-4796-be16-be0cd670df8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837295497 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.3837295497 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.3634076031
Short name T1070
Test name
Test status
Simulation time 126471146 ps
CPU time 2.93 seconds
Started Aug 09 07:18:04 PM PDT 24
Finished Aug 09 07:18:07 PM PDT 24
Peak memory 216504 kb
Host smart-43e49218-13c0-49e4-8788-f6726de2b057
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634076031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr
_outstanding.3634076031 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.206316735
Short name T1160
Test name
Test status
Simulation time 34177246 ps
CPU time 1.18 seconds
Started Aug 09 07:18:05 PM PDT 24
Finished Aug 09 07:18:06 PM PDT 24
Peak memory 217052 kb
Host smart-50ef45fb-6123-4757-a5e8-66dc5a6f20c2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206316735 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_e
rrors.206316735 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.2320204361
Short name T95
Test name
Test status
Simulation time 63232139 ps
CPU time 1.64 seconds
Started Aug 09 07:18:05 PM PDT 24
Finished Aug 09 07:18:07 PM PDT 24
Peak memory 216508 kb
Host smart-0fd39c2f-d90d-47d2-854e-9ebcc9d56f71
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320204361 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac
_shadow_reg_errors_with_csr_rw.2320204361 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_tl_errors.2473194368
Short name T1169
Test name
Test status
Simulation time 1908075553 ps
CPU time 3.91 seconds
Started Aug 09 07:18:04 PM PDT 24
Finished Aug 09 07:18:08 PM PDT 24
Peak memory 216680 kb
Host smart-6b2327db-88d1-4efb-a2b7-9d3819a7b4d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473194368 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.2473194368 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.3160979617
Short name T1181
Test name
Test status
Simulation time 177893081 ps
CPU time 4.21 seconds
Started Aug 09 07:18:04 PM PDT 24
Finished Aug 09 07:18:08 PM PDT 24
Peak memory 216572 kb
Host smart-eee2b150-7df2-4731-916b-54e3439432fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160979617 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.31609
79617 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.1971487881
Short name T1056
Test name
Test status
Simulation time 60933015 ps
CPU time 2.59 seconds
Started Aug 09 07:18:03 PM PDT 24
Finished Aug 09 07:18:06 PM PDT 24
Peak memory 220940 kb
Host smart-47f3a78f-140a-404a-a1f6-7a9cb11536b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971487881 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.kmac_csr_mem_rw_with_rand_reset.1971487881 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_csr_rw.3358961075
Short name T1158
Test name
Test status
Simulation time 22902458 ps
CPU time 1.14 seconds
Started Aug 09 07:18:04 PM PDT 24
Finished Aug 09 07:18:05 PM PDT 24
Peak memory 216228 kb
Host smart-b69221c5-2c09-4c0d-b3d5-ec9b7d44cf2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358961075 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.3358961075 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_intr_test.4282629740
Short name T1184
Test name
Test status
Simulation time 52015162 ps
CPU time 0.86 seconds
Started Aug 09 07:18:05 PM PDT 24
Finished Aug 09 07:18:06 PM PDT 24
Peak memory 216320 kb
Host smart-40f0ec8a-b695-4ec2-95e3-6f7b3e0b404c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282629740 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.4282629740 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.2558956986
Short name T1188
Test name
Test status
Simulation time 24255960 ps
CPU time 1.42 seconds
Started Aug 09 07:18:03 PM PDT 24
Finished Aug 09 07:18:05 PM PDT 24
Peak memory 216508 kb
Host smart-719b2904-33b5-4eb8-9feb-c257eb29424e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558956986 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr
_outstanding.2558956986 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.144580219
Short name T1068
Test name
Test status
Simulation time 31269794 ps
CPU time 1.06 seconds
Started Aug 09 07:18:07 PM PDT 24
Finished Aug 09 07:18:08 PM PDT 24
Peak memory 216508 kb
Host smart-fcb38dd0-657e-4bcf-ab5d-e3190fe34def
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144580219 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_e
rrors.144580219 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.2302635163
Short name T1178
Test name
Test status
Simulation time 107845265 ps
CPU time 2.59 seconds
Started Aug 09 07:18:04 PM PDT 24
Finished Aug 09 07:18:07 PM PDT 24
Peak memory 219380 kb
Host smart-50d0ee48-f6f1-4e73-a58c-da7006f8d90e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302635163 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac
_shadow_reg_errors_with_csr_rw.2302635163 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_tl_errors.2988227454
Short name T1170
Test name
Test status
Simulation time 59786792 ps
CPU time 3.68 seconds
Started Aug 09 07:18:05 PM PDT 24
Finished Aug 09 07:18:09 PM PDT 24
Peak memory 216640 kb
Host smart-72046722-4684-49b0-8cca-d16fcb89af8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988227454 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.2988227454 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.3481867852
Short name T176
Test name
Test status
Simulation time 473267565 ps
CPU time 3.16 seconds
Started Aug 09 07:18:02 PM PDT 24
Finished Aug 09 07:18:05 PM PDT 24
Peak memory 216516 kb
Host smart-111dd971-7cfe-45b6-a8cb-119765dcf2c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481867852 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.34818
67852 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.2502252773
Short name T148
Test name
Test status
Simulation time 71726633 ps
CPU time 2.35 seconds
Started Aug 09 07:18:11 PM PDT 24
Finished Aug 09 07:18:14 PM PDT 24
Peak memory 221212 kb
Host smart-b4eb187d-473a-442d-a2c2-d0a9a2add885
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502252773 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.kmac_csr_mem_rw_with_rand_reset.2502252773 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_csr_rw.676232511
Short name T1168
Test name
Test status
Simulation time 33100634 ps
CPU time 0.97 seconds
Started Aug 09 07:18:05 PM PDT 24
Finished Aug 09 07:18:06 PM PDT 24
Peak memory 216244 kb
Host smart-1f1241a2-37a8-4141-81c8-f5f11c7f5620
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676232511 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.676232511 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/9.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_intr_test.3331180212
Short name T1133
Test name
Test status
Simulation time 47068251 ps
CPU time 0.86 seconds
Started Aug 09 07:18:03 PM PDT 24
Finished Aug 09 07:18:04 PM PDT 24
Peak memory 216316 kb
Host smart-2d8f1ade-bce6-4b12-9b4a-d751337e411f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331180212 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.3331180212 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.1290085345
Short name T1118
Test name
Test status
Simulation time 194730865 ps
CPU time 1.62 seconds
Started Aug 09 07:18:12 PM PDT 24
Finished Aug 09 07:18:14 PM PDT 24
Peak memory 216540 kb
Host smart-1c9bdea5-96b5-4761-95cc-446afef1013f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290085345 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr
_outstanding.1290085345 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.3792639576
Short name T101
Test name
Test status
Simulation time 163985650 ps
CPU time 0.95 seconds
Started Aug 09 07:18:03 PM PDT 24
Finished Aug 09 07:18:04 PM PDT 24
Peak memory 216568 kb
Host smart-6d998647-5937-456e-87f9-01e11c6b1525
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792639576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_
errors.3792639576 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.871331544
Short name T1069
Test name
Test status
Simulation time 105174918 ps
CPU time 2.62 seconds
Started Aug 09 07:18:06 PM PDT 24
Finished Aug 09 07:18:09 PM PDT 24
Peak memory 220352 kb
Host smart-fe2bfa86-e06b-4eeb-b7b1-ffbb6017bbf0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871331544 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_
shadow_reg_errors_with_csr_rw.871331544 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_tl_errors.2283647363
Short name T1102
Test name
Test status
Simulation time 59600876 ps
CPU time 1.9 seconds
Started Aug 09 07:18:07 PM PDT 24
Finished Aug 09 07:18:09 PM PDT 24
Peak memory 216528 kb
Host smart-82bb8c63-0772-41d8-b569-92b4b33fd1d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283647363 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.2283647363 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.1700076642
Short name T1185
Test name
Test status
Simulation time 230327724 ps
CPU time 5.17 seconds
Started Aug 09 07:18:03 PM PDT 24
Finished Aug 09 07:18:09 PM PDT 24
Peak memory 216548 kb
Host smart-ca24c6b4-00d0-47f4-b0b8-cdaab13fab69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700076642 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.17000
76642 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.kmac_app.4091180049
Short name T235
Test name
Test status
Simulation time 3526036815 ps
CPU time 149.87 seconds
Started Aug 09 05:53:25 PM PDT 24
Finished Aug 09 05:55:55 PM PDT 24
Peak memory 277272 kb
Host smart-6eb60f4b-761f-45c3-b203-6268af288498
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091180049 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.4091180049 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/0.kmac_app/latest

Test location /workspace/coverage/default/0.kmac_app_with_partial_data.3758998985
Short name T355
Test name
Test status
Simulation time 121899693057 ps
CPU time 134.25 seconds
Started Aug 09 05:53:22 PM PDT 24
Finished Aug 09 05:55:36 PM PDT 24
Peak memory 307564 kb
Host smart-c63ce8a5-79ec-4c55-a873-7c5a68bad19d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758998985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_par
tial_data.3758998985 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/0.kmac_burst_write.3428476287
Short name T913
Test name
Test status
Simulation time 25328810774 ps
CPU time 695.14 seconds
Started Aug 09 05:53:25 PM PDT 24
Finished Aug 09 06:05:01 PM PDT 24
Peak memory 244284 kb
Host smart-ad60b813-d93b-4840-be17-2fc2b38d18c1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428476287 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.3428476287
+enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_burst_write/latest

Test location /workspace/coverage/default/0.kmac_entropy_mode_error.1832165435
Short name T922
Test name
Test status
Simulation time 23176730 ps
CPU time 0.99 seconds
Started Aug 09 05:53:23 PM PDT 24
Finished Aug 09 05:53:25 PM PDT 24
Peak memory 222012 kb
Host smart-cf571a59-0fa9-40d4-a318-a7b57954a499
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1832165435 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.1832165435 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_ready_error.1712019721
Short name T358
Test name
Test status
Simulation time 66493995640 ps
CPU time 67.57 seconds
Started Aug 09 05:53:23 PM PDT 24
Finished Aug 09 05:54:31 PM PDT 24
Peak memory 224396 kb
Host smart-5da7ce7a-680d-42c5-b5b8-acf07e3563e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712019721 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.1712019721 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_refresh.246034169
Short name T1028
Test name
Test status
Simulation time 22132008608 ps
CPU time 282.07 seconds
Started Aug 09 05:53:26 PM PDT 24
Finished Aug 09 05:58:08 PM PDT 24
Peak memory 414620 kb
Host smart-bc1142bc-5e8f-462f-ade7-e43b91e782d5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246034169 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.246
034169 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/0.kmac_error.641237542
Short name T21
Test name
Test status
Simulation time 26096128057 ps
CPU time 455.52 seconds
Started Aug 09 05:53:22 PM PDT 24
Finished Aug 09 06:00:57 PM PDT 24
Peak memory 568812 kb
Host smart-3ca6344b-ebeb-4fd4-a33c-d8fe0008d0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641237542 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.641237542 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_error/latest

Test location /workspace/coverage/default/0.kmac_key_error.3664675984
Short name T323
Test name
Test status
Simulation time 5510215269 ps
CPU time 11.92 seconds
Started Aug 09 05:53:22 PM PDT 24
Finished Aug 09 05:53:34 PM PDT 24
Peak memory 226760 kb
Host smart-9e626662-7f50-42fa-985a-43fb990150b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664675984 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.3664675984 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_key_error/latest

Test location /workspace/coverage/default/0.kmac_long_msg_and_output.3426710127
Short name T289
Test name
Test status
Simulation time 21148205984 ps
CPU time 900.73 seconds
Started Aug 09 05:53:24 PM PDT 24
Finished Aug 09 06:08:25 PM PDT 24
Peak memory 1159108 kb
Host smart-cbe8d535-c018-405f-a374-d96c68fc2428
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426710127 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_an
d_output.3426710127 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/0.kmac_mubi.1141368743
Short name T694
Test name
Test status
Simulation time 9407459108 ps
CPU time 315.57 seconds
Started Aug 09 05:53:24 PM PDT 24
Finished Aug 09 05:58:40 PM PDT 24
Peak memory 449516 kb
Host smart-27b236b2-6200-4d86-a640-49602c34b768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141368743 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.1141368743 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_mubi/latest

Test location /workspace/coverage/default/0.kmac_sec_cm.2498450989
Short name T124
Test name
Test status
Simulation time 64461065421 ps
CPU time 90.92 seconds
Started Aug 09 05:53:23 PM PDT 24
Finished Aug 09 05:54:54 PM PDT 24
Peak memory 284628 kb
Host smart-48d4cab4-640d-4eab-aa95-87c0b79c16ec
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498450989 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.2498450989 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspace/0.kmac_sec_cm/latest

Test location /workspace/coverage/default/0.kmac_sideload.824492155
Short name T764
Test name
Test status
Simulation time 3665034551 ps
CPU time 189.31 seconds
Started Aug 09 05:53:25 PM PDT 24
Finished Aug 09 05:56:35 PM PDT 24
Peak memory 287456 kb
Host smart-aa5876ed-d5ad-4f6c-975f-dd041d8f6767
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824492155 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.824492155 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_sideload/latest

Test location /workspace/coverage/default/0.kmac_smoke.3125018260
Short name T788
Test name
Test status
Simulation time 95875395 ps
CPU time 2.62 seconds
Started Aug 09 05:53:25 PM PDT 24
Finished Aug 09 05:53:28 PM PDT 24
Peak memory 226520 kb
Host smart-53272942-a2f9-4fdd-a4ce-9bfa8740230d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125018260 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.3125018260 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_smoke/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_kmac.208283493
Short name T826
Test name
Test status
Simulation time 183919849 ps
CPU time 6.12 seconds
Started Aug 09 05:53:25 PM PDT 24
Finished Aug 09 05:53:31 PM PDT 24
Peak memory 219792 kb
Host smart-6b1359f2-4850-4f21-902f-f13c64e410db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208283493 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.kmac_test_vectors_kmac.208283493 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_kmac_xof.1796702083
Short name T523
Test name
Test status
Simulation time 767511171 ps
CPU time 6.42 seconds
Started Aug 09 05:53:24 PM PDT 24
Finished Aug 09 05:53:31 PM PDT 24
Peak memory 219788 kb
Host smart-df4259a1-d52d-4210-bafc-a87095adde1a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796702083 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.kmac_test_vectors_kmac_xof.1796702083 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_224.3399640691
Short name T294
Test name
Test status
Simulation time 1377398816011 ps
CPU time 4236.91 seconds
Started Aug 09 05:53:22 PM PDT 24
Finished Aug 09 07:04:00 PM PDT 24
Peak memory 3212984 kb
Host smart-331da743-545e-4277-8c9b-56325ae04bf7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3399640691 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.3399640691 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_256.3913752686
Short name T421
Test name
Test status
Simulation time 298818786080 ps
CPU time 3336 seconds
Started Aug 09 05:53:29 PM PDT 24
Finished Aug 09 06:49:06 PM PDT 24
Peak memory 3093820 kb
Host smart-eb4393fb-e413-44d4-98fe-0c93dc22ae19
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3913752686 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.3913752686 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_384.637817984
Short name T234
Test name
Test status
Simulation time 75406130040 ps
CPU time 2486.13 seconds
Started Aug 09 05:53:25 PM PDT 24
Finished Aug 09 06:34:51 PM PDT 24
Peak memory 2336704 kb
Host smart-163c3966-2c4c-4b9a-9a5e-e353f6f21a35
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=637817984 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.637817984 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_512.3774022391
Short name T375
Test name
Test status
Simulation time 112151756933 ps
CPU time 1812.58 seconds
Started Aug 09 05:53:24 PM PDT 24
Finished Aug 09 06:23:37 PM PDT 24
Peak memory 1764836 kb
Host smart-50dbc83f-6d83-49b5-bdbb-8d3b54015d1e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3774022391 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.3774022391 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_shake_128.936165626
Short name T497
Test name
Test status
Simulation time 126511032912 ps
CPU time 6614.16 seconds
Started Aug 09 05:53:23 PM PDT 24
Finished Aug 09 07:43:38 PM PDT 24
Peak memory 2724008 kb
Host smart-5d85ce1b-5699-4c83-b830-e08e624c8aa9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=936165626 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.936165626 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_shake_256.1681697882
Short name T113
Test name
Test status
Simulation time 939881005142 ps
CPU time 10678.8 seconds
Started Aug 09 05:53:21 PM PDT 24
Finished Aug 09 08:51:21 PM PDT 24
Peak memory 6318432 kb
Host smart-77df29dd-0c4f-4d60-862a-c49120ab6612
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1681697882 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.1681697882 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/1.kmac_alert_test.4209006231
Short name T798
Test name
Test status
Simulation time 125699694 ps
CPU time 0.89 seconds
Started Aug 09 05:53:30 PM PDT 24
Finished Aug 09 05:53:31 PM PDT 24
Peak memory 218588 kb
Host smart-6ade74d9-1409-48aa-9cc1-72dc2ae657e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209006231 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.4209006231 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_alert_test/latest

Test location /workspace/coverage/default/1.kmac_app.2139190320
Short name T992
Test name
Test status
Simulation time 6362740859 ps
CPU time 44.76 seconds
Started Aug 09 05:53:39 PM PDT 24
Finished Aug 09 05:54:24 PM PDT 24
Peak memory 253696 kb
Host smart-b501bb80-850d-4c59-a6d6-eecafd5bcee9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139190320 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.2139190320 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/1.kmac_app/latest

Test location /workspace/coverage/default/1.kmac_app_with_partial_data.117154293
Short name T110
Test name
Test status
Simulation time 543154248 ps
CPU time 9.58 seconds
Started Aug 09 05:53:29 PM PDT 24
Finished Aug 09 05:53:39 PM PDT 24
Peak memory 235252 kb
Host smart-c22093b1-a730-45fe-8cde-dc0a4a0f2913
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117154293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_parti
al_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_part
ial_data.117154293 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/1.kmac_burst_write.1836818762
Short name T581
Test name
Test status
Simulation time 95800568141 ps
CPU time 1426.01 seconds
Started Aug 09 05:53:23 PM PDT 24
Finished Aug 09 06:17:09 PM PDT 24
Peak memory 248440 kb
Host smart-a3a97e4d-5d4a-4852-9374-45d591720ee2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836818762 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.1836818762
+enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_burst_write/latest

Test location /workspace/coverage/default/1.kmac_edn_timeout_error.3925710157
Short name T686
Test name
Test status
Simulation time 19292748 ps
CPU time 0.94 seconds
Started Aug 09 05:53:32 PM PDT 24
Finished Aug 09 05:53:33 PM PDT 24
Peak memory 218436 kb
Host smart-11b0c383-c158-479a-8a52-7bb84d527c9a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3925710157 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.3925710157 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_refresh.2336817202
Short name T968
Test name
Test status
Simulation time 17119206548 ps
CPU time 115.61 seconds
Started Aug 09 05:53:34 PM PDT 24
Finished Aug 09 05:55:29 PM PDT 24
Peak memory 296092 kb
Host smart-62383e9f-fd73-4bc0-9eac-fc17f0307ed8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336817202 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.23
36817202 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/1.kmac_key_error.896771038
Short name T840
Test name
Test status
Simulation time 1020326417 ps
CPU time 7.64 seconds
Started Aug 09 05:53:31 PM PDT 24
Finished Aug 09 05:53:39 PM PDT 24
Peak memory 226692 kb
Host smart-15b30aab-58d9-484d-b5b3-b18aa0601bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896771038 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.896771038 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_key_error/latest

Test location /workspace/coverage/default/1.kmac_lc_escalation.1596331641
Short name T423
Test name
Test status
Simulation time 138472078 ps
CPU time 4.75 seconds
Started Aug 09 05:53:29 PM PDT 24
Finished Aug 09 05:53:34 PM PDT 24
Peak memory 235096 kb
Host smart-7f8d72ea-1c29-46ea-8e98-c46f8060357d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596331641 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.1596331641 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/1.kmac_lc_escalation/latest

Test location /workspace/coverage/default/1.kmac_long_msg_and_output.3745892634
Short name T263
Test name
Test status
Simulation time 99030177436 ps
CPU time 4697.55 seconds
Started Aug 09 05:53:25 PM PDT 24
Finished Aug 09 07:11:43 PM PDT 24
Peak memory 3659148 kb
Host smart-eca452ae-c1ea-4ece-a966-e4d3efa0b468
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745892634 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_an
d_output.3745892634 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/1.kmac_mubi.3800246094
Short name T443
Test name
Test status
Simulation time 17138438258 ps
CPU time 78.65 seconds
Started Aug 09 05:53:34 PM PDT 24
Finished Aug 09 05:54:53 PM PDT 24
Peak memory 276848 kb
Host smart-c3057bfe-df7a-40fd-8e17-801ce9ef701b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800246094 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.3800246094 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_mubi/latest

Test location /workspace/coverage/default/1.kmac_sec_cm.952023918
Short name T86
Test name
Test status
Simulation time 6698392920 ps
CPU time 84.14 seconds
Started Aug 09 05:53:31 PM PDT 24
Finished Aug 09 05:54:55 PM PDT 24
Peak memory 279396 kb
Host smart-97b78a07-d343-4c06-81d4-11b248445e97
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952023918 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.952023918 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/1.kmac_sec_cm/latest

Test location /workspace/coverage/default/1.kmac_sideload.1820986567
Short name T493
Test name
Test status
Simulation time 62638553533 ps
CPU time 590.61 seconds
Started Aug 09 05:53:27 PM PDT 24
Finished Aug 09 06:03:18 PM PDT 24
Peak memory 624540 kb
Host smart-ed0b247d-bada-4ee7-a2cb-393e84e95021
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820986567 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.1820986567 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_sideload/latest

Test location /workspace/coverage/default/1.kmac_smoke.2994299813
Short name T433
Test name
Test status
Simulation time 21997576162 ps
CPU time 56.73 seconds
Started Aug 09 05:53:25 PM PDT 24
Finished Aug 09 05:54:21 PM PDT 24
Peak memory 226864 kb
Host smart-6a61c804-ee98-49f5-a6ba-127622e73906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994299813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.2994299813 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_smoke/latest

Test location /workspace/coverage/default/1.kmac_stress_all.199098316
Short name T61
Test name
Test status
Simulation time 96023611074 ps
CPU time 2122.46 seconds
Started Aug 09 05:53:32 PM PDT 24
Finished Aug 09 06:28:55 PM PDT 24
Peak memory 813320 kb
Host smart-ce286299-6ca6-4ee0-b64f-cc6febb05e3e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=199098316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.199098316 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_stress_all/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_kmac.520592167
Short name T224
Test name
Test status
Simulation time 565829817 ps
CPU time 5.75 seconds
Started Aug 09 05:53:26 PM PDT 24
Finished Aug 09 05:53:31 PM PDT 24
Peak memory 219776 kb
Host smart-cc746991-5744-471d-9e85-8961be14c19c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520592167 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.kmac_test_vectors_kmac.520592167 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_kmac_xof.3347380750
Short name T207
Test name
Test status
Simulation time 106535726 ps
CPU time 5.73 seconds
Started Aug 09 05:53:32 PM PDT 24
Finished Aug 09 05:53:38 PM PDT 24
Peak memory 219844 kb
Host smart-2303a60e-c2b6-4326-83fe-6b81079038f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347380750 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.kmac_test_vectors_kmac_xof.3347380750 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_224.2548475123
Short name T831
Test name
Test status
Simulation time 68845462781 ps
CPU time 2154.52 seconds
Started Aug 09 05:53:26 PM PDT 24
Finished Aug 09 06:29:20 PM PDT 24
Peak memory 1175756 kb
Host smart-e5208af5-9980-43eb-a23e-01b44fc8b7ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2548475123 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.2548475123 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_256.810623590
Short name T947
Test name
Test status
Simulation time 39720163642 ps
CPU time 2138.31 seconds
Started Aug 09 05:53:25 PM PDT 24
Finished Aug 09 06:29:04 PM PDT 24
Peak memory 1132476 kb
Host smart-a9eab5bf-dcdd-4089-be25-0ba0932b90c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=810623590 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.810623590 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_384.2844852373
Short name T209
Test name
Test status
Simulation time 16572029661 ps
CPU time 1650.74 seconds
Started Aug 09 05:53:28 PM PDT 24
Finished Aug 09 06:20:59 PM PDT 24
Peak memory 919336 kb
Host smart-4058bae7-2ed2-4fbb-bfa4-9c37d4747f00
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2844852373 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.2844852373 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_512.57906272
Short name T459
Test name
Test status
Simulation time 88912511934 ps
CPU time 1875.43 seconds
Started Aug 09 05:53:23 PM PDT 24
Finished Aug 09 06:24:39 PM PDT 24
Peak memory 1746624 kb
Host smart-2e726823-1944-4de9-bcd2-d916ff3321d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=57906272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.57906272 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_shake_256.1168265037
Short name T527
Test name
Test status
Simulation time 281536868301 ps
CPU time 9698.81 seconds
Started Aug 09 05:53:27 PM PDT 24
Finished Aug 09 08:35:08 PM PDT 24
Peak memory 6424128 kb
Host smart-757d15a9-781f-487a-887a-22ae6d3092ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1168265037 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.1168265037 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/10.kmac_alert_test.1348133318
Short name T895
Test name
Test status
Simulation time 41654838 ps
CPU time 0.82 seconds
Started Aug 09 05:54:09 PM PDT 24
Finished Aug 09 05:54:09 PM PDT 24
Peak memory 218428 kb
Host smart-396b0e9c-5aa2-40b7-a896-66569bf2f303
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348133318 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.1348133318 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_alert_test/latest

Test location /workspace/coverage/default/10.kmac_app.272842739
Short name T370
Test name
Test status
Simulation time 19567582326 ps
CPU time 182.65 seconds
Started Aug 09 05:54:03 PM PDT 24
Finished Aug 09 05:57:06 PM PDT 24
Peak memory 356448 kb
Host smart-eabadc26-626b-4cd2-bba2-4b449c46265e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272842739 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.272842739 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/10.kmac_app/latest

Test location /workspace/coverage/default/10.kmac_burst_write.2887721912
Short name T732
Test name
Test status
Simulation time 39918506718 ps
CPU time 1743.32 seconds
Started Aug 09 05:54:05 PM PDT 24
Finished Aug 09 06:23:09 PM PDT 24
Peak memory 268956 kb
Host smart-66c82dcc-bac7-4d8e-b65d-a66f8de4c11e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887721912 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.288772191
2 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_burst_write/latest

Test location /workspace/coverage/default/10.kmac_edn_timeout_error.3775055557
Short name T1037
Test name
Test status
Simulation time 1681780142 ps
CPU time 13.52 seconds
Started Aug 09 05:54:06 PM PDT 24
Finished Aug 09 05:54:20 PM PDT 24
Peak memory 222512 kb
Host smart-b1c4e951-7eaa-4013-92b5-2bb74cf32c63
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3775055557 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.3775055557 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/10.kmac_entropy_mode_error.4142434778
Short name T524
Test name
Test status
Simulation time 68487087 ps
CPU time 0.98 seconds
Started Aug 09 05:54:07 PM PDT 24
Finished Aug 09 05:54:08 PM PDT 24
Peak memory 221572 kb
Host smart-76104328-6306-406b-92eb-d6f545e9c15c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4142434778 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.4142434778 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/10.kmac_entropy_refresh.152912819
Short name T832
Test name
Test status
Simulation time 9610066895 ps
CPU time 76.8 seconds
Started Aug 09 05:54:12 PM PDT 24
Finished Aug 09 05:55:29 PM PDT 24
Peak memory 247060 kb
Host smart-ac99a3b8-d495-43d1-a4f9-a84a30d13a90
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152912819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.15
2912819 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/10.kmac_error.393336272
Short name T407
Test name
Test status
Simulation time 56693942991 ps
CPU time 129.91 seconds
Started Aug 09 05:54:08 PM PDT 24
Finished Aug 09 05:56:18 PM PDT 24
Peak memory 334332 kb
Host smart-029b7232-532c-45d2-80e7-311443b99a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393336272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.393336272 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_error/latest

Test location /workspace/coverage/default/10.kmac_key_error.2372623502
Short name T428
Test name
Test status
Simulation time 274371480 ps
CPU time 1.92 seconds
Started Aug 09 05:54:08 PM PDT 24
Finished Aug 09 05:54:10 PM PDT 24
Peak memory 226652 kb
Host smart-debde721-b8b2-4347-9cf9-0aa8b053d3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372623502 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.2372623502 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_key_error/latest

Test location /workspace/coverage/default/10.kmac_long_msg_and_output.1448975726
Short name T189
Test name
Test status
Simulation time 26416448560 ps
CPU time 1473.79 seconds
Started Aug 09 05:54:02 PM PDT 24
Finished Aug 09 06:18:36 PM PDT 24
Peak memory 954360 kb
Host smart-b6a1af88-1f3b-414a-9fce-330f595cd07b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448975726 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_a
nd_output.1448975726 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/10.kmac_sideload.2221331518
Short name T327
Test name
Test status
Simulation time 12073899269 ps
CPU time 454.87 seconds
Started Aug 09 05:53:59 PM PDT 24
Finished Aug 09 06:01:34 PM PDT 24
Peak memory 386964 kb
Host smart-09c37faa-c981-4ded-886a-80dfb3e28f75
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221331518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.2221331518 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_sideload/latest

Test location /workspace/coverage/default/10.kmac_smoke.1429812261
Short name T956
Test name
Test status
Simulation time 8344478039 ps
CPU time 80.55 seconds
Started Aug 09 05:54:02 PM PDT 24
Finished Aug 09 05:55:23 PM PDT 24
Peak memory 223492 kb
Host smart-c1d2fc16-c18a-4328-b842-0c0ea43b9dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429812261 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.1429812261 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_smoke/latest

Test location /workspace/coverage/default/10.kmac_stress_all.26276788
Short name T623
Test name
Test status
Simulation time 2068367725 ps
CPU time 162.52 seconds
Started Aug 09 05:54:07 PM PDT 24
Finished Aug 09 05:56:49 PM PDT 24
Peak memory 264788 kb
Host smart-78bba5d8-8dd4-4d01-8259-008b645d0a63
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=26276788 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.26276788 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_stress_all/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_kmac.746970995
Short name T376
Test name
Test status
Simulation time 535906088 ps
CPU time 7.05 seconds
Started Aug 09 05:54:01 PM PDT 24
Finished Aug 09 05:54:08 PM PDT 24
Peak memory 220116 kb
Host smart-32928f20-cdb0-4eb5-9431-3f93891e4a83
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746970995 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.kmac_test_vectors_kmac.746970995 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_kmac_xof.4011668214
Short name T762
Test name
Test status
Simulation time 1829768091 ps
CPU time 7.36 seconds
Started Aug 09 05:54:03 PM PDT 24
Finished Aug 09 05:54:11 PM PDT 24
Peak memory 218932 kb
Host smart-1537ad04-b5dc-490c-8960-a7f3fed49c71
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011668214 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.kmac_test_vectors_kmac_xof.4011668214 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_224.3418786098
Short name T588
Test name
Test status
Simulation time 42622226900 ps
CPU time 2351.23 seconds
Started Aug 09 05:54:05 PM PDT 24
Finished Aug 09 06:33:16 PM PDT 24
Peak memory 1203336 kb
Host smart-1d502bfe-a284-472a-b309-6315a074a67e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3418786098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_224.3418786098 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_256.2655199685
Short name T622
Test name
Test status
Simulation time 261755814473 ps
CPU time 3016.58 seconds
Started Aug 09 05:54:06 PM PDT 24
Finished Aug 09 06:44:24 PM PDT 24
Peak memory 3100960 kb
Host smart-34c176d3-f072-41c3-9e3d-3a1e4ebd9f78
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2655199685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_256.2655199685 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_384.1247096743
Short name T474
Test name
Test status
Simulation time 187711949688 ps
CPU time 2330.63 seconds
Started Aug 09 05:54:01 PM PDT 24
Finished Aug 09 06:32:52 PM PDT 24
Peak memory 2363036 kb
Host smart-f067107b-a334-420f-8161-ebd373d357d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1247096743 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_384.1247096743 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_512.3776091489
Short name T48
Test name
Test status
Simulation time 13924891867 ps
CPU time 1281.5 seconds
Started Aug 09 05:54:05 PM PDT 24
Finished Aug 09 06:15:27 PM PDT 24
Peak memory 714924 kb
Host smart-30d463fc-2116-4f82-86e6-ed7d9742a446
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3776091489 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_512.3776091489 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_shake_128.4086446773
Short name T65
Test name
Test status
Simulation time 67075985496 ps
CPU time 6055.73 seconds
Started Aug 09 05:54:01 PM PDT 24
Finished Aug 09 07:34:58 PM PDT 24
Peak memory 2717068 kb
Host smart-489714d4-76e6-4171-8c93-dc6ba0a127dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4086446773 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_shake_128.4086446773 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/11.kmac_alert_test.1128240019
Short name T653
Test name
Test status
Simulation time 35186504 ps
CPU time 0.86 seconds
Started Aug 09 05:54:05 PM PDT 24
Finished Aug 09 05:54:06 PM PDT 24
Peak memory 218468 kb
Host smart-c066574c-c8f5-4bc3-86ba-a9b3cd29e81b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128240019 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.1128240019 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_alert_test/latest

Test location /workspace/coverage/default/11.kmac_app.4004841127
Short name T636
Test name
Test status
Simulation time 7521518642 ps
CPU time 121.82 seconds
Started Aug 09 05:54:09 PM PDT 24
Finished Aug 09 05:56:11 PM PDT 24
Peak memory 313836 kb
Host smart-b545f96f-cefc-436a-9122-7ac1aafc6e5f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004841127 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.4004841127 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/11.kmac_app/latest

Test location /workspace/coverage/default/11.kmac_burst_write.2178976507
Short name T716
Test name
Test status
Simulation time 31323312829 ps
CPU time 929.92 seconds
Started Aug 09 05:54:12 PM PDT 24
Finished Aug 09 06:09:42 PM PDT 24
Peak memory 250432 kb
Host smart-3bebc32d-cfc6-4cd4-a3e5-9b22f9c313dc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178976507 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.217897650
7 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_burst_write/latest

Test location /workspace/coverage/default/11.kmac_edn_timeout_error.1828195149
Short name T255
Test name
Test status
Simulation time 177124772 ps
CPU time 3.63 seconds
Started Aug 09 05:54:03 PM PDT 24
Finished Aug 09 05:54:07 PM PDT 24
Peak memory 223732 kb
Host smart-21aae955-4f96-4aea-a1a4-9b8172b36a99
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1828195149 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.1828195149 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/11.kmac_entropy_mode_error.1416721176
Short name T77
Test name
Test status
Simulation time 21901466 ps
CPU time 1.12 seconds
Started Aug 09 05:54:08 PM PDT 24
Finished Aug 09 05:54:10 PM PDT 24
Peak memory 222156 kb
Host smart-de1f0cd0-eb16-423e-b32a-ba78fa6d757a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1416721176 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.1416721176 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/11.kmac_lc_escalation.398945415
Short name T26
Test name
Test status
Simulation time 14212789041 ps
CPU time 38.5 seconds
Started Aug 09 05:54:06 PM PDT 24
Finished Aug 09 05:54:44 PM PDT 24
Peak memory 243412 kb
Host smart-19be4d51-e2b7-498b-acd1-637eb5ba1165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398945415 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.398945415 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/11.kmac_lc_escalation/latest

Test location /workspace/coverage/default/11.kmac_long_msg_and_output.755227542
Short name T558
Test name
Test status
Simulation time 90520691098 ps
CPU time 4117.92 seconds
Started Aug 09 05:54:01 PM PDT 24
Finished Aug 09 07:02:39 PM PDT 24
Peak memory 3317288 kb
Host smart-49802ad6-19e7-4b92-8d5e-b21b80ca5567
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755227542 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_an
d_output.755227542 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/11.kmac_sideload.3114775571
Short name T670
Test name
Test status
Simulation time 4032017864 ps
CPU time 168.79 seconds
Started Aug 09 05:54:08 PM PDT 24
Finished Aug 09 05:56:56 PM PDT 24
Peak memory 279936 kb
Host smart-20eaf28d-22ff-43c2-9856-1d9dfb73e88e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114775571 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.3114775571 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_sideload/latest

Test location /workspace/coverage/default/11.kmac_smoke.2037128498
Short name T3
Test name
Test status
Simulation time 293443760 ps
CPU time 6.71 seconds
Started Aug 09 05:54:02 PM PDT 24
Finished Aug 09 05:54:08 PM PDT 24
Peak memory 226612 kb
Host smart-5ced0272-3dcb-46ad-91fd-35208798be6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037128498 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.2037128498 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_smoke/latest

Test location /workspace/coverage/default/11.kmac_stress_all.4092896927
Short name T491
Test name
Test status
Simulation time 2109069632 ps
CPU time 160.39 seconds
Started Aug 09 05:54:06 PM PDT 24
Finished Aug 09 05:56:46 PM PDT 24
Peak memory 308560 kb
Host smart-a42b6d10-641b-4e6f-986e-23b22b1c763c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4092896927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.4092896927 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_stress_all/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_kmac.880461024
Short name T812
Test name
Test status
Simulation time 781184062 ps
CPU time 6.34 seconds
Started Aug 09 05:54:08 PM PDT 24
Finished Aug 09 05:54:15 PM PDT 24
Peak memory 218996 kb
Host smart-1017573b-95b1-4845-b2a0-c72ddd24d5cf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880461024 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.kmac_test_vectors_kmac.880461024 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_kmac_xof.3439240303
Short name T1009
Test name
Test status
Simulation time 125884447 ps
CPU time 5.98 seconds
Started Aug 09 05:54:09 PM PDT 24
Finished Aug 09 05:54:15 PM PDT 24
Peak memory 219880 kb
Host smart-01c6718d-9ca7-4e12-8977-b28b7cc4bcfc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439240303 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.kmac_test_vectors_kmac_xof.3439240303 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_224.3652305658
Short name T293
Test name
Test status
Simulation time 22052936590 ps
CPU time 2186.42 seconds
Started Aug 09 05:54:13 PM PDT 24
Finished Aug 09 06:30:40 PM PDT 24
Peak memory 1172356 kb
Host smart-90e46781-619a-4a19-8b86-630b30289986
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3652305658 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_224.3652305658 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_256.2243407196
Short name T801
Test name
Test status
Simulation time 380157734828 ps
CPU time 3751.31 seconds
Started Aug 09 05:54:06 PM PDT 24
Finished Aug 09 06:56:38 PM PDT 24
Peak memory 3054812 kb
Host smart-ba97c89f-588b-4849-80dc-75ae35efd4c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2243407196 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_256.2243407196 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_384.169707535
Short name T233
Test name
Test status
Simulation time 95134629544 ps
CPU time 2741.66 seconds
Started Aug 09 05:54:06 PM PDT 24
Finished Aug 09 06:39:49 PM PDT 24
Peak memory 2325500 kb
Host smart-f620c0b5-139b-474b-8b7d-a9fc826127bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=169707535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_384.169707535 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_512.3233147125
Short name T775
Test name
Test status
Simulation time 49948373765 ps
CPU time 1878.9 seconds
Started Aug 09 05:54:05 PM PDT 24
Finished Aug 09 06:25:25 PM PDT 24
Peak memory 1753504 kb
Host smart-c4d854cd-7853-4abd-a5cb-b7188e7ea83e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3233147125 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_512.3233147125 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_shake_256.915174613
Short name T363
Test name
Test status
Simulation time 594010118882 ps
CPU time 5584.98 seconds
Started Aug 09 05:54:09 PM PDT 24
Finished Aug 09 07:27:14 PM PDT 24
Peak memory 2254016 kb
Host smart-415b711e-3ba1-4ef4-96fa-aa111af58d1c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=915174613 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_256.915174613 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/12.kmac_alert_test.535897233
Short name T773
Test name
Test status
Simulation time 19718962 ps
CPU time 0.86 seconds
Started Aug 09 05:54:16 PM PDT 24
Finished Aug 09 05:54:17 PM PDT 24
Peak memory 218432 kb
Host smart-1daa4325-3b82-4bee-990c-ed3e115f0b3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535897233 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.535897233 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/12.kmac_alert_test/latest

Test location /workspace/coverage/default/12.kmac_burst_write.2291786212
Short name T290
Test name
Test status
Simulation time 6816399694 ps
CPU time 593.26 seconds
Started Aug 09 05:54:12 PM PDT 24
Finished Aug 09 06:04:05 PM PDT 24
Peak memory 237192 kb
Host smart-b6b386c5-ea08-4462-93c5-bf098e3fcc5d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291786212 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.229178621
2 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_burst_write/latest

Test location /workspace/coverage/default/12.kmac_edn_timeout_error.3312002237
Short name T306
Test name
Test status
Simulation time 23032061 ps
CPU time 0.83 seconds
Started Aug 09 05:54:13 PM PDT 24
Finished Aug 09 05:54:14 PM PDT 24
Peak memory 218472 kb
Host smart-3540b05d-8dde-4ac6-bd0a-099344af343d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3312002237 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.3312002237 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/12.kmac_entropy_mode_error.4054770105
Short name T687
Test name
Test status
Simulation time 79343641 ps
CPU time 1.08 seconds
Started Aug 09 05:54:10 PM PDT 24
Finished Aug 09 05:54:11 PM PDT 24
Peak memory 222144 kb
Host smart-612676eb-f360-43bb-9f8c-bf0c7c6b608d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4054770105 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.4054770105 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/12.kmac_entropy_refresh.1642970075
Short name T977
Test name
Test status
Simulation time 5633717062 ps
CPU time 224.86 seconds
Started Aug 09 05:54:13 PM PDT 24
Finished Aug 09 05:57:58 PM PDT 24
Peak memory 288764 kb
Host smart-79efd4ad-86e4-48c9-ac08-84f8e6325fac
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642970075 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.1
642970075 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/12.kmac_key_error.566076013
Short name T659
Test name
Test status
Simulation time 3028455986 ps
CPU time 7.25 seconds
Started Aug 09 05:54:11 PM PDT 24
Finished Aug 09 05:54:18 PM PDT 24
Peak memory 226840 kb
Host smart-d8f7ce32-2838-47b0-978e-fc99dc27a8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566076013 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.566076013 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_key_error/latest

Test location /workspace/coverage/default/12.kmac_lc_escalation.3810360567
Short name T11
Test name
Test status
Simulation time 127220138 ps
CPU time 1.28 seconds
Started Aug 09 05:54:13 PM PDT 24
Finished Aug 09 05:54:14 PM PDT 24
Peak memory 226880 kb
Host smart-bede3c5e-5f6c-4cff-941e-5d19dbb69f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810360567 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.3810360567 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/12.kmac_lc_escalation/latest

Test location /workspace/coverage/default/12.kmac_long_msg_and_output.4246494506
Short name T366
Test name
Test status
Simulation time 41711541183 ps
CPU time 2058.23 seconds
Started Aug 09 05:54:09 PM PDT 24
Finished Aug 09 06:28:28 PM PDT 24
Peak memory 2073104 kb
Host smart-215031ba-948f-4e4d-aa5f-af5279d23216
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246494506 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_a
nd_output.4246494506 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/12.kmac_sideload.1976568426
Short name T706
Test name
Test status
Simulation time 2500980946 ps
CPU time 63.52 seconds
Started Aug 09 05:54:10 PM PDT 24
Finished Aug 09 05:55:14 PM PDT 24
Peak memory 278864 kb
Host smart-5fc09101-8235-4bc9-8596-3336af0cb7a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976568426 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.1976568426 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_sideload/latest

Test location /workspace/coverage/default/12.kmac_smoke.4039564424
Short name T380
Test name
Test status
Simulation time 1199470010 ps
CPU time 22.89 seconds
Started Aug 09 05:54:03 PM PDT 24
Finished Aug 09 05:54:26 PM PDT 24
Peak memory 226972 kb
Host smart-a4205378-55af-40ee-bc5d-b6f9328560d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039564424 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.4039564424 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_smoke/latest

Test location /workspace/coverage/default/12.kmac_stress_all.1784108420
Short name T861
Test name
Test status
Simulation time 48611546905 ps
CPU time 427.39 seconds
Started Aug 09 05:54:14 PM PDT 24
Finished Aug 09 06:01:21 PM PDT 24
Peak memory 300492 kb
Host smart-c2868a95-7cf3-4edc-8c72-b65f29197815
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1784108420 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.1784108420 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_stress_all/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_kmac.1919694952
Short name T251
Test name
Test status
Simulation time 129117814 ps
CPU time 5.69 seconds
Started Aug 09 05:54:12 PM PDT 24
Finished Aug 09 05:54:18 PM PDT 24
Peak memory 218828 kb
Host smart-d15e0878-7011-49ef-abef-cb2182a8d227
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919694952 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.kmac_test_vectors_kmac.1919694952 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_kmac_xof.3661657398
Short name T772
Test name
Test status
Simulation time 248953091 ps
CPU time 6.43 seconds
Started Aug 09 05:54:10 PM PDT 24
Finished Aug 09 05:54:17 PM PDT 24
Peak memory 218932 kb
Host smart-3e533fb6-11f2-4a46-a110-6c2e92d61013
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661657398 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.kmac_test_vectors_kmac_xof.3661657398 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_224.1274747531
Short name T125
Test name
Test status
Simulation time 181473292192 ps
CPU time 3611.12 seconds
Started Aug 09 05:54:08 PM PDT 24
Finished Aug 09 06:54:20 PM PDT 24
Peak memory 3256872 kb
Host smart-e98c1096-6667-4416-bf1c-5e747933e5ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1274747531 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_224.1274747531 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_256.2786030417
Short name T549
Test name
Test status
Simulation time 97185461082 ps
CPU time 3549.61 seconds
Started Aug 09 05:54:12 PM PDT 24
Finished Aug 09 06:53:22 PM PDT 24
Peak memory 3065652 kb
Host smart-c6aae1b2-732d-4db0-9b51-7bbfa2a1d250
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2786030417 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_256.2786030417 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_384.4042150777
Short name T243
Test name
Test status
Simulation time 80396693710 ps
CPU time 1659.27 seconds
Started Aug 09 05:54:14 PM PDT 24
Finished Aug 09 06:21:53 PM PDT 24
Peak memory 930528 kb
Host smart-64ed5256-5e02-422d-a192-f0a34ddd895a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4042150777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_384.4042150777 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_512.1549250614
Short name T1016
Test name
Test status
Simulation time 133078921247 ps
CPU time 1268.34 seconds
Started Aug 09 05:54:10 PM PDT 24
Finished Aug 09 06:15:18 PM PDT 24
Peak memory 714940 kb
Host smart-e1a3937b-2141-4c15-a7fb-5515080aa838
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1549250614 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_512.1549250614 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_shake_128.3525922843
Short name T902
Test name
Test status
Simulation time 77016732675 ps
CPU time 6337.06 seconds
Started Aug 09 05:54:08 PM PDT 24
Finished Aug 09 07:39:46 PM PDT 24
Peak memory 2673188 kb
Host smart-e497d7a1-eb0d-4f92-ba8c-4db56164178b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3525922843 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_128.3525922843 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/13.kmac_alert_test.677035856
Short name T430
Test name
Test status
Simulation time 56310458 ps
CPU time 0.82 seconds
Started Aug 09 05:54:22 PM PDT 24
Finished Aug 09 05:54:23 PM PDT 24
Peak memory 218492 kb
Host smart-3e63b1ef-70aa-4505-b324-1c86dd0a41c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677035856 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.677035856 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/13.kmac_alert_test/latest

Test location /workspace/coverage/default/13.kmac_app.3142324100
Short name T820
Test name
Test status
Simulation time 4265411768 ps
CPU time 234.14 seconds
Started Aug 09 05:54:15 PM PDT 24
Finished Aug 09 05:58:09 PM PDT 24
Peak memory 292688 kb
Host smart-7f2312e5-ff79-4792-a526-aa197e010ccc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142324100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.3142324100 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/13.kmac_app/latest

Test location /workspace/coverage/default/13.kmac_burst_write.153950541
Short name T146
Test name
Test status
Simulation time 5849772707 ps
CPU time 176.3 seconds
Started Aug 09 05:54:15 PM PDT 24
Finished Aug 09 05:57:11 PM PDT 24
Peak memory 229284 kb
Host smart-c7d22629-1a49-421a-b0a0-ca1103a9edf8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153950541 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.153950541
+enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_burst_write/latest

Test location /workspace/coverage/default/13.kmac_edn_timeout_error.1627583451
Short name T555
Test name
Test status
Simulation time 69899783 ps
CPU time 1.19 seconds
Started Aug 09 05:54:21 PM PDT 24
Finished Aug 09 05:54:23 PM PDT 24
Peak memory 218512 kb
Host smart-b08a4043-d525-4b22-a81a-9879cd1dd227
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1627583451 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.1627583451 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/13.kmac_entropy_mode_error.4188479516
Short name T841
Test name
Test status
Simulation time 22081706 ps
CPU time 0.99 seconds
Started Aug 09 05:54:22 PM PDT 24
Finished Aug 09 05:54:23 PM PDT 24
Peak memory 220596 kb
Host smart-66045adc-fb47-4206-a861-95c14cad5ff8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4188479516 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.4188479516 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/13.kmac_error.453776697
Short name T892
Test name
Test status
Simulation time 26553714386 ps
CPU time 173.33 seconds
Started Aug 09 05:54:22 PM PDT 24
Finished Aug 09 05:57:16 PM PDT 24
Peak memory 360072 kb
Host smart-75978a66-db09-4ac7-901e-b109a252ce33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453776697 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.453776697 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_error/latest

Test location /workspace/coverage/default/13.kmac_key_error.296883067
Short name T943
Test name
Test status
Simulation time 4838090942 ps
CPU time 12.45 seconds
Started Aug 09 05:54:24 PM PDT 24
Finished Aug 09 05:54:37 PM PDT 24
Peak memory 226708 kb
Host smart-2bdf1699-bd47-4e32-8dea-e4ab17110c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296883067 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.296883067 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_key_error/latest

Test location /workspace/coverage/default/13.kmac_lc_escalation.2107784667
Short name T526
Test name
Test status
Simulation time 215576759 ps
CPU time 1.43 seconds
Started Aug 09 05:54:19 PM PDT 24
Finished Aug 09 05:54:21 PM PDT 24
Peak memory 226916 kb
Host smart-35b6333d-10bd-4007-8475-a796a7be06f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107784667 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.2107784667 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/13.kmac_lc_escalation/latest

Test location /workspace/coverage/default/13.kmac_long_msg_and_output.2209648859
Short name T42
Test name
Test status
Simulation time 120146664594 ps
CPU time 990.84 seconds
Started Aug 09 05:54:15 PM PDT 24
Finished Aug 09 06:10:46 PM PDT 24
Peak memory 1214148 kb
Host smart-21df3f57-bf6a-4f0e-949d-9f6046de57ee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209648859 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_a
nd_output.2209648859 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/13.kmac_sideload.3567266386
Short name T269
Test name
Test status
Simulation time 17947832594 ps
CPU time 498.81 seconds
Started Aug 09 05:54:14 PM PDT 24
Finished Aug 09 06:02:33 PM PDT 24
Peak memory 579840 kb
Host smart-170c454c-69db-460d-abf2-e2728d021e3b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567266386 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.3567266386 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_sideload/latest

Test location /workspace/coverage/default/13.kmac_smoke.756295260
Short name T413
Test name
Test status
Simulation time 245317895 ps
CPU time 2.42 seconds
Started Aug 09 05:54:13 PM PDT 24
Finished Aug 09 05:54:16 PM PDT 24
Peak memory 219860 kb
Host smart-5ae77334-1746-46cb-93d5-8e0d4b77b30f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756295260 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.756295260 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_smoke/latest

Test location /workspace/coverage/default/13.kmac_stress_all.1344401872
Short name T504
Test name
Test status
Simulation time 23882914797 ps
CPU time 132.95 seconds
Started Aug 09 05:54:21 PM PDT 24
Finished Aug 09 05:56:34 PM PDT 24
Peak memory 307796 kb
Host smart-66a4dbac-6cd5-4b6f-b786-59a4ac942967
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1344401872 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.1344401872 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_stress_all/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_kmac.3674694301
Short name T395
Test name
Test status
Simulation time 243068156 ps
CPU time 5.91 seconds
Started Aug 09 05:54:16 PM PDT 24
Finished Aug 09 05:54:22 PM PDT 24
Peak memory 218900 kb
Host smart-348ecc19-0d32-4f65-8dc3-24176c47e91b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674694301 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.kmac_test_vectors_kmac.3674694301 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_kmac_xof.3188549533
Short name T231
Test name
Test status
Simulation time 957622451 ps
CPU time 6.77 seconds
Started Aug 09 05:54:13 PM PDT 24
Finished Aug 09 05:54:20 PM PDT 24
Peak memory 219808 kb
Host smart-8bea6adb-304b-47cd-aab0-6285d51af234
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188549533 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.kmac_test_vectors_kmac_xof.3188549533 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_224.339501165
Short name T679
Test name
Test status
Simulation time 65614086833 ps
CPU time 3117.87 seconds
Started Aug 09 05:54:14 PM PDT 24
Finished Aug 09 06:46:12 PM PDT 24
Peak memory 3231928 kb
Host smart-53fc5f8e-3756-45ff-88bd-2084e05990aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=339501165 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_224.339501165 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_256.2659323897
Short name T456
Test name
Test status
Simulation time 39110719325 ps
CPU time 2095.19 seconds
Started Aug 09 05:54:16 PM PDT 24
Finished Aug 09 06:29:11 PM PDT 24
Peak memory 1160608 kb
Host smart-e02a7ffb-d9b2-4e15-a218-c84a5fcc7d9c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2659323897 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_256.2659323897 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_384.3960809327
Short name T702
Test name
Test status
Simulation time 48014462347 ps
CPU time 2344.88 seconds
Started Aug 09 05:54:14 PM PDT 24
Finished Aug 09 06:33:19 PM PDT 24
Peak memory 2417520 kb
Host smart-d7c1bfe9-8107-4335-951b-9789161f3b05
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3960809327 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_384.3960809327 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_512.1521178473
Short name T909
Test name
Test status
Simulation time 10519262436 ps
CPU time 1334.4 seconds
Started Aug 09 05:54:16 PM PDT 24
Finished Aug 09 06:16:31 PM PDT 24
Peak memory 700228 kb
Host smart-3a57d55c-b472-47b2-815b-a66ec6df0b38
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1521178473 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_512.1521178473 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_shake_128.1285433916
Short name T276
Test name
Test status
Simulation time 70940999379 ps
CPU time 6586.23 seconds
Started Aug 09 05:54:14 PM PDT 24
Finished Aug 09 07:44:01 PM PDT 24
Peak memory 2664204 kb
Host smart-98504ca9-00ed-4063-ab6d-1c76a2bc9c4c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1285433916 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_128.1285433916 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_shake_256.2916872961
Short name T304
Test name
Test status
Simulation time 151988705707 ps
CPU time 9046.77 seconds
Started Aug 09 05:54:15 PM PDT 24
Finished Aug 09 08:25:03 PM PDT 24
Peak memory 6444396 kb
Host smart-dd913554-4d9d-4353-9e3c-fe9f50e32702
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2916872961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_256.2916872961 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/14.kmac_alert_test.1799311817
Short name T119
Test name
Test status
Simulation time 12964437 ps
CPU time 0.84 seconds
Started Aug 09 05:54:35 PM PDT 24
Finished Aug 09 05:54:36 PM PDT 24
Peak memory 218564 kb
Host smart-ab300cb0-cf00-4dd9-a905-12307f077aba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799311817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.1799311817 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_alert_test/latest

Test location /workspace/coverage/default/14.kmac_app.652181360
Short name T682
Test name
Test status
Simulation time 9660300127 ps
CPU time 322.69 seconds
Started Aug 09 05:54:27 PM PDT 24
Finished Aug 09 05:59:50 PM PDT 24
Peak memory 335448 kb
Host smart-3cdc26f2-72cc-4ead-909c-39e3ad4c878b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652181360 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.652181360 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/14.kmac_app/latest

Test location /workspace/coverage/default/14.kmac_burst_write.3868892535
Short name T288
Test name
Test status
Simulation time 13599856460 ps
CPU time 163.38 seconds
Started Aug 09 05:54:23 PM PDT 24
Finished Aug 09 05:57:06 PM PDT 24
Peak memory 230056 kb
Host smart-8636ebea-f3a3-4197-9359-f62cf3971be0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868892535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.386889253
5 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_burst_write/latest

Test location /workspace/coverage/default/14.kmac_edn_timeout_error.705020636
Short name T667
Test name
Test status
Simulation time 113939774 ps
CPU time 1.14 seconds
Started Aug 09 05:54:32 PM PDT 24
Finished Aug 09 05:54:33 PM PDT 24
Peak memory 218664 kb
Host smart-40647624-45b1-47fe-b556-e812b0f43a6f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=705020636 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.705020636 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/14.kmac_entropy_mode_error.1747162599
Short name T305
Test name
Test status
Simulation time 257219171 ps
CPU time 1.17 seconds
Started Aug 09 05:54:32 PM PDT 24
Finished Aug 09 05:54:33 PM PDT 24
Peak memory 222440 kb
Host smart-7ad05e1e-9552-46c0-bbfa-296827a28686
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1747162599 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.1747162599 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/14.kmac_entropy_refresh.687578977
Short name T514
Test name
Test status
Simulation time 21540852677 ps
CPU time 326.64 seconds
Started Aug 09 05:54:28 PM PDT 24
Finished Aug 09 05:59:55 PM PDT 24
Peak memory 450404 kb
Host smart-58feeb3a-211d-40cd-ba33-ce2ae6bdd265
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687578977 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.68
7578977 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/14.kmac_error.3253309993
Short name T23
Test name
Test status
Simulation time 24135186725 ps
CPU time 182.31 seconds
Started Aug 09 05:54:33 PM PDT 24
Finished Aug 09 05:57:35 PM PDT 24
Peak memory 381432 kb
Host smart-85efdb83-11e3-417f-9989-b991e78573f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253309993 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.3253309993 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_error/latest

Test location /workspace/coverage/default/14.kmac_key_error.3318946828
Short name T554
Test name
Test status
Simulation time 971918302 ps
CPU time 7.79 seconds
Started Aug 09 05:54:33 PM PDT 24
Finished Aug 09 05:54:41 PM PDT 24
Peak memory 226656 kb
Host smart-ef98efb3-efd5-4bcd-86a2-f05b75e4bd91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318946828 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.3318946828 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_key_error/latest

Test location /workspace/coverage/default/14.kmac_long_msg_and_output.62469927
Short name T282
Test name
Test status
Simulation time 51800519464 ps
CPU time 3539.62 seconds
Started Aug 09 05:54:23 PM PDT 24
Finished Aug 09 06:53:23 PM PDT 24
Peak memory 1772624 kb
Host smart-da181412-32ae-416d-a752-b519c049d988
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62469927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and
_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_and
_output.62469927 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/14.kmac_sideload.229597415
Short name T414
Test name
Test status
Simulation time 45147485642 ps
CPU time 338.63 seconds
Started Aug 09 05:54:22 PM PDT 24
Finished Aug 09 06:00:01 PM PDT 24
Peak memory 475828 kb
Host smart-273d54fd-41fc-4e12-b8a4-4c40656e8789
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229597415 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.229597415 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_sideload/latest

Test location /workspace/coverage/default/14.kmac_smoke.561013212
Short name T632
Test name
Test status
Simulation time 200477260 ps
CPU time 3.37 seconds
Started Aug 09 05:54:20 PM PDT 24
Finished Aug 09 05:54:24 PM PDT 24
Peak memory 226576 kb
Host smart-72ec7c4e-737a-4966-a290-d6c63f046834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561013212 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.561013212 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_smoke/latest

Test location /workspace/coverage/default/14.kmac_stress_all.1628621762
Short name T949
Test name
Test status
Simulation time 1950103336 ps
CPU time 65 seconds
Started Aug 09 05:54:32 PM PDT 24
Finished Aug 09 05:55:37 PM PDT 24
Peak memory 276136 kb
Host smart-69f68375-a55c-43f1-8266-dca955ac5edd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1628621762 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.1628621762 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_stress_all/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_kmac.2317544977
Short name T905
Test name
Test status
Simulation time 856484213 ps
CPU time 6.95 seconds
Started Aug 09 05:54:28 PM PDT 24
Finished Aug 09 05:54:36 PM PDT 24
Peak memory 218960 kb
Host smart-be188f0d-e17d-4aed-97c6-90f36e370c9f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317544977 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.kmac_test_vectors_kmac.2317544977 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_kmac_xof.3127258737
Short name T818
Test name
Test status
Simulation time 1314040928 ps
CPU time 6.59 seconds
Started Aug 09 05:54:29 PM PDT 24
Finished Aug 09 05:54:35 PM PDT 24
Peak memory 219848 kb
Host smart-2d322ed4-8293-4128-aa19-a2a8fad7b03d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127258737 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.kmac_test_vectors_kmac_xof.3127258737 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_224.2061435846
Short name T229
Test name
Test status
Simulation time 66891647009 ps
CPU time 3411.7 seconds
Started Aug 09 05:54:26 PM PDT 24
Finished Aug 09 06:51:18 PM PDT 24
Peak memory 3258248 kb
Host smart-db1e906f-0c1d-4b5b-87c4-0f18ae87c550
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2061435846 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_224.2061435846 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_256.1217164859
Short name T484
Test name
Test status
Simulation time 123692400754 ps
CPU time 3027.13 seconds
Started Aug 09 05:54:27 PM PDT 24
Finished Aug 09 06:44:55 PM PDT 24
Peak memory 3086640 kb
Host smart-482563f5-61af-457d-a3c9-e1f684f5ec06
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1217164859 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_256.1217164859 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_384.1690501929
Short name T307
Test name
Test status
Simulation time 29936555686 ps
CPU time 1670.58 seconds
Started Aug 09 05:54:26 PM PDT 24
Finished Aug 09 06:22:17 PM PDT 24
Peak memory 921196 kb
Host smart-1326c2ef-51b2-4648-b28a-c34cd1eb76a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1690501929 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_384.1690501929 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_512.3265815317
Short name T950
Test name
Test status
Simulation time 21700105874 ps
CPU time 1258.55 seconds
Started Aug 09 05:54:27 PM PDT 24
Finished Aug 09 06:15:25 PM PDT 24
Peak memory 708164 kb
Host smart-2b89b13f-68df-49b8-9e8a-00701edf8662
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3265815317 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_512.3265815317 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_shake_128.2119978920
Short name T633
Test name
Test status
Simulation time 248904475672 ps
CPU time 6383.92 seconds
Started Aug 09 05:54:29 PM PDT 24
Finished Aug 09 07:40:54 PM PDT 24
Peak memory 2685688 kb
Host smart-7fb7cb74-9803-410c-8a80-9977a8fc62a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2119978920 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_128.2119978920 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_shake_256.3437904234
Short name T939
Test name
Test status
Simulation time 217009852392 ps
CPU time 5692.66 seconds
Started Aug 09 05:54:31 PM PDT 24
Finished Aug 09 07:29:25 PM PDT 24
Peak memory 2210272 kb
Host smart-c408840b-aa11-4662-a5a1-38cc7ab772d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3437904234 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_256.3437904234 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/15.kmac_alert_test.1205034886
Short name T429
Test name
Test status
Simulation time 48857341 ps
CPU time 0.84 seconds
Started Aug 09 05:54:38 PM PDT 24
Finished Aug 09 05:54:39 PM PDT 24
Peak memory 218480 kb
Host smart-c755e073-9ef0-4eb0-890e-01749e6b2c66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205034886 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.1205034886 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_alert_test/latest

Test location /workspace/coverage/default/15.kmac_app.2891190767
Short name T326
Test name
Test status
Simulation time 10694531783 ps
CPU time 139.88 seconds
Started Aug 09 05:54:39 PM PDT 24
Finished Aug 09 05:56:59 PM PDT 24
Peak memory 318584 kb
Host smart-a3ed0364-f79d-4d06-a0e3-25f6eb9d46e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891190767 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.2891190767 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/15.kmac_app/latest

Test location /workspace/coverage/default/15.kmac_burst_write.4219315191
Short name T105
Test name
Test status
Simulation time 87111535221 ps
CPU time 1295.71 seconds
Started Aug 09 05:54:32 PM PDT 24
Finished Aug 09 06:16:08 PM PDT 24
Peak memory 255572 kb
Host smart-a3f56100-5455-4689-a307-6e5a4ee05a6f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219315191 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.421931519
1 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_burst_write/latest

Test location /workspace/coverage/default/15.kmac_edn_timeout_error.1768549000
Short name T822
Test name
Test status
Simulation time 15418930 ps
CPU time 0.85 seconds
Started Aug 09 05:54:38 PM PDT 24
Finished Aug 09 05:54:39 PM PDT 24
Peak memory 218432 kb
Host smart-16b1622e-31fa-4c53-bc19-bbee8235ce6d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1768549000 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.1768549000 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/15.kmac_entropy_mode_error.2120427500
Short name T873
Test name
Test status
Simulation time 217361332 ps
CPU time 15.24 seconds
Started Aug 09 05:54:42 PM PDT 24
Finished Aug 09 05:54:57 PM PDT 24
Peak memory 227176 kb
Host smart-8af1d3eb-df13-4071-8192-9eaeae0a5d6a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2120427500 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.2120427500 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/15.kmac_entropy_refresh.3598237463
Short name T796
Test name
Test status
Simulation time 875047077 ps
CPU time 37.5 seconds
Started Aug 09 05:54:39 PM PDT 24
Finished Aug 09 05:55:17 PM PDT 24
Peak memory 235844 kb
Host smart-53be1e60-4ead-443a-a48b-be06d182961e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598237463 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.3
598237463 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/15.kmac_error.3142029321
Short name T651
Test name
Test status
Simulation time 14710811581 ps
CPU time 507.16 seconds
Started Aug 09 05:54:38 PM PDT 24
Finished Aug 09 06:03:05 PM PDT 24
Peak memory 630204 kb
Host smart-10f8541d-f392-449f-9681-0e37b20f92bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142029321 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.3142029321 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_error/latest

Test location /workspace/coverage/default/15.kmac_key_error.3798166719
Short name T883
Test name
Test status
Simulation time 3489210584 ps
CPU time 6.73 seconds
Started Aug 09 05:54:38 PM PDT 24
Finished Aug 09 05:54:45 PM PDT 24
Peak memory 226764 kb
Host smart-0f738587-0fcd-484a-8837-713a99ddf1f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798166719 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.3798166719 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_key_error/latest

Test location /workspace/coverage/default/15.kmac_long_msg_and_output.1755387230
Short name T530
Test name
Test status
Simulation time 20788699678 ps
CPU time 439.56 seconds
Started Aug 09 05:54:35 PM PDT 24
Finished Aug 09 06:01:55 PM PDT 24
Peak memory 434484 kb
Host smart-58cdcb70-469e-4de3-834e-972827ce28e6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755387230 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_a
nd_output.1755387230 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/15.kmac_sideload.1867489619
Short name T757
Test name
Test status
Simulation time 52438916997 ps
CPU time 432.61 seconds
Started Aug 09 05:54:36 PM PDT 24
Finished Aug 09 06:01:49 PM PDT 24
Peak memory 536828 kb
Host smart-c946d141-aeb7-44ad-94dd-2e037ad75ff9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867489619 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.1867489619 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_sideload/latest

Test location /workspace/coverage/default/15.kmac_smoke.1376010407
Short name T592
Test name
Test status
Simulation time 1290243329 ps
CPU time 40.36 seconds
Started Aug 09 05:54:32 PM PDT 24
Finished Aug 09 05:55:13 PM PDT 24
Peak memory 223600 kb
Host smart-89d89954-dfd1-4cab-b6c7-229f2fa318ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376010407 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.1376010407 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_smoke/latest

Test location /workspace/coverage/default/15.kmac_stress_all.3454885390
Short name T104
Test name
Test status
Simulation time 65784963583 ps
CPU time 1009.27 seconds
Started Aug 09 05:54:38 PM PDT 24
Finished Aug 09 06:11:28 PM PDT 24
Peak memory 957724 kb
Host smart-f45eb2e4-f4a8-4988-b914-2debc3c91379
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3454885390 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.3454885390 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_stress_all/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_kmac.4150258626
Short name T799
Test name
Test status
Simulation time 180111018 ps
CPU time 5.93 seconds
Started Aug 09 05:54:32 PM PDT 24
Finished Aug 09 05:54:38 PM PDT 24
Peak memory 218812 kb
Host smart-4ed13a99-b876-4d43-bc05-77d37420c372
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150258626 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.kmac_test_vectors_kmac.4150258626 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_kmac_xof.14427364
Short name T126
Test name
Test status
Simulation time 363152367 ps
CPU time 5.76 seconds
Started Aug 09 05:54:36 PM PDT 24
Finished Aug 09 05:54:42 PM PDT 24
Peak memory 219164 kb
Host smart-063d40a9-4c38-42a0-8105-2693b8f7cd5d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14427364 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.kmac_test_vectors_kmac_xof.14427364 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_224.657011510
Short name T218
Test name
Test status
Simulation time 201011927634 ps
CPU time 3982.9 seconds
Started Aug 09 05:54:35 PM PDT 24
Finished Aug 09 07:00:58 PM PDT 24
Peak memory 3215216 kb
Host smart-a6d82556-ee46-4945-9cd0-e40d666217ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=657011510 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_224.657011510 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_256.114003859
Short name T442
Test name
Test status
Simulation time 41500011059 ps
CPU time 2210.45 seconds
Started Aug 09 05:54:32 PM PDT 24
Finished Aug 09 06:31:23 PM PDT 24
Peak memory 1156400 kb
Host smart-c67b782e-885c-4a28-8f18-edd2ad337a3e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=114003859 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_256.114003859 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_384.1886932213
Short name T639
Test name
Test status
Simulation time 195801252319 ps
CPU time 2406.91 seconds
Started Aug 09 05:54:35 PM PDT 24
Finished Aug 09 06:34:42 PM PDT 24
Peak memory 2375232 kb
Host smart-75ff4bfc-b581-43aa-be09-94207d1ec4f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1886932213 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_384.1886932213 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_512.2958421573
Short name T546
Test name
Test status
Simulation time 197762156722 ps
CPU time 1903.35 seconds
Started Aug 09 05:54:36 PM PDT 24
Finished Aug 09 06:26:20 PM PDT 24
Peak memory 1740288 kb
Host smart-5763036d-594c-4395-9bcb-4541c152e1ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2958421573 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_512.2958421573 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_shake_128.1810925461
Short name T907
Test name
Test status
Simulation time 306113233494 ps
CPU time 6848.06 seconds
Started Aug 09 05:54:35 PM PDT 24
Finished Aug 09 07:48:44 PM PDT 24
Peak memory 2765212 kb
Host smart-feb91597-6160-4c29-afdf-0700fa23dc36
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1810925461 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_128.1810925461 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_shake_256.129292711
Short name T859
Test name
Test status
Simulation time 151614070422 ps
CPU time 9390.53 seconds
Started Aug 09 05:54:32 PM PDT 24
Finished Aug 09 08:31:04 PM PDT 24
Peak memory 6457320 kb
Host smart-fa408c02-d861-4de7-9722-2a671430f888
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=129292711 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_256.129292711 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/16.kmac_alert_test.1669266053
Short name T247
Test name
Test status
Simulation time 17229644 ps
CPU time 0.79 seconds
Started Aug 09 05:54:46 PM PDT 24
Finished Aug 09 05:54:47 PM PDT 24
Peak memory 218524 kb
Host smart-7b4c63d5-a949-4f6e-af6b-6e5a0dae636a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669266053 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.1669266053 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_alert_test/latest

Test location /workspace/coverage/default/16.kmac_app.687408810
Short name T316
Test name
Test status
Simulation time 5156087119 ps
CPU time 75.02 seconds
Started Aug 09 05:54:44 PM PDT 24
Finished Aug 09 05:55:59 PM PDT 24
Peak memory 274736 kb
Host smart-fb363286-71f0-45f4-a03f-30eb92791d78
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687408810 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.687408810 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/16.kmac_app/latest

Test location /workspace/coverage/default/16.kmac_burst_write.2969901297
Short name T698
Test name
Test status
Simulation time 120247575328 ps
CPU time 1019.03 seconds
Started Aug 09 05:54:39 PM PDT 24
Finished Aug 09 06:11:38 PM PDT 24
Peak memory 253432 kb
Host smart-27452433-0095-46aa-a2b4-60807b8cf14c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969901297 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.296990129
7 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_burst_write/latest

Test location /workspace/coverage/default/16.kmac_edn_timeout_error.2560262571
Short name T419
Test name
Test status
Simulation time 383438392 ps
CPU time 28.64 seconds
Started Aug 09 05:54:46 PM PDT 24
Finished Aug 09 05:55:15 PM PDT 24
Peak memory 233304 kb
Host smart-48c7607b-5182-4d42-97df-4b6a5b597226
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2560262571 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.2560262571 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/16.kmac_entropy_mode_error.3306000514
Short name T952
Test name
Test status
Simulation time 1983528287 ps
CPU time 28.97 seconds
Started Aug 09 05:54:46 PM PDT 24
Finished Aug 09 05:55:15 PM PDT 24
Peak memory 226696 kb
Host smart-842e8718-9332-4030-ace0-f40fd8921c06
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3306000514 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.3306000514 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/16.kmac_entropy_refresh.4072318116
Short name T736
Test name
Test status
Simulation time 12868474482 ps
CPU time 92.18 seconds
Started Aug 09 05:54:45 PM PDT 24
Finished Aug 09 05:56:17 PM PDT 24
Peak memory 276364 kb
Host smart-833f133d-74b9-46eb-881f-45cd2d0f668f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072318116 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.4
072318116 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/16.kmac_error.1462630495
Short name T441
Test name
Test status
Simulation time 12021580488 ps
CPU time 324.82 seconds
Started Aug 09 05:54:45 PM PDT 24
Finished Aug 09 06:00:10 PM PDT 24
Peak memory 492556 kb
Host smart-2d581f6f-d7cd-437d-bc21-7c5e5b064fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462630495 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.1462630495 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_error/latest

Test location /workspace/coverage/default/16.kmac_key_error.286333366
Short name T541
Test name
Test status
Simulation time 2836753748 ps
CPU time 5.31 seconds
Started Aug 09 05:54:44 PM PDT 24
Finished Aug 09 05:54:49 PM PDT 24
Peak memory 226784 kb
Host smart-3b024238-66f5-45e7-a82a-6b9d08cef366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286333366 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.286333366 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_key_error/latest

Test location /workspace/coverage/default/16.kmac_lc_escalation.1105538531
Short name T766
Test name
Test status
Simulation time 39384930 ps
CPU time 1.3 seconds
Started Aug 09 05:54:44 PM PDT 24
Finished Aug 09 05:54:45 PM PDT 24
Peak memory 226892 kb
Host smart-6aea6c32-4794-41fc-93ed-49b04e72c5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105538531 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.1105538531 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/16.kmac_lc_escalation/latest

Test location /workspace/coverage/default/16.kmac_long_msg_and_output.1391396530
Short name T345
Test name
Test status
Simulation time 24135120310 ps
CPU time 3160.9 seconds
Started Aug 09 05:54:38 PM PDT 24
Finished Aug 09 06:47:19 PM PDT 24
Peak memory 1652280 kb
Host smart-ffa9aa03-8db5-494f-b573-c94a6d531499
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391396530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_a
nd_output.1391396530 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/16.kmac_sideload.2518493545
Short name T785
Test name
Test status
Simulation time 17850661669 ps
CPU time 142.28 seconds
Started Aug 09 05:54:39 PM PDT 24
Finished Aug 09 05:57:02 PM PDT 24
Peak memory 328812 kb
Host smart-f39c849c-8341-4088-9fb1-9b4b132da4e1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518493545 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.2518493545 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_sideload/latest

Test location /workspace/coverage/default/16.kmac_smoke.3719808231
Short name T372
Test name
Test status
Simulation time 187926892 ps
CPU time 8.4 seconds
Started Aug 09 05:54:39 PM PDT 24
Finished Aug 09 05:54:47 PM PDT 24
Peak memory 223684 kb
Host smart-d67511eb-1c33-4885-bce6-23071e0d0c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719808231 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.3719808231 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_smoke/latest

Test location /workspace/coverage/default/16.kmac_stress_all.3556014562
Short name T275
Test name
Test status
Simulation time 98355972303 ps
CPU time 1460.53 seconds
Started Aug 09 05:54:50 PM PDT 24
Finished Aug 09 06:19:11 PM PDT 24
Peak memory 1224828 kb
Host smart-33e2550b-05b7-4b6c-8cf2-2518959c2d82
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3556014562 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all.3556014562 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_stress_all/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_kmac.3207159219
Short name T615
Test name
Test status
Simulation time 192890891 ps
CPU time 6.26 seconds
Started Aug 09 05:54:44 PM PDT 24
Finished Aug 09 05:54:50 PM PDT 24
Peak memory 219792 kb
Host smart-32e98c42-28bb-4497-9b90-72a61b4d987a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207159219 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.kmac_test_vectors_kmac.3207159219 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_kmac_xof.1154961926
Short name T978
Test name
Test status
Simulation time 192171886 ps
CPU time 5.89 seconds
Started Aug 09 05:54:47 PM PDT 24
Finished Aug 09 05:54:53 PM PDT 24
Peak memory 218876 kb
Host smart-c3ed5c59-bc38-4b6e-85e2-e71a2fa9af26
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154961926 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.kmac_test_vectors_kmac_xof.1154961926 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_224.3288846276
Short name T713
Test name
Test status
Simulation time 198881989788 ps
CPU time 3600.67 seconds
Started Aug 09 05:54:39 PM PDT 24
Finished Aug 09 06:54:40 PM PDT 24
Peak memory 3241444 kb
Host smart-1a0786d3-c0df-479f-9177-8b526a75fdbc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3288846276 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_224.3288846276 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_256.4126682569
Short name T245
Test name
Test status
Simulation time 80384305729 ps
CPU time 3449.84 seconds
Started Aug 09 05:54:40 PM PDT 24
Finished Aug 09 06:52:10 PM PDT 24
Peak memory 3068800 kb
Host smart-f58887d2-f3fc-4885-a4c9-ff63ebdeb69f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4126682569 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_256.4126682569 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_384.2429454556
Short name T647
Test name
Test status
Simulation time 282443530153 ps
CPU time 2896.77 seconds
Started Aug 09 05:54:45 PM PDT 24
Finished Aug 09 06:43:02 PM PDT 24
Peak memory 2395632 kb
Host smart-049d3daa-c4d2-46b0-a457-f439be79152a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2429454556 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_384.2429454556 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_512.1696893252
Short name T451
Test name
Test status
Simulation time 177917037028 ps
CPU time 1684.67 seconds
Started Aug 09 05:54:44 PM PDT 24
Finished Aug 09 06:22:49 PM PDT 24
Peak memory 1720492 kb
Host smart-6ffdad54-0b61-44b3-9bb4-8be7722156b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1696893252 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_512.1696893252 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_shake_256.223255906
Short name T560
Test name
Test status
Simulation time 210842562645 ps
CPU time 5769.36 seconds
Started Aug 09 05:54:44 PM PDT 24
Finished Aug 09 07:30:54 PM PDT 24
Peak memory 2273984 kb
Host smart-e7dce092-2376-48c3-af7d-9d082216e565
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=223255906 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_256.223255906 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/17.kmac_alert_test.117201541
Short name T616
Test name
Test status
Simulation time 46982429 ps
CPU time 0.82 seconds
Started Aug 09 05:54:51 PM PDT 24
Finished Aug 09 05:54:52 PM PDT 24
Peak memory 218536 kb
Host smart-4e981091-e318-4693-9828-62ab91de6148
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117201541 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.117201541 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/17.kmac_alert_test/latest

Test location /workspace/coverage/default/17.kmac_app.1354734450
Short name T715
Test name
Test status
Simulation time 5234386952 ps
CPU time 243.56 seconds
Started Aug 09 05:54:52 PM PDT 24
Finished Aug 09 05:58:55 PM PDT 24
Peak memory 308072 kb
Host smart-7d665aef-52ab-4c96-9db2-b563c147e97c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354734450 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.1354734450 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/17.kmac_app/latest

Test location /workspace/coverage/default/17.kmac_burst_write.367579518
Short name T522
Test name
Test status
Simulation time 13709141097 ps
CPU time 746.93 seconds
Started Aug 09 05:54:44 PM PDT 24
Finished Aug 09 06:07:12 PM PDT 24
Peak memory 249984 kb
Host smart-1e054aae-6b8e-4b6d-bed3-8659c940b946
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367579518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.367579518
+enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_burst_write/latest

Test location /workspace/coverage/default/17.kmac_edn_timeout_error.1226028416
Short name T750
Test name
Test status
Simulation time 2748465509 ps
CPU time 40.35 seconds
Started Aug 09 05:54:52 PM PDT 24
Finished Aug 09 05:55:32 PM PDT 24
Peak memory 228000 kb
Host smart-274a22b3-cfd5-4855-8c80-cd7d6328a0f3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1226028416 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.1226028416 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/17.kmac_entropy_mode_error.116337950
Short name T502
Test name
Test status
Simulation time 21700915 ps
CPU time 0.83 seconds
Started Aug 09 05:54:50 PM PDT 24
Finished Aug 09 05:54:51 PM PDT 24
Peak memory 220684 kb
Host smart-bdca24c9-8695-4c75-854b-ef1adfb9a2e7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=116337950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.116337950 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/17.kmac_entropy_refresh.2465565518
Short name T668
Test name
Test status
Simulation time 8501597039 ps
CPU time 113.06 seconds
Started Aug 09 05:54:52 PM PDT 24
Finished Aug 09 05:56:45 PM PDT 24
Peak memory 297448 kb
Host smart-09004cad-64fc-4b25-8715-6490dae50c4c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465565518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.2
465565518 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/17.kmac_error.3586833677
Short name T884
Test name
Test status
Simulation time 12700208910 ps
CPU time 162.07 seconds
Started Aug 09 05:54:51 PM PDT 24
Finished Aug 09 05:57:33 PM PDT 24
Peak memory 350260 kb
Host smart-f5629de9-599b-49da-8dab-317004835259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586833677 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.3586833677 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_error/latest

Test location /workspace/coverage/default/17.kmac_key_error.1355906430
Short name T347
Test name
Test status
Simulation time 1400035002 ps
CPU time 10.59 seconds
Started Aug 09 05:54:49 PM PDT 24
Finished Aug 09 05:54:59 PM PDT 24
Peak memory 226724 kb
Host smart-ef374a9f-53e3-4b77-8217-147d4529fcc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355906430 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.1355906430 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_key_error/latest

Test location /workspace/coverage/default/17.kmac_lc_escalation.3496585836
Short name T648
Test name
Test status
Simulation time 43386342 ps
CPU time 1.35 seconds
Started Aug 09 05:54:52 PM PDT 24
Finished Aug 09 05:54:53 PM PDT 24
Peak memory 226852 kb
Host smart-7e3504e8-6876-4521-98b6-f45bdeca8d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496585836 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.3496585836 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/17.kmac_lc_escalation/latest

Test location /workspace/coverage/default/17.kmac_long_msg_and_output.1108356264
Short name T279
Test name
Test status
Simulation time 21710111641 ps
CPU time 1257.08 seconds
Started Aug 09 05:54:42 PM PDT 24
Finished Aug 09 06:15:40 PM PDT 24
Peak memory 805004 kb
Host smart-eaa7d656-cf19-492e-b283-8fb31e841813
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108356264 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_a
nd_output.1108356264 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/17.kmac_sideload.3266748470
Short name T143
Test name
Test status
Simulation time 33376620078 ps
CPU time 180.84 seconds
Started Aug 09 05:54:43 PM PDT 24
Finished Aug 09 05:57:44 PM PDT 24
Peak memory 286820 kb
Host smart-70f0c571-c25a-4bd6-a66b-b9f386d87c87
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266748470 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.3266748470 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_sideload/latest

Test location /workspace/coverage/default/17.kmac_smoke.1572920238
Short name T662
Test name
Test status
Simulation time 6648619109 ps
CPU time 41.22 seconds
Started Aug 09 05:54:44 PM PDT 24
Finished Aug 09 05:55:25 PM PDT 24
Peak memory 226976 kb
Host smart-ccaa086b-37f6-4d2e-96e3-ff9971b50f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572920238 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.1572920238 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_smoke/latest

Test location /workspace/coverage/default/17.kmac_stress_all.4165465193
Short name T1030
Test name
Test status
Simulation time 106867007199 ps
CPU time 1880.64 seconds
Started Aug 09 05:54:50 PM PDT 24
Finished Aug 09 06:26:12 PM PDT 24
Peak memory 612864 kb
Host smart-0d9f6068-26b1-4652-95cc-40db7c2af4e9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4165465193 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.4165465193 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_stress_all/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_kmac.2732508586
Short name T212
Test name
Test status
Simulation time 1868497161 ps
CPU time 6.93 seconds
Started Aug 09 05:54:50 PM PDT 24
Finished Aug 09 05:54:57 PM PDT 24
Peak memory 218816 kb
Host smart-cac1d335-14f1-4a0e-baac-8dab5830931a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732508586 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.kmac_test_vectors_kmac.2732508586 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_kmac_xof.2221164080
Short name T936
Test name
Test status
Simulation time 387792440 ps
CPU time 6.47 seconds
Started Aug 09 05:54:51 PM PDT 24
Finished Aug 09 05:54:57 PM PDT 24
Peak memory 219684 kb
Host smart-b94c2ccb-6916-43ca-a002-5347cd57199f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221164080 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.kmac_test_vectors_kmac_xof.2221164080 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_224.1926717319
Short name T728
Test name
Test status
Simulation time 42035495478 ps
CPU time 2416.27 seconds
Started Aug 09 05:54:47 PM PDT 24
Finished Aug 09 06:35:03 PM PDT 24
Peak memory 1220276 kb
Host smart-1115a72b-24a1-40c7-8f2e-93b4d14d9017
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1926717319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_224.1926717319 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_256.265602171
Short name T704
Test name
Test status
Simulation time 122322639392 ps
CPU time 3415.67 seconds
Started Aug 09 05:54:50 PM PDT 24
Finished Aug 09 06:51:47 PM PDT 24
Peak memory 3015412 kb
Host smart-16511f6d-9d95-413a-8de7-b1d4657b9666
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=265602171 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_256.265602171 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_384.2554598916
Short name T434
Test name
Test status
Simulation time 47825265908 ps
CPU time 2231.66 seconds
Started Aug 09 05:54:43 PM PDT 24
Finished Aug 09 06:31:55 PM PDT 24
Peak memory 2320968 kb
Host smart-12675fe1-9997-4f9d-9a04-ac6f0108f63d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2554598916 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_384.2554598916 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_512.3570530736
Short name T525
Test name
Test status
Simulation time 213084013872 ps
CPU time 1796.09 seconds
Started Aug 09 05:54:50 PM PDT 24
Finished Aug 09 06:24:47 PM PDT 24
Peak memory 1726712 kb
Host smart-0ff63034-2eb2-4e6a-a12c-99bc2b5e85cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3570530736 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_512.3570530736 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_shake_256.3154382666
Short name T629
Test name
Test status
Simulation time 226140139569 ps
CPU time 10251.2 seconds
Started Aug 09 05:54:49 PM PDT 24
Finished Aug 09 08:45:41 PM PDT 24
Peak memory 6379292 kb
Host smart-61b19961-9628-4992-9b0b-f33d7c158930
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3154382666 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_256.3154382666 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/18.kmac_alert_test.2415759662
Short name T534
Test name
Test status
Simulation time 12206439 ps
CPU time 0.81 seconds
Started Aug 09 05:54:57 PM PDT 24
Finished Aug 09 05:54:58 PM PDT 24
Peak memory 218544 kb
Host smart-2a16d9ab-bf08-482a-988e-33c5088c54cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415759662 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.2415759662 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_alert_test/latest

Test location /workspace/coverage/default/18.kmac_app.3581771262
Short name T793
Test name
Test status
Simulation time 1683667147 ps
CPU time 52.61 seconds
Started Aug 09 05:54:56 PM PDT 24
Finished Aug 09 05:55:49 PM PDT 24
Peak memory 260004 kb
Host smart-0cc3b083-1572-4127-949d-d470c9822c76
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581771262 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.3581771262 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/18.kmac_app/latest

Test location /workspace/coverage/default/18.kmac_burst_write.2734965455
Short name T696
Test name
Test status
Simulation time 86544003226 ps
CPU time 1292.05 seconds
Started Aug 09 05:54:50 PM PDT 24
Finished Aug 09 06:16:22 PM PDT 24
Peak memory 258424 kb
Host smart-570b7c19-a5e9-4848-aa9d-3ea0503d8ea0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734965455 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.273496545
5 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_burst_write/latest

Test location /workspace/coverage/default/18.kmac_edn_timeout_error.3914557587
Short name T71
Test name
Test status
Simulation time 367985285 ps
CPU time 1.17 seconds
Started Aug 09 05:54:56 PM PDT 24
Finished Aug 09 05:54:57 PM PDT 24
Peak memory 218628 kb
Host smart-dc758021-e0c9-4efb-be4e-ffd9569432da
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3914557587 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.3914557587 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/18.kmac_entropy_mode_error.1015050105
Short name T804
Test name
Test status
Simulation time 39888690 ps
CPU time 0.82 seconds
Started Aug 09 05:54:55 PM PDT 24
Finished Aug 09 05:54:56 PM PDT 24
Peak memory 220564 kb
Host smart-847d347d-6cb5-4699-8928-dbbc63735997
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1015050105 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.1015050105 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/18.kmac_entropy_refresh.3095460172
Short name T75
Test name
Test status
Simulation time 19653053366 ps
CPU time 421.52 seconds
Started Aug 09 05:54:54 PM PDT 24
Finished Aug 09 06:01:56 PM PDT 24
Peak memory 492556 kb
Host smart-a4499231-5fb3-43d0-acba-bb5f80df7d51
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095460172 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.3
095460172 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/18.kmac_error.3934829179
Short name T422
Test name
Test status
Simulation time 14341632178 ps
CPU time 278.32 seconds
Started Aug 09 05:54:55 PM PDT 24
Finished Aug 09 05:59:34 PM PDT 24
Peak memory 338444 kb
Host smart-df1bf829-7562-4a85-aa33-67a1a0a0da89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934829179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.3934829179 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_error/latest

Test location /workspace/coverage/default/18.kmac_key_error.1669739986
Short name T1010
Test name
Test status
Simulation time 6856533631 ps
CPU time 12.2 seconds
Started Aug 09 05:54:57 PM PDT 24
Finished Aug 09 05:55:10 PM PDT 24
Peak memory 226800 kb
Host smart-b0d71b44-7c6b-4106-a861-d7c2e4dea378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669739986 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.1669739986 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_key_error/latest

Test location /workspace/coverage/default/18.kmac_lc_escalation.3635601404
Short name T53
Test name
Test status
Simulation time 54475394 ps
CPU time 1.64 seconds
Started Aug 09 05:54:58 PM PDT 24
Finished Aug 09 05:55:00 PM PDT 24
Peak memory 226984 kb
Host smart-2659a2ba-3014-44d8-8afc-4a39d1725acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635601404 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.3635601404 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/18.kmac_lc_escalation/latest

Test location /workspace/coverage/default/18.kmac_long_msg_and_output.2465073416
Short name T699
Test name
Test status
Simulation time 12026997124 ps
CPU time 359.9 seconds
Started Aug 09 05:54:53 PM PDT 24
Finished Aug 09 06:00:53 PM PDT 24
Peak memory 630668 kb
Host smart-37a27ff6-0f2f-4ee2-b3e0-3847293d7252
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465073416 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_a
nd_output.2465073416 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/18.kmac_sideload.1750192213
Short name T337
Test name
Test status
Simulation time 34366174960 ps
CPU time 465.64 seconds
Started Aug 09 05:54:48 PM PDT 24
Finished Aug 09 06:02:34 PM PDT 24
Peak memory 583092 kb
Host smart-e5c6b5c8-6a9e-42c6-a1df-6d3f002cb424
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750192213 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.1750192213 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_sideload/latest

Test location /workspace/coverage/default/18.kmac_smoke.1371375168
Short name T828
Test name
Test status
Simulation time 5508375536 ps
CPU time 23.02 seconds
Started Aug 09 05:54:50 PM PDT 24
Finished Aug 09 05:55:14 PM PDT 24
Peak memory 223248 kb
Host smart-a9b31356-fa05-45d4-a8e4-e92d155d4227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371375168 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.1371375168 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_smoke/latest

Test location /workspace/coverage/default/18.kmac_stress_all.726155500
Short name T58
Test name
Test status
Simulation time 9191979231 ps
CPU time 787.04 seconds
Started Aug 09 05:54:57 PM PDT 24
Finished Aug 09 06:08:04 PM PDT 24
Peak memory 500520 kb
Host smart-b8b2513f-e981-44ab-a1c9-ab5d7871ed9d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=726155500 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all.726155500 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_stress_all/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_kmac.3833120776
Short name T663
Test name
Test status
Simulation time 3345934800 ps
CPU time 5.85 seconds
Started Aug 09 05:54:56 PM PDT 24
Finished Aug 09 05:55:02 PM PDT 24
Peak memory 219740 kb
Host smart-af3809f6-3f0d-473e-9531-2bebf7d74992
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833120776 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.kmac_test_vectors_kmac.3833120776 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_kmac_xof.1948629255
Short name T239
Test name
Test status
Simulation time 966534065 ps
CPU time 5.54 seconds
Started Aug 09 05:54:57 PM PDT 24
Finished Aug 09 05:55:03 PM PDT 24
Peak memory 219832 kb
Host smart-6b0b9300-dce0-4fdd-9d63-d3691267a1e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948629255 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.kmac_test_vectors_kmac_xof.1948629255 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_224.664622315
Short name T951
Test name
Test status
Simulation time 44417659100 ps
CPU time 1935.3 seconds
Started Aug 09 05:54:52 PM PDT 24
Finished Aug 09 06:27:08 PM PDT 24
Peak memory 1206560 kb
Host smart-f117b7f2-a54d-4af4-8cd7-5021ee238f91
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=664622315 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_224.664622315 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_256.2048488251
Short name T745
Test name
Test status
Simulation time 91410197092 ps
CPU time 3303.94 seconds
Started Aug 09 05:54:51 PM PDT 24
Finished Aug 09 06:49:55 PM PDT 24
Peak memory 3007900 kb
Host smart-2d8d6e83-ad27-4195-af78-0370a4052743
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2048488251 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_256.2048488251 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_384.3920930699
Short name T562
Test name
Test status
Simulation time 30863703119 ps
CPU time 1788.51 seconds
Started Aug 09 05:54:51 PM PDT 24
Finished Aug 09 06:24:40 PM PDT 24
Peak memory 930948 kb
Host smart-588efc16-9244-4e62-8a51-e72a69a802f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3920930699 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_384.3920930699 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_512.1438836256
Short name T854
Test name
Test status
Simulation time 125796994648 ps
CPU time 1774.13 seconds
Started Aug 09 05:54:57 PM PDT 24
Finished Aug 09 06:24:32 PM PDT 24
Peak memory 1722712 kb
Host smart-b3a51580-2ffd-47fa-8687-276c8b1e082c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1438836256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_512.1438836256 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_shake_256.3465560673
Short name T265
Test name
Test status
Simulation time 153230376548 ps
CPU time 9074.92 seconds
Started Aug 09 05:54:55 PM PDT 24
Finished Aug 09 08:26:11 PM PDT 24
Peak memory 6528952 kb
Host smart-3c969673-29d6-4876-9026-ee8f29be7890
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3465560673 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_256.3465560673 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/19.kmac_alert_test.2243984342
Short name T457
Test name
Test status
Simulation time 38712749 ps
CPU time 0.81 seconds
Started Aug 09 05:55:20 PM PDT 24
Finished Aug 09 05:55:20 PM PDT 24
Peak memory 218404 kb
Host smart-95738fe4-e2a4-407d-a762-8be094073066
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243984342 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.2243984342 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_alert_test/latest

Test location /workspace/coverage/default/19.kmac_app.691815237
Short name T36
Test name
Test status
Simulation time 17417384221 ps
CPU time 90.5 seconds
Started Aug 09 05:55:08 PM PDT 24
Finished Aug 09 05:56:38 PM PDT 24
Peak memory 283008 kb
Host smart-9cbc787a-f689-4c7b-bb8e-3a2fab35706d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691815237 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.691815237 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/19.kmac_app/latest

Test location /workspace/coverage/default/19.kmac_burst_write.1621607161
Short name T803
Test name
Test status
Simulation time 148140848380 ps
CPU time 1756.24 seconds
Started Aug 09 05:55:02 PM PDT 24
Finished Aug 09 06:24:19 PM PDT 24
Peak memory 267612 kb
Host smart-3ef8eb1a-4ad7-46f2-af96-a34a8c75403c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621607161 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.162160716
1 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_burst_write/latest

Test location /workspace/coverage/default/19.kmac_edn_timeout_error.548861735
Short name T545
Test name
Test status
Simulation time 79468151 ps
CPU time 1.2 seconds
Started Aug 09 05:55:07 PM PDT 24
Finished Aug 09 05:55:08 PM PDT 24
Peak memory 218640 kb
Host smart-78c3d85a-e279-453b-b010-4fc26acf47cb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=548861735 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.548861735 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/19.kmac_entropy_mode_error.3807296895
Short name T1008
Test name
Test status
Simulation time 121379346 ps
CPU time 1.03 seconds
Started Aug 09 05:55:16 PM PDT 24
Finished Aug 09 05:55:17 PM PDT 24
Peak memory 221984 kb
Host smart-11c8905f-5bf5-4442-940d-cf60cc55053b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3807296895 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.3807296895 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/19.kmac_entropy_refresh.4066630466
Short name T751
Test name
Test status
Simulation time 2470915625 ps
CPU time 15.71 seconds
Started Aug 09 05:55:06 PM PDT 24
Finished Aug 09 05:55:22 PM PDT 24
Peak memory 232328 kb
Host smart-68eca3f7-8495-4380-b1dd-e7e93066a717
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066630466 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.4
066630466 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/19.kmac_error.935900365
Short name T957
Test name
Test status
Simulation time 19167674449 ps
CPU time 155.93 seconds
Started Aug 09 05:55:08 PM PDT 24
Finished Aug 09 05:57:44 PM PDT 24
Peak memory 363528 kb
Host smart-8a1421ae-c28d-4161-bec1-42e6ca2807da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935900365 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.935900365 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_error/latest

Test location /workspace/coverage/default/19.kmac_key_error.3228261452
Short name T917
Test name
Test status
Simulation time 1739708426 ps
CPU time 3.69 seconds
Started Aug 09 05:55:07 PM PDT 24
Finished Aug 09 05:55:11 PM PDT 24
Peak memory 226580 kb
Host smart-ad9bfec5-7496-4eed-b198-cedf49f44ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228261452 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.3228261452 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_key_error/latest

Test location /workspace/coverage/default/19.kmac_long_msg_and_output.3614061411
Short name T31
Test name
Test status
Simulation time 112158569789 ps
CPU time 3976.36 seconds
Started Aug 09 05:55:02 PM PDT 24
Finished Aug 09 07:01:19 PM PDT 24
Peak memory 1891256 kb
Host smart-eec5877e-718f-4075-a887-0c1f02759817
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614061411 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_a
nd_output.3614061411 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/19.kmac_sideload.3666818089
Short name T733
Test name
Test status
Simulation time 2747806607 ps
CPU time 63.91 seconds
Started Aug 09 05:55:01 PM PDT 24
Finished Aug 09 05:56:05 PM PDT 24
Peak memory 276816 kb
Host smart-945f3dc5-5ba6-43b3-958d-83da6ee64bb2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666818089 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.3666818089 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_sideload/latest

Test location /workspace/coverage/default/19.kmac_smoke.1641282809
Short name T128
Test name
Test status
Simulation time 1943158095 ps
CPU time 18.67 seconds
Started Aug 09 05:55:00 PM PDT 24
Finished Aug 09 05:55:19 PM PDT 24
Peak memory 226972 kb
Host smart-fd3b1387-7fa2-4b46-b724-e8b00643de95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641282809 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.1641282809 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_smoke/latest

Test location /workspace/coverage/default/19.kmac_stress_all.3321059807
Short name T250
Test name
Test status
Simulation time 99341421214 ps
CPU time 1152.92 seconds
Started Aug 09 05:55:15 PM PDT 24
Finished Aug 09 06:14:28 PM PDT 24
Peak memory 1023124 kb
Host smart-9d8d6f94-a3ef-45e7-abe8-2ee247e5329f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3321059807 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.3321059807 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_stress_all/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_kmac.1121700622
Short name T397
Test name
Test status
Simulation time 107503077 ps
CPU time 5.98 seconds
Started Aug 09 05:55:08 PM PDT 24
Finished Aug 09 05:55:14 PM PDT 24
Peak memory 218840 kb
Host smart-9b90aa69-fd41-4c6c-972e-02ab58552f16
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121700622 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.kmac_test_vectors_kmac.1121700622 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_kmac_xof.3636740532
Short name T619
Test name
Test status
Simulation time 180820931 ps
CPU time 6.12 seconds
Started Aug 09 05:55:08 PM PDT 24
Finished Aug 09 05:55:15 PM PDT 24
Peak memory 218772 kb
Host smart-0408bb18-d822-4c07-b323-969d43d84b7f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636740532 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.kmac_test_vectors_kmac_xof.3636740532 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_224.2984096186
Short name T115
Test name
Test status
Simulation time 87830996730 ps
CPU time 3347.46 seconds
Started Aug 09 05:55:01 PM PDT 24
Finished Aug 09 06:50:49 PM PDT 24
Peak memory 3192588 kb
Host smart-a93d4258-bbb2-478d-b9df-69a5f641e7cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2984096186 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_224.2984096186 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_256.1921305230
Short name T872
Test name
Test status
Simulation time 228680098330 ps
CPU time 3035.45 seconds
Started Aug 09 05:55:02 PM PDT 24
Finished Aug 09 06:45:38 PM PDT 24
Peak memory 3031828 kb
Host smart-6ed96dc7-91ca-4406-bc60-898632fbc754
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1921305230 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_256.1921305230 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_384.922907242
Short name T495
Test name
Test status
Simulation time 80650518260 ps
CPU time 2541.94 seconds
Started Aug 09 05:55:02 PM PDT 24
Finished Aug 09 06:37:24 PM PDT 24
Peak memory 2383264 kb
Host smart-2f385330-fe1a-4153-bc61-b91d73630941
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=922907242 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_384.922907242 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_512.2478791649
Short name T912
Test name
Test status
Simulation time 158787871363 ps
CPU time 1761.7 seconds
Started Aug 09 05:55:01 PM PDT 24
Finished Aug 09 06:24:23 PM PDT 24
Peak memory 1801104 kb
Host smart-c1aad871-ee58-4886-b6c2-91fc6df3a1a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2478791649 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_512.2478791649 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_shake_256.1339802714
Short name T216
Test name
Test status
Simulation time 107181505975 ps
CPU time 5213.85 seconds
Started Aug 09 05:55:01 PM PDT 24
Finished Aug 09 07:21:56 PM PDT 24
Peak memory 2204172 kb
Host smart-52af1d59-b485-4717-a65a-0b1a7dec7f9c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1339802714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_256.1339802714 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/2.kmac_alert_test.3297886673
Short name T887
Test name
Test status
Simulation time 56398865 ps
CPU time 0.84 seconds
Started Aug 09 05:53:41 PM PDT 24
Finished Aug 09 05:53:42 PM PDT 24
Peak memory 218540 kb
Host smart-4c401000-45a5-433a-8f98-2ca33012194d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297886673 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.3297886673 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_alert_test/latest

Test location /workspace/coverage/default/2.kmac_app.1548884589
Short name T400
Test name
Test status
Simulation time 36011170448 ps
CPU time 306.74 seconds
Started Aug 09 05:53:32 PM PDT 24
Finished Aug 09 05:58:39 PM PDT 24
Peak memory 439748 kb
Host smart-f53bf8ff-f4c8-4ece-92f7-fcf6ed05d151
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548884589 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.1548884589 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/2.kmac_app/latest

Test location /workspace/coverage/default/2.kmac_app_with_partial_data.2870455113
Short name T240
Test name
Test status
Simulation time 4652487220 ps
CPU time 242.58 seconds
Started Aug 09 05:53:32 PM PDT 24
Finished Aug 09 05:57:35 PM PDT 24
Peak memory 299336 kb
Host smart-7736ab8e-3863-4b85-a073-a15ba8670ddf
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870455113 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_par
tial_data.2870455113 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/2.kmac_burst_write.1371990652
Short name T550
Test name
Test status
Simulation time 100345907984 ps
CPU time 1402.45 seconds
Started Aug 09 05:53:31 PM PDT 24
Finished Aug 09 06:16:54 PM PDT 24
Peak memory 263132 kb
Host smart-7376d023-d9e3-4228-87f2-f226db05fedd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371990652 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.1371990652
+enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_burst_write/latest

Test location /workspace/coverage/default/2.kmac_edn_timeout_error.3818314541
Short name T506
Test name
Test status
Simulation time 75546129 ps
CPU time 1.12 seconds
Started Aug 09 05:53:38 PM PDT 24
Finished Aug 09 05:53:39 PM PDT 24
Peak memory 218564 kb
Host smart-bbc064ae-efcc-4146-921c-8670999a38d1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3818314541 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.3818314541 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_mode_error.1205624767
Short name T1004
Test name
Test status
Simulation time 86486612 ps
CPU time 1.05 seconds
Started Aug 09 05:53:37 PM PDT 24
Finished Aug 09 05:53:38 PM PDT 24
Peak memory 221596 kb
Host smart-175114f1-57fe-4f8e-b963-22a136b57119
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1205624767 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.1205624767 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_ready_error.4104086068
Short name T8
Test name
Test status
Simulation time 35903370772 ps
CPU time 92.18 seconds
Started Aug 09 05:53:31 PM PDT 24
Finished Aug 09 05:55:04 PM PDT 24
Peak memory 227044 kb
Host smart-2871e5a5-b94a-4b22-acf2-b4b7dbd5c308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104086068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.4104086068 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_refresh.3092378177
Short name T73
Test name
Test status
Simulation time 10732833610 ps
CPU time 122.13 seconds
Started Aug 09 05:53:32 PM PDT 24
Finished Aug 09 05:55:35 PM PDT 24
Peak memory 264280 kb
Host smart-73a2eeb9-ad73-4868-9232-3c3e2cc79a6a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092378177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.30
92378177 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/2.kmac_error.708521049
Short name T112
Test name
Test status
Simulation time 41807273114 ps
CPU time 258.73 seconds
Started Aug 09 05:53:34 PM PDT 24
Finished Aug 09 05:57:53 PM PDT 24
Peak memory 428116 kb
Host smart-ecc598b3-5c17-4afb-bc9f-9c9b8d9eb7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708521049 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.708521049 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_error/latest

Test location /workspace/coverage/default/2.kmac_lc_escalation.239471229
Short name T66
Test name
Test status
Simulation time 197316849 ps
CPU time 1.36 seconds
Started Aug 09 05:53:37 PM PDT 24
Finished Aug 09 05:53:38 PM PDT 24
Peak memory 226944 kb
Host smart-a4a32c06-08f6-463c-8ad7-1bcce13ec9dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239471229 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.239471229 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_lc_escalation/latest

Test location /workspace/coverage/default/2.kmac_long_msg_and_output.2424685020
Short name T673
Test name
Test status
Simulation time 54583488230 ps
CPU time 3025.45 seconds
Started Aug 09 05:53:38 PM PDT 24
Finished Aug 09 06:44:04 PM PDT 24
Peak memory 2631592 kb
Host smart-3425adca-71cd-486a-8321-6d341eba715a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424685020 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_an
d_output.2424685020 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/2.kmac_mubi.96932279
Short name T340
Test name
Test status
Simulation time 3434701668 ps
CPU time 202.18 seconds
Started Aug 09 05:53:29 PM PDT 24
Finished Aug 09 05:56:51 PM PDT 24
Peak memory 294520 kb
Host smart-c78c2525-b0b6-4de2-96d8-8293a5d535f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96932279 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.96932279 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_mubi/latest

Test location /workspace/coverage/default/2.kmac_sideload.3882433733
Short name T649
Test name
Test status
Simulation time 14309998990 ps
CPU time 264.53 seconds
Started Aug 09 05:53:34 PM PDT 24
Finished Aug 09 05:57:59 PM PDT 24
Peak memory 317956 kb
Host smart-16e66dc8-b12c-498b-bde7-fc77aea9ca89
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882433733 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.3882433733 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_sideload/latest

Test location /workspace/coverage/default/2.kmac_smoke.3597093791
Short name T620
Test name
Test status
Simulation time 27636047712 ps
CPU time 97.74 seconds
Started Aug 09 05:53:30 PM PDT 24
Finished Aug 09 05:55:08 PM PDT 24
Peak memory 230376 kb
Host smart-4e68ed26-e8a3-4ce3-81f9-f92a89451081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597093791 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.3597093791 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_smoke/latest

Test location /workspace/coverage/default/2.kmac_stress_all.2862560111
Short name T664
Test name
Test status
Simulation time 18991808080 ps
CPU time 1455.08 seconds
Started Aug 09 05:53:37 PM PDT 24
Finished Aug 09 06:17:52 PM PDT 24
Peak memory 704112 kb
Host smart-53b2e90f-da95-4a12-be04-585ae0772f22
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2862560111 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.2862560111 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_stress_all/latest

Test location /workspace/coverage/default/2.kmac_stress_all_with_rand_reset.1177220462
Short name T46
Test name
Test status
Simulation time 70865969211 ps
CPU time 1801.72 seconds
Started Aug 09 05:53:31 PM PDT 24
Finished Aug 09 06:23:33 PM PDT 24
Peak memory 476472 kb
Host smart-b2e413a3-d898-4893-88a1-57cf416e37d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1177220462 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all_with_rand_reset.1177220462 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_kmac.1495105564
Short name T1001
Test name
Test status
Simulation time 1017637595 ps
CPU time 6.23 seconds
Started Aug 09 05:53:29 PM PDT 24
Finished Aug 09 05:53:36 PM PDT 24
Peak memory 219824 kb
Host smart-3cd37ba9-d7b8-42ac-8eaf-99a2587606fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495105564 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.kmac_test_vectors_kmac.1495105564 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_kmac_xof.2397275253
Short name T63
Test name
Test status
Simulation time 772107463 ps
CPU time 6.39 seconds
Started Aug 09 05:53:32 PM PDT 24
Finished Aug 09 05:53:38 PM PDT 24
Peak memory 219788 kb
Host smart-9c266685-1195-4907-a4df-b490cf35d707
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397275253 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.kmac_test_vectors_kmac_xof.2397275253 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_224.666950808
Short name T916
Test name
Test status
Simulation time 34172887245 ps
CPU time 2262.6 seconds
Started Aug 09 05:53:28 PM PDT 24
Finished Aug 09 06:31:11 PM PDT 24
Peak memory 1206296 kb
Host smart-1ace079c-d1cb-44dc-8bdb-a9637b697d23
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=666950808 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.666950808 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_256.417495212
Short name T435
Test name
Test status
Simulation time 20830541841 ps
CPU time 2285.85 seconds
Started Aug 09 05:53:27 PM PDT 24
Finished Aug 09 06:31:34 PM PDT 24
Peak memory 1154836 kb
Host smart-b2441644-d4ca-40ab-9e06-a933059e7f8c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=417495212 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.417495212 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_384.3022856614
Short name T774
Test name
Test status
Simulation time 96431664930 ps
CPU time 2357.38 seconds
Started Aug 09 05:53:32 PM PDT 24
Finished Aug 09 06:32:50 PM PDT 24
Peak memory 2398372 kb
Host smart-71a1fc49-4373-48e9-a004-f5089ad5bbc3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3022856614 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.3022856614 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_512.122348403
Short name T463
Test name
Test status
Simulation time 33864180844 ps
CPU time 1614.91 seconds
Started Aug 09 05:53:27 PM PDT 24
Finished Aug 09 06:20:22 PM PDT 24
Peak memory 1744716 kb
Host smart-a46f15ce-e2b4-4d9d-a973-03a98d5d8291
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=122348403 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.122348403 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_shake_256.3211150327
Short name T399
Test name
Test status
Simulation time 402912660188 ps
CPU time 10346.6 seconds
Started Aug 09 05:53:30 PM PDT 24
Finished Aug 09 08:45:58 PM PDT 24
Peak memory 6408720 kb
Host smart-d5d3e84e-a0bb-4319-b734-7dee40be20cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3211150327 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.3211150327 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/20.kmac_alert_test.3445173384
Short name T848
Test name
Test status
Simulation time 35857020 ps
CPU time 0.79 seconds
Started Aug 09 05:55:21 PM PDT 24
Finished Aug 09 05:55:22 PM PDT 24
Peak memory 218580 kb
Host smart-344e50a5-b6b2-4f59-9b9e-7d2fe3d66c28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445173384 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.3445173384 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_alert_test/latest

Test location /workspace/coverage/default/20.kmac_app.3796654719
Short name T230
Test name
Test status
Simulation time 14221074694 ps
CPU time 306.31 seconds
Started Aug 09 05:55:19 PM PDT 24
Finished Aug 09 06:00:25 PM PDT 24
Peak memory 447860 kb
Host smart-0bc99266-4c80-4ce5-86cf-8551b0fc9962
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796654719 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.3796654719 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/20.kmac_app/latest

Test location /workspace/coverage/default/20.kmac_burst_write.543173051
Short name T789
Test name
Test status
Simulation time 7007455644 ps
CPU time 350.03 seconds
Started Aug 09 05:55:13 PM PDT 24
Finished Aug 09 06:01:03 PM PDT 24
Peak memory 233588 kb
Host smart-48a143ba-8f97-4988-8ab0-3157970b95c8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543173051 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.543173051
+enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_burst_write/latest

Test location /workspace/coverage/default/20.kmac_entropy_refresh.3329924187
Short name T359
Test name
Test status
Simulation time 75244860160 ps
CPU time 372.17 seconds
Started Aug 09 05:55:20 PM PDT 24
Finished Aug 09 06:01:32 PM PDT 24
Peak memory 455788 kb
Host smart-9711a233-9194-40ec-9aa6-9d6ccb03fd39
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329924187 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.3
329924187 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/20.kmac_error.3730693894
Short name T817
Test name
Test status
Simulation time 13046437676 ps
CPU time 496.59 seconds
Started Aug 09 05:55:21 PM PDT 24
Finished Aug 09 06:03:37 PM PDT 24
Peak memory 573996 kb
Host smart-a0e7028b-53ce-4898-965a-4d376b2c1af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730693894 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.3730693894 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_error/latest

Test location /workspace/coverage/default/20.kmac_key_error.3733549223
Short name T461
Test name
Test status
Simulation time 1141396640 ps
CPU time 7.76 seconds
Started Aug 09 05:55:21 PM PDT 24
Finished Aug 09 05:55:29 PM PDT 24
Peak memory 226616 kb
Host smart-4217f15c-a277-4981-9999-244db8f174c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733549223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.3733549223 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_key_error/latest

Test location /workspace/coverage/default/20.kmac_lc_escalation.282697880
Short name T993
Test name
Test status
Simulation time 2980402373 ps
CPU time 46.05 seconds
Started Aug 09 05:55:19 PM PDT 24
Finished Aug 09 05:56:06 PM PDT 24
Peak memory 246760 kb
Host smart-3f20c14b-5d49-432f-a133-99a65b72609d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282697880 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.282697880 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/20.kmac_lc_escalation/latest

Test location /workspace/coverage/default/20.kmac_long_msg_and_output.104662746
Short name T510
Test name
Test status
Simulation time 16508666676 ps
CPU time 576.49 seconds
Started Aug 09 05:55:14 PM PDT 24
Finished Aug 09 06:04:51 PM PDT 24
Peak memory 841856 kb
Host smart-d40fa928-6bd1-4661-a01b-c4c37ee429aa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104662746 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_an
d_output.104662746 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/20.kmac_sideload.1514176213
Short name T697
Test name
Test status
Simulation time 1840782802 ps
CPU time 41.54 seconds
Started Aug 09 05:55:20 PM PDT 24
Finished Aug 09 05:56:01 PM PDT 24
Peak memory 234044 kb
Host smart-cd08d704-3b69-48fe-8b09-a65e8a276598
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514176213 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.1514176213 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_sideload/latest

Test location /workspace/coverage/default/20.kmac_smoke.1209835589
Short name T328
Test name
Test status
Simulation time 2176167899 ps
CPU time 56.56 seconds
Started Aug 09 05:55:14 PM PDT 24
Finished Aug 09 05:56:11 PM PDT 24
Peak memory 227112 kb
Host smart-31f3ac9b-953e-448f-9a59-52d1b3f2c014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209835589 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.1209835589 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_smoke/latest

Test location /workspace/coverage/default/20.kmac_stress_all.1557019428
Short name T718
Test name
Test status
Simulation time 211829044 ps
CPU time 6.41 seconds
Started Aug 09 05:55:19 PM PDT 24
Finished Aug 09 05:55:26 PM PDT 24
Peak memory 219760 kb
Host smart-20cebaad-2d13-4a98-9125-d5842c995d62
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1557019428 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.1557019428 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_stress_all/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_kmac.2873484021
Short name T973
Test name
Test status
Simulation time 481909051 ps
CPU time 5.96 seconds
Started Aug 09 05:55:20 PM PDT 24
Finished Aug 09 05:55:26 PM PDT 24
Peak memory 219816 kb
Host smart-8b1e5920-59cc-4f3e-b6c6-31727f9ee864
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873484021 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.kmac_test_vectors_kmac.2873484021 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_kmac_xof.875104509
Short name T657
Test name
Test status
Simulation time 745551965 ps
CPU time 5.85 seconds
Started Aug 09 05:55:20 PM PDT 24
Finished Aug 09 05:55:26 PM PDT 24
Peak memory 218856 kb
Host smart-8e764608-ebe7-473e-9b4e-389600c3fe73
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875104509 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.kmac_test_vectors_kmac_xof.875104509 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_224.2935514059
Short name T84
Test name
Test status
Simulation time 26723330299 ps
CPU time 2124.7 seconds
Started Aug 09 05:55:14 PM PDT 24
Finished Aug 09 06:30:39 PM PDT 24
Peak memory 1150540 kb
Host smart-59ff16d7-895b-45d3-8373-0b514fd829da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2935514059 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_224.2935514059 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_256.1313835293
Short name T458
Test name
Test status
Simulation time 20132602492 ps
CPU time 2159.93 seconds
Started Aug 09 05:55:14 PM PDT 24
Finished Aug 09 06:31:14 PM PDT 24
Peak memory 1129332 kb
Host smart-597abb6f-9902-4470-9c37-7b4ae6d21011
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1313835293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_256.1313835293 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_384.2896573068
Short name T277
Test name
Test status
Simulation time 97225149996 ps
CPU time 2318.26 seconds
Started Aug 09 05:55:19 PM PDT 24
Finished Aug 09 06:33:58 PM PDT 24
Peak memory 2405484 kb
Host smart-686bcd5a-665e-4a01-b717-8ecb47de32dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2896573068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_384.2896573068 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_512.3172586884
Short name T267
Test name
Test status
Simulation time 59501201591 ps
CPU time 1223.46 seconds
Started Aug 09 05:55:16 PM PDT 24
Finished Aug 09 06:15:40 PM PDT 24
Peak memory 708672 kb
Host smart-a4fb9243-cacf-4919-8e82-2512ad8cd561
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3172586884 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_512.3172586884 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_shake_128.2596585793
Short name T680
Test name
Test status
Simulation time 121212382582 ps
CPU time 6599.57 seconds
Started Aug 09 05:55:14 PM PDT 24
Finished Aug 09 07:45:15 PM PDT 24
Peak memory 2693432 kb
Host smart-fd9e2ce7-131e-4a34-b4bc-044e70265a3e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2596585793 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_128.2596585793 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_shake_256.463700674
Short name T195
Test name
Test status
Simulation time 52479421908 ps
CPU time 5216.76 seconds
Started Aug 09 05:55:20 PM PDT 24
Finished Aug 09 07:22:17 PM PDT 24
Peak memory 2234028 kb
Host smart-6fcad267-69cd-4cf8-af0e-20048a2508e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=463700674 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_256.463700674 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/21.kmac_alert_test.3280551126
Short name T825
Test name
Test status
Simulation time 12649239 ps
CPU time 0.83 seconds
Started Aug 09 05:55:34 PM PDT 24
Finished Aug 09 05:55:35 PM PDT 24
Peak memory 218544 kb
Host smart-0e0e7874-649c-4db5-b8f2-74a8ceaa04f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280551126 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.3280551126 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_alert_test/latest

Test location /workspace/coverage/default/21.kmac_app.584972460
Short name T860
Test name
Test status
Simulation time 8033343272 ps
CPU time 105.72 seconds
Started Aug 09 05:55:34 PM PDT 24
Finished Aug 09 05:57:19 PM PDT 24
Peak memory 295940 kb
Host smart-04ccb087-5b2d-4ec0-ae1c-628867265c47
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584972460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.584972460 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/21.kmac_app/latest

Test location /workspace/coverage/default/21.kmac_burst_write.2548200902
Short name T606
Test name
Test status
Simulation time 16733155391 ps
CPU time 1030.28 seconds
Started Aug 09 05:55:25 PM PDT 24
Finished Aug 09 06:12:35 PM PDT 24
Peak memory 251384 kb
Host smart-dbdb7b4b-2517-4203-884d-2bf49c490008
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548200902 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.254820090
2 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_burst_write/latest

Test location /workspace/coverage/default/21.kmac_error.1739837910
Short name T515
Test name
Test status
Simulation time 11804470780 ps
CPU time 157.98 seconds
Started Aug 09 05:55:35 PM PDT 24
Finished Aug 09 05:58:13 PM PDT 24
Peak memory 347680 kb
Host smart-8705d853-866b-477f-84a2-6d3cbda64057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739837910 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_error.1739837910 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_error/latest

Test location /workspace/coverage/default/21.kmac_key_error.2057803544
Short name T959
Test name
Test status
Simulation time 5079365086 ps
CPU time 12.4 seconds
Started Aug 09 05:55:32 PM PDT 24
Finished Aug 09 05:55:45 PM PDT 24
Peak memory 226776 kb
Host smart-a19b1408-9422-46e8-8658-26868ccde9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057803544 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.2057803544 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_key_error/latest

Test location /workspace/coverage/default/21.kmac_lc_escalation.390335017
Short name T80
Test name
Test status
Simulation time 45866217 ps
CPU time 1.69 seconds
Started Aug 09 05:55:32 PM PDT 24
Finished Aug 09 05:55:34 PM PDT 24
Peak memory 222016 kb
Host smart-be53256c-9828-4779-a6cc-fe54e89b3762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390335017 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.390335017 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/21.kmac_lc_escalation/latest

Test location /workspace/coverage/default/21.kmac_long_msg_and_output.3416195024
Short name T631
Test name
Test status
Simulation time 413714881784 ps
CPU time 3727.24 seconds
Started Aug 09 05:55:20 PM PDT 24
Finished Aug 09 06:57:28 PM PDT 24
Peak memory 3137116 kb
Host smart-1ff6b54c-c9af-4517-b8d7-526e1693c944
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416195024 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_a
nd_output.3416195024 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/21.kmac_sideload.2477999653
Short name T645
Test name
Test status
Simulation time 165905427 ps
CPU time 6.75 seconds
Started Aug 09 05:55:26 PM PDT 24
Finished Aug 09 05:55:33 PM PDT 24
Peak memory 225800 kb
Host smart-44fcdfcd-f83f-4641-8f9f-d5ced38a0956
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477999653 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.2477999653 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_sideload/latest

Test location /workspace/coverage/default/21.kmac_smoke.4281606304
Short name T863
Test name
Test status
Simulation time 1475933806 ps
CPU time 30.58 seconds
Started Aug 09 05:55:19 PM PDT 24
Finished Aug 09 05:55:50 PM PDT 24
Peak memory 226868 kb
Host smart-6d7601da-2afc-4b2e-91f6-90795f4d3879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281606304 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.4281606304 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_smoke/latest

Test location /workspace/coverage/default/21.kmac_stress_all.2250632630
Short name T915
Test name
Test status
Simulation time 21543389688 ps
CPU time 169.72 seconds
Started Aug 09 05:55:31 PM PDT 24
Finished Aug 09 05:58:21 PM PDT 24
Peak memory 333508 kb
Host smart-496921e6-7e62-41c4-bbc5-222b25addf8c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2250632630 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.2250632630 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_stress_all/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_kmac.3854484355
Short name T771
Test name
Test status
Simulation time 439388986 ps
CPU time 5.9 seconds
Started Aug 09 05:55:23 PM PDT 24
Finished Aug 09 05:55:29 PM PDT 24
Peak memory 219140 kb
Host smart-23e4e4a0-3b5b-41c4-b3f4-d826fffae622
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854484355 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.kmac_test_vectors_kmac.3854484355 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_kmac_xof.3345047980
Short name T392
Test name
Test status
Simulation time 1928298302 ps
CPU time 6.11 seconds
Started Aug 09 05:55:32 PM PDT 24
Finished Aug 09 05:55:38 PM PDT 24
Peak memory 219848 kb
Host smart-34ad7479-09ff-4376-ac0a-220c3fe7a8ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345047980 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.kmac_test_vectors_kmac_xof.3345047980 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_224.1997511459
Short name T256
Test name
Test status
Simulation time 271093409537 ps
CPU time 3505.24 seconds
Started Aug 09 05:55:25 PM PDT 24
Finished Aug 09 06:53:50 PM PDT 24
Peak memory 3215688 kb
Host smart-68484dca-b16f-4ad4-a4b1-2fff1a706d57
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1997511459 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_224.1997511459 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_256.2067446143
Short name T331
Test name
Test status
Simulation time 250558951365 ps
CPU time 3027.5 seconds
Started Aug 09 05:55:25 PM PDT 24
Finished Aug 09 06:45:53 PM PDT 24
Peak memory 2966492 kb
Host smart-5e140c0c-d975-4474-9f85-f3490f4ac985
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2067446143 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_256.2067446143 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_384.1996130704
Short name T377
Test name
Test status
Simulation time 15392386101 ps
CPU time 1815.45 seconds
Started Aug 09 05:55:26 PM PDT 24
Finished Aug 09 06:25:42 PM PDT 24
Peak memory 933388 kb
Host smart-469fb722-de67-4967-9623-8b9b53d3138e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1996130704 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_384.1996130704 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_512.2072520697
Short name T404
Test name
Test status
Simulation time 42233315057 ps
CPU time 1259.41 seconds
Started Aug 09 05:55:25 PM PDT 24
Finished Aug 09 06:16:25 PM PDT 24
Peak memory 707956 kb
Host smart-b50af032-400f-4705-8716-3037f716ff0a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2072520697 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_512.2072520697 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_shake_256.3947244299
Short name T390
Test name
Test status
Simulation time 1883621017691 ps
CPU time 10298.4 seconds
Started Aug 09 05:55:26 PM PDT 24
Finished Aug 09 08:47:06 PM PDT 24
Peak memory 6420104 kb
Host smart-c7f87e44-4081-473f-b634-bbd13dbb309f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3947244299 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_256.3947244299 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/22.kmac_alert_test.3974676887
Short name T589
Test name
Test status
Simulation time 43155488 ps
CPU time 0.82 seconds
Started Aug 09 05:55:37 PM PDT 24
Finished Aug 09 05:55:38 PM PDT 24
Peak memory 218568 kb
Host smart-4ec50bea-258c-41f0-bccf-eae12259e0d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974676887 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.3974676887 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_alert_test/latest

Test location /workspace/coverage/default/22.kmac_app.63125343
Short name T341
Test name
Test status
Simulation time 46472493262 ps
CPU time 353.42 seconds
Started Aug 09 05:55:39 PM PDT 24
Finished Aug 09 06:01:32 PM PDT 24
Peak memory 341760 kb
Host smart-fb6b35e1-beb9-4d0b-9283-5a92b5c0a405
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63125343 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.63125343 +enable_masking=1
+sw_key_masked=0
Directory /workspace/22.kmac_app/latest

Test location /workspace/coverage/default/22.kmac_burst_write.2393900304
Short name T452
Test name
Test status
Simulation time 906457299 ps
CPU time 9.85 seconds
Started Aug 09 05:55:31 PM PDT 24
Finished Aug 09 05:55:41 PM PDT 24
Peak memory 224696 kb
Host smart-b1d81938-4c26-4d76-a390-a53dc8fbc325
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393900304 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.239390030
4 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_burst_write/latest

Test location /workspace/coverage/default/22.kmac_entropy_refresh.643498805
Short name T942
Test name
Test status
Simulation time 55532485304 ps
CPU time 213.6 seconds
Started Aug 09 05:55:40 PM PDT 24
Finished Aug 09 05:59:14 PM PDT 24
Peak memory 382556 kb
Host smart-69e99586-585d-47fc-94ae-0d7be35b8cdd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643498805 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.64
3498805 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/22.kmac_error.2453642198
Short name T563
Test name
Test status
Simulation time 26138633878 ps
CPU time 363.24 seconds
Started Aug 09 05:55:38 PM PDT 24
Finished Aug 09 06:01:42 PM PDT 24
Peak memory 499464 kb
Host smart-736d3c00-c063-4a3b-9690-a3cf1821d883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453642198 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.2453642198 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_error/latest

Test location /workspace/coverage/default/22.kmac_key_error.1867197055
Short name T1043
Test name
Test status
Simulation time 5584655482 ps
CPU time 12.43 seconds
Started Aug 09 05:55:39 PM PDT 24
Finished Aug 09 05:55:51 PM PDT 24
Peak memory 226788 kb
Host smart-3decc3fd-f833-42e3-a37e-8d984efde108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867197055 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.1867197055 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_key_error/latest

Test location /workspace/coverage/default/22.kmac_lc_escalation.3473666176
Short name T521
Test name
Test status
Simulation time 379356047 ps
CPU time 1.36 seconds
Started Aug 09 05:55:38 PM PDT 24
Finished Aug 09 05:55:40 PM PDT 24
Peak memory 226856 kb
Host smart-d51f8cc4-1c20-4a20-a553-5ccf7ef033b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473666176 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.3473666176 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/22.kmac_lc_escalation/latest

Test location /workspace/coverage/default/22.kmac_long_msg_and_output.1318083714
Short name T348
Test name
Test status
Simulation time 22194180772 ps
CPU time 755.3 seconds
Started Aug 09 05:55:35 PM PDT 24
Finished Aug 09 06:08:10 PM PDT 24
Peak memory 984224 kb
Host smart-b974ec90-8f02-4386-b731-219e02a7a004
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318083714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_a
nd_output.1318083714 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/22.kmac_sideload.3976221935
Short name T356
Test name
Test status
Simulation time 320713794 ps
CPU time 14.8 seconds
Started Aug 09 05:55:34 PM PDT 24
Finished Aug 09 05:55:49 PM PDT 24
Peak memory 226076 kb
Host smart-0cf71d1f-71fa-4d4a-bc1b-d18fc64fdebb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976221935 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.3976221935 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_sideload/latest

Test location /workspace/coverage/default/22.kmac_smoke.1803530688
Short name T544
Test name
Test status
Simulation time 14049808572 ps
CPU time 77.34 seconds
Started Aug 09 05:55:32 PM PDT 24
Finished Aug 09 05:56:50 PM PDT 24
Peak memory 227060 kb
Host smart-f32ba92c-bea8-4588-97c5-fcbb4023f910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803530688 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.1803530688 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_smoke/latest

Test location /workspace/coverage/default/22.kmac_stress_all.79611587
Short name T852
Test name
Test status
Simulation time 64910077003 ps
CPU time 1403.34 seconds
Started Aug 09 05:55:39 PM PDT 24
Finished Aug 09 06:19:03 PM PDT 24
Peak memory 572616 kb
Host smart-12841d83-e0d2-4740-b58b-57f14b60efc5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=79611587 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.79611587 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_stress_all/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_kmac.456604282
Short name T811
Test name
Test status
Simulation time 238399943 ps
CPU time 6.29 seconds
Started Aug 09 05:55:40 PM PDT 24
Finished Aug 09 05:55:46 PM PDT 24
Peak memory 218844 kb
Host smart-b1914f37-f6d4-4ee3-b0ec-52c69dc36449
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456604282 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.kmac_test_vectors_kmac.456604282 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_kmac_xof.1350315476
Short name T791
Test name
Test status
Simulation time 813984488 ps
CPU time 6.41 seconds
Started Aug 09 05:55:39 PM PDT 24
Finished Aug 09 05:55:45 PM PDT 24
Peak memory 219720 kb
Host smart-bc5ab5f6-e4a7-4351-8408-c16234ef511a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350315476 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.kmac_test_vectors_kmac_xof.1350315476 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_224.401071318
Short name T467
Test name
Test status
Simulation time 41399436989 ps
CPU time 2410.08 seconds
Started Aug 09 05:55:32 PM PDT 24
Finished Aug 09 06:35:43 PM PDT 24
Peak memory 1214832 kb
Host smart-60b3bb78-381d-4f53-9b01-91390e5942c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=401071318 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_224.401071318 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_256.619020155
Short name T868
Test name
Test status
Simulation time 85557053317 ps
CPU time 3179.48 seconds
Started Aug 09 05:55:33 PM PDT 24
Finished Aug 09 06:48:33 PM PDT 24
Peak memory 3112744 kb
Host smart-c9310bea-ac9d-4782-b182-8de7fda42473
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=619020155 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_256.619020155 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_384.3385222416
Short name T983
Test name
Test status
Simulation time 71325885483 ps
CPU time 2603.43 seconds
Started Aug 09 05:55:33 PM PDT 24
Finished Aug 09 06:38:57 PM PDT 24
Peak memory 2320840 kb
Host smart-dcf72673-3892-4cd8-90b4-61425d5a70a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3385222416 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_384.3385222416 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_512.4134878961
Short name T710
Test name
Test status
Simulation time 40876970755 ps
CPU time 1278.64 seconds
Started Aug 09 05:55:34 PM PDT 24
Finished Aug 09 06:16:53 PM PDT 24
Peak memory 717180 kb
Host smart-d4a5fa5a-c432-4d48-8b87-321e0778549a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4134878961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_512.4134878961 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_shake_128.4077001560
Short name T225
Test name
Test status
Simulation time 379487759114 ps
CPU time 6239.96 seconds
Started Aug 09 05:55:33 PM PDT 24
Finished Aug 09 07:39:33 PM PDT 24
Peak memory 2696072 kb
Host smart-0f18784a-b4d1-44ee-a2f6-59e75cc99afc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4077001560 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_128.4077001560 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_shake_256.3996906639
Short name T249
Test name
Test status
Simulation time 982845135813 ps
CPU time 9370.2 seconds
Started Aug 09 05:55:32 PM PDT 24
Finished Aug 09 08:31:43 PM PDT 24
Peak memory 6311384 kb
Host smart-e5fa8149-8fad-4a45-8fc2-82ec01ab3a85
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3996906639 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_256.3996906639 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/23.kmac_alert_test.1979819862
Short name T688
Test name
Test status
Simulation time 19342765 ps
CPU time 0.8 seconds
Started Aug 09 05:55:52 PM PDT 24
Finished Aug 09 05:55:53 PM PDT 24
Peak memory 218560 kb
Host smart-f89a1b1f-02f7-4c09-9d92-59d2a1afc347
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979819862 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.1979819862 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_alert_test/latest

Test location /workspace/coverage/default/23.kmac_app.1519417039
Short name T672
Test name
Test status
Simulation time 2020136156 ps
CPU time 20.88 seconds
Started Aug 09 05:55:53 PM PDT 24
Finished Aug 09 05:56:14 PM PDT 24
Peak memory 240940 kb
Host smart-9b771cbf-5342-46ce-a6e3-614dd1b65d8b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519417039 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.1519417039 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/23.kmac_app/latest

Test location /workspace/coverage/default/23.kmac_burst_write.4182202811
Short name T156
Test name
Test status
Simulation time 12074736976 ps
CPU time 583.88 seconds
Started Aug 09 05:55:45 PM PDT 24
Finished Aug 09 06:05:29 PM PDT 24
Peak memory 243600 kb
Host smart-26228df6-f73f-412e-ad12-a7cea07c5806
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182202811 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.418220281
1 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_burst_write/latest

Test location /workspace/coverage/default/23.kmac_entropy_refresh.3275501436
Short name T70
Test name
Test status
Simulation time 14135854090 ps
CPU time 321.17 seconds
Started Aug 09 05:55:54 PM PDT 24
Finished Aug 09 06:01:15 PM PDT 24
Peak memory 330340 kb
Host smart-8e5c3569-b82f-49b1-bb55-b0a0f76857c9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275501436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.3
275501436 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/23.kmac_error.586134502
Short name T726
Test name
Test status
Simulation time 5100625349 ps
CPU time 230.58 seconds
Started Aug 09 05:55:52 PM PDT 24
Finished Aug 09 05:59:43 PM PDT 24
Peak memory 308368 kb
Host smart-26255035-b9cc-4724-a7c8-19b43b04569d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586134502 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.586134502 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_error/latest

Test location /workspace/coverage/default/23.kmac_key_error.1391816340
Short name T876
Test name
Test status
Simulation time 2759496330 ps
CPU time 4 seconds
Started Aug 09 05:55:54 PM PDT 24
Finished Aug 09 05:55:58 PM PDT 24
Peak memory 226792 kb
Host smart-93de42df-e597-4d6c-b7f2-1c05dfdfbed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391816340 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.1391816340 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_key_error/latest

Test location /workspace/coverage/default/23.kmac_lc_escalation.3296175931
Short name T794
Test name
Test status
Simulation time 171234196 ps
CPU time 1.46 seconds
Started Aug 09 05:55:54 PM PDT 24
Finished Aug 09 05:55:55 PM PDT 24
Peak memory 226792 kb
Host smart-933ddccb-13a9-44f2-a17f-6cb08de1f303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296175931 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.3296175931 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/23.kmac_lc_escalation/latest

Test location /workspace/coverage/default/23.kmac_long_msg_and_output.1187481483
Short name T927
Test name
Test status
Simulation time 24966620438 ps
CPU time 175.95 seconds
Started Aug 09 05:55:46 PM PDT 24
Finished Aug 09 05:58:42 PM PDT 24
Peak memory 445364 kb
Host smart-d270fbc3-695b-4836-ba30-a7cffc1b51bb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187481483 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_a
nd_output.1187481483 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/23.kmac_sideload.275568949
Short name T808
Test name
Test status
Simulation time 7504705030 ps
CPU time 77.94 seconds
Started Aug 09 05:55:47 PM PDT 24
Finished Aug 09 05:57:05 PM PDT 24
Peak memory 279128 kb
Host smart-a68325c9-1409-4c8d-98e0-85238c630887
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275568949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.275568949 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_sideload/latest

Test location /workspace/coverage/default/23.kmac_smoke.3601131529
Short name T862
Test name
Test status
Simulation time 4850517692 ps
CPU time 46.65 seconds
Started Aug 09 05:55:46 PM PDT 24
Finished Aug 09 05:56:33 PM PDT 24
Peak memory 227028 kb
Host smart-d6272ed0-726f-4f83-8a49-283b5293f674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601131529 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.3601131529 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_smoke/latest

Test location /workspace/coverage/default/23.kmac_stress_all.4078126525
Short name T933
Test name
Test status
Simulation time 27417996136 ps
CPU time 471.22 seconds
Started Aug 09 05:55:54 PM PDT 24
Finished Aug 09 06:03:46 PM PDT 24
Peak memory 333780 kb
Host smart-e957e00c-c828-4019-937d-5ee265846767
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4078126525 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.4078126525 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_stress_all/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_kmac.1779020798
Short name T897
Test name
Test status
Simulation time 442180803 ps
CPU time 5.83 seconds
Started Aug 09 05:55:53 PM PDT 24
Finished Aug 09 05:55:59 PM PDT 24
Peak memory 219828 kb
Host smart-8976f165-b650-4a5e-9983-2b570920f1bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779020798 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.kmac_test_vectors_kmac.1779020798 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_kmac_xof.381880491
Short name T564
Test name
Test status
Simulation time 105953540 ps
CPU time 6.24 seconds
Started Aug 09 05:55:53 PM PDT 24
Finished Aug 09 05:56:00 PM PDT 24
Peak memory 218900 kb
Host smart-c4307fbb-b7e4-44b2-a6f2-e1a4faf76828
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381880491 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.kmac_test_vectors_kmac_xof.381880491 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_224.3241132570
Short name T268
Test name
Test status
Simulation time 272025337513 ps
CPU time 3349.78 seconds
Started Aug 09 05:55:44 PM PDT 24
Finished Aug 09 06:51:34 PM PDT 24
Peak memory 3207508 kb
Host smart-6dd320df-ad25-426d-a996-4ca2eecec36a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3241132570 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_224.3241132570 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_256.2226040808
Short name T743
Test name
Test status
Simulation time 67243814225 ps
CPU time 3117.84 seconds
Started Aug 09 05:55:45 PM PDT 24
Finished Aug 09 06:47:44 PM PDT 24
Peak memory 3019348 kb
Host smart-ed242cbf-ccf6-41cd-8696-6398ccb1c1de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2226040808 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_256.2226040808 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_384.1430802799
Short name T127
Test name
Test status
Simulation time 520034710688 ps
CPU time 2457.45 seconds
Started Aug 09 05:55:45 PM PDT 24
Finished Aug 09 06:36:43 PM PDT 24
Peak memory 2358524 kb
Host smart-62d93863-3c4f-4f02-91bf-a880c0b825cb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1430802799 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_384.1430802799 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_512.3019950069
Short name T339
Test name
Test status
Simulation time 12256729862 ps
CPU time 1129.07 seconds
Started Aug 09 05:55:45 PM PDT 24
Finished Aug 09 06:14:34 PM PDT 24
Peak memory 696268 kb
Host smart-eeee352a-a193-411b-9521-53944c1347e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3019950069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_512.3019950069 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_shake_256.3006758886
Short name T130
Test name
Test status
Simulation time 105570623217 ps
CPU time 5346.71 seconds
Started Aug 09 05:55:53 PM PDT 24
Finished Aug 09 07:25:01 PM PDT 24
Peak memory 2273764 kb
Host smart-dee19863-175c-4afd-86d6-bf00dccaba1b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3006758886 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_256.3006758886 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/24.kmac_alert_test.1662823454
Short name T567
Test name
Test status
Simulation time 14965688 ps
CPU time 0.82 seconds
Started Aug 09 05:56:04 PM PDT 24
Finished Aug 09 05:56:05 PM PDT 24
Peak memory 218584 kb
Host smart-dfd3492d-23a9-4ecb-8bb3-62d4aef00d04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662823454 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.1662823454 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_alert_test/latest

Test location /workspace/coverage/default/24.kmac_app.3539527361
Short name T396
Test name
Test status
Simulation time 9262199118 ps
CPU time 231.93 seconds
Started Aug 09 05:56:04 PM PDT 24
Finished Aug 09 05:59:56 PM PDT 24
Peak memory 378132 kb
Host smart-6a33a00e-56af-4fb4-a1f8-c536875dd227
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539527361 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.3539527361 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/24.kmac_app/latest

Test location /workspace/coverage/default/24.kmac_burst_write.1283710414
Short name T280
Test name
Test status
Simulation time 29766897863 ps
CPU time 808.68 seconds
Started Aug 09 05:55:59 PM PDT 24
Finished Aug 09 06:09:28 PM PDT 24
Peak memory 248748 kb
Host smart-fd1161c4-27d5-45e8-8d2c-a89a161aad2b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283710414 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.128371041
4 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_burst_write/latest

Test location /workspace/coverage/default/24.kmac_entropy_refresh.3193485593
Short name T69
Test name
Test status
Simulation time 14248115203 ps
CPU time 420.04 seconds
Started Aug 09 05:56:04 PM PDT 24
Finished Aug 09 06:03:05 PM PDT 24
Peak memory 349876 kb
Host smart-fbb73edf-64bc-402b-92d2-c856951728b7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193485593 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.3
193485593 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/24.kmac_error.3321220110
Short name T690
Test name
Test status
Simulation time 85546182 ps
CPU time 3.43 seconds
Started Aug 09 05:56:03 PM PDT 24
Finished Aug 09 05:56:07 PM PDT 24
Peak memory 225828 kb
Host smart-06ab2c79-4c50-4f08-87f7-787658e87729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321220110 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.3321220110 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_error/latest

Test location /workspace/coverage/default/24.kmac_key_error.2322007166
Short name T518
Test name
Test status
Simulation time 1625695770 ps
CPU time 3.88 seconds
Started Aug 09 05:56:04 PM PDT 24
Finished Aug 09 05:56:08 PM PDT 24
Peak memory 226604 kb
Host smart-45a99ed9-8d23-48aa-9dcf-52f7f292d5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322007166 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.2322007166 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_key_error/latest

Test location /workspace/coverage/default/24.kmac_lc_escalation.978984006
Short name T470
Test name
Test status
Simulation time 399592551 ps
CPU time 7.58 seconds
Started Aug 09 05:56:05 PM PDT 24
Finished Aug 09 05:56:13 PM PDT 24
Peak memory 235208 kb
Host smart-132f12c8-d6c2-4ff7-981d-4c430da516f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978984006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.978984006 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/24.kmac_lc_escalation/latest

Test location /workspace/coverage/default/24.kmac_long_msg_and_output.2356496033
Short name T191
Test name
Test status
Simulation time 98070723172 ps
CPU time 5276.48 seconds
Started Aug 09 05:55:54 PM PDT 24
Finished Aug 09 07:23:52 PM PDT 24
Peak memory 3933000 kb
Host smart-e27b8d43-4dc9-430e-a363-8499afc11dea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356496033 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_a
nd_output.2356496033 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/24.kmac_sideload.977128199
Short name T644
Test name
Test status
Simulation time 9566038686 ps
CPU time 239.11 seconds
Started Aug 09 05:55:52 PM PDT 24
Finished Aug 09 05:59:51 PM PDT 24
Peak memory 309392 kb
Host smart-2ef16477-c384-488a-bb09-0a43c1048804
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977128199 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.977128199 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_sideload/latest

Test location /workspace/coverage/default/24.kmac_smoke.477095818
Short name T613
Test name
Test status
Simulation time 3691072515 ps
CPU time 18.11 seconds
Started Aug 09 05:55:53 PM PDT 24
Finished Aug 09 05:56:12 PM PDT 24
Peak memory 227060 kb
Host smart-c603afbc-a3ea-48a6-83f9-e71a1a4b8708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477095818 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.477095818 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_smoke/latest

Test location /workspace/coverage/default/24.kmac_stress_all.119972903
Short name T689
Test name
Test status
Simulation time 43657820594 ps
CPU time 1351.38 seconds
Started Aug 09 05:56:03 PM PDT 24
Finished Aug 09 06:18:35 PM PDT 24
Peak memory 780756 kb
Host smart-ac3da473-92fb-482d-89b3-32828cff544d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=119972903 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.119972903 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_stress_all/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_kmac.361440384
Short name T298
Test name
Test status
Simulation time 101516029 ps
CPU time 6.17 seconds
Started Aug 09 05:56:04 PM PDT 24
Finished Aug 09 05:56:11 PM PDT 24
Peak memory 218896 kb
Host smart-e3b0592d-a73a-40f8-a70e-bf1f8ed5da02
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361440384 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.kmac_test_vectors_kmac.361440384 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_kmac_xof.1447564052
Short name T200
Test name
Test status
Simulation time 232028098 ps
CPU time 5.89 seconds
Started Aug 09 05:56:02 PM PDT 24
Finished Aug 09 05:56:08 PM PDT 24
Peak memory 220072 kb
Host smart-31d03d43-19da-46d4-bdce-be121addfe7c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447564052 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.kmac_test_vectors_kmac_xof.1447564052 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_224.2565028137
Short name T1033
Test name
Test status
Simulation time 435997202516 ps
CPU time 3282.15 seconds
Started Aug 09 05:55:58 PM PDT 24
Finished Aug 09 06:50:40 PM PDT 24
Peak memory 3225816 kb
Host smart-73b58342-441e-4f97-81f8-f056893dd790
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2565028137 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_224.2565028137 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_256.206788946
Short name T827
Test name
Test status
Simulation time 96599492647 ps
CPU time 3333.12 seconds
Started Aug 09 05:55:59 PM PDT 24
Finished Aug 09 06:51:33 PM PDT 24
Peak memory 3051676 kb
Host smart-e84f8f04-a916-4967-985d-e51893b9a786
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=206788946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_256.206788946 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_384.4188843018
Short name T894
Test name
Test status
Simulation time 206045410811 ps
CPU time 2338.32 seconds
Started Aug 09 05:56:01 PM PDT 24
Finished Aug 09 06:34:59 PM PDT 24
Peak memory 2388468 kb
Host smart-e8683072-cc3b-4501-ade2-2b0ecc200611
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4188843018 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_384.4188843018 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_512.3996622109
Short name T850
Test name
Test status
Simulation time 130194939799 ps
CPU time 1627.67 seconds
Started Aug 09 05:56:02 PM PDT 24
Finished Aug 09 06:23:10 PM PDT 24
Peak memory 1681340 kb
Host smart-85ba6963-e0a2-4d43-8fc3-62a33b0f567e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3996622109 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_512.3996622109 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_shake_128.2221838431
Short name T842
Test name
Test status
Simulation time 73380961401 ps
CPU time 6773.86 seconds
Started Aug 09 05:56:00 PM PDT 24
Finished Aug 09 07:48:55 PM PDT 24
Peak memory 2719900 kb
Host smart-cda8a032-5866-4279-80f9-71e926809814
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2221838431 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_128.2221838431 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_shake_256.1411668590
Short name T215
Test name
Test status
Simulation time 383239942441 ps
CPU time 9805.87 seconds
Started Aug 09 05:55:59 PM PDT 24
Finished Aug 09 08:39:27 PM PDT 24
Peak memory 6434288 kb
Host smart-da22a875-1628-460b-86cf-0d2d6c19fa2c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1411668590 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_256.1411668590 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/25.kmac_alert_test.1661137637
Short name T490
Test name
Test status
Simulation time 13021137 ps
CPU time 0.8 seconds
Started Aug 09 05:56:15 PM PDT 24
Finished Aug 09 05:56:16 PM PDT 24
Peak memory 218560 kb
Host smart-47a4564f-9b62-4fcc-a890-26e5cb1e703d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661137637 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.1661137637 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_alert_test/latest

Test location /workspace/coverage/default/25.kmac_app.1508092017
Short name T384
Test name
Test status
Simulation time 932549041 ps
CPU time 30.96 seconds
Started Aug 09 05:56:12 PM PDT 24
Finished Aug 09 05:56:43 PM PDT 24
Peak memory 232308 kb
Host smart-3852b49c-b7a7-4cec-8e91-dfa1d7308d9e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508092017 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.1508092017 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/25.kmac_app/latest

Test location /workspace/coverage/default/25.kmac_burst_write.3622390099
Short name T39
Test name
Test status
Simulation time 48991674742 ps
CPU time 461.31 seconds
Started Aug 09 05:56:11 PM PDT 24
Finished Aug 09 06:03:53 PM PDT 24
Peak memory 241344 kb
Host smart-bf49ae18-f48c-4e2b-9757-f5f70836fb69
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622390099 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.362239009
9 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_burst_write/latest

Test location /workspace/coverage/default/25.kmac_entropy_refresh.3683670575
Short name T787
Test name
Test status
Simulation time 45203365447 ps
CPU time 225.11 seconds
Started Aug 09 05:56:10 PM PDT 24
Finished Aug 09 05:59:56 PM PDT 24
Peak memory 389584 kb
Host smart-d7834998-ac70-458e-8572-73f10d6087f6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683670575 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.3
683670575 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/25.kmac_error.1201799803
Short name T311
Test name
Test status
Simulation time 885686886 ps
CPU time 12.5 seconds
Started Aug 09 05:56:14 PM PDT 24
Finished Aug 09 05:56:26 PM PDT 24
Peak memory 243272 kb
Host smart-0bd187da-473d-412f-8ae6-395ad9f63f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201799803 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_error.1201799803 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_error/latest

Test location /workspace/coverage/default/25.kmac_key_error.449068735
Short name T350
Test name
Test status
Simulation time 2378466989 ps
CPU time 5.21 seconds
Started Aug 09 05:56:15 PM PDT 24
Finished Aug 09 05:56:20 PM PDT 24
Peak memory 226736 kb
Host smart-97057c9b-3fa7-401d-bbc7-bc21fcfec246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449068735 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.449068735 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_key_error/latest

Test location /workspace/coverage/default/25.kmac_lc_escalation.696545972
Short name T1015
Test name
Test status
Simulation time 36999664 ps
CPU time 1.39 seconds
Started Aug 09 05:56:15 PM PDT 24
Finished Aug 09 05:56:16 PM PDT 24
Peak memory 226896 kb
Host smart-72d12eb8-e6fe-45e4-9324-93ed486669e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696545972 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.696545972 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/25.kmac_lc_escalation/latest

Test location /workspace/coverage/default/25.kmac_long_msg_and_output.3632970141
Short name T503
Test name
Test status
Simulation time 83771413273 ps
CPU time 5250.28 seconds
Started Aug 09 05:56:14 PM PDT 24
Finished Aug 09 07:23:45 PM PDT 24
Peak memory 3971300 kb
Host smart-5828abe6-6f30-4e60-a31c-6485d3111f1f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632970141 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_a
nd_output.3632970141 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/25.kmac_sideload.15091683
Short name T360
Test name
Test status
Simulation time 6380462357 ps
CPU time 226.12 seconds
Started Aug 09 05:56:10 PM PDT 24
Finished Aug 09 05:59:56 PM PDT 24
Peak memory 391996 kb
Host smart-311c4d04-eed1-4e65-b933-731bed6df087
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15091683 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.15091683 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_sideload/latest

Test location /workspace/coverage/default/25.kmac_smoke.790639856
Short name T1040
Test name
Test status
Simulation time 6130598297 ps
CPU time 57.61 seconds
Started Aug 09 05:56:05 PM PDT 24
Finished Aug 09 05:57:03 PM PDT 24
Peak memory 223748 kb
Host smart-5a64530b-16a2-4157-9155-a1ae23ce6950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790639856 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.790639856 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_smoke/latest

Test location /workspace/coverage/default/25.kmac_stress_all.3967535918
Short name T244
Test name
Test status
Simulation time 1061366669 ps
CPU time 24.62 seconds
Started Aug 09 05:56:14 PM PDT 24
Finished Aug 09 05:56:39 PM PDT 24
Peak memory 232604 kb
Host smart-fa9f1b63-ad43-478f-b086-2033045428fe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3967535918 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.3967535918 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_stress_all/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_kmac.2664880128
Short name T220
Test name
Test status
Simulation time 379654524 ps
CPU time 6.43 seconds
Started Aug 09 05:56:09 PM PDT 24
Finished Aug 09 05:56:16 PM PDT 24
Peak memory 219764 kb
Host smart-4e1fe1ae-a60e-481b-b851-5ae237c90e31
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664880128 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.kmac_test_vectors_kmac.2664880128 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_kmac_xof.3140732695
Short name T486
Test name
Test status
Simulation time 261283221 ps
CPU time 6.99 seconds
Started Aug 09 05:56:11 PM PDT 24
Finished Aug 09 05:56:18 PM PDT 24
Peak memory 218992 kb
Host smart-dd10c5a3-b989-42e9-b608-dd35294132fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140732695 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.kmac_test_vectors_kmac_xof.3140732695 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_224.23414819
Short name T1005
Test name
Test status
Simulation time 88445682056 ps
CPU time 2160.13 seconds
Started Aug 09 05:56:09 PM PDT 24
Finished Aug 09 06:32:09 PM PDT 24
Peak memory 1207232 kb
Host smart-f72814d6-41ef-4a9e-9863-75c2b6b354b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=23414819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_224.23414819 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_256.3693609873
Short name T449
Test name
Test status
Simulation time 19519209944 ps
CPU time 1942.32 seconds
Started Aug 09 05:56:14 PM PDT 24
Finished Aug 09 06:28:36 PM PDT 24
Peak memory 1131660 kb
Host smart-bbe892ef-d2c2-4602-a852-022dd9e70784
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3693609873 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_256.3693609873 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_384.113076014
Short name T1039
Test name
Test status
Simulation time 145873485741 ps
CPU time 2734.52 seconds
Started Aug 09 05:56:11 PM PDT 24
Finished Aug 09 06:41:46 PM PDT 24
Peak memory 2484888 kb
Host smart-9be6ddc0-705e-470f-8c1c-22b107d8aea8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=113076014 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_384.113076014 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_512.3474168258
Short name T885
Test name
Test status
Simulation time 138590151159 ps
CPU time 1549.84 seconds
Started Aug 09 05:56:10 PM PDT 24
Finished Aug 09 06:22:00 PM PDT 24
Peak memory 1716720 kb
Host smart-3768f6a1-2dd0-4326-b741-44ae4766a5d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3474168258 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_512.3474168258 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_shake_128.2862009238
Short name T227
Test name
Test status
Simulation time 1003729446136 ps
CPU time 6463.56 seconds
Started Aug 09 05:56:13 PM PDT 24
Finished Aug 09 07:43:57 PM PDT 24
Peak memory 2713884 kb
Host smart-1e22bd8e-c0ce-4680-a1d9-50359f31c1c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2862009238 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_128.2862009238 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/26.kmac_alert_test.1779600578
Short name T1023
Test name
Test status
Simulation time 41454588 ps
CPU time 0.8 seconds
Started Aug 09 05:56:32 PM PDT 24
Finished Aug 09 05:56:33 PM PDT 24
Peak memory 218464 kb
Host smart-663f8289-1066-4092-9c71-0949ec6d046f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779600578 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.1779600578 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_alert_test/latest

Test location /workspace/coverage/default/26.kmac_app.1893389740
Short name T893
Test name
Test status
Simulation time 14386649884 ps
CPU time 332.97 seconds
Started Aug 09 05:56:27 PM PDT 24
Finished Aug 09 06:02:01 PM PDT 24
Peak memory 338664 kb
Host smart-659aa371-c6b9-41c2-a7e6-8b281ab4bf1a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893389740 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.1893389740 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/26.kmac_app/latest

Test location /workspace/coverage/default/26.kmac_burst_write.202011988
Short name T593
Test name
Test status
Simulation time 68229068992 ps
CPU time 830.5 seconds
Started Aug 09 05:56:20 PM PDT 24
Finished Aug 09 06:10:11 PM PDT 24
Peak memory 243440 kb
Host smart-3d4dac85-6c83-4d40-a611-86ce45da2030
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202011988 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.202011988
+enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_burst_write/latest

Test location /workspace/coverage/default/26.kmac_entropy_refresh.3501263116
Short name T570
Test name
Test status
Simulation time 26656794769 ps
CPU time 295.8 seconds
Started Aug 09 05:56:28 PM PDT 24
Finished Aug 09 06:01:24 PM PDT 24
Peak memory 444192 kb
Host smart-5e36d52c-8464-48ce-910f-1d8ce9b9cfc8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501263116 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.3
501263116 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/26.kmac_error.3486701929
Short name T999
Test name
Test status
Simulation time 13402057103 ps
CPU time 286.55 seconds
Started Aug 09 05:56:28 PM PDT 24
Finished Aug 09 06:01:14 PM PDT 24
Peak memory 310812 kb
Host smart-877597d4-4ab8-493f-8db1-6852301a1393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486701929 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.3486701929 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_error/latest

Test location /workspace/coverage/default/26.kmac_key_error.3490172302
Short name T512
Test name
Test status
Simulation time 1694196142 ps
CPU time 12.05 seconds
Started Aug 09 05:56:28 PM PDT 24
Finished Aug 09 05:56:40 PM PDT 24
Peak memory 226704 kb
Host smart-746a19c1-9ee4-41f0-8b1d-176e7750421b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490172302 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.3490172302 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_key_error/latest

Test location /workspace/coverage/default/26.kmac_lc_escalation.836828380
Short name T120
Test name
Test status
Simulation time 88649016 ps
CPU time 1.39 seconds
Started Aug 09 05:56:27 PM PDT 24
Finished Aug 09 05:56:29 PM PDT 24
Peak memory 226836 kb
Host smart-482ef229-2e65-43de-a437-e1022e952ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836828380 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.836828380 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/26.kmac_lc_escalation/latest

Test location /workspace/coverage/default/26.kmac_long_msg_and_output.3761251660
Short name T921
Test name
Test status
Simulation time 262360392832 ps
CPU time 3426.86 seconds
Started Aug 09 05:56:14 PM PDT 24
Finished Aug 09 06:53:22 PM PDT 24
Peak memory 2691976 kb
Host smart-a9372a08-d740-4915-9f81-43c5e6a14fe9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761251660 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_a
nd_output.3761251660 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/26.kmac_sideload.346590637
Short name T637
Test name
Test status
Simulation time 524894303 ps
CPU time 38.18 seconds
Started Aug 09 05:56:15 PM PDT 24
Finished Aug 09 05:56:53 PM PDT 24
Peak memory 234372 kb
Host smart-c93ec9a8-4156-4704-af5c-2e28114b4d64
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346590637 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.346590637 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_sideload/latest

Test location /workspace/coverage/default/26.kmac_smoke.3153033507
Short name T533
Test name
Test status
Simulation time 3473971284 ps
CPU time 23.74 seconds
Started Aug 09 05:56:15 PM PDT 24
Finished Aug 09 05:56:39 PM PDT 24
Peak memory 222604 kb
Host smart-853aecef-c92d-4ef4-9b8a-36618e368ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153033507 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.3153033507 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_smoke/latest

Test location /workspace/coverage/default/26.kmac_stress_all.3488138180
Short name T308
Test name
Test status
Simulation time 48667823554 ps
CPU time 314.28 seconds
Started Aug 09 05:56:35 PM PDT 24
Finished Aug 09 06:01:50 PM PDT 24
Peak memory 416352 kb
Host smart-4753c98b-b01e-4f9e-b2b4-31c6510d8dfc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3488138180 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.3488138180 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_stress_all/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_kmac.1128938283
Short name T671
Test name
Test status
Simulation time 121718721 ps
CPU time 6.16 seconds
Started Aug 09 05:56:28 PM PDT 24
Finished Aug 09 05:56:34 PM PDT 24
Peak memory 218896 kb
Host smart-6ef19f13-cbfc-43d6-bd6b-91ef0494148f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128938283 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.kmac_test_vectors_kmac.1128938283 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_kmac_xof.1899743692
Short name T264
Test name
Test status
Simulation time 188317114 ps
CPU time 5.49 seconds
Started Aug 09 05:56:28 PM PDT 24
Finished Aug 09 05:56:34 PM PDT 24
Peak memory 219784 kb
Host smart-07dd5770-397f-4319-abcd-d262b6f84359
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899743692 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.kmac_test_vectors_kmac_xof.1899743692 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_224.1634664775
Short name T426
Test name
Test status
Simulation time 20813963115 ps
CPU time 2247.09 seconds
Started Aug 09 05:56:21 PM PDT 24
Finished Aug 09 06:33:48 PM PDT 24
Peak memory 1189272 kb
Host smart-e0fcd6ec-50de-4665-a4d9-c440535c334a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1634664775 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_224.1634664775 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_256.65077877
Short name T561
Test name
Test status
Simulation time 80517818145 ps
CPU time 2171.26 seconds
Started Aug 09 05:56:20 PM PDT 24
Finished Aug 09 06:32:31 PM PDT 24
Peak memory 1142580 kb
Host smart-511ee847-f197-4e2a-b0d4-2be36f7a9d25
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=65077877 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_256.65077877 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_384.8966917
Short name T602
Test name
Test status
Simulation time 120154444246 ps
CPU time 2276.1 seconds
Started Aug 09 05:56:21 PM PDT 24
Finished Aug 09 06:34:17 PM PDT 24
Peak memory 2370480 kb
Host smart-34ba0d69-40bf-45c3-8a33-10bbfeafcd74
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=8966917 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_384.8966917 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_512.559776304
Short name T937
Test name
Test status
Simulation time 10524120008 ps
CPU time 1229.93 seconds
Started Aug 09 05:56:20 PM PDT 24
Finished Aug 09 06:16:50 PM PDT 24
Peak memory 710432 kb
Host smart-a86af4aa-96d9-4c57-8875-10bf703efc1b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=559776304 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_512.559776304 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_shake_256.3833855417
Short name T500
Test name
Test status
Simulation time 150014220532 ps
CPU time 8272.27 seconds
Started Aug 09 05:56:27 PM PDT 24
Finished Aug 09 08:14:20 PM PDT 24
Peak memory 6365508 kb
Host smart-8f75d751-f619-4745-907e-3fc12357d819
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3833855417 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_256.3833855417 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/27.kmac_alert_test.2314051024
Short name T118
Test name
Test status
Simulation time 16759174 ps
CPU time 0.88 seconds
Started Aug 09 05:56:48 PM PDT 24
Finished Aug 09 05:56:49 PM PDT 24
Peak memory 218472 kb
Host smart-59e38069-50f7-4e12-9c48-cc9de5496c26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314051024 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.2314051024 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_alert_test/latest

Test location /workspace/coverage/default/27.kmac_app.2507827252
Short name T402
Test name
Test status
Simulation time 15277462728 ps
CPU time 250.03 seconds
Started Aug 09 05:56:46 PM PDT 24
Finished Aug 09 06:00:56 PM PDT 24
Peak memory 307376 kb
Host smart-6c0f5646-3303-451f-99ba-c7ec3389ac2f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507827252 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.2507827252 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/27.kmac_app/latest

Test location /workspace/coverage/default/27.kmac_burst_write.134719750
Short name T284
Test name
Test status
Simulation time 129550840006 ps
CPU time 1338.68 seconds
Started Aug 09 05:56:33 PM PDT 24
Finished Aug 09 06:18:52 PM PDT 24
Peak memory 261616 kb
Host smart-9e6406ba-abf1-40f4-9c32-a2dbeda8f2c1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134719750 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.134719750
+enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_burst_write/latest

Test location /workspace/coverage/default/27.kmac_entropy_refresh.3850710123
Short name T595
Test name
Test status
Simulation time 16823551978 ps
CPU time 488.81 seconds
Started Aug 09 05:56:46 PM PDT 24
Finished Aug 09 06:04:55 PM PDT 24
Peak memory 532220 kb
Host smart-9206601d-1e7a-491d-8b17-59cf009340b3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850710123 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.3
850710123 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/27.kmac_error.3016416557
Short name T547
Test name
Test status
Simulation time 23203268642 ps
CPU time 413.29 seconds
Started Aug 09 05:56:44 PM PDT 24
Finished Aug 09 06:03:37 PM PDT 24
Peak memory 352920 kb
Host smart-d9e4d826-0c1f-4d7e-97cd-3532616c0573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016416557 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.3016416557 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_error/latest

Test location /workspace/coverage/default/27.kmac_key_error.3028899702
Short name T1021
Test name
Test status
Simulation time 1627265582 ps
CPU time 11.55 seconds
Started Aug 09 05:56:48 PM PDT 24
Finished Aug 09 05:57:00 PM PDT 24
Peak memory 218584 kb
Host smart-e5cf2441-d170-464b-b9b6-ec4fcd5b3fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028899702 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.3028899702 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_key_error/latest

Test location /workspace/coverage/default/27.kmac_lc_escalation.468800830
Short name T54
Test name
Test status
Simulation time 800827796 ps
CPU time 51.64 seconds
Started Aug 09 05:56:45 PM PDT 24
Finished Aug 09 05:57:37 PM PDT 24
Peak memory 252688 kb
Host smart-aa5e52cf-b7d4-4ada-a6e5-f116a1ecc447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468800830 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.468800830 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/27.kmac_lc_escalation/latest

Test location /workspace/coverage/default/27.kmac_long_msg_and_output.517488339
Short name T930
Test name
Test status
Simulation time 145205919371 ps
CPU time 332.21 seconds
Started Aug 09 05:56:33 PM PDT 24
Finished Aug 09 06:02:05 PM PDT 24
Peak memory 624836 kb
Host smart-271808fe-6c63-477d-add7-3c5cfabdb191
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517488339 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_an
d_output.517488339 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/27.kmac_sideload.1901587903
Short name T292
Test name
Test status
Simulation time 86643594080 ps
CPU time 569.01 seconds
Started Aug 09 05:56:35 PM PDT 24
Finished Aug 09 06:06:04 PM PDT 24
Peak memory 661140 kb
Host smart-6910fdd6-edea-481f-8495-5372755dd45b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901587903 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.1901587903 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_sideload/latest

Test location /workspace/coverage/default/27.kmac_smoke.1263759950
Short name T603
Test name
Test status
Simulation time 13109661758 ps
CPU time 83.43 seconds
Started Aug 09 05:56:36 PM PDT 24
Finished Aug 09 05:57:59 PM PDT 24
Peak memory 227908 kb
Host smart-b8842e77-6d4a-44e4-9cb3-63bceaa35735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263759950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.1263759950 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_smoke/latest

Test location /workspace/coverage/default/27.kmac_stress_all.2753719960
Short name T741
Test name
Test status
Simulation time 77745743941 ps
CPU time 990.84 seconds
Started Aug 09 05:56:45 PM PDT 24
Finished Aug 09 06:13:16 PM PDT 24
Peak memory 744200 kb
Host smart-411fab9b-6fd4-4803-8385-e1cc9b11f975
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2753719960 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all.2753719960 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_stress_all/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_kmac.1747185157
Short name T1034
Test name
Test status
Simulation time 1792404704 ps
CPU time 6.81 seconds
Started Aug 09 05:56:46 PM PDT 24
Finished Aug 09 05:56:53 PM PDT 24
Peak memory 218932 kb
Host smart-70daf81a-a116-4311-9381-a5c43ff63bdf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747185157 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.kmac_test_vectors_kmac.1747185157 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_kmac_xof.2951392461
Short name T881
Test name
Test status
Simulation time 443679981 ps
CPU time 6.48 seconds
Started Aug 09 05:56:42 PM PDT 24
Finished Aug 09 05:56:48 PM PDT 24
Peak memory 220072 kb
Host smart-507e747b-2c75-4f06-8d4b-83d4b269b16f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951392461 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.kmac_test_vectors_kmac_xof.2951392461 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_224.764230578
Short name T424
Test name
Test status
Simulation time 566577441417 ps
CPU time 4141.73 seconds
Started Aug 09 05:56:32 PM PDT 24
Finished Aug 09 07:05:35 PM PDT 24
Peak memory 3207524 kb
Host smart-fe907ea6-f6ca-4524-b9e1-9f85d3712768
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=764230578 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_224.764230578 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_256.622240047
Short name T535
Test name
Test status
Simulation time 80080491431 ps
CPU time 2269.87 seconds
Started Aug 09 05:56:40 PM PDT 24
Finished Aug 09 06:34:30 PM PDT 24
Peak memory 1139768 kb
Host smart-344e3e07-754e-4c4e-a867-f9f9422fda80
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=622240047 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_256.622240047 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_384.888087303
Short name T618
Test name
Test status
Simulation time 784529799210 ps
CPU time 2150.84 seconds
Started Aug 09 05:56:38 PM PDT 24
Finished Aug 09 06:32:29 PM PDT 24
Peak memory 2360264 kb
Host smart-d5e4d8a0-7ce2-4e66-b74d-a025b406cb81
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=888087303 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_384.888087303 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_512.3464312251
Short name T436
Test name
Test status
Simulation time 103035858477 ps
CPU time 1818.82 seconds
Started Aug 09 05:56:38 PM PDT 24
Finished Aug 09 06:26:57 PM PDT 24
Peak memory 1771976 kb
Host smart-36dfd290-40de-4a63-b1a2-66f79a2cb23b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3464312251 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_512.3464312251 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_shake_128.2982101271
Short name T109
Test name
Test status
Simulation time 467319158477 ps
CPU time 6755.4 seconds
Started Aug 09 05:56:39 PM PDT 24
Finished Aug 09 07:49:15 PM PDT 24
Peak memory 2730052 kb
Host smart-e1afde31-2fc0-40b8-99d4-ffbefc192619
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2982101271 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_128.2982101271 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_shake_256.2182643120
Short name T920
Test name
Test status
Simulation time 209960882299 ps
CPU time 5092.93 seconds
Started Aug 09 05:56:39 PM PDT 24
Finished Aug 09 07:21:33 PM PDT 24
Peak memory 2233372 kb
Host smart-b755ee7f-9c3d-4e4a-a3fd-7ebf1fe7ab99
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2182643120 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_256.2182643120 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/28.kmac_alert_test.371130542
Short name T911
Test name
Test status
Simulation time 15457720 ps
CPU time 0.85 seconds
Started Aug 09 05:57:07 PM PDT 24
Finished Aug 09 05:57:08 PM PDT 24
Peak memory 218524 kb
Host smart-f44adfd8-7938-4bfd-aa51-018e8d7b029e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371130542 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.371130542 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/28.kmac_alert_test/latest

Test location /workspace/coverage/default/28.kmac_app.3881298766
Short name T371
Test name
Test status
Simulation time 4208222820 ps
CPU time 335.93 seconds
Started Aug 09 05:56:57 PM PDT 24
Finished Aug 09 06:02:33 PM PDT 24
Peak memory 327604 kb
Host smart-5ce2f454-4696-4071-a57d-708527490fea
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881298766 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.3881298766 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/28.kmac_app/latest

Test location /workspace/coverage/default/28.kmac_burst_write.459815228
Short name T412
Test name
Test status
Simulation time 93298626344 ps
CPU time 765.3 seconds
Started Aug 09 05:56:51 PM PDT 24
Finished Aug 09 06:09:36 PM PDT 24
Peak memory 247368 kb
Host smart-7b199805-cdb6-4f2f-8f58-7e8dc75552b3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459815228 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.459815228
+enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_burst_write/latest

Test location /workspace/coverage/default/28.kmac_error.3884179433
Short name T7
Test name
Test status
Simulation time 2507985055 ps
CPU time 214.14 seconds
Started Aug 09 05:57:08 PM PDT 24
Finished Aug 09 06:00:42 PM PDT 24
Peak memory 308156 kb
Host smart-72c17676-4957-4773-bf00-b7cc3c2087e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884179433 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.3884179433 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_error/latest

Test location /workspace/coverage/default/28.kmac_key_error.558522615
Short name T1042
Test name
Test status
Simulation time 2784840485 ps
CPU time 10.78 seconds
Started Aug 09 05:57:08 PM PDT 24
Finished Aug 09 05:57:19 PM PDT 24
Peak memory 226752 kb
Host smart-97204487-23a7-4dc8-ad16-a06b723ea0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558522615 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.558522615 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_key_error/latest

Test location /workspace/coverage/default/28.kmac_lc_escalation.3141982721
Short name T580
Test name
Test status
Simulation time 140649992 ps
CPU time 1.29 seconds
Started Aug 09 05:57:13 PM PDT 24
Finished Aug 09 05:57:15 PM PDT 24
Peak memory 226852 kb
Host smart-a0a13b9f-4815-4725-a9ce-662204e2e25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141982721 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.3141982721 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/28.kmac_lc_escalation/latest

Test location /workspace/coverage/default/28.kmac_long_msg_and_output.3375857372
Short name T612
Test name
Test status
Simulation time 119490386044 ps
CPU time 4299.56 seconds
Started Aug 09 05:56:52 PM PDT 24
Finished Aug 09 07:08:32 PM PDT 24
Peak memory 1926472 kb
Host smart-fa885c2f-e469-404b-93a0-8bc0e65d4e96
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375857372 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_a
nd_output.3375857372 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/28.kmac_sideload.1968267200
Short name T301
Test name
Test status
Simulation time 12151134698 ps
CPU time 457.94 seconds
Started Aug 09 05:56:52 PM PDT 24
Finished Aug 09 06:04:30 PM PDT 24
Peak memory 386484 kb
Host smart-1a0e0190-43f2-4ccd-b721-dce0cb304636
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968267200 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.1968267200 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_sideload/latest

Test location /workspace/coverage/default/28.kmac_smoke.3231492070
Short name T273
Test name
Test status
Simulation time 5645517718 ps
CPU time 30.3 seconds
Started Aug 09 05:56:46 PM PDT 24
Finished Aug 09 05:57:16 PM PDT 24
Peak memory 227004 kb
Host smart-5071b4d4-0758-4fdb-abd0-176a33cfdab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231492070 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.3231492070 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_smoke/latest

Test location /workspace/coverage/default/28.kmac_stress_all.1649549546
Short name T296
Test name
Test status
Simulation time 5698350476 ps
CPU time 539.98 seconds
Started Aug 09 05:57:07 PM PDT 24
Finished Aug 09 06:06:07 PM PDT 24
Peak memory 306052 kb
Host smart-c3872976-7295-479f-a310-b0697965ad58
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1649549546 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.1649549546 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_stress_all/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_kmac.90034294
Short name T985
Test name
Test status
Simulation time 547717689 ps
CPU time 7.23 seconds
Started Aug 09 05:56:56 PM PDT 24
Finished Aug 09 05:57:04 PM PDT 24
Peak memory 219732 kb
Host smart-4121abbd-a692-42bb-a675-0d1891bc9470
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90034294 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 28.kmac_test_vectors_kmac.90034294 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_kmac_xof.2255355541
Short name T198
Test name
Test status
Simulation time 369682297 ps
CPU time 6.38 seconds
Started Aug 09 05:56:56 PM PDT 24
Finished Aug 09 05:57:03 PM PDT 24
Peak memory 219184 kb
Host smart-e6f1a890-41ad-4535-aad9-79dd01b6c031
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255355541 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.kmac_test_vectors_kmac_xof.2255355541 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_224.2152624573
Short name T650
Test name
Test status
Simulation time 142866051626 ps
CPU time 3504.22 seconds
Started Aug 09 05:56:50 PM PDT 24
Finished Aug 09 06:55:15 PM PDT 24
Peak memory 3262604 kb
Host smart-72cf3093-9869-4bd3-81d0-4e86f8bb93e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2152624573 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_224.2152624573 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_256.224565319
Short name T505
Test name
Test status
Simulation time 94041268489 ps
CPU time 3403.24 seconds
Started Aug 09 05:56:51 PM PDT 24
Finished Aug 09 06:53:34 PM PDT 24
Peak memory 3072588 kb
Host smart-c69a2d47-b388-4935-8a50-530a76ba7f86
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=224565319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_256.224565319 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_384.4204333296
Short name T585
Test name
Test status
Simulation time 262504808557 ps
CPU time 2370.77 seconds
Started Aug 09 05:56:54 PM PDT 24
Finished Aug 09 06:36:25 PM PDT 24
Peak memory 2379072 kb
Host smart-9ce9acb1-6ad6-42ec-838d-d16473111b0e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4204333296 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_384.4204333296 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_512.3859830145
Short name T242
Test name
Test status
Simulation time 65637100379 ps
CPU time 1329.55 seconds
Started Aug 09 05:56:51 PM PDT 24
Finished Aug 09 06:19:01 PM PDT 24
Peak memory 701552 kb
Host smart-ed8123cc-5643-47cc-ae76-8559c848f436
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3859830145 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_512.3859830145 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_shake_128.304615237
Short name T769
Test name
Test status
Simulation time 242206342935 ps
CPU time 6389.39 seconds
Started Aug 09 05:56:52 PM PDT 24
Finished Aug 09 07:43:22 PM PDT 24
Peak memory 2662844 kb
Host smart-2784db15-fba7-4f41-8691-2cfaf93be9f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=304615237 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_128.304615237 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_shake_256.2098387437
Short name T839
Test name
Test status
Simulation time 266176331023 ps
CPU time 5292.81 seconds
Started Aug 09 05:56:56 PM PDT 24
Finished Aug 09 07:25:09 PM PDT 24
Peak memory 2197588 kb
Host smart-c2d82afc-7ce6-466c-ba3a-8f94f41d8792
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2098387437 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_256.2098387437 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/29.kmac_alert_test.3126986177
Short name T643
Test name
Test status
Simulation time 38554536 ps
CPU time 0.8 seconds
Started Aug 09 05:57:24 PM PDT 24
Finished Aug 09 05:57:25 PM PDT 24
Peak memory 218524 kb
Host smart-448004f2-b80a-4ea6-8feb-21b7f24343c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126986177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.3126986177 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_alert_test/latest

Test location /workspace/coverage/default/29.kmac_app.152564228
Short name T971
Test name
Test status
Simulation time 2567060096 ps
CPU time 41.39 seconds
Started Aug 09 05:57:15 PM PDT 24
Finished Aug 09 05:57:56 PM PDT 24
Peak memory 233912 kb
Host smart-ff5a54c3-6b2f-437c-926f-a6ed6631de5a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152564228 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.152564228 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/29.kmac_app/latest

Test location /workspace/coverage/default/29.kmac_burst_write.1579724221
Short name T965
Test name
Test status
Simulation time 50288644596 ps
CPU time 955.61 seconds
Started Aug 09 05:57:16 PM PDT 24
Finished Aug 09 06:13:12 PM PDT 24
Peak memory 241692 kb
Host smart-aeb6bf91-51d3-4133-84eb-5c8cbb307896
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579724221 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.157972422
1 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_burst_write/latest

Test location /workspace/coverage/default/29.kmac_entropy_refresh.1021974254
Short name T37
Test name
Test status
Simulation time 51232554559 ps
CPU time 188.41 seconds
Started Aug 09 05:57:14 PM PDT 24
Finished Aug 09 06:00:23 PM PDT 24
Peak memory 341172 kb
Host smart-145f39c9-3c38-46af-b119-bb63067a8aba
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021974254 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.1
021974254 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/29.kmac_error.4033528131
Short name T776
Test name
Test status
Simulation time 81752286448 ps
CPU time 562.16 seconds
Started Aug 09 05:57:19 PM PDT 24
Finished Aug 09 06:06:41 PM PDT 24
Peak memory 579736 kb
Host smart-7af23991-ae85-4f70-8633-ec981713834b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033528131 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.4033528131 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_error/latest

Test location /workspace/coverage/default/29.kmac_key_error.1648473076
Short name T121
Test name
Test status
Simulation time 200090978 ps
CPU time 2.22 seconds
Started Aug 09 05:57:20 PM PDT 24
Finished Aug 09 05:57:22 PM PDT 24
Peak memory 226592 kb
Host smart-b9b1de27-26f7-4d8a-ab91-f58f6d2dc469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648473076 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.1648473076 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_key_error/latest

Test location /workspace/coverage/default/29.kmac_lc_escalation.3874334272
Short name T52
Test name
Test status
Simulation time 5125296328 ps
CPU time 19.21 seconds
Started Aug 09 05:57:20 PM PDT 24
Finished Aug 09 05:57:39 PM PDT 24
Peak memory 244408 kb
Host smart-94897289-2345-49a1-8558-e7598d91b15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874334272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.3874334272 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/29.kmac_lc_escalation/latest

Test location /workspace/coverage/default/29.kmac_long_msg_and_output.1377679771
Short name T487
Test name
Test status
Simulation time 38658615019 ps
CPU time 1597.63 seconds
Started Aug 09 05:57:08 PM PDT 24
Finished Aug 09 06:23:46 PM PDT 24
Peak memory 1765224 kb
Host smart-df6c4446-4f32-48bc-bf21-326295f4d201
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377679771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_a
nd_output.1377679771 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/29.kmac_sideload.4156654841
Short name T387
Test name
Test status
Simulation time 5185561323 ps
CPU time 106.23 seconds
Started Aug 09 05:57:09 PM PDT 24
Finished Aug 09 05:58:55 PM PDT 24
Peak memory 265044 kb
Host smart-564b3f12-5cdc-4f83-aff0-634a5d5eb3eb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156654841 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.4156654841 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_sideload/latest

Test location /workspace/coverage/default/29.kmac_smoke.938292533
Short name T1003
Test name
Test status
Simulation time 5898983787 ps
CPU time 50.48 seconds
Started Aug 09 05:57:08 PM PDT 24
Finished Aug 09 05:57:59 PM PDT 24
Peak memory 227056 kb
Host smart-1845f457-2d5c-4a86-820a-e071df9fc834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938292533 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.938292533 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_smoke/latest

Test location /workspace/coverage/default/29.kmac_stress_all.2686061679
Short name T855
Test name
Test status
Simulation time 27386759821 ps
CPU time 484.92 seconds
Started Aug 09 05:57:20 PM PDT 24
Finished Aug 09 06:05:26 PM PDT 24
Peak memory 289816 kb
Host smart-c820602b-5b2b-41db-8a66-0f129485e9d6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2686061679 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.2686061679 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_stress_all/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_kmac.3969869863
Short name T556
Test name
Test status
Simulation time 106620635 ps
CPU time 5.44 seconds
Started Aug 09 05:57:13 PM PDT 24
Finished Aug 09 05:57:18 PM PDT 24
Peak memory 219768 kb
Host smart-82997d5a-a0a9-4fcf-beb8-64663d7c5790
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969869863 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.kmac_test_vectors_kmac.3969869863 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_kmac_xof.2089439490
Short name T904
Test name
Test status
Simulation time 617629640 ps
CPU time 6.01 seconds
Started Aug 09 05:57:15 PM PDT 24
Finished Aug 09 05:57:22 PM PDT 24
Peak memory 218904 kb
Host smart-270b8c6a-190f-4ed4-a34e-924a15fa1e19
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089439490 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.kmac_test_vectors_kmac_xof.2089439490 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_224.1863054868
Short name T843
Test name
Test status
Simulation time 255520000285 ps
CPU time 4185.12 seconds
Started Aug 09 05:57:10 PM PDT 24
Finished Aug 09 07:06:56 PM PDT 24
Peak memory 3318908 kb
Host smart-0fcb1bab-bcd4-492f-920d-9384f0d442b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1863054868 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_224.1863054868 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_256.613825396
Short name T129
Test name
Test status
Simulation time 95536584404 ps
CPU time 3480.19 seconds
Started Aug 09 05:57:09 PM PDT 24
Finished Aug 09 06:55:10 PM PDT 24
Peak memory 3061236 kb
Host smart-f83afbab-dab0-4318-931f-e3c38a247d35
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=613825396 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_256.613825396 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_384.3714708772
Short name T703
Test name
Test status
Simulation time 258924868536 ps
CPU time 2862.64 seconds
Started Aug 09 05:57:13 PM PDT 24
Finished Aug 09 06:44:56 PM PDT 24
Peak memory 2374720 kb
Host smart-d7615783-5bde-4e50-bf9a-800d342b07ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3714708772 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_384.3714708772 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_512.2780406736
Short name T946
Test name
Test status
Simulation time 34257974005 ps
CPU time 1649.01 seconds
Started Aug 09 05:57:15 PM PDT 24
Finished Aug 09 06:24:44 PM PDT 24
Peak memory 1703792 kb
Host smart-cf73d7ec-4a14-4e67-bdb0-fdb071fa1566
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2780406736 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_512.2780406736 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_shake_128.1558868688
Short name T361
Test name
Test status
Simulation time 126587473346 ps
CPU time 6515.86 seconds
Started Aug 09 05:57:13 PM PDT 24
Finished Aug 09 07:45:50 PM PDT 24
Peak memory 2754728 kb
Host smart-537848cd-8d34-4fd6-95c6-5bd8e8c5cf9f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1558868688 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_128.1558868688 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_shake_256.3827108522
Short name T405
Test name
Test status
Simulation time 210782853352 ps
CPU time 5293.86 seconds
Started Aug 09 05:57:18 PM PDT 24
Finished Aug 09 07:25:32 PM PDT 24
Peak memory 2215196 kb
Host smart-d1d0e3a8-94db-44c3-9c8c-55a520bb926e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3827108522 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_256.3827108522 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/3.kmac_alert_test.3016515314
Short name T961
Test name
Test status
Simulation time 35474378 ps
CPU time 0.85 seconds
Started Aug 09 05:53:45 PM PDT 24
Finished Aug 09 05:53:46 PM PDT 24
Peak memory 218512 kb
Host smart-e1a0bbfb-dc44-43c3-9d9d-77bed16b15e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016515314 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.3016515314 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_alert_test/latest

Test location /workspace/coverage/default/3.kmac_app.3527687730
Short name T834
Test name
Test status
Simulation time 6383535086 ps
CPU time 216.65 seconds
Started Aug 09 05:53:33 PM PDT 24
Finished Aug 09 05:57:10 PM PDT 24
Peak memory 295032 kb
Host smart-d20dac86-098e-4b3e-8357-ea7eb5c567e1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527687730 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.3527687730 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/3.kmac_app/latest

Test location /workspace/coverage/default/3.kmac_app_with_partial_data.1060757197
Short name T203
Test name
Test status
Simulation time 11140925961 ps
CPU time 244.29 seconds
Started Aug 09 05:53:32 PM PDT 24
Finished Aug 09 05:57:36 PM PDT 24
Peak memory 305296 kb
Host smart-3ae53efa-ed12-4ebc-8f58-57da08123ac3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060757197 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_par
tial_data.1060757197 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/3.kmac_burst_write.4203315624
Short name T353
Test name
Test status
Simulation time 43420644752 ps
CPU time 996.15 seconds
Started Aug 09 05:53:32 PM PDT 24
Finished Aug 09 06:10:09 PM PDT 24
Peak memory 261828 kb
Host smart-118bd54c-b22c-40d7-8a03-bfcd9bf40d4f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203315624 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.4203315624
+enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_burst_write/latest

Test location /workspace/coverage/default/3.kmac_edn_timeout_error.1230422348
Short name T540
Test name
Test status
Simulation time 578695760 ps
CPU time 38.88 seconds
Started Aug 09 05:53:42 PM PDT 24
Finished Aug 09 05:54:21 PM PDT 24
Peak memory 234340 kb
Host smart-4ebc23cb-e973-417d-b1e8-d68d563d1b3a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1230422348 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.1230422348 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_mode_error.3402844143
Short name T364
Test name
Test status
Simulation time 36243252 ps
CPU time 1.14 seconds
Started Aug 09 05:53:49 PM PDT 24
Finished Aug 09 05:53:50 PM PDT 24
Peak memory 222284 kb
Host smart-61603ffe-a051-44a3-8af5-6347dd7b7c50
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3402844143 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.3402844143 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_ready_error.1419718530
Short name T813
Test name
Test status
Simulation time 1868438726 ps
CPU time 30.83 seconds
Started Aug 09 05:53:39 PM PDT 24
Finished Aug 09 05:54:10 PM PDT 24
Peak memory 222152 kb
Host smart-ca1dc0d6-012f-46c3-9471-34db4b80a695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419718530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.1419718530 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_refresh.4119793348
Short name T719
Test name
Test status
Simulation time 6899679532 ps
CPU time 373.56 seconds
Started Aug 09 05:53:35 PM PDT 24
Finished Aug 09 05:59:49 PM PDT 24
Peak memory 338464 kb
Host smart-0f694b69-a2af-4f1a-a7be-cb50998b2297
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119793348 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.41
19793348 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/3.kmac_error.1742804079
Short name T754
Test name
Test status
Simulation time 17289681644 ps
CPU time 312.87 seconds
Started Aug 09 05:53:35 PM PDT 24
Finished Aug 09 05:58:48 PM PDT 24
Peak memory 329992 kb
Host smart-d6bdc8a2-2929-4a81-9163-12f59ea3aa4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742804079 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.1742804079 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_error/latest

Test location /workspace/coverage/default/3.kmac_key_error.3992672509
Short name T747
Test name
Test status
Simulation time 705764789 ps
CPU time 5.74 seconds
Started Aug 09 05:53:33 PM PDT 24
Finished Aug 09 05:53:38 PM PDT 24
Peak memory 226664 kb
Host smart-314f1707-11cb-4939-8904-b8e6f0952711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992672509 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.3992672509 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_key_error/latest

Test location /workspace/coverage/default/3.kmac_lc_escalation.824775195
Short name T55
Test name
Test status
Simulation time 109141755 ps
CPU time 1.48 seconds
Started Aug 09 05:53:55 PM PDT 24
Finished Aug 09 05:53:56 PM PDT 24
Peak memory 226904 kb
Host smart-f62068ce-84d4-4e37-9d5f-6f4bb1a09371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824775195 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.824775195 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_lc_escalation/latest

Test location /workspace/coverage/default/3.kmac_long_msg_and_output.217888345
Short name T438
Test name
Test status
Simulation time 27005376551 ps
CPU time 3634.94 seconds
Started Aug 09 05:53:34 PM PDT 24
Finished Aug 09 06:54:10 PM PDT 24
Peak memory 1689512 kb
Host smart-8c56a490-0426-462a-bb25-5a2a08928d58
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217888345 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_and
_output.217888345 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/3.kmac_mubi.2900695494
Short name T734
Test name
Test status
Simulation time 27691685538 ps
CPU time 43.1 seconds
Started Aug 09 05:53:31 PM PDT 24
Finished Aug 09 05:54:15 PM PDT 24
Peak memory 251180 kb
Host smart-d12dd324-03db-4091-b5a1-fa929ee60289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900695494 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.2900695494 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_mubi/latest

Test location /workspace/coverage/default/3.kmac_sec_cm.3166746168
Short name T28
Test name
Test status
Simulation time 28487918417 ps
CPU time 111.55 seconds
Started Aug 09 05:53:50 PM PDT 24
Finished Aug 09 05:55:42 PM PDT 24
Peak memory 294964 kb
Host smart-3752b6a4-9440-414f-a59f-47d1c79f9b9b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166746168 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.3166746168 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspace/3.kmac_sec_cm/latest

Test location /workspace/coverage/default/3.kmac_sideload.3751412550
Short name T469
Test name
Test status
Simulation time 2934418348 ps
CPU time 121.07 seconds
Started Aug 09 05:53:34 PM PDT 24
Finished Aug 09 05:55:35 PM PDT 24
Peak memory 268096 kb
Host smart-15969403-5b36-4254-895b-38e777792753
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751412550 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.3751412550 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_sideload/latest

Test location /workspace/coverage/default/3.kmac_smoke.3424473794
Short name T383
Test name
Test status
Simulation time 999941393 ps
CPU time 6 seconds
Started Aug 09 05:53:40 PM PDT 24
Finished Aug 09 05:53:46 PM PDT 24
Peak memory 226880 kb
Host smart-5abf7780-9b98-4f0b-bd5d-f16fa2a7cd1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424473794 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.3424473794 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_smoke/latest

Test location /workspace/coverage/default/3.kmac_stress_all.3570888007
Short name T714
Test name
Test status
Simulation time 359675047435 ps
CPU time 3001.97 seconds
Started Aug 09 05:53:38 PM PDT 24
Finished Aug 09 06:43:40 PM PDT 24
Peak memory 1354108 kb
Host smart-58dd4eb8-1ea4-4809-b0a8-f493c4f448dc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3570888007 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.3570888007 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_stress_all/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_kmac.563488637
Short name T536
Test name
Test status
Simulation time 216029341 ps
CPU time 6.24 seconds
Started Aug 09 05:53:44 PM PDT 24
Finished Aug 09 05:53:51 PM PDT 24
Peak memory 218876 kb
Host smart-04070761-b5a8-46be-b9d2-24410d25fedd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563488637 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.kmac_test_vectors_kmac.563488637 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_kmac_xof.1775561546
Short name T824
Test name
Test status
Simulation time 584103824 ps
CPU time 6.04 seconds
Started Aug 09 05:53:44 PM PDT 24
Finished Aug 09 05:53:51 PM PDT 24
Peak memory 218912 kb
Host smart-0374c72e-42f1-4ae8-9c78-757262532a15
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775561546 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.kmac_test_vectors_kmac_xof.1775561546 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_224.2955575374
Short name T260
Test name
Test status
Simulation time 1203903807027 ps
CPU time 3768.96 seconds
Started Aug 09 05:53:34 PM PDT 24
Finished Aug 09 06:56:23 PM PDT 24
Peak memory 3212056 kb
Host smart-8ce99724-e11c-495b-ab92-f4a89cf8969c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2955575374 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.2955575374 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_256.1813926187
Short name T199
Test name
Test status
Simulation time 271678071204 ps
CPU time 3232.41 seconds
Started Aug 09 05:53:34 PM PDT 24
Finished Aug 09 06:47:27 PM PDT 24
Peak memory 3081196 kb
Host smart-622beff5-9aa2-43fd-adb8-c8f85f446df5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1813926187 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.1813926187 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_384.1608496584
Short name T332
Test name
Test status
Simulation time 143307456508 ps
CPU time 2556.56 seconds
Started Aug 09 05:53:34 PM PDT 24
Finished Aug 09 06:36:11 PM PDT 24
Peak memory 2425864 kb
Host smart-9ea8d468-97de-4907-aebb-511b150419f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1608496584 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.1608496584 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_512.2649226923
Short name T1022
Test name
Test status
Simulation time 10916345962 ps
CPU time 1342.08 seconds
Started Aug 09 05:53:35 PM PDT 24
Finished Aug 09 06:15:57 PM PDT 24
Peak memory 726484 kb
Host smart-e87dd3f8-0550-4400-880a-9e72aaaa1063
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2649226923 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.2649226923 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/30.kmac_alert_test.2014434915
Short name T994
Test name
Test status
Simulation time 16841452 ps
CPU time 0.89 seconds
Started Aug 09 05:57:38 PM PDT 24
Finished Aug 09 05:57:39 PM PDT 24
Peak memory 218512 kb
Host smart-6c1fe6e8-97b9-409d-b827-cdbab48aae64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014434915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.2014434915 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_alert_test/latest

Test location /workspace/coverage/default/30.kmac_app.3179953339
Short name T219
Test name
Test status
Simulation time 12964582052 ps
CPU time 339.61 seconds
Started Aug 09 05:57:35 PM PDT 24
Finished Aug 09 06:03:15 PM PDT 24
Peak memory 465644 kb
Host smart-a124cbde-53ab-411f-8162-35c0de47d3f5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179953339 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.3179953339 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/30.kmac_app/latest

Test location /workspace/coverage/default/30.kmac_burst_write.560504114
Short name T755
Test name
Test status
Simulation time 10824442448 ps
CPU time 133.65 seconds
Started Aug 09 05:57:25 PM PDT 24
Finished Aug 09 05:59:38 PM PDT 24
Peak memory 237476 kb
Host smart-233fee25-0366-4f4b-a740-3b232c2cee86
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560504114 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.560504114
+enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_burst_write/latest

Test location /workspace/coverage/default/30.kmac_entropy_refresh.1369277565
Short name T967
Test name
Test status
Simulation time 14520430129 ps
CPU time 315.51 seconds
Started Aug 09 05:57:31 PM PDT 24
Finished Aug 09 06:02:47 PM PDT 24
Peak memory 325012 kb
Host smart-792ee415-28dd-435e-96ce-e045f6103c40
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369277565 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_entropy_refresh.1
369277565 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/30.kmac_error.3021369668
Short name T379
Test name
Test status
Simulation time 15097447546 ps
CPU time 56.98 seconds
Started Aug 09 05:57:36 PM PDT 24
Finished Aug 09 05:58:34 PM PDT 24
Peak memory 268344 kb
Host smart-c45eae79-24a0-42e6-847b-d624066e1908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021369668 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.3021369668 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_error/latest

Test location /workspace/coverage/default/30.kmac_key_error.3149750350
Short name T638
Test name
Test status
Simulation time 3842087691 ps
CPU time 10.93 seconds
Started Aug 09 05:57:37 PM PDT 24
Finished Aug 09 05:57:48 PM PDT 24
Peak memory 226712 kb
Host smart-54d59062-1717-4bba-8729-b4b1f1ff5db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149750350 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.3149750350 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_key_error/latest

Test location /workspace/coverage/default/30.kmac_lc_escalation.2165575423
Short name T56
Test name
Test status
Simulation time 53646460 ps
CPU time 1.3 seconds
Started Aug 09 05:57:36 PM PDT 24
Finished Aug 09 05:57:38 PM PDT 24
Peak memory 226832 kb
Host smart-aaa0e2ea-82fe-4bac-b384-c67741126248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165575423 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.2165575423 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/30.kmac_lc_escalation/latest

Test location /workspace/coverage/default/30.kmac_long_msg_and_output.2717996886
Short name T617
Test name
Test status
Simulation time 12418008317 ps
CPU time 1633.33 seconds
Started Aug 09 05:57:26 PM PDT 24
Finished Aug 09 06:24:39 PM PDT 24
Peak memory 986780 kb
Host smart-5a3488a8-a85c-4c48-ab06-370157cbd381
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717996886 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_a
nd_output.2717996886 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/30.kmac_sideload.523601557
Short name T857
Test name
Test status
Simulation time 83531361616 ps
CPU time 572.14 seconds
Started Aug 09 05:57:23 PM PDT 24
Finished Aug 09 06:06:55 PM PDT 24
Peak memory 687752 kb
Host smart-a18c39d5-b7bc-4aa3-a845-9bf8f23657c5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523601557 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.523601557 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_sideload/latest

Test location /workspace/coverage/default/30.kmac_smoke.638790441
Short name T640
Test name
Test status
Simulation time 3559238782 ps
CPU time 46.14 seconds
Started Aug 09 05:57:25 PM PDT 24
Finished Aug 09 05:58:11 PM PDT 24
Peak memory 226880 kb
Host smart-10f35ba9-ac69-416d-9166-2022a71b839b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638790441 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.638790441 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_smoke/latest

Test location /workspace/coverage/default/30.kmac_stress_all.2799182400
Short name T485
Test name
Test status
Simulation time 72728343152 ps
CPU time 1039.14 seconds
Started Aug 09 05:57:35 PM PDT 24
Finished Aug 09 06:14:55 PM PDT 24
Peak memory 743060 kb
Host smart-ff8b4d12-4979-4ccd-b5fe-4ea036c0ba73
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2799182400 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.2799182400 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_stress_all/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_kmac.1154492195
Short name T759
Test name
Test status
Simulation time 1017817804 ps
CPU time 6.29 seconds
Started Aug 09 05:57:35 PM PDT 24
Finished Aug 09 05:57:42 PM PDT 24
Peak memory 219768 kb
Host smart-69b01e1f-6b55-4e28-b872-244ba59265cf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154492195 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.kmac_test_vectors_kmac.1154492195 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_kmac_xof.1842892975
Short name T286
Test name
Test status
Simulation time 1027643129 ps
CPU time 6.65 seconds
Started Aug 09 05:57:31 PM PDT 24
Finished Aug 09 05:57:38 PM PDT 24
Peak memory 219748 kb
Host smart-0ad47d75-9279-4d35-b86f-4444e8daf99f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842892975 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.kmac_test_vectors_kmac_xof.1842892975 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_224.105902664
Short name T351
Test name
Test status
Simulation time 72330939386 ps
CPU time 3133.07 seconds
Started Aug 09 05:57:26 PM PDT 24
Finished Aug 09 06:49:39 PM PDT 24
Peak memory 3271100 kb
Host smart-cb1d427e-5ca9-4fd2-988f-b338768b1608
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=105902664 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_224.105902664 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_256.1924355946
Short name T980
Test name
Test status
Simulation time 76690137058 ps
CPU time 2159.63 seconds
Started Aug 09 05:57:29 PM PDT 24
Finished Aug 09 06:33:29 PM PDT 24
Peak memory 1143012 kb
Host smart-8e45e877-a86a-4183-8fef-5b764adfa247
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1924355946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_256.1924355946 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_384.4191561869
Short name T891
Test name
Test status
Simulation time 49374150168 ps
CPU time 2428.12 seconds
Started Aug 09 05:57:25 PM PDT 24
Finished Aug 09 06:37:53 PM PDT 24
Peak memory 2393364 kb
Host smart-fb24c5d1-f980-4525-a0fa-5a52beb4501b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4191561869 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_384.4191561869 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_512.219049049
Short name T330
Test name
Test status
Simulation time 39051724183 ps
CPU time 1638.86 seconds
Started Aug 09 05:57:31 PM PDT 24
Finished Aug 09 06:24:50 PM PDT 24
Peak memory 1740340 kb
Host smart-f15223d8-2d94-478d-a98a-f02dd35a892f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=219049049 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_512.219049049 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_shake_128.2518014042
Short name T354
Test name
Test status
Simulation time 141957994842 ps
CPU time 6613.94 seconds
Started Aug 09 05:57:30 PM PDT 24
Finished Aug 09 07:47:44 PM PDT 24
Peak memory 2691208 kb
Host smart-58c682b4-3dfa-4050-9a44-723dfadcd242
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2518014042 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_128.2518014042 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/31.kmac_alert_test.3668677883
Short name T253
Test name
Test status
Simulation time 30044470 ps
CPU time 0.8 seconds
Started Aug 09 05:57:55 PM PDT 24
Finished Aug 09 05:57:56 PM PDT 24
Peak memory 218448 kb
Host smart-c364ae20-bb72-4f28-b357-d20217ac55fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668677883 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.3668677883 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_alert_test/latest

Test location /workspace/coverage/default/31.kmac_app.3807458645
Short name T431
Test name
Test status
Simulation time 2271936511 ps
CPU time 23.45 seconds
Started Aug 09 05:57:50 PM PDT 24
Finished Aug 09 05:58:14 PM PDT 24
Peak memory 227716 kb
Host smart-b0335275-643a-4a84-a425-d480823f54e3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807458645 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.3807458645 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/31.kmac_app/latest

Test location /workspace/coverage/default/31.kmac_burst_write.2670706099
Short name T676
Test name
Test status
Simulation time 43923631424 ps
CPU time 1086.34 seconds
Started Aug 09 05:57:37 PM PDT 24
Finished Aug 09 06:15:44 PM PDT 24
Peak memory 255216 kb
Host smart-c3b5177f-f3cf-4ede-883b-54cd7b7f3e26
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670706099 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_write.267070609
9 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_burst_write/latest

Test location /workspace/coverage/default/31.kmac_entropy_refresh.3973205218
Short name T780
Test name
Test status
Simulation time 11966412816 ps
CPU time 313.87 seconds
Started Aug 09 05:57:49 PM PDT 24
Finished Aug 09 06:03:03 PM PDT 24
Peak memory 445664 kb
Host smart-d0bd5b2e-109a-4b6a-a61e-431cdb9d3f54
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973205218 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.3
973205218 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/31.kmac_error.31983569
Short name T336
Test name
Test status
Simulation time 33137109103 ps
CPU time 366.46 seconds
Started Aug 09 05:57:48 PM PDT 24
Finished Aug 09 06:03:54 PM PDT 24
Peak memory 354172 kb
Host smart-22fbc187-cef5-4115-a82a-43b2b331d69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31983569 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.31983569 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_error/latest

Test location /workspace/coverage/default/31.kmac_key_error.1460877091
Short name T847
Test name
Test status
Simulation time 15568505113 ps
CPU time 10.13 seconds
Started Aug 09 05:57:50 PM PDT 24
Finished Aug 09 05:58:00 PM PDT 24
Peak memory 226760 kb
Host smart-5cd78fe7-7fbc-4724-8cd9-3ca0cf576932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460877091 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.1460877091 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_key_error/latest

Test location /workspace/coverage/default/31.kmac_lc_escalation.1119656765
Short name T797
Test name
Test status
Simulation time 3974761500 ps
CPU time 20.86 seconds
Started Aug 09 05:57:49 PM PDT 24
Finished Aug 09 05:58:10 PM PDT 24
Peak memory 243392 kb
Host smart-80e88e72-7fe5-4a60-b67e-86878c568a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119656765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.1119656765 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/31.kmac_lc_escalation/latest

Test location /workspace/coverage/default/31.kmac_long_msg_and_output.2248753932
Short name T417
Test name
Test status
Simulation time 21379140866 ps
CPU time 564.59 seconds
Started Aug 09 05:57:37 PM PDT 24
Finished Aug 09 06:07:02 PM PDT 24
Peak memory 535528 kb
Host smart-4e903b5d-43ce-4002-abdc-478f7872cfd7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248753932 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_a
nd_output.2248753932 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/31.kmac_sideload.1379106591
Short name T642
Test name
Test status
Simulation time 35816600454 ps
CPU time 329.43 seconds
Started Aug 09 05:57:37 PM PDT 24
Finished Aug 09 06:03:07 PM PDT 24
Peak memory 469988 kb
Host smart-e9398765-bd6b-4a3b-ab51-79dcff42c7ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379106591 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.1379106591 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_sideload/latest

Test location /workspace/coverage/default/31.kmac_smoke.1786137400
Short name T401
Test name
Test status
Simulation time 11281571673 ps
CPU time 65.5 seconds
Started Aug 09 05:57:38 PM PDT 24
Finished Aug 09 05:58:43 PM PDT 24
Peak memory 226840 kb
Host smart-56cfacf5-39e4-4331-9ac2-3eae6b2ed991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786137400 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.1786137400 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_smoke/latest

Test location /workspace/coverage/default/31.kmac_stress_all.1028474130
Short name T398
Test name
Test status
Simulation time 12138047782 ps
CPU time 885.91 seconds
Started Aug 09 05:57:57 PM PDT 24
Finished Aug 09 06:12:43 PM PDT 24
Peak memory 497756 kb
Host smart-d219956e-8889-4d05-8a45-346eeae6d589
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1028474130 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.1028474130 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_stress_all/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_kmac.3075034256
Short name T995
Test name
Test status
Simulation time 276751953 ps
CPU time 7.12 seconds
Started Aug 09 05:57:43 PM PDT 24
Finished Aug 09 05:57:50 PM PDT 24
Peak memory 218808 kb
Host smart-57cd6fef-9bbe-4a31-a6e8-37cb1b557845
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075034256 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.kmac_test_vectors_kmac.3075034256 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_kmac_xof.819247144
Short name T1002
Test name
Test status
Simulation time 218434783 ps
CPU time 6.32 seconds
Started Aug 09 05:57:43 PM PDT 24
Finished Aug 09 05:57:49 PM PDT 24
Peak memory 219832 kb
Host smart-37dfa984-a529-4966-88fc-049bd3dd616f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819247144 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 31.kmac_test_vectors_kmac_xof.819247144 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_224.1458612379
Short name T439
Test name
Test status
Simulation time 409772264331 ps
CPU time 3777.9 seconds
Started Aug 09 05:57:37 PM PDT 24
Finished Aug 09 07:00:35 PM PDT 24
Peak memory 3267784 kb
Host smart-40aa5700-0cd2-4044-933c-4fbc43333338
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1458612379 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_224.1458612379 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_256.131403145
Short name T879
Test name
Test status
Simulation time 50010044044 ps
CPU time 2152.72 seconds
Started Aug 09 05:57:43 PM PDT 24
Finished Aug 09 06:33:36 PM PDT 24
Peak memory 1128852 kb
Host smart-f9529738-36d2-49eb-9dd7-c59c56961bbf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=131403145 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_256.131403145 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_384.2453785093
Short name T816
Test name
Test status
Simulation time 15488949213 ps
CPU time 1680.2 seconds
Started Aug 09 05:57:45 PM PDT 24
Finished Aug 09 06:25:45 PM PDT 24
Peak memory 928716 kb
Host smart-5123367f-568c-4a2f-8741-25ed772df676
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2453785093 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_384.2453785093 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_512.950020823
Short name T310
Test name
Test status
Simulation time 47305527124 ps
CPU time 1320 seconds
Started Aug 09 05:57:42 PM PDT 24
Finished Aug 09 06:19:42 PM PDT 24
Peak memory 711164 kb
Host smart-4d7564e2-43ed-4763-b2ea-ab30260ac74b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=950020823 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_512.950020823 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_shake_256.3627886908
Short name T333
Test name
Test status
Simulation time 267813313054 ps
CPU time 10027.2 seconds
Started Aug 09 05:57:43 PM PDT 24
Finished Aug 09 08:44:52 PM PDT 24
Peak memory 6395416 kb
Host smart-1842fd98-556b-4a43-a225-1e7a3ff74439
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3627886908 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_256.3627886908 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/32.kmac_alert_test.1719542564
Short name T117
Test name
Test status
Simulation time 86401413 ps
CPU time 0.89 seconds
Started Aug 09 05:58:17 PM PDT 24
Finished Aug 09 05:58:18 PM PDT 24
Peak memory 218528 kb
Host smart-f18c032c-e75b-4f4b-b400-55d32a910e85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719542564 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.1719542564 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_alert_test/latest

Test location /workspace/coverage/default/32.kmac_app.2300543878
Short name T236
Test name
Test status
Simulation time 17626562192 ps
CPU time 240.44 seconds
Started Aug 09 05:58:10 PM PDT 24
Finished Aug 09 06:02:11 PM PDT 24
Peak memory 301252 kb
Host smart-03198f64-be86-4d26-a601-2c8bd4f83f86
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300543878 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.2300543878 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/32.kmac_app/latest

Test location /workspace/coverage/default/32.kmac_burst_write.1550308506
Short name T821
Test name
Test status
Simulation time 25125234370 ps
CPU time 1329.22 seconds
Started Aug 09 05:57:55 PM PDT 24
Finished Aug 09 06:20:04 PM PDT 24
Peak memory 260828 kb
Host smart-5daccc46-9bd5-405e-af02-a780db8bad33
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550308506 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.155030850
6 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_burst_write/latest

Test location /workspace/coverage/default/32.kmac_entropy_refresh.3973787563
Short name T784
Test name
Test status
Simulation time 51454051960 ps
CPU time 342.71 seconds
Started Aug 09 05:58:11 PM PDT 24
Finished Aug 09 06:03:54 PM PDT 24
Peak memory 460912 kb
Host smart-17b3d3bf-6471-46ba-a216-1c2340d63ce4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973787563 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.3
973787563 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/32.kmac_error.1963468463
Short name T142
Test name
Test status
Simulation time 25389956247 ps
CPU time 177.63 seconds
Started Aug 09 05:58:10 PM PDT 24
Finished Aug 09 06:01:08 PM PDT 24
Peak memory 343844 kb
Host smart-9bbba2e2-91b6-4992-8830-1e6819034b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963468463 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.1963468463 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_error/latest

Test location /workspace/coverage/default/32.kmac_key_error.2262117851
Short name T565
Test name
Test status
Simulation time 1275958370 ps
CPU time 5.85 seconds
Started Aug 09 05:58:11 PM PDT 24
Finished Aug 09 05:58:17 PM PDT 24
Peak memory 226656 kb
Host smart-60b78a36-cf3f-44ae-bb05-9372b870ff7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262117851 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.2262117851 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_key_error/latest

Test location /workspace/coverage/default/32.kmac_lc_escalation.2773796918
Short name T685
Test name
Test status
Simulation time 271613891 ps
CPU time 1.31 seconds
Started Aug 09 05:58:17 PM PDT 24
Finished Aug 09 05:58:18 PM PDT 24
Peak memory 226936 kb
Host smart-7e902a13-b266-45f5-a285-6e9caf29ba72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773796918 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.2773796918 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/32.kmac_lc_escalation/latest

Test location /workspace/coverage/default/32.kmac_long_msg_and_output.2537461838
Short name T205
Test name
Test status
Simulation time 129877494466 ps
CPU time 4193.77 seconds
Started Aug 09 05:57:55 PM PDT 24
Finished Aug 09 07:07:50 PM PDT 24
Peak memory 3218868 kb
Host smart-53521b97-7a4a-405e-ad06-39543fa10287
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537461838 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_long_msg_a
nd_output.2537461838 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/32.kmac_sideload.1592142665
Short name T483
Test name
Test status
Simulation time 1940645682 ps
CPU time 144 seconds
Started Aug 09 05:57:55 PM PDT 24
Finished Aug 09 06:00:19 PM PDT 24
Peak memory 274200 kb
Host smart-50534c3a-1e4a-42d3-8138-17f9d1ca4f82
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592142665 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.1592142665 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_sideload/latest

Test location /workspace/coverage/default/32.kmac_smoke.1468942739
Short name T962
Test name
Test status
Simulation time 5345468136 ps
CPU time 20.53 seconds
Started Aug 09 05:57:55 PM PDT 24
Finished Aug 09 05:58:16 PM PDT 24
Peak memory 223088 kb
Host smart-177f93e2-a5ae-4f19-8b3a-b913702297e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468942739 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.1468942739 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_smoke/latest

Test location /workspace/coverage/default/32.kmac_stress_all.3843308169
Short name T494
Test name
Test status
Simulation time 205227481090 ps
CPU time 2283.15 seconds
Started Aug 09 05:58:17 PM PDT 24
Finished Aug 09 06:36:21 PM PDT 24
Peak memory 725768 kb
Host smart-c8b81210-1c42-4f5a-a3b0-adfb07414a04
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3843308169 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.3843308169 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_stress_all/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_kmac.2300895224
Short name T815
Test name
Test status
Simulation time 573069663 ps
CPU time 5.68 seconds
Started Aug 09 05:58:03 PM PDT 24
Finished Aug 09 05:58:09 PM PDT 24
Peak memory 218892 kb
Host smart-f31b568b-3b4f-4fa9-b982-fdb39b71dc04
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300895224 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.kmac_test_vectors_kmac.2300895224 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_kmac_xof.3309232460
Short name T374
Test name
Test status
Simulation time 189296935 ps
CPU time 6.67 seconds
Started Aug 09 05:58:03 PM PDT 24
Finished Aug 09 05:58:10 PM PDT 24
Peak memory 218968 kb
Host smart-0aaa85c2-9ab2-4aff-ac60-a60c94c046aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309232460 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.kmac_test_vectors_kmac_xof.3309232460 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_224.3865533175
Short name T511
Test name
Test status
Simulation time 192162341945 ps
CPU time 4041.08 seconds
Started Aug 09 05:57:56 PM PDT 24
Finished Aug 09 07:05:18 PM PDT 24
Peak memory 3259184 kb
Host smart-3e9c3de5-9e3d-4053-a5b5-4a8514be2270
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3865533175 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_224.3865533175 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_256.3150914074
Short name T836
Test name
Test status
Simulation time 19412556207 ps
CPU time 2197.47 seconds
Started Aug 09 05:57:56 PM PDT 24
Finished Aug 09 06:34:34 PM PDT 24
Peak memory 1142044 kb
Host smart-e22c88e4-1eb7-4f76-a8ef-8ec6de367c08
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3150914074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_256.3150914074 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_384.1442690699
Short name T357
Test name
Test status
Simulation time 49934213187 ps
CPU time 2256.45 seconds
Started Aug 09 05:58:03 PM PDT 24
Finished Aug 09 06:35:39 PM PDT 24
Peak memory 2401652 kb
Host smart-4ceacb82-6d8c-40a8-aac4-081794916725
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1442690699 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_384.1442690699 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_512.4248832629
Short name T630
Test name
Test status
Simulation time 15838175777 ps
CPU time 1240.05 seconds
Started Aug 09 05:58:03 PM PDT 24
Finished Aug 09 06:18:43 PM PDT 24
Peak memory 697380 kb
Host smart-bfc8df03-8bb3-4bb5-9a78-5d79d4e5f534
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4248832629 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_512.4248832629 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_shake_128.531011190
Short name T403
Test name
Test status
Simulation time 141485719768 ps
CPU time 6698.41 seconds
Started Aug 09 05:58:02 PM PDT 24
Finished Aug 09 07:49:41 PM PDT 24
Peak memory 2680116 kb
Host smart-866e4866-a349-4f16-94da-c8f41ac7ea3d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=531011190 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_128.531011190 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_shake_256.2736864392
Short name T1024
Test name
Test status
Simulation time 2535206853809 ps
CPU time 9718.97 seconds
Started Aug 09 05:58:02 PM PDT 24
Finished Aug 09 08:40:02 PM PDT 24
Peak memory 6479396 kb
Host smart-00041cb9-c266-4a29-822d-92e5392fcafb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2736864392 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_256.2736864392 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/33.kmac_alert_test.1149318645
Short name T551
Test name
Test status
Simulation time 20665820 ps
CPU time 0.9 seconds
Started Aug 09 05:58:32 PM PDT 24
Finished Aug 09 05:58:33 PM PDT 24
Peak memory 218452 kb
Host smart-d2b0de1f-9bb7-4ea6-a524-f8013d20a88b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149318645 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.1149318645 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_alert_test/latest

Test location /workspace/coverage/default/33.kmac_app.1707923549
Short name T228
Test name
Test status
Simulation time 22548594502 ps
CPU time 168.84 seconds
Started Aug 09 05:58:29 PM PDT 24
Finished Aug 09 06:01:18 PM PDT 24
Peak memory 347284 kb
Host smart-3ec89962-7e0b-4cb3-9bd9-fd8d329dc313
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707923549 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.1707923549 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/33.kmac_app/latest

Test location /workspace/coverage/default/33.kmac_burst_write.3281369488
Short name T996
Test name
Test status
Simulation time 64137076095 ps
CPU time 1219.68 seconds
Started Aug 09 05:58:16 PM PDT 24
Finished Aug 09 06:18:36 PM PDT 24
Peak memory 257908 kb
Host smart-36da40e1-5b8e-4397-972a-bdd1bab2cc26
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281369488 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.328136948
8 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_burst_write/latest

Test location /workspace/coverage/default/33.kmac_entropy_refresh.1919562514
Short name T362
Test name
Test status
Simulation time 15261403063 ps
CPU time 345.6 seconds
Started Aug 09 05:58:28 PM PDT 24
Finished Aug 09 06:04:14 PM PDT 24
Peak memory 337640 kb
Host smart-eb91f07d-83f3-41ae-98ba-c4ba9c11537a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919562514 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.1
919562514 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/33.kmac_error.242425346
Short name T878
Test name
Test status
Simulation time 17246512383 ps
CPU time 117.09 seconds
Started Aug 09 05:58:26 PM PDT 24
Finished Aug 09 06:00:23 PM PDT 24
Peak memory 327720 kb
Host smart-7fe3f691-2916-4b37-a127-21bc909126b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242425346 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.242425346 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_error/latest

Test location /workspace/coverage/default/33.kmac_key_error.2045976813
Short name T721
Test name
Test status
Simulation time 399704985 ps
CPU time 2.24 seconds
Started Aug 09 05:58:27 PM PDT 24
Finished Aug 09 05:58:30 PM PDT 24
Peak memory 226760 kb
Host smart-88340821-38db-4cda-883d-54c73de6e4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045976813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.2045976813 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_key_error/latest

Test location /workspace/coverage/default/33.kmac_lc_escalation.3567831914
Short name T576
Test name
Test status
Simulation time 1807518332 ps
CPU time 20.68 seconds
Started Aug 09 05:58:27 PM PDT 24
Finished Aug 09 05:58:48 PM PDT 24
Peak memory 245084 kb
Host smart-b3302581-f510-46e6-aab3-4c047668a4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567831914 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.3567831914 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/33.kmac_lc_escalation/latest

Test location /workspace/coverage/default/33.kmac_sideload.3688865308
Short name T238
Test name
Test status
Simulation time 6355622001 ps
CPU time 224.04 seconds
Started Aug 09 05:58:17 PM PDT 24
Finished Aug 09 06:02:01 PM PDT 24
Peak memory 299980 kb
Host smart-8a860a7b-a6e9-4351-8072-a4bc2aeaa1fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688865308 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.3688865308 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_sideload/latest

Test location /workspace/coverage/default/33.kmac_smoke.3196577474
Short name T480
Test name
Test status
Simulation time 1170486970 ps
CPU time 17.63 seconds
Started Aug 09 05:58:18 PM PDT 24
Finished Aug 09 05:58:35 PM PDT 24
Peak memory 220308 kb
Host smart-b2a8e5b5-e19f-435c-a276-585282cc1c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196577474 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.3196577474 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_smoke/latest

Test location /workspace/coverage/default/33.kmac_stress_all.2154608956
Short name T906
Test name
Test status
Simulation time 128533133041 ps
CPU time 2999.7 seconds
Started Aug 09 05:58:32 PM PDT 24
Finished Aug 09 06:48:32 PM PDT 24
Peak memory 1675484 kb
Host smart-bfdd33fd-2a6d-4163-822d-f13dbf465241
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2154608956 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.2154608956 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_stress_all/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_kmac.3700041163
Short name T204
Test name
Test status
Simulation time 824404632 ps
CPU time 6.39 seconds
Started Aug 09 05:58:22 PM PDT 24
Finished Aug 09 05:58:28 PM PDT 24
Peak memory 218824 kb
Host smart-a6fd82c8-01db-4064-8369-581582636347
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700041163 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.kmac_test_vectors_kmac.3700041163 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_kmac_xof.3263314902
Short name T970
Test name
Test status
Simulation time 111636350 ps
CPU time 6.36 seconds
Started Aug 09 05:58:21 PM PDT 24
Finished Aug 09 05:58:28 PM PDT 24
Peak memory 218924 kb
Host smart-7a0bc2b8-7a69-40db-adc1-c2cd3c40b0ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263314902 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.kmac_test_vectors_kmac_xof.3263314902 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_224.1938846279
Short name T509
Test name
Test status
Simulation time 103219302123 ps
CPU time 3696.07 seconds
Started Aug 09 05:58:16 PM PDT 24
Finished Aug 09 06:59:53 PM PDT 24
Peak memory 3248200 kb
Host smart-85fba9f6-fad0-4202-b443-4094ba6d1133
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1938846279 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_224.1938846279 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_256.2948623944
Short name T508
Test name
Test status
Simulation time 89419845717 ps
CPU time 3500.37 seconds
Started Aug 09 05:58:16 PM PDT 24
Finished Aug 09 06:56:37 PM PDT 24
Peak memory 2952220 kb
Host smart-3690af96-7c47-4444-b27b-869b429c7b48
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2948623944 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_256.2948623944 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_384.4063881569
Short name T373
Test name
Test status
Simulation time 178142264062 ps
CPU time 2513.96 seconds
Started Aug 09 05:58:17 PM PDT 24
Finished Aug 09 06:40:11 PM PDT 24
Peak memory 2360696 kb
Host smart-4b0927cd-b719-447c-9294-7b674211a72e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4063881569 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_384.4063881569 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_512.3351802854
Short name T572
Test name
Test status
Simulation time 100779596021 ps
CPU time 1821.8 seconds
Started Aug 09 05:58:22 PM PDT 24
Finished Aug 09 06:28:44 PM PDT 24
Peak memory 1702856 kb
Host smart-5052f89f-c237-4522-9b34-dd76d8da144d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3351802854 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_512.3351802854 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_shake_256.2065435087
Short name T584
Test name
Test status
Simulation time 638606146938 ps
CPU time 8798.79 seconds
Started Aug 09 05:58:20 PM PDT 24
Finished Aug 09 08:25:00 PM PDT 24
Peak memory 6259320 kb
Host smart-d5befdae-ed65-4f47-b44b-a72961b7afbc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2065435087 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_256.2065435087 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/34.kmac_alert_test.915382368
Short name T425
Test name
Test status
Simulation time 25345581 ps
CPU time 0.89 seconds
Started Aug 09 05:58:49 PM PDT 24
Finished Aug 09 05:58:50 PM PDT 24
Peak memory 218428 kb
Host smart-3d3c9413-16f2-4be1-a168-caa00b625242
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915382368 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.915382368 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/34.kmac_alert_test/latest

Test location /workspace/coverage/default/34.kmac_app.1414696825
Short name T324
Test name
Test status
Simulation time 11818914496 ps
CPU time 357.77 seconds
Started Aug 09 05:58:43 PM PDT 24
Finished Aug 09 06:04:41 PM PDT 24
Peak memory 326800 kb
Host smart-56d884fa-5dee-45b1-874e-e2662e43c7ac
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414696825 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.1414696825 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/34.kmac_app/latest

Test location /workspace/coverage/default/34.kmac_burst_write.2977906938
Short name T116
Test name
Test status
Simulation time 29698080188 ps
CPU time 1327.75 seconds
Started Aug 09 05:58:31 PM PDT 24
Finished Aug 09 06:20:39 PM PDT 24
Peak memory 264388 kb
Host smart-2ea04f0d-0366-443e-8f86-949d026e9ad4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977906938 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.297790693
8 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_burst_write/latest

Test location /workspace/coverage/default/34.kmac_entropy_refresh.2181962378
Short name T420
Test name
Test status
Simulation time 6915493274 ps
CPU time 43.73 seconds
Started Aug 09 05:58:44 PM PDT 24
Finished Aug 09 05:59:27 PM PDT 24
Peak memory 256524 kb
Host smart-9364b33c-e0d2-40e7-9e81-458360846be1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181962378 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.2
181962378 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/34.kmac_error.4214631737
Short name T415
Test name
Test status
Simulation time 20741969480 ps
CPU time 509.31 seconds
Started Aug 09 05:58:43 PM PDT 24
Finished Aug 09 06:07:12 PM PDT 24
Peak memory 651912 kb
Host smart-18450358-3ad3-4aa0-9f03-81758823513d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214631737 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.4214631737 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_error/latest

Test location /workspace/coverage/default/34.kmac_key_error.1867888380
Short name T507
Test name
Test status
Simulation time 1059052747 ps
CPU time 7.47 seconds
Started Aug 09 05:58:44 PM PDT 24
Finished Aug 09 05:58:52 PM PDT 24
Peak memory 218636 kb
Host smart-cc96676e-fd12-497c-aa64-5c3300d6c8bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867888380 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.1867888380 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_key_error/latest

Test location /workspace/coverage/default/34.kmac_lc_escalation.2877475297
Short name T926
Test name
Test status
Simulation time 142205516 ps
CPU time 1.41 seconds
Started Aug 09 05:58:49 PM PDT 24
Finished Aug 09 05:58:51 PM PDT 24
Peak memory 226860 kb
Host smart-07158d13-0a4a-49f4-b8bf-42cc73aef789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877475297 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.2877475297 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/34.kmac_lc_escalation/latest

Test location /workspace/coverage/default/34.kmac_long_msg_and_output.1022342865
Short name T312
Test name
Test status
Simulation time 70467543441 ps
CPU time 4299.14 seconds
Started Aug 09 05:58:33 PM PDT 24
Finished Aug 09 07:10:13 PM PDT 24
Peak memory 3455088 kb
Host smart-41924015-b69f-47c6-a24f-fb6c9533c89a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022342865 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_a
nd_output.1022342865 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/34.kmac_sideload.2789365959
Short name T998
Test name
Test status
Simulation time 14473400944 ps
CPU time 40.79 seconds
Started Aug 09 05:58:32 PM PDT 24
Finished Aug 09 05:59:13 PM PDT 24
Peak memory 251284 kb
Host smart-be6c7ac3-207a-4b4f-a8fe-e3e77f400d7f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789365959 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.2789365959 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_sideload/latest

Test location /workspace/coverage/default/34.kmac_smoke.2825518685
Short name T64
Test name
Test status
Simulation time 1070414535 ps
CPU time 11.03 seconds
Started Aug 09 05:58:31 PM PDT 24
Finished Aug 09 05:58:43 PM PDT 24
Peak memory 226892 kb
Host smart-8c8ab9a9-ed18-4ccf-b489-d10d0169b6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825518685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.2825518685 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_smoke/latest

Test location /workspace/coverage/default/34.kmac_stress_all.150372858
Short name T154
Test name
Test status
Simulation time 8355119056 ps
CPU time 410.85 seconds
Started Aug 09 05:58:49 PM PDT 24
Finished Aug 09 06:05:40 PM PDT 24
Peak memory 315276 kb
Host smart-4b2b7087-7f24-4e1f-984c-47b98ddde2d4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=150372858 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.150372858 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_stress_all/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_kmac.1075196561
Short name T489
Test name
Test status
Simulation time 193527900 ps
CPU time 6.26 seconds
Started Aug 09 05:58:45 PM PDT 24
Finished Aug 09 05:58:51 PM PDT 24
Peak memory 218888 kb
Host smart-8ef0f532-3f99-49c1-9289-8e99e0c0d73a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075196561 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.kmac_test_vectors_kmac.1075196561 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_kmac_xof.2338715650
Short name T856
Test name
Test status
Simulation time 909815518 ps
CPU time 6.98 seconds
Started Aug 09 05:58:43 PM PDT 24
Finished Aug 09 05:58:50 PM PDT 24
Peak memory 219752 kb
Host smart-b52c3b20-5327-4022-a846-f12363813ea4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338715650 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.kmac_test_vectors_kmac_xof.2338715650 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_224.3092573371
Short name T948
Test name
Test status
Simulation time 100897841619 ps
CPU time 3424.53 seconds
Started Aug 09 05:58:32 PM PDT 24
Finished Aug 09 06:55:37 PM PDT 24
Peak memory 3217164 kb
Host smart-79171fac-b974-4558-aa5f-e35898b68aeb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3092573371 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_224.3092573371 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_256.1760775482
Short name T1036
Test name
Test status
Simulation time 261484557779 ps
CPU time 3039.36 seconds
Started Aug 09 05:58:31 PM PDT 24
Finished Aug 09 06:49:11 PM PDT 24
Peak memory 3100228 kb
Host smart-d8f4d4b4-7cad-48fd-b373-599f9c1d66a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1760775482 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_256.1760775482 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_384.4086616117
Short name T792
Test name
Test status
Simulation time 315480723304 ps
CPU time 2533.99 seconds
Started Aug 09 05:58:33 PM PDT 24
Finished Aug 09 06:40:47 PM PDT 24
Peak memory 2345348 kb
Host smart-fabf80dc-f2b8-4b6d-8edf-81805c1c9f12
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4086616117 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_384.4086616117 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_512.2713495777
Short name T210
Test name
Test status
Simulation time 51776309964 ps
CPU time 1836.2 seconds
Started Aug 09 05:58:39 PM PDT 24
Finished Aug 09 06:29:15 PM PDT 24
Peak memory 1744436 kb
Host smart-439ec065-fbef-4002-bfa0-c7ef6456cdf1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2713495777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_512.2713495777 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_shake_256.1230737338
Short name T322
Test name
Test status
Simulation time 409598377658 ps
CPU time 8955.64 seconds
Started Aug 09 05:58:38 PM PDT 24
Finished Aug 09 08:27:55 PM PDT 24
Peak memory 6444208 kb
Host smart-91438ad7-9809-4228-b953-e1f9f512de03
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1230737338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_256.1230737338 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/35.kmac_alert_test.1886570424
Short name T805
Test name
Test status
Simulation time 18817850 ps
CPU time 0.82 seconds
Started Aug 09 05:59:13 PM PDT 24
Finished Aug 09 05:59:14 PM PDT 24
Peak memory 218544 kb
Host smart-11e93694-9da8-4d90-8cca-184f1989ad9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886570424 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.1886570424 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_alert_test/latest

Test location /workspace/coverage/default/35.kmac_app.1202926999
Short name T605
Test name
Test status
Simulation time 1617506904 ps
CPU time 107.72 seconds
Started Aug 09 05:59:07 PM PDT 24
Finished Aug 09 06:00:55 PM PDT 24
Peak memory 260504 kb
Host smart-7e04bb52-2515-4f07-9ab3-cec91f0908eb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202926999 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.1202926999 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/35.kmac_app/latest

Test location /workspace/coverage/default/35.kmac_burst_write.3063327066
Short name T800
Test name
Test status
Simulation time 27692964208 ps
CPU time 1369.01 seconds
Started Aug 09 05:58:56 PM PDT 24
Finished Aug 09 06:21:45 PM PDT 24
Peak memory 261044 kb
Host smart-75cb3442-ff87-49dd-9985-1fd12bd15ded
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063327066 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.306332706
6 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_burst_write/latest

Test location /workspace/coverage/default/35.kmac_entropy_refresh.3581418924
Short name T241
Test name
Test status
Simulation time 8999539177 ps
CPU time 350.78 seconds
Started Aug 09 05:59:07 PM PDT 24
Finished Aug 09 06:04:58 PM PDT 24
Peak memory 319980 kb
Host smart-60ecd452-6632-4c7a-aa4c-972bd0877d79
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581418924 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.3
581418924 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/35.kmac_error.1520336502
Short name T1029
Test name
Test status
Simulation time 25537311357 ps
CPU time 239.49 seconds
Started Aug 09 05:59:12 PM PDT 24
Finished Aug 09 06:03:12 PM PDT 24
Peak memory 409996 kb
Host smart-6c9f787d-e354-4e42-a50b-e3c542f0ea97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520336502 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.1520336502 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_error/latest

Test location /workspace/coverage/default/35.kmac_key_error.488290094
Short name T945
Test name
Test status
Simulation time 182108254 ps
CPU time 2.14 seconds
Started Aug 09 05:59:13 PM PDT 24
Finished Aug 09 05:59:15 PM PDT 24
Peak memory 226804 kb
Host smart-19e62cac-8e67-4674-906e-5edb9d6db1d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488290094 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.488290094 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_key_error/latest

Test location /workspace/coverage/default/35.kmac_lc_escalation.1564227950
Short name T432
Test name
Test status
Simulation time 88512186 ps
CPU time 1.53 seconds
Started Aug 09 05:59:13 PM PDT 24
Finished Aug 09 05:59:14 PM PDT 24
Peak memory 226800 kb
Host smart-f5b01701-92bf-4be0-b457-60ff46d9aac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564227950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.1564227950 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/35.kmac_lc_escalation/latest

Test location /workspace/coverage/default/35.kmac_long_msg_and_output.679670647
Short name T394
Test name
Test status
Simulation time 131074687732 ps
CPU time 4214.72 seconds
Started Aug 09 05:58:49 PM PDT 24
Finished Aug 09 07:09:04 PM PDT 24
Peak memory 1940720 kb
Host smart-ee269d2d-0f86-437e-9d99-17b986202efe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679670647 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_an
d_output.679670647 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/35.kmac_sideload.1342393906
Short name T569
Test name
Test status
Simulation time 10702629019 ps
CPU time 74.32 seconds
Started Aug 09 05:58:56 PM PDT 24
Finished Aug 09 06:00:10 PM PDT 24
Peak memory 273240 kb
Host smart-addb8aaa-ee3a-4f5d-90c9-a3b8959e8192
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342393906 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.1342393906 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_sideload/latest

Test location /workspace/coverage/default/35.kmac_smoke.3311639335
Short name T695
Test name
Test status
Simulation time 5407751439 ps
CPU time 50.57 seconds
Started Aug 09 05:58:48 PM PDT 24
Finished Aug 09 05:59:39 PM PDT 24
Peak memory 222644 kb
Host smart-f93a3eb1-9e08-4220-bd08-5bcfcd2fa973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311639335 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.3311639335 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_smoke/latest

Test location /workspace/coverage/default/35.kmac_stress_all.1493345689
Short name T709
Test name
Test status
Simulation time 119656215417 ps
CPU time 1362.15 seconds
Started Aug 09 05:59:13 PM PDT 24
Finished Aug 09 06:21:55 PM PDT 24
Peak memory 963732 kb
Host smart-e617691e-ca5e-40a3-bdec-265d1b2249f0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1493345689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.1493345689 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_stress_all/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_kmac.1523765332
Short name T388
Test name
Test status
Simulation time 418197249 ps
CPU time 6 seconds
Started Aug 09 05:59:07 PM PDT 24
Finished Aug 09 05:59:13 PM PDT 24
Peak memory 219896 kb
Host smart-65c8c16f-3af8-46e8-b75f-975b7194cb42
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523765332 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.kmac_test_vectors_kmac.1523765332 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_kmac_xof.1199905484
Short name T516
Test name
Test status
Simulation time 750164403 ps
CPU time 6.64 seconds
Started Aug 09 05:59:07 PM PDT 24
Finished Aug 09 05:59:14 PM PDT 24
Peak memory 219808 kb
Host smart-e0738c62-f806-4239-8ef2-6349844eac7a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199905484 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.kmac_test_vectors_kmac_xof.1199905484 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_224.2858267231
Short name T1025
Test name
Test status
Simulation time 109122269672 ps
CPU time 3751.12 seconds
Started Aug 09 05:58:56 PM PDT 24
Finished Aug 09 07:01:28 PM PDT 24
Peak memory 3218588 kb
Host smart-cff1fc32-b96b-48de-ab9d-b689da8c7e8c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2858267231 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_224.2858267231 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_256.3121694117
Short name T846
Test name
Test status
Simulation time 190038972627 ps
CPU time 3690.29 seconds
Started Aug 09 05:58:56 PM PDT 24
Finished Aug 09 07:00:27 PM PDT 24
Peak memory 3102896 kb
Host smart-e434f952-7ff9-4f30-b756-b7973481848f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3121694117 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_256.3121694117 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_384.2870351240
Short name T748
Test name
Test status
Simulation time 213147791873 ps
CPU time 2167.99 seconds
Started Aug 09 05:59:01 PM PDT 24
Finished Aug 09 06:35:10 PM PDT 24
Peak memory 2343496 kb
Host smart-233915e3-8172-44dd-86df-e56760f95466
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2870351240 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_384.2870351240 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_512.2339074053
Short name T577
Test name
Test status
Simulation time 51865617154 ps
CPU time 1951.2 seconds
Started Aug 09 05:59:01 PM PDT 24
Finished Aug 09 06:31:33 PM PDT 24
Peak memory 1750220 kb
Host smart-bb85fcc4-9f5e-486e-91d0-407dfdbe39ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2339074053 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_512.2339074053 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_shake_128.2252286837
Short name T299
Test name
Test status
Simulation time 149951587366 ps
CPU time 6344.93 seconds
Started Aug 09 05:59:01 PM PDT 24
Finished Aug 09 07:44:47 PM PDT 24
Peak memory 2673616 kb
Host smart-3feac359-84c9-4a39-bc9f-8ec938cfb87c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2252286837 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_shake_128.2252286837 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/36.kmac_alert_test.3536042365
Short name T737
Test name
Test status
Simulation time 47787913 ps
CPU time 0.96 seconds
Started Aug 09 05:59:37 PM PDT 24
Finished Aug 09 05:59:38 PM PDT 24
Peak memory 218524 kb
Host smart-b0c25b98-a544-42b9-9c08-3f0fc483da98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536042365 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.3536042365 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_alert_test/latest

Test location /workspace/coverage/default/36.kmac_app.3742414196
Short name T32
Test name
Test status
Simulation time 12271397684 ps
CPU time 351.35 seconds
Started Aug 09 05:59:25 PM PDT 24
Finished Aug 09 06:05:17 PM PDT 24
Peak memory 470208 kb
Host smart-d9c3bfc1-035b-415b-8a9e-b2c6b2727f6d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742414196 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.3742414196 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/36.kmac_app/latest

Test location /workspace/coverage/default/36.kmac_burst_write.152877306
Short name T153
Test name
Test status
Simulation time 112999415599 ps
CPU time 1371.02 seconds
Started Aug 09 05:59:19 PM PDT 24
Finished Aug 09 06:22:10 PM PDT 24
Peak memory 259048 kb
Host smart-87382e0c-3240-4129-8720-d4b194be3e97
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152877306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.152877306
+enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_burst_write/latest

Test location /workspace/coverage/default/36.kmac_entropy_refresh.816673744
Short name T931
Test name
Test status
Simulation time 32899921233 ps
CPU time 245.02 seconds
Started Aug 09 05:59:25 PM PDT 24
Finished Aug 09 06:03:30 PM PDT 24
Peak memory 388596 kb
Host smart-e5718e85-a16f-43ea-b1e2-af1903b25ae0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816673744 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.81
6673744 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/36.kmac_error.2248568651
Short name T468
Test name
Test status
Simulation time 2419769658 ps
CPU time 26.4 seconds
Started Aug 09 05:59:31 PM PDT 24
Finished Aug 09 05:59:58 PM PDT 24
Peak memory 243388 kb
Host smart-a409c2f3-7d24-44e0-9bc4-7fe84c47fb96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248568651 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.2248568651 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_error/latest

Test location /workspace/coverage/default/36.kmac_key_error.3772431277
Short name T513
Test name
Test status
Simulation time 695648769 ps
CPU time 5.31 seconds
Started Aug 09 05:59:32 PM PDT 24
Finished Aug 09 05:59:37 PM PDT 24
Peak memory 226636 kb
Host smart-834f9d1c-7010-4701-a43a-1310d3cd1bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772431277 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.3772431277 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_key_error/latest

Test location /workspace/coverage/default/36.kmac_lc_escalation.1322398979
Short name T954
Test name
Test status
Simulation time 60035635 ps
CPU time 1.4 seconds
Started Aug 09 05:59:31 PM PDT 24
Finished Aug 09 05:59:33 PM PDT 24
Peak memory 226848 kb
Host smart-fd7a2397-96f6-4e82-80a4-535b71a57eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322398979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.1322398979 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/36.kmac_lc_escalation/latest

Test location /workspace/coverage/default/36.kmac_long_msg_and_output.3999506512
Short name T529
Test name
Test status
Simulation time 400887788301 ps
CPU time 4786.41 seconds
Started Aug 09 05:59:19 PM PDT 24
Finished Aug 09 07:19:06 PM PDT 24
Peak memory 3448336 kb
Host smart-865a8a02-7129-4a00-bd58-7e0a8e061c49
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999506512 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_a
nd_output.3999506512 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/36.kmac_sideload.2946549677
Short name T476
Test name
Test status
Simulation time 45886007 ps
CPU time 5.09 seconds
Started Aug 09 05:59:18 PM PDT 24
Finished Aug 09 05:59:23 PM PDT 24
Peak memory 226860 kb
Host smart-31c22a14-a68b-46bd-807c-7126ab210656
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946549677 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.2946549677 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_sideload/latest

Test location /workspace/coverage/default/36.kmac_smoke.3256105264
Short name T940
Test name
Test status
Simulation time 1573814485 ps
CPU time 32.69 seconds
Started Aug 09 05:59:19 PM PDT 24
Finished Aug 09 05:59:51 PM PDT 24
Peak memory 227008 kb
Host smart-0a405dfe-d204-4f0e-818e-becc8c95e5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256105264 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.3256105264 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_smoke/latest

Test location /workspace/coverage/default/36.kmac_stress_all.1860294282
Short name T367
Test name
Test status
Simulation time 7516546720 ps
CPU time 301.15 seconds
Started Aug 09 05:59:36 PM PDT 24
Finished Aug 09 06:04:37 PM PDT 24
Peak memory 321744 kb
Host smart-3eabdce5-811b-4bb1-ab8b-616e2f285a48
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1860294282 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all.1860294282 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_stress_all/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_kmac.2526932318
Short name T739
Test name
Test status
Simulation time 198226974 ps
CPU time 7.12 seconds
Started Aug 09 05:59:27 PM PDT 24
Finished Aug 09 05:59:34 PM PDT 24
Peak memory 218960 kb
Host smart-e2ee11a6-e8ec-4666-b7c5-3e83cc053968
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526932318 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.kmac_test_vectors_kmac.2526932318 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_kmac_xof.3947677584
Short name T655
Test name
Test status
Simulation time 546398436 ps
CPU time 7.04 seconds
Started Aug 09 05:59:27 PM PDT 24
Finished Aug 09 05:59:34 PM PDT 24
Peak memory 218932 kb
Host smart-b7f8070f-8dc4-4109-bdcb-aae5e5572398
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947677584 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.kmac_test_vectors_kmac_xof.3947677584 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_224.269393953
Short name T197
Test name
Test status
Simulation time 408918997267 ps
CPU time 4076.65 seconds
Started Aug 09 05:59:19 PM PDT 24
Finished Aug 09 07:07:16 PM PDT 24
Peak memory 3254688 kb
Host smart-4c70e064-193d-4135-be4d-160554a77872
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=269393953 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_224.269393953 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_256.2508383585
Short name T542
Test name
Test status
Simulation time 20140933447 ps
CPU time 2387.11 seconds
Started Aug 09 05:59:24 PM PDT 24
Finished Aug 09 06:39:11 PM PDT 24
Peak memory 1171576 kb
Host smart-86e8a307-a892-49c3-8551-07ade57d0df9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2508383585 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_256.2508383585 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_384.2089823
Short name T408
Test name
Test status
Simulation time 18273724151 ps
CPU time 1624.29 seconds
Started Aug 09 05:59:25 PM PDT 24
Finished Aug 09 06:26:29 PM PDT 24
Peak memory 907960 kb
Host smart-c38f34d3-388b-45e2-83a1-51d810cee405
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2089823 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_384.2089823 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_512.4100722116
Short name T475
Test name
Test status
Simulation time 978293135258 ps
CPU time 1781.27 seconds
Started Aug 09 05:59:26 PM PDT 24
Finished Aug 09 06:29:08 PM PDT 24
Peak memory 1717760 kb
Host smart-ca8c76b5-3055-4357-8a2e-563439e7bf4a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4100722116 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_512.4100722116 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_shake_256.1008922247
Short name T406
Test name
Test status
Simulation time 218564298996 ps
CPU time 5228.52 seconds
Started Aug 09 05:59:25 PM PDT 24
Finished Aug 09 07:26:34 PM PDT 24
Peak memory 2211748 kb
Host smart-3d4554f1-341d-4d05-a85a-eb153a0dcdec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1008922247 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_shake_256.1008922247 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/37.kmac_alert_test.1993568012
Short name T531
Test name
Test status
Simulation time 25292006 ps
CPU time 0.93 seconds
Started Aug 09 06:00:07 PM PDT 24
Finished Aug 09 06:00:08 PM PDT 24
Peak memory 218540 kb
Host smart-3af0ab78-a143-4f1e-8b1f-c37b77aab7c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993568012 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.1993568012 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_alert_test/latest

Test location /workspace/coverage/default/37.kmac_app.1981131277
Short name T720
Test name
Test status
Simulation time 7997490371 ps
CPU time 56.31 seconds
Started Aug 09 05:59:51 PM PDT 24
Finished Aug 09 06:00:47 PM PDT 24
Peak memory 270372 kb
Host smart-c75d08d5-a1fa-4d6f-b863-514a4534b709
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981131277 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.1981131277 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/37.kmac_app/latest

Test location /workspace/coverage/default/37.kmac_burst_write.4269576982
Short name T108
Test name
Test status
Simulation time 5729748947 ps
CPU time 618.85 seconds
Started Aug 09 05:59:49 PM PDT 24
Finished Aug 09 06:10:08 PM PDT 24
Peak memory 237440 kb
Host smart-696a532d-2217-49b8-ad5e-a55bcbe6392a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269576982 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.426957698
2 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_burst_write/latest

Test location /workspace/coverage/default/37.kmac_entropy_refresh.2168526992
Short name T919
Test name
Test status
Simulation time 207534571 ps
CPU time 3.73 seconds
Started Aug 09 05:59:51 PM PDT 24
Finished Aug 09 05:59:55 PM PDT 24
Peak memory 221288 kb
Host smart-37b20ffe-9394-44f9-ad26-676f18f4ea93
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168526992 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.2
168526992 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/37.kmac_error.3610249076
Short name T488
Test name
Test status
Simulation time 93607944989 ps
CPU time 500.76 seconds
Started Aug 09 05:59:55 PM PDT 24
Finished Aug 09 06:08:16 PM PDT 24
Peak memory 616884 kb
Host smart-d8eba8d8-d430-4378-91db-3cf1a3972f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610249076 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.3610249076 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_error/latest

Test location /workspace/coverage/default/37.kmac_key_error.3701165795
Short name T568
Test name
Test status
Simulation time 593416467 ps
CPU time 5.15 seconds
Started Aug 09 05:59:54 PM PDT 24
Finished Aug 09 05:59:59 PM PDT 24
Peak memory 218660 kb
Host smart-dcbe01c9-f308-4e13-94ec-33deacc94d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701165795 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.3701165795 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_key_error/latest

Test location /workspace/coverage/default/37.kmac_sideload.157269958
Short name T528
Test name
Test status
Simulation time 15889930562 ps
CPU time 341.48 seconds
Started Aug 09 05:59:44 PM PDT 24
Finished Aug 09 06:05:26 PM PDT 24
Peak memory 332696 kb
Host smart-b29ef906-c4fc-4ba7-878f-8dc8e8d98e9a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157269958 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.157269958 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_sideload/latest

Test location /workspace/coverage/default/37.kmac_smoke.490305644
Short name T454
Test name
Test status
Simulation time 14250149444 ps
CPU time 89.45 seconds
Started Aug 09 05:59:37 PM PDT 24
Finished Aug 09 06:01:07 PM PDT 24
Peak memory 228832 kb
Host smart-8b58a3e7-b0e6-423a-b915-c082c00ec0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490305644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.490305644 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_smoke/latest

Test location /workspace/coverage/default/37.kmac_stress_all.1770149588
Short name T62
Test name
Test status
Simulation time 183300867918 ps
CPU time 1671.8 seconds
Started Aug 09 06:00:00 PM PDT 24
Finished Aug 09 06:27:52 PM PDT 24
Peak memory 1125292 kb
Host smart-6bf117f8-2755-4216-b75f-be0c4f2ff3a8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1770149588 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.1770149588 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_stress_all/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_kmac.1523284999
Short name T35
Test name
Test status
Simulation time 182499606 ps
CPU time 6.26 seconds
Started Aug 09 05:59:50 PM PDT 24
Finished Aug 09 05:59:56 PM PDT 24
Peak memory 219808 kb
Host smart-b2619f9a-30cc-4c6a-b59a-d357672dd909
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523284999 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.kmac_test_vectors_kmac.1523284999 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_kmac_xof.3294095617
Short name T790
Test name
Test status
Simulation time 241589822 ps
CPU time 5.84 seconds
Started Aug 09 05:59:48 PM PDT 24
Finished Aug 09 05:59:54 PM PDT 24
Peak memory 219808 kb
Host smart-191dd95f-e86f-4517-9e3b-99a4cd46e646
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294095617 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.kmac_test_vectors_kmac_xof.3294095617 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_224.1784562061
Short name T660
Test name
Test status
Simulation time 911271342291 ps
CPU time 3167.67 seconds
Started Aug 09 05:59:48 PM PDT 24
Finished Aug 09 06:52:37 PM PDT 24
Peak memory 3135960 kb
Host smart-d28354e7-6930-4811-b005-2ef9e037e248
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1784562061 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_224.1784562061 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_256.296782087
Short name T674
Test name
Test status
Simulation time 248396448980 ps
CPU time 3338.48 seconds
Started Aug 09 05:59:49 PM PDT 24
Finished Aug 09 06:55:28 PM PDT 24
Peak memory 3067456 kb
Host smart-aff2e4da-cc57-406f-b9fe-bfff80264fae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=296782087 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_256.296782087 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_384.1210484497
Short name T729
Test name
Test status
Simulation time 49710032402 ps
CPU time 2313.79 seconds
Started Aug 09 05:59:49 PM PDT 24
Finished Aug 09 06:38:23 PM PDT 24
Peak memory 2383488 kb
Host smart-f345d2a5-5694-497d-b503-ee20cb6c45bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1210484497 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_384.1210484497 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_512.3190299448
Short name T254
Test name
Test status
Simulation time 137481703308 ps
CPU time 1765.88 seconds
Started Aug 09 05:59:50 PM PDT 24
Finished Aug 09 06:29:16 PM PDT 24
Peak memory 1720752 kb
Host smart-7aacead8-aa26-479b-bd3b-5cc81556df2d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3190299448 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_512.3190299448 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_shake_128.1419706444
Short name T566
Test name
Test status
Simulation time 1205338138345 ps
CPU time 6713.56 seconds
Started Aug 09 05:59:51 PM PDT 24
Finished Aug 09 07:51:46 PM PDT 24
Peak memory 2704344 kb
Host smart-fe88436a-7403-40a3-a4f7-56880bdcc32e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1419706444 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_128.1419706444 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_shake_256.3314462760
Short name T944
Test name
Test status
Simulation time 1281372671292 ps
CPU time 10741.5 seconds
Started Aug 09 05:59:48 PM PDT 24
Finished Aug 09 08:58:51 PM PDT 24
Peak memory 6396540 kb
Host smart-bb527e89-7133-46f3-8a2b-6a462f74182c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3314462760 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_256.3314462760 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/38.kmac_alert_test.3710830430
Short name T1007
Test name
Test status
Simulation time 111675638 ps
CPU time 0.86 seconds
Started Aug 09 06:00:24 PM PDT 24
Finished Aug 09 06:00:25 PM PDT 24
Peak memory 218564 kb
Host smart-fdec9d0c-f24c-43c9-9b03-7e5b45096f8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710830430 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.3710830430 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_alert_test/latest

Test location /workspace/coverage/default/38.kmac_app.489483575
Short name T628
Test name
Test status
Simulation time 5240900520 ps
CPU time 132.43 seconds
Started Aug 09 06:00:14 PM PDT 24
Finished Aug 09 06:02:26 PM PDT 24
Peak memory 309856 kb
Host smart-bd909c1c-8cbc-4401-b8db-11e6588cd02c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489483575 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.489483575 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/38.kmac_app/latest

Test location /workspace/coverage/default/38.kmac_burst_write.2074100606
Short name T641
Test name
Test status
Simulation time 9399506368 ps
CPU time 798.89 seconds
Started Aug 09 06:00:14 PM PDT 24
Finished Aug 09 06:13:33 PM PDT 24
Peak memory 241352 kb
Host smart-fcf3f2dd-b99a-48f4-8614-f16b7822fda3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074100606 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.207410060
6 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_burst_write/latest

Test location /workspace/coverage/default/38.kmac_entropy_refresh.3533135232
Short name T837
Test name
Test status
Simulation time 15563650218 ps
CPU time 90.77 seconds
Started Aug 09 06:00:19 PM PDT 24
Finished Aug 09 06:01:50 PM PDT 24
Peak memory 247104 kb
Host smart-474b1409-cf2a-4609-af86-e250b435e564
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533135232 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.3
533135232 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/38.kmac_error.3954168573
Short name T752
Test name
Test status
Simulation time 17442984421 ps
CPU time 154.3 seconds
Started Aug 09 06:00:18 PM PDT 24
Finished Aug 09 06:02:53 PM PDT 24
Peak memory 341020 kb
Host smart-816971d0-84ce-4a73-9b95-7e10e437d43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954168573 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.3954168573 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_error/latest

Test location /workspace/coverage/default/38.kmac_key_error.1141585907
Short name T666
Test name
Test status
Simulation time 3934625867 ps
CPU time 14.21 seconds
Started Aug 09 06:00:20 PM PDT 24
Finished Aug 09 06:00:34 PM PDT 24
Peak memory 226800 kb
Host smart-01a81dcd-e334-4cb8-99f1-bc83f3e841ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141585907 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.1141585907 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_key_error/latest

Test location /workspace/coverage/default/38.kmac_lc_escalation.3627413081
Short name T661
Test name
Test status
Simulation time 45006663 ps
CPU time 1.74 seconds
Started Aug 09 06:00:24 PM PDT 24
Finished Aug 09 06:00:25 PM PDT 24
Peak memory 226924 kb
Host smart-6c76ee03-9b8b-4467-a74a-508b9913c2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627413081 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.3627413081 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/38.kmac_lc_escalation/latest

Test location /workspace/coverage/default/38.kmac_long_msg_and_output.435295108
Short name T437
Test name
Test status
Simulation time 24793487348 ps
CPU time 2956.5 seconds
Started Aug 09 06:00:06 PM PDT 24
Finished Aug 09 06:49:23 PM PDT 24
Peak memory 1464152 kb
Host smart-0dc025ef-8db5-46be-9ac4-fedb5271d843
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435295108 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_an
d_output.435295108 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/38.kmac_sideload.2341965083
Short name T213
Test name
Test status
Simulation time 22294838212 ps
CPU time 321.89 seconds
Started Aug 09 06:00:08 PM PDT 24
Finished Aug 09 06:05:30 PM PDT 24
Peak memory 482536 kb
Host smart-2af71c22-12ad-4893-b254-75cbf12e4b2d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341965083 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.2341965083 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_sideload/latest

Test location /workspace/coverage/default/38.kmac_smoke.3456707026
Short name T744
Test name
Test status
Simulation time 354532692 ps
CPU time 15.8 seconds
Started Aug 09 06:00:07 PM PDT 24
Finished Aug 09 06:00:23 PM PDT 24
Peak memory 227000 kb
Host smart-d7f37ff7-2a95-4283-970c-1076c5c712d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456707026 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.3456707026 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_smoke/latest

Test location /workspace/coverage/default/38.kmac_stress_all.2290812671
Short name T851
Test name
Test status
Simulation time 1098138035968 ps
CPU time 1842.15 seconds
Started Aug 09 06:00:24 PM PDT 24
Finished Aug 09 06:31:07 PM PDT 24
Peak memory 895164 kb
Host smart-11772a9d-c599-49cd-87a6-5c90c487a0d5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2290812671 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.2290812671 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_stress_all/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_kmac.2964472529
Short name T723
Test name
Test status
Simulation time 803978221 ps
CPU time 6.88 seconds
Started Aug 09 06:00:14 PM PDT 24
Finished Aug 09 06:00:21 PM PDT 24
Peak memory 220064 kb
Host smart-8c9678b0-4564-4fe2-8a1c-13eb0d2b7de3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964472529 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.kmac_test_vectors_kmac.2964472529 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_kmac_xof.1580321171
Short name T749
Test name
Test status
Simulation time 471648292 ps
CPU time 6.33 seconds
Started Aug 09 06:00:14 PM PDT 24
Finished Aug 09 06:00:20 PM PDT 24
Peak memory 218852 kb
Host smart-cbe808fa-1d71-4ccb-a06f-dfc62bbedd4d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580321171 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.kmac_test_vectors_kmac_xof.1580321171 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_224.1981500276
Short name T571
Test name
Test status
Simulation time 67781705816 ps
CPU time 3347.24 seconds
Started Aug 09 06:00:13 PM PDT 24
Finished Aug 09 06:56:01 PM PDT 24
Peak memory 3203556 kb
Host smart-080bf5e9-519e-4af0-82e5-376cdb10f1b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1981500276 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_224.1981500276 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_256.1105191855
Short name T573
Test name
Test status
Simulation time 77607861538 ps
CPU time 2202.09 seconds
Started Aug 09 06:00:12 PM PDT 24
Finished Aug 09 06:36:55 PM PDT 24
Peak memory 1158348 kb
Host smart-1f8e7ec8-3d2d-4cc5-87b8-cb6208c670c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1105191855 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_256.1105191855 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_384.3762576148
Short name T991
Test name
Test status
Simulation time 60430155815 ps
CPU time 1651.54 seconds
Started Aug 09 06:00:13 PM PDT 24
Finished Aug 09 06:27:45 PM PDT 24
Peak memory 936412 kb
Host smart-4047d08c-08bc-4f0c-8025-300260227617
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3762576148 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_384.3762576148 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_512.3598586351
Short name T908
Test name
Test status
Simulation time 41908964450 ps
CPU time 1297.12 seconds
Started Aug 09 06:00:13 PM PDT 24
Finished Aug 09 06:21:51 PM PDT 24
Peak memory 708004 kb
Host smart-b32637c1-333c-4002-b0dc-178cd0a41ad3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3598586351 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_512.3598586351 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_shake_128.3726396146
Short name T731
Test name
Test status
Simulation time 128582881295 ps
CPU time 6406.16 seconds
Started Aug 09 06:00:14 PM PDT 24
Finished Aug 09 07:47:01 PM PDT 24
Peak memory 2655496 kb
Host smart-fc2ed0b7-8ede-4be8-87e8-381ddb03cc11
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3726396146 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_128.3726396146 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_shake_256.3933910216
Short name T624
Test name
Test status
Simulation time 223366484843 ps
CPU time 10445.9 seconds
Started Aug 09 06:00:13 PM PDT 24
Finished Aug 09 08:54:20 PM PDT 24
Peak memory 6442892 kb
Host smart-4312c76c-f617-49a5-b2fa-c669b3bebfdf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3933910216 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_256.3933910216 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/39.kmac_alert_test.3836368124
Short name T246
Test name
Test status
Simulation time 19532775 ps
CPU time 0.87 seconds
Started Aug 09 06:00:41 PM PDT 24
Finished Aug 09 06:00:42 PM PDT 24
Peak memory 218556 kb
Host smart-9b73dc58-10c9-49fd-8bd0-5131d87bc2e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836368124 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.3836368124 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_alert_test/latest

Test location /workspace/coverage/default/39.kmac_app.2467322913
Short name T344
Test name
Test status
Simulation time 79850500727 ps
CPU time 176.48 seconds
Started Aug 09 06:00:30 PM PDT 24
Finished Aug 09 06:03:27 PM PDT 24
Peak memory 338420 kb
Host smart-ba771b2b-0b75-45e4-a754-7d06e292ca9d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467322913 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.2467322913 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/39.kmac_app/latest

Test location /workspace/coverage/default/39.kmac_burst_write.638495831
Short name T829
Test name
Test status
Simulation time 423511130479 ps
CPU time 1516.25 seconds
Started Aug 09 06:00:25 PM PDT 24
Finished Aug 09 06:25:42 PM PDT 24
Peak memory 265028 kb
Host smart-d99886e4-cc55-4f25-ba0a-efd2df4eee71
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638495831 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.638495831
+enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_burst_write/latest

Test location /workspace/coverage/default/39.kmac_entropy_refresh.3326762027
Short name T74
Test name
Test status
Simulation time 9359117807 ps
CPU time 355.65 seconds
Started Aug 09 06:00:32 PM PDT 24
Finished Aug 09 06:06:28 PM PDT 24
Peak memory 327272 kb
Host smart-32b8d698-a667-4e73-b419-e1a6908781f5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326762027 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.3
326762027 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/39.kmac_error.769074842
Short name T498
Test name
Test status
Simulation time 60727627793 ps
CPU time 336.53 seconds
Started Aug 09 06:00:35 PM PDT 24
Finished Aug 09 06:06:12 PM PDT 24
Peak memory 505072 kb
Host smart-2528d5f3-0726-4f79-8fcb-531afa234794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769074842 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.769074842 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_error/latest

Test location /workspace/coverage/default/39.kmac_key_error.3196575837
Short name T123
Test name
Test status
Simulation time 236894468 ps
CPU time 3.25 seconds
Started Aug 09 06:00:36 PM PDT 24
Finished Aug 09 06:00:40 PM PDT 24
Peak memory 226652 kb
Host smart-beaa3333-c72d-4e81-8863-097730ebdf90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196575837 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.3196575837 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_key_error/latest

Test location /workspace/coverage/default/39.kmac_lc_escalation.2624277945
Short name T12
Test name
Test status
Simulation time 39772447 ps
CPU time 1.35 seconds
Started Aug 09 06:00:36 PM PDT 24
Finished Aug 09 06:00:37 PM PDT 24
Peak memory 226892 kb
Host smart-996e91c7-8442-4b9a-ae42-66e57ddcb73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624277945 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.2624277945 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/39.kmac_lc_escalation/latest

Test location /workspace/coverage/default/39.kmac_long_msg_and_output.664496195
Short name T445
Test name
Test status
Simulation time 24221580468 ps
CPU time 3279.69 seconds
Started Aug 09 06:00:27 PM PDT 24
Finished Aug 09 06:55:07 PM PDT 24
Peak memory 1662384 kb
Host smart-b32d8c9e-6ce6-4071-8243-d44f62195976
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664496195 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_an
d_output.664496195 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/39.kmac_sideload.1565143958
Short name T925
Test name
Test status
Simulation time 39158323221 ps
CPU time 240.52 seconds
Started Aug 09 06:00:23 PM PDT 24
Finished Aug 09 06:04:24 PM PDT 24
Peak memory 403876 kb
Host smart-61ef8c96-454a-4c81-9a49-5ad4e855cef9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565143958 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.1565143958 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_sideload/latest

Test location /workspace/coverage/default/39.kmac_smoke.397444405
Short name T411
Test name
Test status
Simulation time 180621175 ps
CPU time 7.56 seconds
Started Aug 09 06:00:24 PM PDT 24
Finished Aug 09 06:00:32 PM PDT 24
Peak memory 226892 kb
Host smart-695d33d7-d729-4ce9-bac4-9397806a3446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397444405 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.397444405 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_smoke/latest

Test location /workspace/coverage/default/39.kmac_stress_all.3312897591
Short name T15
Test name
Test status
Simulation time 34278347756 ps
CPU time 2533.23 seconds
Started Aug 09 06:00:33 PM PDT 24
Finished Aug 09 06:42:47 PM PDT 24
Peak memory 902960 kb
Host smart-e8a210b5-fe7d-4806-9e3b-40cac28e75f6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3312897591 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.3312897591 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_stress_all/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_kmac.4184759959
Short name T271
Test name
Test status
Simulation time 366366320 ps
CPU time 6.25 seconds
Started Aug 09 06:00:30 PM PDT 24
Finished Aug 09 06:00:36 PM PDT 24
Peak memory 220040 kb
Host smart-daad46e5-c363-4b9e-9597-175ed5bbbe12
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184759959 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.kmac_test_vectors_kmac.4184759959 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_kmac_xof.3211317343
Short name T1020
Test name
Test status
Simulation time 521143489 ps
CPU time 6.77 seconds
Started Aug 09 06:00:30 PM PDT 24
Finished Aug 09 06:00:37 PM PDT 24
Peak memory 219856 kb
Host smart-b4c58fd2-b63e-44fb-a2e7-43f2b1d9f0f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211317343 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.kmac_test_vectors_kmac_xof.3211317343 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_224.906309899
Short name T976
Test name
Test status
Simulation time 66249465406 ps
CPU time 3236 seconds
Started Aug 09 06:00:32 PM PDT 24
Finished Aug 09 06:54:28 PM PDT 24
Peak memory 3126232 kb
Host smart-c5d965fa-24cd-4f88-b68a-fdf5f91f7bc3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=906309899 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_224.906309899 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_256.2447587203
Short name T583
Test name
Test status
Simulation time 91878678319 ps
CPU time 3329.33 seconds
Started Aug 09 06:00:29 PM PDT 24
Finished Aug 09 06:55:59 PM PDT 24
Peak memory 2970900 kb
Host smart-573448a3-f593-424c-81fd-39989891a9c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2447587203 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_256.2447587203 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_384.815624411
Short name T838
Test name
Test status
Simulation time 63472273239 ps
CPU time 1855.07 seconds
Started Aug 09 06:00:31 PM PDT 24
Finished Aug 09 06:31:26 PM PDT 24
Peak memory 934068 kb
Host smart-c487e267-2671-46b4-ae4e-9f2b045309cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=815624411 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_384.815624411 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_512.3624259436
Short name T1027
Test name
Test status
Simulation time 10354415999 ps
CPU time 1204.79 seconds
Started Aug 09 06:00:32 PM PDT 24
Finished Aug 09 06:20:37 PM PDT 24
Peak memory 689360 kb
Host smart-c12467a4-a9a7-4fea-9935-dc30bb751fb8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3624259436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_512.3624259436 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/4.kmac_alert_test.476068984
Short name T810
Test name
Test status
Simulation time 37611800 ps
CPU time 0.86 seconds
Started Aug 09 05:53:54 PM PDT 24
Finished Aug 09 05:53:55 PM PDT 24
Peak memory 218532 kb
Host smart-eca49462-e00e-450c-894b-fa381fb02a14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476068984 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.476068984 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/4.kmac_alert_test/latest

Test location /workspace/coverage/default/4.kmac_app.2042027998
Short name T18
Test name
Test status
Simulation time 4913033454 ps
CPU time 355.51 seconds
Started Aug 09 05:53:50 PM PDT 24
Finished Aug 09 05:59:45 PM PDT 24
Peak memory 343440 kb
Host smart-23a10dfe-8736-4752-84e4-49498d98a94b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042027998 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.2042027998 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/4.kmac_app/latest

Test location /workspace/coverage/default/4.kmac_app_with_partial_data.3650981255
Short name T103
Test name
Test status
Simulation time 12096378304 ps
CPU time 370.68 seconds
Started Aug 09 05:53:42 PM PDT 24
Finished Aug 09 05:59:53 PM PDT 24
Peak memory 479304 kb
Host smart-bc0b56a9-b07f-4127-9ccb-a5e7b71c858f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650981255 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_par
tial_data.3650981255 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/4.kmac_burst_write.644939117
Short name T654
Test name
Test status
Simulation time 30381393233 ps
CPU time 1362.35 seconds
Started Aug 09 05:53:44 PM PDT 24
Finished Aug 09 06:16:27 PM PDT 24
Peak memory 264572 kb
Host smart-6193104f-cfb6-4988-a86b-e92a1a6d5493
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644939117 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.644939117 +
enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_burst_write/latest

Test location /workspace/coverage/default/4.kmac_edn_timeout_error.232074668
Short name T898
Test name
Test status
Simulation time 1857075522 ps
CPU time 28.69 seconds
Started Aug 09 05:53:45 PM PDT 24
Finished Aug 09 05:54:13 PM PDT 24
Peak memory 234812 kb
Host smart-c6b442a7-28ff-4078-bebc-180da41f6311
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=232074668 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.232074668 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_mode_error.2114064117
Short name T346
Test name
Test status
Simulation time 614905305 ps
CPU time 13.92 seconds
Started Aug 09 05:53:44 PM PDT 24
Finished Aug 09 05:53:58 PM PDT 24
Peak memory 226688 kb
Host smart-dce57c4e-871d-434e-aff9-396c6347fc9c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2114064117 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.2114064117 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_ready_error.4080457826
Short name T982
Test name
Test status
Simulation time 3284004558 ps
CPU time 57.72 seconds
Started Aug 09 05:53:50 PM PDT 24
Finished Aug 09 05:54:48 PM PDT 24
Peak memory 227060 kb
Host smart-b1f1ae1f-64a9-4de0-8ac8-fc884e9f6b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080457826 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.4080457826 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_refresh.4071677712
Short name T869
Test name
Test status
Simulation time 1666242714 ps
CPU time 10.39 seconds
Started Aug 09 05:53:50 PM PDT 24
Finished Aug 09 05:54:01 PM PDT 24
Peak memory 234988 kb
Host smart-d416f2db-da1b-4e9c-b690-bb2269767eed
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071677712 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.40
71677712 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/4.kmac_error.1223098979
Short name T382
Test name
Test status
Simulation time 2787722423 ps
CPU time 233.66 seconds
Started Aug 09 05:53:45 PM PDT 24
Finished Aug 09 05:57:39 PM PDT 24
Peak memory 309628 kb
Host smart-4a03ec1e-0384-4798-90b6-828646ebe7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223098979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.1223098979 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_error/latest

Test location /workspace/coverage/default/4.kmac_key_error.2300591967
Short name T309
Test name
Test status
Simulation time 4831239937 ps
CPU time 9.89 seconds
Started Aug 09 05:53:44 PM PDT 24
Finished Aug 09 05:53:54 PM PDT 24
Peak memory 226656 kb
Host smart-840a313a-a965-4382-8633-1dcd0e8751bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300591967 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.2300591967 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_key_error/latest

Test location /workspace/coverage/default/4.kmac_lc_escalation.1374886543
Short name T814
Test name
Test status
Simulation time 45665985 ps
CPU time 1.37 seconds
Started Aug 09 05:53:50 PM PDT 24
Finished Aug 09 05:53:52 PM PDT 24
Peak memory 226928 kb
Host smart-8ef0ad85-b322-4f42-9118-6cf88777f9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374886543 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.1374886543 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/4.kmac_lc_escalation/latest

Test location /workspace/coverage/default/4.kmac_long_msg_and_output.4126185349
Short name T473
Test name
Test status
Simulation time 89483923547 ps
CPU time 2429.48 seconds
Started Aug 09 05:53:46 PM PDT 24
Finished Aug 09 06:34:16 PM PDT 24
Peak memory 1328624 kb
Host smart-fd2919da-dcf2-4288-bf6f-96666414e008
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126185349 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_an
d_output.4126185349 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/4.kmac_mubi.1049239872
Short name T625
Test name
Test status
Simulation time 19799528360 ps
CPU time 294.6 seconds
Started Aug 09 05:53:49 PM PDT 24
Finished Aug 09 05:58:44 PM PDT 24
Peak memory 321760 kb
Host smart-e5dcb870-b27e-49fc-a77f-2d6f0ee9162b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049239872 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.1049239872 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_mubi/latest

Test location /workspace/coverage/default/4.kmac_sec_cm.2777096767
Short name T29
Test name
Test status
Simulation time 4628260849 ps
CPU time 59.91 seconds
Started Aug 09 05:53:53 PM PDT 24
Finished Aug 09 05:54:53 PM PDT 24
Peak memory 271244 kb
Host smart-a187ec0b-c4d2-44b7-930c-74422de45995
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777096767 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.2777096767 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspace/4.kmac_sec_cm/latest

Test location /workspace/coverage/default/4.kmac_sideload.637214037
Short name T1031
Test name
Test status
Simulation time 14517593168 ps
CPU time 196.65 seconds
Started Aug 09 05:53:46 PM PDT 24
Finished Aug 09 05:57:03 PM PDT 24
Peak memory 384116 kb
Host smart-6488de77-c94a-4333-ae5c-9b216c8d2aac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637214037 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.637214037 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_sideload/latest

Test location /workspace/coverage/default/4.kmac_smoke.4021899317
Short name T806
Test name
Test status
Simulation time 2697036540 ps
CPU time 51.52 seconds
Started Aug 09 05:53:40 PM PDT 24
Finished Aug 09 05:54:32 PM PDT 24
Peak memory 223336 kb
Host smart-1817b38b-8e7e-4774-8ee2-e0976e0a200a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021899317 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.4021899317 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_smoke/latest

Test location /workspace/coverage/default/4.kmac_stress_all.203078536
Short name T57
Test name
Test status
Simulation time 133010631196 ps
CPU time 1362.64 seconds
Started Aug 09 05:53:51 PM PDT 24
Finished Aug 09 06:16:34 PM PDT 24
Peak memory 767548 kb
Host smart-f595037b-0c14-4133-828f-dc37d692ddfb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=203078536 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.203078536 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_stress_all/latest

Test location /workspace/coverage/default/4.kmac_stress_all_with_rand_reset.2472984772
Short name T83
Test name
Test status
Simulation time 559754691093 ps
CPU time 1909.63 seconds
Started Aug 09 05:53:50 PM PDT 24
Finished Aug 09 06:25:39 PM PDT 24
Peak memory 421204 kb
Host smart-3fc97bed-aef0-4681-96f6-710ac20e8b29
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2472984772 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all_with_rand_reset.2472984772 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_kmac.2287035647
Short name T41
Test name
Test status
Simulation time 613498721 ps
CPU time 7.04 seconds
Started Aug 09 05:53:40 PM PDT 24
Finished Aug 09 05:53:47 PM PDT 24
Peak memory 219832 kb
Host smart-d90adca3-bfdc-430f-b04d-d95f58083972
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287035647 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.kmac_test_vectors_kmac.2287035647 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_kmac_xof.538581905
Short name T144
Test name
Test status
Simulation time 422674678 ps
CPU time 5.69 seconds
Started Aug 09 05:53:39 PM PDT 24
Finished Aug 09 05:53:45 PM PDT 24
Peak memory 219768 kb
Host smart-b2702043-a0c3-4970-b0d9-b71823186b15
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538581905 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.kmac_test_vectors_kmac_xof.538581905 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_224.2155485644
Short name T532
Test name
Test status
Simulation time 864369479570 ps
CPU time 4156.61 seconds
Started Aug 09 05:53:39 PM PDT 24
Finished Aug 09 07:02:57 PM PDT 24
Peak memory 3172660 kb
Host smart-83b7d9e9-30db-4881-990b-c025ee50226b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2155485644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.2155485644 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_256.922213393
Short name T777
Test name
Test status
Simulation time 62638671408 ps
CPU time 3083.85 seconds
Started Aug 09 05:53:40 PM PDT 24
Finished Aug 09 06:45:04 PM PDT 24
Peak memory 3001020 kb
Host smart-f41e2bf4-25ca-4b4b-abc4-5aea218756ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=922213393 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.922213393 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_384.1895823272
Short name T334
Test name
Test status
Simulation time 17639375951 ps
CPU time 1693.89 seconds
Started Aug 09 05:53:44 PM PDT 24
Finished Aug 09 06:21:58 PM PDT 24
Peak memory 937980 kb
Host smart-a7731c48-048b-4023-a36e-ce8114bd5000
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1895823272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.1895823272 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_512.1426243090
Short name T574
Test name
Test status
Simulation time 43106778583 ps
CPU time 1266.46 seconds
Started Aug 09 05:53:45 PM PDT 24
Finished Aug 09 06:14:52 PM PDT 24
Peak memory 700508 kb
Host smart-17cabe61-abcd-4528-a098-4bcc4931787f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1426243090 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.1426243090 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_shake_256.2734703129
Short name T409
Test name
Test status
Simulation time 833448260431 ps
CPU time 9904.8 seconds
Started Aug 09 05:53:50 PM PDT 24
Finished Aug 09 08:38:56 PM PDT 24
Peak memory 6462700 kb
Host smart-4e794143-b925-4ec1-ac73-0d7f7ebb8144
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2734703129 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.2734703129 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/40.kmac_alert_test.4011534155
Short name T910
Test name
Test status
Simulation time 39116077 ps
CPU time 0.84 seconds
Started Aug 09 06:01:02 PM PDT 24
Finished Aug 09 06:01:02 PM PDT 24
Peak memory 218592 kb
Host smart-ecc9e1c0-e721-4fad-a9eb-67aa98dd3517
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011534155 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.4011534155 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_alert_test/latest

Test location /workspace/coverage/default/40.kmac_app.2744574557
Short name T33
Test name
Test status
Simulation time 5710659049 ps
CPU time 83.24 seconds
Started Aug 09 06:00:57 PM PDT 24
Finished Aug 09 06:02:20 PM PDT 24
Peak memory 246612 kb
Host smart-b611f04c-733a-4761-bc31-b5aa50a0e4f7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744574557 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.2744574557 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/40.kmac_app/latest

Test location /workspace/coverage/default/40.kmac_burst_write.3427656924
Short name T608
Test name
Test status
Simulation time 1776540829 ps
CPU time 198.5 seconds
Started Aug 09 06:00:46 PM PDT 24
Finished Aug 09 06:04:05 PM PDT 24
Peak memory 228532 kb
Host smart-ac47912d-9fd6-4413-b2a0-b890c701900d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427656924 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.342765692
4 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_burst_write/latest

Test location /workspace/coverage/default/40.kmac_entropy_refresh.2866103724
Short name T989
Test name
Test status
Simulation time 33789316203 ps
CPU time 107.76 seconds
Started Aug 09 06:00:57 PM PDT 24
Finished Aug 09 06:02:44 PM PDT 24
Peak memory 257216 kb
Host smart-282bc2c0-96a2-4457-84be-9039ed1e3927
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866103724 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.2
866103724 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/40.kmac_error.1130235474
Short name T960
Test name
Test status
Simulation time 10579006206 ps
CPU time 418.25 seconds
Started Aug 09 06:00:56 PM PDT 24
Finished Aug 09 06:07:55 PM PDT 24
Peak memory 380768 kb
Host smart-9174b0c5-3d6a-4849-88ca-5f537d1319f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130235474 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.1130235474 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_error/latest

Test location /workspace/coverage/default/40.kmac_key_error.2474810121
Short name T900
Test name
Test status
Simulation time 1735852090 ps
CPU time 3.14 seconds
Started Aug 09 06:00:58 PM PDT 24
Finished Aug 09 06:01:01 PM PDT 24
Peak memory 226728 kb
Host smart-ab2c0197-3838-43bb-92cc-b0c871197c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474810121 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.2474810121 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_key_error/latest

Test location /workspace/coverage/default/40.kmac_lc_escalation.129464754
Short name T111
Test name
Test status
Simulation time 38685633 ps
CPU time 1.35 seconds
Started Aug 09 06:01:02 PM PDT 24
Finished Aug 09 06:01:04 PM PDT 24
Peak memory 226836 kb
Host smart-d402bf97-8fe5-4b71-aaf1-f638633acd5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129464754 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.129464754 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/40.kmac_lc_escalation/latest

Test location /workspace/coverage/default/40.kmac_long_msg_and_output.1418424819
Short name T539
Test name
Test status
Simulation time 203316671885 ps
CPU time 5063.21 seconds
Started Aug 09 06:00:39 PM PDT 24
Finished Aug 09 07:25:03 PM PDT 24
Peak memory 3543200 kb
Host smart-f8a3e452-233f-48d9-a23c-846bb9372296
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418424819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_a
nd_output.1418424819 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/40.kmac_sideload.3411002028
Short name T1032
Test name
Test status
Simulation time 148181188229 ps
CPU time 440.28 seconds
Started Aug 09 06:00:39 PM PDT 24
Finished Aug 09 06:07:59 PM PDT 24
Peak memory 533808 kb
Host smart-de0354a6-98b7-4e27-8bca-a2d241b120c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411002028 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.3411002028 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_sideload/latest

Test location /workspace/coverage/default/40.kmac_smoke.2188297818
Short name T770
Test name
Test status
Simulation time 946402709 ps
CPU time 8.63 seconds
Started Aug 09 06:00:40 PM PDT 24
Finished Aug 09 06:00:49 PM PDT 24
Peak memory 226608 kb
Host smart-080770dd-6ea6-471b-86e3-80e3520b2f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188297818 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.2188297818 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_smoke/latest

Test location /workspace/coverage/default/40.kmac_stress_all.4228641200
Short name T938
Test name
Test status
Simulation time 16016373352 ps
CPU time 1246.53 seconds
Started Aug 09 06:01:01 PM PDT 24
Finished Aug 09 06:21:48 PM PDT 24
Peak memory 547320 kb
Host smart-2fe27ad3-848c-4421-92a8-03890db9bbcd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4228641200 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.4228641200 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_stress_all/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_kmac.2684503692
Short name T724
Test name
Test status
Simulation time 173108057 ps
CPU time 5.68 seconds
Started Aug 09 06:00:58 PM PDT 24
Finished Aug 09 06:01:03 PM PDT 24
Peak memory 219732 kb
Host smart-c86e92d7-c6a2-412a-89dd-9ec214a64cae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684503692 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.kmac_test_vectors_kmac.2684503692 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_kmac_xof.3685146246
Short name T462
Test name
Test status
Simulation time 209721113 ps
CPU time 6.26 seconds
Started Aug 09 06:00:56 PM PDT 24
Finished Aug 09 06:01:03 PM PDT 24
Peak memory 218924 kb
Host smart-1162eebb-011a-4f4d-be58-17b052618720
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685146246 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.kmac_test_vectors_kmac_xof.3685146246 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_224.1262481517
Short name T538
Test name
Test status
Simulation time 41955069086 ps
CPU time 2230.65 seconds
Started Aug 09 06:00:45 PM PDT 24
Finished Aug 09 06:37:56 PM PDT 24
Peak memory 1161460 kb
Host smart-953c519e-233b-456e-87d0-44d8047bd3a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1262481517 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_224.1262481517 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_256.515355102
Short name T237
Test name
Test status
Simulation time 436811988375 ps
CPU time 3611.01 seconds
Started Aug 09 06:00:45 PM PDT 24
Finished Aug 09 07:00:57 PM PDT 24
Peak memory 3058652 kb
Host smart-1bf5e023-cc6e-4bdc-8536-37468771b714
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=515355102 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_256.515355102 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_384.3697611861
Short name T477
Test name
Test status
Simulation time 186001661122 ps
CPU time 2211.28 seconds
Started Aug 09 06:00:46 PM PDT 24
Finished Aug 09 06:37:37 PM PDT 24
Peak memory 2339556 kb
Host smart-2cbecc98-81f9-4043-b97d-a8f647ea3bcc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3697611861 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_384.3697611861 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_512.1709524323
Short name T496
Test name
Test status
Simulation time 150588051568 ps
CPU time 1681.63 seconds
Started Aug 09 06:00:52 PM PDT 24
Finished Aug 09 06:28:54 PM PDT 24
Peak memory 1707204 kb
Host smart-18de9ee2-8007-44cb-afb5-a4b6d22e6087
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1709524323 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_512.1709524323 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_shake_256.2720414771
Short name T222
Test name
Test status
Simulation time 158210376804 ps
CPU time 8890.78 seconds
Started Aug 09 06:00:57 PM PDT 24
Finished Aug 09 08:29:09 PM PDT 24
Peak memory 6408000 kb
Host smart-e89995c9-3d14-4d94-903c-ae799cdce4e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2720414771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_256.2720414771 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/41.kmac_alert_test.1731913523
Short name T272
Test name
Test status
Simulation time 23319808 ps
CPU time 0.83 seconds
Started Aug 09 06:01:31 PM PDT 24
Finished Aug 09 06:01:32 PM PDT 24
Peak memory 218576 kb
Host smart-2d52040c-7227-493b-a1e1-1f25f758592a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731913523 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.1731913523 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_alert_test/latest

Test location /workspace/coverage/default/41.kmac_app.2553137977
Short name T809
Test name
Test status
Simulation time 4558497993 ps
CPU time 313.93 seconds
Started Aug 09 06:01:18 PM PDT 24
Finished Aug 09 06:06:32 PM PDT 24
Peak memory 321024 kb
Host smart-481a8f2a-4b7d-4ad6-865e-8ed4da271615
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553137977 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.2553137977 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/41.kmac_app/latest

Test location /workspace/coverage/default/41.kmac_burst_write.2051488195
Short name T988
Test name
Test status
Simulation time 2972098056 ps
CPU time 331.1 seconds
Started Aug 09 06:01:13 PM PDT 24
Finished Aug 09 06:06:44 PM PDT 24
Peak memory 232672 kb
Host smart-78a3aed0-6226-4256-865c-bd2de5db5010
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051488195 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.205148819
5 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_burst_write/latest

Test location /workspace/coverage/default/41.kmac_entropy_refresh.4237762812
Short name T781
Test name
Test status
Simulation time 4735772651 ps
CPU time 93.64 seconds
Started Aug 09 06:01:25 PM PDT 24
Finished Aug 09 06:02:59 PM PDT 24
Peak memory 286336 kb
Host smart-2fa4ecf3-a475-4a23-91c9-b26bf1228bef
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237762812 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_entropy_refresh.4
237762812 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/41.kmac_error.1456045663
Short name T941
Test name
Test status
Simulation time 2170700616 ps
CPU time 71.88 seconds
Started Aug 09 06:01:25 PM PDT 24
Finished Aug 09 06:02:37 PM PDT 24
Peak memory 300636 kb
Host smart-690f9687-2179-4b4c-aaf3-5941e2c25584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456045663 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.1456045663 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_error/latest

Test location /workspace/coverage/default/41.kmac_key_error.1695359987
Short name T492
Test name
Test status
Simulation time 893547434 ps
CPU time 7.64 seconds
Started Aug 09 06:01:32 PM PDT 24
Finished Aug 09 06:01:40 PM PDT 24
Peak memory 226720 kb
Host smart-d2154550-9b29-4689-a969-05155c4f241a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695359987 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.1695359987 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_key_error/latest

Test location /workspace/coverage/default/41.kmac_lc_escalation.2369093830
Short name T44
Test name
Test status
Simulation time 1757248137 ps
CPU time 28.34 seconds
Started Aug 09 06:01:32 PM PDT 24
Finished Aug 09 06:02:01 PM PDT 24
Peak memory 251684 kb
Host smart-73e82eca-0498-440d-b56c-fbd884b7c5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369093830 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.2369093830 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/41.kmac_lc_escalation/latest

Test location /workspace/coverage/default/41.kmac_long_msg_and_output.26919714
Short name T314
Test name
Test status
Simulation time 7633653093 ps
CPU time 903.03 seconds
Started Aug 09 06:01:03 PM PDT 24
Finished Aug 09 06:16:06 PM PDT 24
Peak memory 649324 kb
Host smart-ee8a458c-603d-467e-9559-12864efc46db
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26919714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and
_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_and
_output.26919714 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/41.kmac_sideload.1638093769
Short name T447
Test name
Test status
Simulation time 6234656034 ps
CPU time 201.04 seconds
Started Aug 09 06:01:06 PM PDT 24
Finished Aug 09 06:04:28 PM PDT 24
Peak memory 382004 kb
Host smart-30267f8c-c5ed-4983-aa48-696ff68239fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638093769 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.1638093769 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_sideload/latest

Test location /workspace/coverage/default/41.kmac_smoke.91166158
Short name T864
Test name
Test status
Simulation time 11784723536 ps
CPU time 61.24 seconds
Started Aug 09 06:01:02 PM PDT 24
Finished Aug 09 06:02:03 PM PDT 24
Peak memory 226912 kb
Host smart-1d060367-633c-409a-a37f-c3e435ad1b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91166158 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.91166158 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_smoke/latest

Test location /workspace/coverage/default/41.kmac_stress_all.4113220885
Short name T705
Test name
Test status
Simulation time 2621473121 ps
CPU time 17.43 seconds
Started Aug 09 06:01:32 PM PDT 24
Finished Aug 09 06:01:50 PM PDT 24
Peak memory 234852 kb
Host smart-68d75f9f-3791-4025-b6c3-12b98773fc78
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4113220885 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.4113220885 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_stress_all/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_kmac.3968282251
Short name T712
Test name
Test status
Simulation time 1303366172 ps
CPU time 7.18 seconds
Started Aug 09 06:01:19 PM PDT 24
Finished Aug 09 06:01:27 PM PDT 24
Peak memory 219772 kb
Host smart-c002e616-c276-4ea1-9630-0e13658050b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968282251 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.kmac_test_vectors_kmac.3968282251 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_kmac_xof.1163662463
Short name T935
Test name
Test status
Simulation time 137338327 ps
CPU time 5.91 seconds
Started Aug 09 06:01:18 PM PDT 24
Finished Aug 09 06:01:24 PM PDT 24
Peak memory 219816 kb
Host smart-847857c4-584e-42a8-961f-17ae4c713135
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163662463 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.kmac_test_vectors_kmac_xof.1163662463 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_224.2187685769
Short name T634
Test name
Test status
Simulation time 98229818885 ps
CPU time 3962.19 seconds
Started Aug 09 06:01:12 PM PDT 24
Finished Aug 09 07:07:15 PM PDT 24
Peak memory 3167520 kb
Host smart-a4c070bd-c885-41ec-84ff-efaf3c98fbae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2187685769 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_224.2187685769 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_256.313706671
Short name T929
Test name
Test status
Simulation time 189087907157 ps
CPU time 3834.29 seconds
Started Aug 09 06:01:13 PM PDT 24
Finished Aug 09 07:05:07 PM PDT 24
Peak memory 3148672 kb
Host smart-db867d59-84b0-4a72-baa0-5349b678aa59
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=313706671 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_256.313706671 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_384.2060025466
Short name T903
Test name
Test status
Simulation time 19421441304 ps
CPU time 1628.88 seconds
Started Aug 09 06:01:13 PM PDT 24
Finished Aug 09 06:28:22 PM PDT 24
Peak memory 920416 kb
Host smart-d81b5773-0095-4da3-9531-5c8def173720
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2060025466 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_384.2060025466 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_512.724537142
Short name T972
Test name
Test status
Simulation time 49698561037 ps
CPU time 1716.11 seconds
Started Aug 09 06:01:13 PM PDT 24
Finished Aug 09 06:29:49 PM PDT 24
Peak memory 1671504 kb
Host smart-d743172e-1c7b-4423-a5b9-d003740b22af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=724537142 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_512.724537142 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/42.kmac_alert_test.2589008017
Short name T730
Test name
Test status
Simulation time 64026116 ps
CPU time 0.91 seconds
Started Aug 09 06:01:51 PM PDT 24
Finished Aug 09 06:01:52 PM PDT 24
Peak memory 218532 kb
Host smart-46ccc235-7598-47ca-b797-fff5773724c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589008017 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.2589008017 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_alert_test/latest

Test location /workspace/coverage/default/42.kmac_app.1393273553
Short name T297
Test name
Test status
Simulation time 141874086707 ps
CPU time 413.29 seconds
Started Aug 09 06:01:40 PM PDT 24
Finished Aug 09 06:08:33 PM PDT 24
Peak memory 517168 kb
Host smart-a2796523-407b-454a-95ae-6a442f590f98
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393273553 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.1393273553 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/42.kmac_app/latest

Test location /workspace/coverage/default/42.kmac_burst_write.2775687314
Short name T923
Test name
Test status
Simulation time 1178300011 ps
CPU time 65.75 seconds
Started Aug 09 06:01:40 PM PDT 24
Finished Aug 09 06:02:46 PM PDT 24
Peak memory 226984 kb
Host smart-5cc9f48f-e826-4089-9cb9-dd66f36fa8a4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775687314 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.277568731
4 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_burst_write/latest

Test location /workspace/coverage/default/42.kmac_entropy_refresh.1562237592
Short name T17
Test name
Test status
Simulation time 10081092708 ps
CPU time 90.4 seconds
Started Aug 09 06:01:44 PM PDT 24
Finished Aug 09 06:03:15 PM PDT 24
Peak memory 248852 kb
Host smart-bebbf928-8f00-4af8-8d17-6c9d53f9c511
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562237592 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.1
562237592 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/42.kmac_error.795571900
Short name T168
Test name
Test status
Simulation time 15661015815 ps
CPU time 472.19 seconds
Started Aug 09 06:01:43 PM PDT 24
Finished Aug 09 06:09:36 PM PDT 24
Peak memory 554896 kb
Host smart-07c61ac0-2495-49cd-a2a4-999cb21004cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795571900 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.795571900 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_error/latest

Test location /workspace/coverage/default/42.kmac_key_error.907224738
Short name T553
Test name
Test status
Simulation time 607450281 ps
CPU time 4.68 seconds
Started Aug 09 06:01:49 PM PDT 24
Finished Aug 09 06:01:54 PM PDT 24
Peak memory 226704 kb
Host smart-f59073dc-5ed2-4ef3-8ed1-172bb617d30c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907224738 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.907224738 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_key_error/latest

Test location /workspace/coverage/default/42.kmac_lc_escalation.3349212935
Short name T317
Test name
Test status
Simulation time 4766198686 ps
CPU time 34.43 seconds
Started Aug 09 06:01:51 PM PDT 24
Finished Aug 09 06:02:26 PM PDT 24
Peak memory 235372 kb
Host smart-e67d8788-d49f-4cb1-ab4a-51b7faab3e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349212935 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.3349212935 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/42.kmac_lc_escalation/latest

Test location /workspace/coverage/default/42.kmac_long_msg_and_output.3108773809
Short name T257
Test name
Test status
Simulation time 11780919197 ps
CPU time 1550.88 seconds
Started Aug 09 06:01:31 PM PDT 24
Finished Aug 09 06:27:22 PM PDT 24
Peak memory 922640 kb
Host smart-66983379-299e-40df-8902-84c4d24ab685
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108773809 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_a
nd_output.3108773809 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/42.kmac_sideload.4191972887
Short name T735
Test name
Test status
Simulation time 2521248407 ps
CPU time 108.96 seconds
Started Aug 09 06:01:31 PM PDT 24
Finished Aug 09 06:03:20 PM PDT 24
Peak memory 260992 kb
Host smart-38881e6e-6bed-469c-9dc2-7665054f75c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191972887 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.4191972887 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_sideload/latest

Test location /workspace/coverage/default/42.kmac_smoke.4137319531
Short name T342
Test name
Test status
Simulation time 4519063148 ps
CPU time 36.36 seconds
Started Aug 09 06:01:32 PM PDT 24
Finished Aug 09 06:02:09 PM PDT 24
Peak memory 223476 kb
Host smart-770b072b-7647-4186-a7c1-35517d0a3804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137319531 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.4137319531 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_smoke/latest

Test location /workspace/coverage/default/42.kmac_stress_all.1183510436
Short name T171
Test name
Test status
Simulation time 65711193318 ps
CPU time 1610.17 seconds
Started Aug 09 06:01:50 PM PDT 24
Finished Aug 09 06:28:40 PM PDT 24
Peak memory 748036 kb
Host smart-d4ad5802-a6eb-4247-9fe5-2b09b3039695
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1183510436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.1183510436 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_stress_all/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_kmac.2731867225
Short name T482
Test name
Test status
Simulation time 258593870 ps
CPU time 6.95 seconds
Started Aug 09 06:01:39 PM PDT 24
Finished Aug 09 06:01:46 PM PDT 24
Peak memory 218880 kb
Host smart-1df01e52-010e-4dc5-8467-9a9cc30573f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731867225 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.kmac_test_vectors_kmac.2731867225 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_kmac_xof.1480370818
Short name T888
Test name
Test status
Simulation time 704839299 ps
CPU time 5.73 seconds
Started Aug 09 06:01:39 PM PDT 24
Finished Aug 09 06:01:45 PM PDT 24
Peak memory 219768 kb
Host smart-5583252f-189d-49a9-b709-7c96147134c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480370818 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.kmac_test_vectors_kmac_xof.1480370818 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_224.1194856613
Short name T997
Test name
Test status
Simulation time 21364962508 ps
CPU time 2262.67 seconds
Started Aug 09 06:01:39 PM PDT 24
Finished Aug 09 06:39:22 PM PDT 24
Peak memory 1200500 kb
Host smart-d9f5b1a0-654f-4f5f-924b-8d53b3d1ec10
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1194856613 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_224.1194856613 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_256.2605269120
Short name T1011
Test name
Test status
Simulation time 67048793127 ps
CPU time 2971.97 seconds
Started Aug 09 06:01:38 PM PDT 24
Finished Aug 09 06:51:11 PM PDT 24
Peak memory 2993036 kb
Host smart-eb11e929-1473-400f-adb4-4986a7c6039c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2605269120 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_256.2605269120 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_384.3038838486
Short name T763
Test name
Test status
Simulation time 87277458609 ps
CPU time 1771.05 seconds
Started Aug 09 06:01:38 PM PDT 24
Finished Aug 09 06:31:10 PM PDT 24
Peak memory 916772 kb
Host smart-bfba78e5-7360-4842-b130-96c523fd370c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3038838486 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_384.3038838486 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_512.1738185813
Short name T932
Test name
Test status
Simulation time 201771810476 ps
CPU time 1787.79 seconds
Started Aug 09 06:01:38 PM PDT 24
Finished Aug 09 06:31:27 PM PDT 24
Peak memory 1705280 kb
Host smart-16f2a79b-a5cb-4308-a57b-6b06162abaea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1738185813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_512.1738185813 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/43.kmac_alert_test.1714437204
Short name T722
Test name
Test status
Simulation time 13507966 ps
CPU time 0.85 seconds
Started Aug 09 06:02:23 PM PDT 24
Finished Aug 09 06:02:24 PM PDT 24
Peak memory 218512 kb
Host smart-af78084e-5a3f-4858-90b7-923ff0e14d7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714437204 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.1714437204 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_alert_test/latest

Test location /workspace/coverage/default/43.kmac_app.1817122038
Short name T369
Test name
Test status
Simulation time 8919078266 ps
CPU time 291.09 seconds
Started Aug 09 06:02:06 PM PDT 24
Finished Aug 09 06:06:57 PM PDT 24
Peak memory 429788 kb
Host smart-44c552e6-7b5a-47dc-98ea-29c5398bc006
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817122038 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.1817122038 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/43.kmac_app/latest

Test location /workspace/coverage/default/43.kmac_burst_write.2702885174
Short name T711
Test name
Test status
Simulation time 10894500077 ps
CPU time 453.06 seconds
Started Aug 09 06:01:55 PM PDT 24
Finished Aug 09 06:09:28 PM PDT 24
Peak memory 241212 kb
Host smart-8c3007a7-bdb5-4ceb-b069-4f890a7b26ab
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702885174 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.270288517
4 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_burst_write/latest

Test location /workspace/coverage/default/43.kmac_entropy_refresh.1700492729
Short name T440
Test name
Test status
Simulation time 686516790 ps
CPU time 10.5 seconds
Started Aug 09 06:02:10 PM PDT 24
Finished Aug 09 06:02:21 PM PDT 24
Peak memory 233708 kb
Host smart-b331a421-1fab-4acc-ac64-73e8686dfc33
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700492729 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.1
700492729 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/43.kmac_error.3483388739
Short name T20
Test name
Test status
Simulation time 12234851153 ps
CPU time 133.7 seconds
Started Aug 09 06:02:11 PM PDT 24
Finished Aug 09 06:04:25 PM PDT 24
Peak memory 341588 kb
Host smart-e4a48375-9333-430f-99f5-3b601bc14f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483388739 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.3483388739 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_error/latest

Test location /workspace/coverage/default/43.kmac_key_error.651394403
Short name T901
Test name
Test status
Simulation time 2338146058 ps
CPU time 9.24 seconds
Started Aug 09 06:02:17 PM PDT 24
Finished Aug 09 06:02:26 PM PDT 24
Peak memory 226752 kb
Host smart-493dd824-52dc-4595-9a6f-315a3179cbe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651394403 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.651394403 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_key_error/latest

Test location /workspace/coverage/default/43.kmac_lc_escalation.2047043585
Short name T67
Test name
Test status
Simulation time 38917721 ps
CPU time 1.35 seconds
Started Aug 09 06:02:17 PM PDT 24
Finished Aug 09 06:02:19 PM PDT 24
Peak memory 226800 kb
Host smart-a48169c3-1321-4848-b1b6-1ff0d349e63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047043585 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.2047043585 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/43.kmac_lc_escalation/latest

Test location /workspace/coverage/default/43.kmac_long_msg_and_output.1098255015
Short name T481
Test name
Test status
Simulation time 93028619978 ps
CPU time 183.97 seconds
Started Aug 09 06:01:55 PM PDT 24
Finished Aug 09 06:04:59 PM PDT 24
Peak memory 443176 kb
Host smart-773efa7b-a24d-435d-8b33-c41e338385e9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098255015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_a
nd_output.1098255015 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/43.kmac_sideload.266847743
Short name T287
Test name
Test status
Simulation time 8162142446 ps
CPU time 205.16 seconds
Started Aug 09 06:01:55 PM PDT 24
Finished Aug 09 06:05:20 PM PDT 24
Peak memory 390892 kb
Host smart-c0c9539f-a8de-4cc3-bead-0951ae73efd4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266847743 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.266847743 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_sideload/latest

Test location /workspace/coverage/default/43.kmac_smoke.1262422548
Short name T708
Test name
Test status
Simulation time 5476532629 ps
CPU time 58 seconds
Started Aug 09 06:01:55 PM PDT 24
Finished Aug 09 06:02:53 PM PDT 24
Peak memory 227028 kb
Host smart-809ecee3-3d54-4fa4-8179-d322c57e5dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262422548 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.1262422548 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_smoke/latest

Test location /workspace/coverage/default/43.kmac_stress_all.895432840
Short name T604
Test name
Test status
Simulation time 14732978648 ps
CPU time 390.1 seconds
Started Aug 09 06:02:24 PM PDT 24
Finished Aug 09 06:08:54 PM PDT 24
Peak memory 233356 kb
Host smart-91bf89ef-63ca-4d20-95c3-de6f06db941f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=895432840 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.895432840 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_stress_all/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_kmac.2737542822
Short name T465
Test name
Test status
Simulation time 332060132 ps
CPU time 5.4 seconds
Started Aug 09 06:02:06 PM PDT 24
Finished Aug 09 06:02:11 PM PDT 24
Peak memory 218812 kb
Host smart-9b855b36-acbe-43c9-9221-580a8ac78fb5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737542822 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.kmac_test_vectors_kmac.2737542822 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_kmac_xof.2373137827
Short name T448
Test name
Test status
Simulation time 122938700 ps
CPU time 5.84 seconds
Started Aug 09 06:02:06 PM PDT 24
Finished Aug 09 06:02:12 PM PDT 24
Peak memory 218932 kb
Host smart-a68ef1c9-e548-4aa4-990c-04c7b34ab0bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373137827 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.kmac_test_vectors_kmac_xof.2373137827 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_224.4156021074
Short name T232
Test name
Test status
Simulation time 417294508776 ps
CPU time 3511.35 seconds
Started Aug 09 06:01:55 PM PDT 24
Finished Aug 09 07:00:27 PM PDT 24
Peak memory 3167140 kb
Host smart-d964d3a5-2505-4b9a-8897-128afcd03fa5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4156021074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_224.4156021074 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_256.1333036707
Short name T520
Test name
Test status
Simulation time 66031447408 ps
CPU time 3168.07 seconds
Started Aug 09 06:02:01 PM PDT 24
Finished Aug 09 06:54:49 PM PDT 24
Peak memory 3131796 kb
Host smart-879054f1-646c-4c82-bd51-e14ab24a8cb6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1333036707 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_256.1333036707 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_384.2703161367
Short name T34
Test name
Test status
Simulation time 94786459983 ps
CPU time 2290.95 seconds
Started Aug 09 06:02:01 PM PDT 24
Finished Aug 09 06:40:12 PM PDT 24
Peak memory 2334740 kb
Host smart-6e74ff1b-6fa4-4779-96fe-b3662585a1b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2703161367 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_384.2703161367 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_512.2540698125
Short name T325
Test name
Test status
Simulation time 194797076440 ps
CPU time 1963.05 seconds
Started Aug 09 06:02:01 PM PDT 24
Finished Aug 09 06:34:44 PM PDT 24
Peak memory 1719596 kb
Host smart-3099ac80-4c2d-4996-8f18-cbd7e0918a1d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2540698125 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_512.2540698125 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_shake_128.4228987836
Short name T765
Test name
Test status
Simulation time 66788963674 ps
CPU time 6422.93 seconds
Started Aug 09 06:02:04 PM PDT 24
Finished Aug 09 07:49:08 PM PDT 24
Peak memory 2697688 kb
Host smart-bc5a4272-acba-4c6d-a68f-2ced5066dc15
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4228987836 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_128.4228987836 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_shake_256.191102192
Short name T882
Test name
Test status
Simulation time 403640006550 ps
CPU time 5347.15 seconds
Started Aug 09 06:02:06 PM PDT 24
Finished Aug 09 07:31:14 PM PDT 24
Peak memory 2231036 kb
Host smart-ae1c3dd8-034d-48e9-9b3a-91fb11216426
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=191102192 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_256.191102192 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/44.kmac_alert_test.443872586
Short name T963
Test name
Test status
Simulation time 22602569 ps
CPU time 0.88 seconds
Started Aug 09 06:02:46 PM PDT 24
Finished Aug 09 06:02:47 PM PDT 24
Peak memory 218528 kb
Host smart-2949f625-c900-48ce-8e98-81c7b8c402c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443872586 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.443872586 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/44.kmac_alert_test/latest

Test location /workspace/coverage/default/44.kmac_app.3404028931
Short name T890
Test name
Test status
Simulation time 13130160597 ps
CPU time 183 seconds
Started Aug 09 06:02:37 PM PDT 24
Finished Aug 09 06:05:40 PM PDT 24
Peak memory 346104 kb
Host smart-53113b59-f2f3-4318-9398-17e084186f66
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404028931 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.3404028931 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/44.kmac_app/latest

Test location /workspace/coverage/default/44.kmac_burst_write.2167424668
Short name T786
Test name
Test status
Simulation time 19904585762 ps
CPU time 535.42 seconds
Started Aug 09 06:02:27 PM PDT 24
Finished Aug 09 06:11:22 PM PDT 24
Peak memory 243368 kb
Host smart-b72f2f56-55ef-4b93-82c6-2320988fad11
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167424668 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.216742466
8 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_burst_write/latest

Test location /workspace/coverage/default/44.kmac_entropy_refresh.2698063572
Short name T958
Test name
Test status
Simulation time 14903184296 ps
CPU time 366.45 seconds
Started Aug 09 06:02:39 PM PDT 24
Finished Aug 09 06:08:45 PM PDT 24
Peak memory 474448 kb
Host smart-3e2334be-dc1a-4422-a5a2-b54abd0a4ab8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698063572 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.2
698063572 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/44.kmac_error.1290532359
Short name T601
Test name
Test status
Simulation time 6098422898 ps
CPU time 141.31 seconds
Started Aug 09 06:02:40 PM PDT 24
Finished Aug 09 06:05:01 PM PDT 24
Peak memory 276140 kb
Host smart-6a2fdedc-783a-466a-919b-a47d36896e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290532359 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_error.1290532359 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_error/latest

Test location /workspace/coverage/default/44.kmac_key_error.4164790984
Short name T610
Test name
Test status
Simulation time 543773030 ps
CPU time 3.83 seconds
Started Aug 09 06:02:39 PM PDT 24
Finished Aug 09 06:02:43 PM PDT 24
Peak memory 226756 kb
Host smart-916e3ca2-ea15-4395-a676-d87543d34923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164790984 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.4164790984 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_key_error/latest

Test location /workspace/coverage/default/44.kmac_lc_escalation.4107888976
Short name T82
Test name
Test status
Simulation time 67581387 ps
CPU time 1.46 seconds
Started Aug 09 06:02:39 PM PDT 24
Finished Aug 09 06:02:40 PM PDT 24
Peak memory 226964 kb
Host smart-073854ec-eec6-4b81-a730-c0724ceb44f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107888976 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.4107888976 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/44.kmac_lc_escalation/latest

Test location /workspace/coverage/default/44.kmac_long_msg_and_output.2237824601
Short name T727
Test name
Test status
Simulation time 10423645691 ps
CPU time 1281.04 seconds
Started Aug 09 06:02:25 PM PDT 24
Finished Aug 09 06:23:46 PM PDT 24
Peak memory 822688 kb
Host smart-3588afa0-497b-4821-8a4c-1b5cc8cb6893
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237824601 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_a
nd_output.2237824601 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/44.kmac_sideload.1586115775
Short name T226
Test name
Test status
Simulation time 18054616518 ps
CPU time 375.86 seconds
Started Aug 09 06:02:28 PM PDT 24
Finished Aug 09 06:08:44 PM PDT 24
Peak memory 512408 kb
Host smart-3afbd287-2766-4d52-9a69-45d8dcc4c45d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586115775 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.1586115775 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_sideload/latest

Test location /workspace/coverage/default/44.kmac_smoke.3564143107
Short name T278
Test name
Test status
Simulation time 3504164078 ps
CPU time 64.55 seconds
Started Aug 09 06:02:23 PM PDT 24
Finished Aug 09 06:03:27 PM PDT 24
Peak memory 223536 kb
Host smart-9b68e303-9485-49b5-bf31-96238c5a8c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564143107 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.3564143107 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_smoke/latest

Test location /workspace/coverage/default/44.kmac_stress_all.1186693804
Short name T157
Test name
Test status
Simulation time 41603635923 ps
CPU time 1285.23 seconds
Started Aug 09 06:02:46 PM PDT 24
Finished Aug 09 06:24:12 PM PDT 24
Peak memory 1072192 kb
Host smart-ecb63ce4-4dcd-46cd-93b3-c7def6a2da3c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1186693804 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all.1186693804 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_stress_all/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_kmac.712152286
Short name T352
Test name
Test status
Simulation time 742940216 ps
CPU time 6.84 seconds
Started Aug 09 06:02:38 PM PDT 24
Finished Aug 09 06:02:45 PM PDT 24
Peak memory 219976 kb
Host smart-69d0d662-af41-4490-b3e3-dc9372fc7a58
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712152286 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.kmac_test_vectors_kmac.712152286 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_kmac_xof.1700981028
Short name T1041
Test name
Test status
Simulation time 1635827425 ps
CPU time 5.89 seconds
Started Aug 09 06:02:39 PM PDT 24
Finished Aug 09 06:02:45 PM PDT 24
Peak memory 218904 kb
Host smart-660c1ef4-d22c-4622-bd1f-77050b8e0f9d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700981028 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.kmac_test_vectors_kmac_xof.1700981028 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_224.885991312
Short name T211
Test name
Test status
Simulation time 77189425988 ps
CPU time 3099.44 seconds
Started Aug 09 06:02:28 PM PDT 24
Finished Aug 09 06:54:08 PM PDT 24
Peak memory 3223064 kb
Host smart-38d2c2db-133d-4a4d-add6-043164576848
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=885991312 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_224.885991312 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_256.3543798901
Short name T871
Test name
Test status
Simulation time 134454213588 ps
CPU time 2916.47 seconds
Started Aug 09 06:02:31 PM PDT 24
Finished Aug 09 06:51:07 PM PDT 24
Peak memory 3065636 kb
Host smart-2ec94ec6-a28f-4a76-b5f2-5a27673a9655
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3543798901 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_256.3543798901 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_384.391989994
Short name T717
Test name
Test status
Simulation time 15109184809 ps
CPU time 1793.26 seconds
Started Aug 09 06:02:28 PM PDT 24
Finished Aug 09 06:32:21 PM PDT 24
Peak memory 923856 kb
Host smart-31ba7a99-bbd3-4743-ac6e-ade165e7cee0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=391989994 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_384.391989994 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_512.2898759536
Short name T626
Test name
Test status
Simulation time 45656123169 ps
CPU time 1599.42 seconds
Started Aug 09 06:02:30 PM PDT 24
Finished Aug 09 06:29:10 PM PDT 24
Peak memory 1721632 kb
Host smart-cc3b1c12-0201-4351-8b02-e3e34aea65ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2898759536 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_512.2898759536 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/45.kmac_alert_test.1181818086
Short name T746
Test name
Test status
Simulation time 11908456 ps
CPU time 0.78 seconds
Started Aug 09 06:03:08 PM PDT 24
Finished Aug 09 06:03:09 PM PDT 24
Peak memory 218536 kb
Host smart-dcc0def3-41df-4d0f-9464-7b5aef7db0b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181818086 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.1181818086 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_alert_test/latest

Test location /workspace/coverage/default/45.kmac_app.3947942859
Short name T223
Test name
Test status
Simulation time 411685460 ps
CPU time 10.49 seconds
Started Aug 09 06:03:02 PM PDT 24
Finished Aug 09 06:03:13 PM PDT 24
Peak memory 243260 kb
Host smart-910d7688-b2ff-4af5-9e88-622edd8dc70a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947942859 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.3947942859 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/45.kmac_app/latest

Test location /workspace/coverage/default/45.kmac_burst_write.3359496302
Short name T158
Test name
Test status
Simulation time 2092305311 ps
CPU time 199.27 seconds
Started Aug 09 06:02:50 PM PDT 24
Finished Aug 09 06:06:09 PM PDT 24
Peak memory 228016 kb
Host smart-5bfb2f99-5c21-4f51-9d25-e30a07311b74
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359496302 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.335949630
2 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_burst_write/latest

Test location /workspace/coverage/default/45.kmac_entropy_refresh.2961504193
Short name T594
Test name
Test status
Simulation time 41072972821 ps
CPU time 156.69 seconds
Started Aug 09 06:03:02 PM PDT 24
Finished Aug 09 06:05:39 PM PDT 24
Peak memory 325652 kb
Host smart-a49c1ac0-bb84-436b-a94f-ae72fc39978c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961504193 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_entropy_refresh.2
961504193 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/45.kmac_error.636935512
Short name T389
Test name
Test status
Simulation time 9223227790 ps
CPU time 300.9 seconds
Started Aug 09 06:03:04 PM PDT 24
Finished Aug 09 06:08:05 PM PDT 24
Peak memory 452624 kb
Host smart-eb7081f8-dd6d-4a07-b2c1-ae8079ac002e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636935512 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.636935512 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_error/latest

Test location /workspace/coverage/default/45.kmac_key_error.2833053630
Short name T918
Test name
Test status
Simulation time 386294214 ps
CPU time 1.41 seconds
Started Aug 09 06:03:06 PM PDT 24
Finished Aug 09 06:03:08 PM PDT 24
Peak memory 225376 kb
Host smart-394c1ede-31c1-4531-b85c-0cc2949645e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833053630 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.2833053630 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_key_error/latest

Test location /workspace/coverage/default/45.kmac_lc_escalation.3365364668
Short name T677
Test name
Test status
Simulation time 100789333 ps
CPU time 1.19 seconds
Started Aug 09 06:03:08 PM PDT 24
Finished Aug 09 06:03:09 PM PDT 24
Peak memory 226860 kb
Host smart-befd6fef-879f-42e3-bdd0-e3b03ee516e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365364668 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.3365364668 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/45.kmac_lc_escalation/latest

Test location /workspace/coverage/default/45.kmac_long_msg_and_output.1906565510
Short name T85
Test name
Test status
Simulation time 26827678191 ps
CPU time 670.27 seconds
Started Aug 09 06:02:44 PM PDT 24
Finished Aug 09 06:13:55 PM PDT 24
Peak memory 547872 kb
Host smart-4f6ba4cf-c0f7-4808-ad05-d3c8478a59e5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906565510 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_a
nd_output.1906565510 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/45.kmac_sideload.2842268712
Short name T537
Test name
Test status
Simulation time 895704363 ps
CPU time 69.64 seconds
Started Aug 09 06:02:51 PM PDT 24
Finished Aug 09 06:04:01 PM PDT 24
Peak memory 249404 kb
Host smart-ebc3bb7d-44e9-4ae4-b5ef-2457087c4421
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842268712 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.2842268712 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_sideload/latest

Test location /workspace/coverage/default/45.kmac_smoke.631726608
Short name T270
Test name
Test status
Simulation time 2490452662 ps
CPU time 33.02 seconds
Started Aug 09 06:02:44 PM PDT 24
Finished Aug 09 06:03:17 PM PDT 24
Peak memory 223276 kb
Host smart-2e8623ee-58df-42ad-aada-0be07862d0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631726608 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.631726608 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_smoke/latest

Test location /workspace/coverage/default/45.kmac_stress_all.4049803914
Short name T60
Test name
Test status
Simulation time 9646511488 ps
CPU time 302.37 seconds
Started Aug 09 06:03:07 PM PDT 24
Finished Aug 09 06:08:09 PM PDT 24
Peak memory 382020 kb
Host smart-715e7fd8-aa06-46be-bc88-8f8c20b462bf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4049803914 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.4049803914 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_stress_all/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_kmac.932315964
Short name T844
Test name
Test status
Simulation time 416316718 ps
CPU time 6.85 seconds
Started Aug 09 06:03:03 PM PDT 24
Finished Aug 09 06:03:10 PM PDT 24
Peak memory 219016 kb
Host smart-23ea59bf-871b-484a-b425-ecb1647ef4bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932315964 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.kmac_test_vectors_kmac.932315964 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_kmac_xof.2775319985
Short name T981
Test name
Test status
Simulation time 1358021413 ps
CPU time 6.39 seconds
Started Aug 09 06:03:03 PM PDT 24
Finished Aug 09 06:03:09 PM PDT 24
Peak memory 219828 kb
Host smart-88cdfac2-46c2-4c8e-84e4-79e1e097ab71
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775319985 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.kmac_test_vectors_kmac_xof.2775319985 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_224.2374103595
Short name T669
Test name
Test status
Simulation time 65221233487 ps
CPU time 3055.14 seconds
Started Aug 09 06:02:49 PM PDT 24
Finished Aug 09 06:53:45 PM PDT 24
Peak memory 3220816 kb
Host smart-2db208ce-c0a4-45e4-95d1-8886a34cc497
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2374103595 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_224.2374103595 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_256.4013084436
Short name T678
Test name
Test status
Simulation time 25319338022 ps
CPU time 2099.97 seconds
Started Aug 09 06:02:56 PM PDT 24
Finished Aug 09 06:37:57 PM PDT 24
Peak memory 1149668 kb
Host smart-76b3a38f-6804-45b1-8972-e5b923c6a6d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4013084436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_256.4013084436 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_384.2214521778
Short name T548
Test name
Test status
Simulation time 48782963481 ps
CPU time 2306.03 seconds
Started Aug 09 06:02:57 PM PDT 24
Finished Aug 09 06:41:23 PM PDT 24
Peak memory 2346384 kb
Host smart-1fe9b092-0233-4c47-a948-0bd5ba40e4a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2214521778 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_384.2214521778 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_512.3948284518
Short name T778
Test name
Test status
Simulation time 11213566743 ps
CPU time 1182.29 seconds
Started Aug 09 06:02:57 PM PDT 24
Finished Aug 09 06:22:39 PM PDT 24
Peak memory 711100 kb
Host smart-300aabbf-f6cc-4024-8252-9f269f4a6541
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3948284518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_512.3948284518 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_shake_256.2886352058
Short name T609
Test name
Test status
Simulation time 307260920683 ps
CPU time 8681.42 seconds
Started Aug 09 06:02:57 PM PDT 24
Finished Aug 09 08:27:39 PM PDT 24
Peak memory 6378864 kb
Host smart-4085da55-c8d7-42f5-a5cc-695dc05ab190
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2886352058 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_shake_256.2886352058 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/46.kmac_alert_test.3099644137
Short name T543
Test name
Test status
Simulation time 16885004 ps
CPU time 0.85 seconds
Started Aug 09 06:03:41 PM PDT 24
Finished Aug 09 06:03:42 PM PDT 24
Peak memory 218528 kb
Host smart-d702b8ed-fd63-4e6a-aa7a-35a9a0260978
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099644137 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.3099644137 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_alert_test/latest

Test location /workspace/coverage/default/46.kmac_app.3993353066
Short name T874
Test name
Test status
Simulation time 10270142686 ps
CPU time 352.51 seconds
Started Aug 09 06:03:23 PM PDT 24
Finished Aug 09 06:09:16 PM PDT 24
Peak memory 333084 kb
Host smart-993a7f6d-2e44-46b9-9147-ad3b229962e3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993353066 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.3993353066 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/46.kmac_app/latest

Test location /workspace/coverage/default/46.kmac_burst_write.3311281235
Short name T1006
Test name
Test status
Simulation time 23074924164 ps
CPU time 1328.52 seconds
Started Aug 09 06:03:14 PM PDT 24
Finished Aug 09 06:25:23 PM PDT 24
Peak memory 245652 kb
Host smart-92575eb1-2cd7-4b57-9185-c5ac9330c709
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311281235 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.331128123
5 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_burst_write/latest

Test location /workspace/coverage/default/46.kmac_entropy_refresh.1595350708
Short name T599
Test name
Test status
Simulation time 44174220156 ps
CPU time 275.11 seconds
Started Aug 09 06:03:29 PM PDT 24
Finished Aug 09 06:08:04 PM PDT 24
Peak memory 397600 kb
Host smart-84193a14-1b0d-477d-b4e7-2c9cfc1750f6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595350708 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_entropy_refresh.1
595350708 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/46.kmac_error.4162667704
Short name T315
Test name
Test status
Simulation time 2744575814 ps
CPU time 219.55 seconds
Started Aug 09 06:03:28 PM PDT 24
Finished Aug 09 06:07:08 PM PDT 24
Peak memory 310640 kb
Host smart-437eafbc-dc45-45ae-bda6-536b0bc1e18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162667704 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.4162667704 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_error/latest

Test location /workspace/coverage/default/46.kmac_key_error.2594504397
Short name T122
Test name
Test status
Simulation time 5223662760 ps
CPU time 5.65 seconds
Started Aug 09 06:03:37 PM PDT 24
Finished Aug 09 06:03:43 PM PDT 24
Peak memory 226828 kb
Host smart-cf9b26a7-7968-4729-9dd9-5d18db1da42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594504397 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.2594504397 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_key_error/latest

Test location /workspace/coverage/default/46.kmac_lc_escalation.4109850171
Short name T25
Test name
Test status
Simulation time 2908977989 ps
CPU time 50.83 seconds
Started Aug 09 06:03:41 PM PDT 24
Finished Aug 09 06:04:32 PM PDT 24
Peak memory 248580 kb
Host smart-a4d114b5-214e-4b1a-bfcb-c8d66a1930b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109850171 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.4109850171 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/46.kmac_lc_escalation/latest

Test location /workspace/coverage/default/46.kmac_long_msg_and_output.1009008311
Short name T444
Test name
Test status
Simulation time 4855512470 ps
CPU time 489.06 seconds
Started Aug 09 06:03:12 PM PDT 24
Finished Aug 09 06:11:21 PM PDT 24
Peak memory 505724 kb
Host smart-f217441a-77e0-4881-b71e-d6480323b362
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009008311 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_a
nd_output.1009008311 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/46.kmac_sideload.664113514
Short name T575
Test name
Test status
Simulation time 22120972213 ps
CPU time 522.94 seconds
Started Aug 09 06:03:13 PM PDT 24
Finished Aug 09 06:11:57 PM PDT 24
Peak memory 388444 kb
Host smart-cba8d7ed-dfad-4639-80fb-f3bea75ce271
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664113514 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.664113514 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_sideload/latest

Test location /workspace/coverage/default/46.kmac_smoke.2425980969
Short name T600
Test name
Test status
Simulation time 2588811937 ps
CPU time 27.31 seconds
Started Aug 09 06:03:07 PM PDT 24
Finished Aug 09 06:03:35 PM PDT 24
Peak memory 227036 kb
Host smart-10f6b6d4-4f22-4e9f-8352-2fd390c00fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425980969 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.2425980969 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_smoke/latest

Test location /workspace/coverage/default/46.kmac_stress_all.1482492345
Short name T587
Test name
Test status
Simulation time 114066565351 ps
CPU time 822.79 seconds
Started Aug 09 06:03:41 PM PDT 24
Finished Aug 09 06:17:23 PM PDT 24
Peak memory 560548 kb
Host smart-dc2f6dcc-7af6-4d4b-a02f-015aeee58a5d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1482492345 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.1482492345 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_stress_all/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_kmac.193636906
Short name T849
Test name
Test status
Simulation time 510968480 ps
CPU time 6.37 seconds
Started Aug 09 06:03:18 PM PDT 24
Finished Aug 09 06:03:24 PM PDT 24
Peak memory 219832 kb
Host smart-57da581b-00e5-4fbe-a748-85df8d0c0112
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193636906 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.kmac_test_vectors_kmac.193636906 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_kmac_xof.2131801119
Short name T559
Test name
Test status
Simulation time 471166877 ps
CPU time 6.1 seconds
Started Aug 09 06:03:22 PM PDT 24
Finished Aug 09 06:03:28 PM PDT 24
Peak memory 218964 kb
Host smart-eeb48b84-2bcc-489a-b9ba-cb9aad08bb02
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131801119 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.kmac_test_vectors_kmac_xof.2131801119 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_224.763029193
Short name T381
Test name
Test status
Simulation time 503841583245 ps
CPU time 3795.89 seconds
Started Aug 09 06:03:18 PM PDT 24
Finished Aug 09 07:06:35 PM PDT 24
Peak memory 3275072 kb
Host smart-59fa13d1-516f-4f8e-a865-dc40b7dd2cc4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=763029193 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_224.763029193 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_256.3844509356
Short name T1038
Test name
Test status
Simulation time 64031346760 ps
CPU time 3277.17 seconds
Started Aug 09 06:03:19 PM PDT 24
Finished Aug 09 06:57:57 PM PDT 24
Peak memory 3051900 kb
Host smart-70a80766-065d-4bf2-8d35-1325e5709d6c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3844509356 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_256.3844509356 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_384.3498202266
Short name T453
Test name
Test status
Simulation time 251177483822 ps
CPU time 2283.34 seconds
Started Aug 09 06:03:19 PM PDT 24
Finished Aug 09 06:41:23 PM PDT 24
Peak memory 2346056 kb
Host smart-6790cb03-8439-43de-b103-388816302fe3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3498202266 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_384.3498202266 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_512.2829142549
Short name T1035
Test name
Test status
Simulation time 85458250158 ps
CPU time 1664.74 seconds
Started Aug 09 06:03:20 PM PDT 24
Finished Aug 09 06:31:05 PM PDT 24
Peak memory 1752532 kb
Host smart-7b66258b-2410-4937-b8ed-0a267d587697
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2829142549 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_512.2829142549 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_shake_128.4220148862
Short name T865
Test name
Test status
Simulation time 271037983481 ps
CPU time 6377.63 seconds
Started Aug 09 06:03:20 PM PDT 24
Finished Aug 09 07:49:39 PM PDT 24
Peak memory 2734888 kb
Host smart-616e7ac2-d45e-4f40-a6ec-e2f672e2033e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4220148862 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_128.4220148862 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_shake_256.2013980768
Short name T385
Test name
Test status
Simulation time 231546171855 ps
CPU time 10696.8 seconds
Started Aug 09 06:03:19 PM PDT 24
Finished Aug 09 09:01:37 PM PDT 24
Peak memory 6433724 kb
Host smart-ff9ad7da-12af-4328-9c28-e685d6239151
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2013980768 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_256.2013980768 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/47.kmac_alert_test.3680203591
Short name T1000
Test name
Test status
Simulation time 34956525 ps
CPU time 0.82 seconds
Started Aug 09 06:04:01 PM PDT 24
Finished Aug 09 06:04:02 PM PDT 24
Peak memory 218524 kb
Host smart-199b353d-034c-4bcd-a1e3-f59692a31e29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680203591 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.3680203591 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_alert_test/latest

Test location /workspace/coverage/default/47.kmac_app.2150862905
Short name T596
Test name
Test status
Simulation time 12065348486 ps
CPU time 275.32 seconds
Started Aug 09 06:03:56 PM PDT 24
Finished Aug 09 06:08:32 PM PDT 24
Peak memory 435984 kb
Host smart-4faf729f-6383-4ec0-9c78-eb5c49a191e5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150862905 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.2150862905 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/47.kmac_app/latest

Test location /workspace/coverage/default/47.kmac_burst_write.3173591026
Short name T464
Test name
Test status
Simulation time 29031474177 ps
CPU time 1196.99 seconds
Started Aug 09 06:03:49 PM PDT 24
Finished Aug 09 06:23:46 PM PDT 24
Peak memory 262644 kb
Host smart-e141cec8-5d38-4d55-9321-30fedcfc8eb6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173591026 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.317359102
6 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_burst_write/latest

Test location /workspace/coverage/default/47.kmac_entropy_refresh.1461649992
Short name T867
Test name
Test status
Simulation time 22432559578 ps
CPU time 257.97 seconds
Started Aug 09 06:03:56 PM PDT 24
Finished Aug 09 06:08:14 PM PDT 24
Peak memory 296648 kb
Host smart-bf196aac-1445-4a00-b974-7bb677605bd3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461649992 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.1
461649992 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/47.kmac_error.3630073748
Short name T1019
Test name
Test status
Simulation time 18454113938 ps
CPU time 523.3 seconds
Started Aug 09 06:03:59 PM PDT 24
Finished Aug 09 06:12:42 PM PDT 24
Peak memory 594296 kb
Host smart-caf72cb9-5a84-4c31-93cb-5ddaffb851f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630073748 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.3630073748 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_error/latest

Test location /workspace/coverage/default/47.kmac_key_error.2538217073
Short name T899
Test name
Test status
Simulation time 889137927 ps
CPU time 7.58 seconds
Started Aug 09 06:03:56 PM PDT 24
Finished Aug 09 06:04:04 PM PDT 24
Peak memory 226924 kb
Host smart-cec18563-adec-4db5-99cf-bdf635a4f02a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538217073 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.2538217073 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_key_error/latest

Test location /workspace/coverage/default/47.kmac_lc_escalation.1024095953
Short name T30
Test name
Test status
Simulation time 232000761 ps
CPU time 1.36 seconds
Started Aug 09 06:03:56 PM PDT 24
Finished Aug 09 06:03:57 PM PDT 24
Peak memory 226920 kb
Host smart-1da2a929-ade5-404e-8b85-152e517c2c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024095953 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.1024095953 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/47.kmac_lc_escalation/latest

Test location /workspace/coverage/default/47.kmac_long_msg_and_output.4143464434
Short name T693
Test name
Test status
Simulation time 22204984916 ps
CPU time 2685.78 seconds
Started Aug 09 06:03:45 PM PDT 24
Finished Aug 09 06:48:31 PM PDT 24
Peak memory 1440664 kb
Host smart-9677b8b1-b8d0-43ff-b170-eb355009cc7b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143464434 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_a
nd_output.4143464434 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/47.kmac_sideload.3353596331
Short name T291
Test name
Test status
Simulation time 30445032487 ps
CPU time 555.11 seconds
Started Aug 09 06:03:47 PM PDT 24
Finished Aug 09 06:13:02 PM PDT 24
Peak memory 624468 kb
Host smart-ba4644ff-815f-4bad-814e-59a94c6e373a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353596331 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.3353596331 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_sideload/latest

Test location /workspace/coverage/default/47.kmac_smoke.2153654378
Short name T343
Test name
Test status
Simulation time 6659449699 ps
CPU time 37.34 seconds
Started Aug 09 06:03:47 PM PDT 24
Finished Aug 09 06:04:25 PM PDT 24
Peak memory 222208 kb
Host smart-7c94459c-1dce-4f34-a481-c81b5560996c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153654378 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.2153654378 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_smoke/latest

Test location /workspace/coverage/default/47.kmac_stress_all.2381560133
Short name T386
Test name
Test status
Simulation time 51698790991 ps
CPU time 214.07 seconds
Started Aug 09 06:04:03 PM PDT 24
Finished Aug 09 06:07:37 PM PDT 24
Peak memory 415304 kb
Host smart-9b1c7de3-0f9c-485b-bf1f-2be15f2ec921
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2381560133 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.2381560133 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_stress_all/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_kmac.2771810639
Short name T614
Test name
Test status
Simulation time 736485435 ps
CPU time 7.63 seconds
Started Aug 09 06:03:51 PM PDT 24
Finished Aug 09 06:03:59 PM PDT 24
Peak memory 218920 kb
Host smart-8214dba7-aec8-44ce-97b3-b646a081bcb9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771810639 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.kmac_test_vectors_kmac.2771810639 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_kmac_xof.115540553
Short name T196
Test name
Test status
Simulation time 410706736 ps
CPU time 6.65 seconds
Started Aug 09 06:03:51 PM PDT 24
Finished Aug 09 06:03:58 PM PDT 24
Peak memory 218880 kb
Host smart-58c49de1-f8fe-4c78-9345-f9ecaa3ff340
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115540553 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.kmac_test_vectors_kmac_xof.115540553 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_224.3508159506
Short name T646
Test name
Test status
Simulation time 135810593127 ps
CPU time 3382.53 seconds
Started Aug 09 06:03:44 PM PDT 24
Finished Aug 09 07:00:08 PM PDT 24
Peak memory 3339996 kb
Host smart-e04c2fee-ff5f-438e-a997-96d4323da866
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3508159506 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_224.3508159506 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_256.594253587
Short name T472
Test name
Test status
Simulation time 285158539450 ps
CPU time 3254.67 seconds
Started Aug 09 06:03:46 PM PDT 24
Finished Aug 09 06:58:01 PM PDT 24
Peak memory 3108140 kb
Host smart-d2941bb2-dae5-435f-a8af-2f1cfd754116
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=594253587 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_256.594253587 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_384.1035408684
Short name T501
Test name
Test status
Simulation time 184201809185 ps
CPU time 1746.16 seconds
Started Aug 09 06:03:47 PM PDT 24
Finished Aug 09 06:32:53 PM PDT 24
Peak memory 922900 kb
Host smart-eb10cc51-7a1b-4bc7-852e-c81f450c0bc8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1035408684 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_384.1035408684 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_512.493155797
Short name T259
Test name
Test status
Simulation time 39860243480 ps
CPU time 1279.95 seconds
Started Aug 09 06:03:45 PM PDT 24
Finished Aug 09 06:25:05 PM PDT 24
Peak memory 696048 kb
Host smart-49365bfb-b080-43a0-8391-9e9f7d1699d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=493155797 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_512.493155797 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_shake_256.1845181558
Short name T1017
Test name
Test status
Simulation time 127793653250 ps
CPU time 5686.12 seconds
Started Aug 09 06:03:52 PM PDT 24
Finished Aug 09 07:38:39 PM PDT 24
Peak memory 2243516 kb
Host smart-cec577b7-075e-4fd5-9286-d5dc26c13810
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1845181558 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_shake_256.1845181558 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/48.kmac_alert_test.698153820
Short name T986
Test name
Test status
Simulation time 11744910 ps
CPU time 0.8 seconds
Started Aug 09 06:04:36 PM PDT 24
Finished Aug 09 06:04:37 PM PDT 24
Peak memory 218508 kb
Host smart-b239291c-74c6-4ad5-830b-fb318f77c530
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698153820 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.698153820 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/48.kmac_alert_test/latest

Test location /workspace/coverage/default/48.kmac_app.3653262635
Short name T262
Test name
Test status
Simulation time 27122781188 ps
CPU time 75.56 seconds
Started Aug 09 06:04:24 PM PDT 24
Finished Aug 09 06:05:40 PM PDT 24
Peak memory 268888 kb
Host smart-9cdc34ce-6ee8-44aa-b5b0-7dbee400ed09
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653262635 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.3653262635 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/48.kmac_app/latest

Test location /workspace/coverage/default/48.kmac_burst_write.3355971213
Short name T683
Test name
Test status
Simulation time 28959160762 ps
CPU time 733.7 seconds
Started Aug 09 06:04:07 PM PDT 24
Finished Aug 09 06:16:21 PM PDT 24
Peak memory 240140 kb
Host smart-09a9504d-ed91-4e0b-8e7a-70a76f2b1825
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355971213 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.335597121
3 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_burst_write/latest

Test location /workspace/coverage/default/48.kmac_entropy_refresh.3188139812
Short name T76
Test name
Test status
Simulation time 24968450338 ps
CPU time 378.19 seconds
Started Aug 09 06:04:23 PM PDT 24
Finished Aug 09 06:10:42 PM PDT 24
Peak memory 481528 kb
Host smart-d7dc174d-cfff-49d7-9e83-46f1a4c51843
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188139812 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.3
188139812 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/48.kmac_error.275252521
Short name T302
Test name
Test status
Simulation time 9056571573 ps
CPU time 314.56 seconds
Started Aug 09 06:04:27 PM PDT 24
Finished Aug 09 06:09:42 PM PDT 24
Peak memory 460668 kb
Host smart-7bb3b46b-db74-4ca5-ad27-8f51492bf874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275252521 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.275252521 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_error/latest

Test location /workspace/coverage/default/48.kmac_key_error.3266347838
Short name T975
Test name
Test status
Simulation time 1526513264 ps
CPU time 6.59 seconds
Started Aug 09 06:04:28 PM PDT 24
Finished Aug 09 06:04:35 PM PDT 24
Peak memory 226664 kb
Host smart-c133d910-1ed6-42f0-8375-975b12471971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266347838 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.3266347838 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_key_error/latest

Test location /workspace/coverage/default/48.kmac_lc_escalation.3820338695
Short name T114
Test name
Test status
Simulation time 88685219 ps
CPU time 1.56 seconds
Started Aug 09 06:04:28 PM PDT 24
Finished Aug 09 06:04:30 PM PDT 24
Peak memory 226916 kb
Host smart-0e11c000-aed2-445b-9c02-dc011bd480a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820338695 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.3820338695 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/48.kmac_lc_escalation/latest

Test location /workspace/coverage/default/48.kmac_sideload.2394463393
Short name T208
Test name
Test status
Simulation time 16124475956 ps
CPU time 127.52 seconds
Started Aug 09 06:04:03 PM PDT 24
Finished Aug 09 06:06:10 PM PDT 24
Peak memory 324872 kb
Host smart-23dbb30a-63f6-45cd-948c-56afd6b45918
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394463393 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.2394463393 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_sideload/latest

Test location /workspace/coverage/default/48.kmac_smoke.1589870431
Short name T194
Test name
Test status
Simulation time 3032654054 ps
CPU time 76.36 seconds
Started Aug 09 06:04:00 PM PDT 24
Finished Aug 09 06:05:17 PM PDT 24
Peak memory 227112 kb
Host smart-78709184-33c0-4c6b-b628-2c119c561a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589870431 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.1589870431 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_smoke/latest

Test location /workspace/coverage/default/48.kmac_stress_all.3917358446
Short name T471
Test name
Test status
Simulation time 133329472116 ps
CPU time 1059.47 seconds
Started Aug 09 06:04:34 PM PDT 24
Finished Aug 09 06:22:14 PM PDT 24
Peak memory 865052 kb
Host smart-995174ce-9d54-437b-a31b-28c57260f5c2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3917358446 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.3917358446 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_stress_all/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_kmac.2887464166
Short name T295
Test name
Test status
Simulation time 853978984 ps
CPU time 6.29 seconds
Started Aug 09 06:04:18 PM PDT 24
Finished Aug 09 06:04:25 PM PDT 24
Peak memory 218784 kb
Host smart-3bf7250e-69fa-4cf8-a92d-b212db7a500b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887464166 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.kmac_test_vectors_kmac.2887464166 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_kmac_xof.1309816838
Short name T877
Test name
Test status
Simulation time 228783904 ps
CPU time 6.98 seconds
Started Aug 09 06:04:23 PM PDT 24
Finished Aug 09 06:04:30 PM PDT 24
Peak memory 218968 kb
Host smart-92c64f8f-82a4-4877-8a97-9cc09d488afd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309816838 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.kmac_test_vectors_kmac_xof.1309816838 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_224.3935430903
Short name T598
Test name
Test status
Simulation time 389501738180 ps
CPU time 4059.21 seconds
Started Aug 09 06:04:10 PM PDT 24
Finished Aug 09 07:11:50 PM PDT 24
Peak memory 3237332 kb
Host smart-9597403a-8df0-4219-bcd1-ead05579fc9d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3935430903 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_224.3935430903 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_256.3225814591
Short name T984
Test name
Test status
Simulation time 65604554790 ps
CPU time 3099.24 seconds
Started Aug 09 06:04:06 PM PDT 24
Finished Aug 09 06:55:46 PM PDT 24
Peak memory 3014968 kb
Host smart-16707808-a461-42a3-a502-df1815640cba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3225814591 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_256.3225814591 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_384.657084339
Short name T141
Test name
Test status
Simulation time 50339546882 ps
CPU time 2198.39 seconds
Started Aug 09 06:04:13 PM PDT 24
Finished Aug 09 06:40:51 PM PDT 24
Peak memory 2336968 kb
Host smart-1c44e132-7aa1-44f8-90f7-8628b1ea5d98
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=657084339 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_384.657084339 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_512.414307137
Short name T691
Test name
Test status
Simulation time 13150301524 ps
CPU time 1241.41 seconds
Started Aug 09 06:04:11 PM PDT 24
Finished Aug 09 06:24:53 PM PDT 24
Peak memory 700264 kb
Host smart-6cbf5aed-fd2d-4563-9998-e3f0353080e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=414307137 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_512.414307137 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_shake_256.3159603092
Short name T611
Test name
Test status
Simulation time 109032518462 ps
CPU time 5452.48 seconds
Started Aug 09 06:04:18 PM PDT 24
Finished Aug 09 07:35:11 PM PDT 24
Peak memory 2222496 kb
Host smart-38225240-40f4-468d-b29f-6f56713eace2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3159603092 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_256.3159603092 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/49.kmac_alert_test.2315219022
Short name T760
Test name
Test status
Simulation time 28682661 ps
CPU time 0.78 seconds
Started Aug 09 06:05:07 PM PDT 24
Finished Aug 09 06:05:08 PM PDT 24
Peak memory 218528 kb
Host smart-168fba5e-4bac-4c0b-a5e4-434c3ae57749
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315219022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.2315219022 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_alert_test/latest

Test location /workspace/coverage/default/49.kmac_app.514422146
Short name T172
Test name
Test status
Simulation time 8038729510 ps
CPU time 233.68 seconds
Started Aug 09 06:05:02 PM PDT 24
Finished Aug 09 06:08:55 PM PDT 24
Peak memory 390332 kb
Host smart-e388a183-36ae-4b4a-ab47-eba8130f85cf
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514422146 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.514422146 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/49.kmac_app/latest

Test location /workspace/coverage/default/49.kmac_burst_write.3622200556
Short name T455
Test name
Test status
Simulation time 967168815 ps
CPU time 121.98 seconds
Started Aug 09 06:04:39 PM PDT 24
Finished Aug 09 06:06:41 PM PDT 24
Peak memory 228264 kb
Host smart-22bcd3d4-63cb-4ec9-8967-0d700edd0a4f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622200556 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.362220055
6 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_burst_write/latest

Test location /workspace/coverage/default/49.kmac_entropy_refresh.1213050303
Short name T802
Test name
Test status
Simulation time 17334072144 ps
CPU time 358.12 seconds
Started Aug 09 06:05:01 PM PDT 24
Finished Aug 09 06:10:59 PM PDT 24
Peak memory 437784 kb
Host smart-c536f4c8-3e93-4056-b5ec-954cce082bde
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213050303 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.1
213050303 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/49.kmac_error.4028364637
Short name T22
Test name
Test status
Simulation time 48812319659 ps
CPU time 471.97 seconds
Started Aug 09 06:05:01 PM PDT 24
Finished Aug 09 06:12:53 PM PDT 24
Peak memory 377876 kb
Host smart-e4711164-c0de-4bd1-82f4-512c154f5e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028364637 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.4028364637 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_error/latest

Test location /workspace/coverage/default/49.kmac_key_error.1172616388
Short name T320
Test name
Test status
Simulation time 4082173147 ps
CPU time 7.07 seconds
Started Aug 09 06:05:07 PM PDT 24
Finished Aug 09 06:05:14 PM PDT 24
Peak memory 226812 kb
Host smart-1bfb9ba1-f1cf-40c9-8974-e4b509048ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172616388 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.1172616388 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_key_error/latest

Test location /workspace/coverage/default/49.kmac_lc_escalation.3072382421
Short name T68
Test name
Test status
Simulation time 52202076 ps
CPU time 1.51 seconds
Started Aug 09 06:05:07 PM PDT 24
Finished Aug 09 06:05:09 PM PDT 24
Peak memory 226852 kb
Host smart-9ddf4535-17e9-4729-8988-d692a5350290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072382421 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.3072382421 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/49.kmac_lc_escalation/latest

Test location /workspace/coverage/default/49.kmac_long_msg_and_output.3298118223
Short name T928
Test name
Test status
Simulation time 10085716489 ps
CPU time 379.38 seconds
Started Aug 09 06:04:36 PM PDT 24
Finished Aug 09 06:10:56 PM PDT 24
Peak memory 681972 kb
Host smart-289d348e-d1d8-409a-b33f-b0a4f8fbe0ad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298118223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_a
nd_output.3298118223 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/49.kmac_sideload.4037351202
Short name T391
Test name
Test status
Simulation time 7329872239 ps
CPU time 117.79 seconds
Started Aug 09 06:04:34 PM PDT 24
Finished Aug 09 06:06:32 PM PDT 24
Peak memory 319784 kb
Host smart-30ea73fb-9806-4cb9-a85c-5f67be643f34
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037351202 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.4037351202 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_sideload/latest

Test location /workspace/coverage/default/49.kmac_smoke.1649561227
Short name T1014
Test name
Test status
Simulation time 6124748183 ps
CPU time 53.51 seconds
Started Aug 09 06:04:37 PM PDT 24
Finished Aug 09 06:05:31 PM PDT 24
Peak memory 226960 kb
Host smart-3f5232e1-ad68-4316-81c1-d285945406f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649561227 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.1649561227 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_smoke/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_kmac.3959441172
Short name T700
Test name
Test status
Simulation time 1264714731 ps
CPU time 6.93 seconds
Started Aug 09 06:05:02 PM PDT 24
Finished Aug 09 06:05:09 PM PDT 24
Peak memory 219800 kb
Host smart-93aeff18-2b42-449e-984e-e7d3873c0bc3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959441172 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.kmac_test_vectors_kmac.3959441172 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_kmac_xof.2941325604
Short name T201
Test name
Test status
Simulation time 501650260 ps
CPU time 5.78 seconds
Started Aug 09 06:05:02 PM PDT 24
Finished Aug 09 06:05:08 PM PDT 24
Peak memory 218848 kb
Host smart-b14e004f-3037-4870-9367-db00ed37f1f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941325604 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.kmac_test_vectors_kmac_xof.2941325604 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_224.1126055830
Short name T258
Test name
Test status
Simulation time 81210831821 ps
CPU time 2334.08 seconds
Started Aug 09 06:04:40 PM PDT 24
Finished Aug 09 06:43:35 PM PDT 24
Peak memory 1200264 kb
Host smart-bc934d0b-46a0-4fb5-b5d0-10b190ab57f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1126055830 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_224.1126055830 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_256.309073447
Short name T621
Test name
Test status
Simulation time 19498106253 ps
CPU time 2026.4 seconds
Started Aug 09 06:04:39 PM PDT 24
Finished Aug 09 06:38:26 PM PDT 24
Peak memory 1133816 kb
Host smart-53109458-142d-43b0-bc4e-1c92f74a8350
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=309073447 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_256.309073447 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_384.726993369
Short name T460
Test name
Test status
Simulation time 48900674562 ps
CPU time 1707.26 seconds
Started Aug 09 06:04:42 PM PDT 24
Finished Aug 09 06:33:09 PM PDT 24
Peak memory 917476 kb
Host smart-1dd862e7-80f4-48b5-a9cd-1dbda4fbb0af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=726993369 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_384.726993369 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_512.541524068
Short name T499
Test name
Test status
Simulation time 251513656399 ps
CPU time 1563.83 seconds
Started Aug 09 06:04:40 PM PDT 24
Finished Aug 09 06:30:44 PM PDT 24
Peak memory 1695652 kb
Host smart-0c5297e0-d361-4fe1-b961-0248195037f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=541524068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_512.541524068 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_shake_256.2703217385
Short name T725
Test name
Test status
Simulation time 626975530884 ps
CPU time 9302 seconds
Started Aug 09 06:04:50 PM PDT 24
Finished Aug 09 08:39:54 PM PDT 24
Peak memory 6441632 kb
Host smart-bcac79ea-3f2b-499d-8f6c-1c99da2332e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2703217385 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_256.2703217385 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/5.kmac_alert_test.4147249154
Short name T590
Test name
Test status
Simulation time 67151195 ps
CPU time 0.84 seconds
Started Aug 09 05:53:53 PM PDT 24
Finished Aug 09 05:53:54 PM PDT 24
Peak memory 218548 kb
Host smart-cd006008-cc50-46a8-a78e-05d862ed5d91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147249154 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.4147249154 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_alert_test/latest

Test location /workspace/coverage/default/5.kmac_app.2574333329
Short name T819
Test name
Test status
Simulation time 37631309180 ps
CPU time 271.52 seconds
Started Aug 09 05:53:50 PM PDT 24
Finished Aug 09 05:58:22 PM PDT 24
Peak memory 441184 kb
Host smart-ef19e332-e937-47d9-a235-1b560ee16f07
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574333329 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.2574333329 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/5.kmac_app/latest

Test location /workspace/coverage/default/5.kmac_app_with_partial_data.864826636
Short name T2
Test name
Test status
Simulation time 63824511835 ps
CPU time 504.63 seconds
Started Aug 09 05:53:50 PM PDT 24
Finished Aug 09 06:02:15 PM PDT 24
Peak memory 564032 kb
Host smart-887d18c4-201d-48c0-ad77-607080ff1be2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864826636 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_parti
al_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_part
ial_data.864826636 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/5.kmac_burst_write.2412065013
Short name T675
Test name
Test status
Simulation time 87302529326 ps
CPU time 1321.99 seconds
Started Aug 09 05:53:51 PM PDT 24
Finished Aug 09 06:15:53 PM PDT 24
Peak memory 259952 kb
Host smart-65aa7aeb-a9d7-4d00-ad5c-2ed5a145624b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412065013 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.2412065013
+enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_burst_write/latest

Test location /workspace/coverage/default/5.kmac_edn_timeout_error.1500932293
Short name T261
Test name
Test status
Simulation time 101330651 ps
CPU time 1.25 seconds
Started Aug 09 05:53:51 PM PDT 24
Finished Aug 09 05:53:52 PM PDT 24
Peak memory 218632 kb
Host smart-2ba0e19b-03a6-4c78-a752-ffe71c6b3a79
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1500932293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.1500932293 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_mode_error.120103408
Short name T969
Test name
Test status
Simulation time 18533406 ps
CPU time 0.87 seconds
Started Aug 09 05:53:49 PM PDT 24
Finished Aug 09 05:53:50 PM PDT 24
Peak memory 220832 kb
Host smart-1ebd249b-d860-42e5-8c6e-230c98737753
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=120103408 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.120103408 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_ready_error.3281538974
Short name T582
Test name
Test status
Simulation time 3319216304 ps
CPU time 11.97 seconds
Started Aug 09 05:53:53 PM PDT 24
Finished Aug 09 05:54:05 PM PDT 24
Peak memory 221964 kb
Host smart-8744f320-620e-48f9-b523-27f2cee8a743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281538974 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.3281538974 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_refresh.3719539867
Short name T478
Test name
Test status
Simulation time 5834340481 ps
CPU time 274.18 seconds
Started Aug 09 05:53:49 PM PDT 24
Finished Aug 09 05:58:23 PM PDT 24
Peak memory 312880 kb
Host smart-e36fe19b-edd3-49b8-a29f-6f6fb2325b22
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719539867 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.37
19539867 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/5.kmac_error.3366721091
Short name T1018
Test name
Test status
Simulation time 14069499731 ps
CPU time 412.75 seconds
Started Aug 09 05:53:50 PM PDT 24
Finished Aug 09 06:00:43 PM PDT 24
Peak memory 561580 kb
Host smart-1e0a6629-0b8d-40a5-ba22-655cde24aa6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366721091 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.3366721091 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_error/latest

Test location /workspace/coverage/default/5.kmac_key_error.2159960142
Short name T914
Test name
Test status
Simulation time 313998518 ps
CPU time 2.47 seconds
Started Aug 09 05:53:48 PM PDT 24
Finished Aug 09 05:53:51 PM PDT 24
Peak memory 226720 kb
Host smart-ba0076fb-2efd-42d1-894b-04fb57ec8f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159960142 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.2159960142 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_key_error/latest

Test location /workspace/coverage/default/5.kmac_lc_escalation.797655216
Short name T845
Test name
Test status
Simulation time 899925275 ps
CPU time 7.03 seconds
Started Aug 09 05:53:49 PM PDT 24
Finished Aug 09 05:53:56 PM PDT 24
Peak memory 235328 kb
Host smart-b4e0fc5c-ff33-4890-a5fc-42401d500bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797655216 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.797655216 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_lc_escalation/latest

Test location /workspace/coverage/default/5.kmac_long_msg_and_output.222892384
Short name T833
Test name
Test status
Simulation time 113916040976 ps
CPU time 3790.22 seconds
Started Aug 09 05:53:51 PM PDT 24
Finished Aug 09 06:57:02 PM PDT 24
Peak memory 1894352 kb
Host smart-6279d0a1-4846-4b9d-b7f4-3b025240a387
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222892384 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_and
_output.222892384 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/5.kmac_mubi.637740075
Short name T59
Test name
Test status
Simulation time 25007982337 ps
CPU time 422.8 seconds
Started Aug 09 05:53:52 PM PDT 24
Finished Aug 09 06:00:54 PM PDT 24
Peak memory 521876 kb
Host smart-89b44f3f-3e1f-4441-86ea-2c53b5aad44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637740075 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.637740075 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_mubi/latest

Test location /workspace/coverage/default/5.kmac_sideload.4135723696
Short name T378
Test name
Test status
Simulation time 4203573470 ps
CPU time 81.66 seconds
Started Aug 09 05:53:48 PM PDT 24
Finished Aug 09 05:55:10 PM PDT 24
Peak memory 254020 kb
Host smart-59e2a64f-4bc3-4e35-a2a2-9b4195801043
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135723696 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.4135723696 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_sideload/latest

Test location /workspace/coverage/default/5.kmac_smoke.1802009930
Short name T875
Test name
Test status
Simulation time 2879501857 ps
CPU time 23.68 seconds
Started Aug 09 05:53:49 PM PDT 24
Finished Aug 09 05:54:12 PM PDT 24
Peak memory 227012 kb
Host smart-10aa2c0e-a4b9-48d8-b16f-1937bbf566e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802009930 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.1802009930 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_smoke/latest

Test location /workspace/coverage/default/5.kmac_stress_all.3823554539
Short name T155
Test name
Test status
Simulation time 24843466739 ps
CPU time 638.49 seconds
Started Aug 09 05:53:53 PM PDT 24
Finished Aug 09 06:04:31 PM PDT 24
Peak memory 356184 kb
Host smart-aff1ec75-6798-44f4-9ce0-2d12730e14cc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3823554539 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.3823554539 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_stress_all/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_kmac.2130580961
Short name T990
Test name
Test status
Simulation time 2785492334 ps
CPU time 5.59 seconds
Started Aug 09 05:53:48 PM PDT 24
Finished Aug 09 05:53:54 PM PDT 24
Peak memory 218996 kb
Host smart-b2bf34fe-12ae-4279-9fb4-667483b3fa00
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130580961 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.kmac_test_vectors_kmac.2130580961 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_kmac_xof.377815846
Short name T707
Test name
Test status
Simulation time 317108057 ps
CPU time 5.87 seconds
Started Aug 09 05:53:49 PM PDT 24
Finished Aug 09 05:53:55 PM PDT 24
Peak memory 218896 kb
Host smart-d598d42e-505c-4404-bd6a-448064c9291d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377815846 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.kmac_test_vectors_kmac_xof.377815846 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_224.4060836279
Short name T321
Test name
Test status
Simulation time 389576929790 ps
CPU time 3439 seconds
Started Aug 09 05:53:49 PM PDT 24
Finished Aug 09 06:51:09 PM PDT 24
Peak memory 3256780 kb
Host smart-e3a640b7-5d7b-4344-bb07-2137733bfce1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4060836279 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_224.4060836279 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_256.2047092764
Short name T313
Test name
Test status
Simulation time 79634823649 ps
CPU time 2286.88 seconds
Started Aug 09 05:53:44 PM PDT 24
Finished Aug 09 06:31:52 PM PDT 24
Peak memory 1143988 kb
Host smart-21e8a965-9832-444a-9732-7cbf27ea3152
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2047092764 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_256.2047092764 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_384.782963236
Short name T281
Test name
Test status
Simulation time 291038587190 ps
CPU time 2657.93 seconds
Started Aug 09 05:53:49 PM PDT 24
Finished Aug 09 06:38:08 PM PDT 24
Peak memory 2365368 kb
Host smart-8eb03685-f1ad-491e-854f-5e5b0bad5292
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=782963236 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_384.782963236 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_512.640052293
Short name T880
Test name
Test status
Simulation time 10497181719 ps
CPU time 1268.74 seconds
Started Aug 09 05:53:53 PM PDT 24
Finished Aug 09 06:15:02 PM PDT 24
Peak memory 709716 kb
Host smart-083987e0-e80a-457d-b72a-93b74c2da6f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=640052293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_512.640052293 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_shake_256.3923010135
Short name T966
Test name
Test status
Simulation time 78370421395 ps
CPU time 5105.83 seconds
Started Aug 09 05:53:51 PM PDT 24
Finished Aug 09 07:18:58 PM PDT 24
Peak memory 2229452 kb
Host smart-7fbd287f-ca45-4564-848a-e17c96a46b53
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3923010135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_shake_256.3923010135 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/6.kmac_alert_test.3274091823
Short name T300
Test name
Test status
Simulation time 30561428 ps
CPU time 0.8 seconds
Started Aug 09 05:53:56 PM PDT 24
Finished Aug 09 05:53:56 PM PDT 24
Peak memory 218568 kb
Host smart-3daa6eee-1df9-4ab5-9cdc-76a3c081393c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274091823 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.3274091823 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_alert_test/latest

Test location /workspace/coverage/default/6.kmac_app.4158034747
Short name T823
Test name
Test status
Simulation time 15114502178 ps
CPU time 350.31 seconds
Started Aug 09 05:53:57 PM PDT 24
Finished Aug 09 05:59:47 PM PDT 24
Peak memory 467888 kb
Host smart-f5a207ee-6c0c-45ef-a0fb-ed8630ef2c8d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158034747 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.4158034747 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/6.kmac_app/latest

Test location /workspace/coverage/default/6.kmac_app_with_partial_data.842698296
Short name T106
Test name
Test status
Simulation time 10301195805 ps
CPU time 187.49 seconds
Started Aug 09 05:53:54 PM PDT 24
Finished Aug 09 05:57:02 PM PDT 24
Peak memory 287900 kb
Host smart-2311ea4e-6477-4c99-a0ce-33a81abf2b0e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842698296 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_parti
al_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_part
ial_data.842698296 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/6.kmac_burst_write.3066447340
Short name T252
Test name
Test status
Simulation time 1825705491 ps
CPU time 99.56 seconds
Started Aug 09 05:53:55 PM PDT 24
Finished Aug 09 05:55:35 PM PDT 24
Peak memory 243120 kb
Host smart-8e4e9c2f-e930-4ba8-8101-f223cde14d38
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066447340 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.3066447340
+enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_burst_write/latest

Test location /workspace/coverage/default/6.kmac_edn_timeout_error.2372118085
Short name T807
Test name
Test status
Simulation time 1174930842 ps
CPU time 41.15 seconds
Started Aug 09 05:53:55 PM PDT 24
Finished Aug 09 05:54:36 PM PDT 24
Peak memory 227372 kb
Host smart-8f24e41b-5fff-4e8f-8ce4-615db478a5d2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2372118085 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.2372118085 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_mode_error.1661558302
Short name T446
Test name
Test status
Simulation time 60864798 ps
CPU time 0.84 seconds
Started Aug 09 05:53:56 PM PDT 24
Finished Aug 09 05:53:57 PM PDT 24
Peak memory 220628 kb
Host smart-8b9b3e7c-8fbc-41f5-8163-c64b53f86a1b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1661558302 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.1661558302 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_ready_error.2434626297
Short name T365
Test name
Test status
Simulation time 6217772352 ps
CPU time 61.62 seconds
Started Aug 09 05:54:00 PM PDT 24
Finished Aug 09 05:55:01 PM PDT 24
Peak memory 227012 kb
Host smart-9c8a2132-1eda-458c-8d81-5ce777adc415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434626297 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.2434626297 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_refresh.4273299842
Short name T987
Test name
Test status
Simulation time 5751413740 ps
CPU time 118.8 seconds
Started Aug 09 05:53:54 PM PDT 24
Finished Aug 09 05:55:53 PM PDT 24
Peak memory 299548 kb
Host smart-ef782df9-7908-4e1c-9ce4-f4702e68b382
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273299842 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.42
73299842 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/6.kmac_error.3405173796
Short name T607
Test name
Test status
Simulation time 17562692060 ps
CPU time 257.33 seconds
Started Aug 09 05:53:52 PM PDT 24
Finished Aug 09 05:58:09 PM PDT 24
Peak memory 442680 kb
Host smart-1ccfd156-1ebc-4206-9723-669a2bd6b1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405173796 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.3405173796 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_error/latest

Test location /workspace/coverage/default/6.kmac_key_error.580382173
Short name T684
Test name
Test status
Simulation time 1932954287 ps
CPU time 8.95 seconds
Started Aug 09 05:53:54 PM PDT 24
Finished Aug 09 05:54:03 PM PDT 24
Peak memory 226696 kb
Host smart-75332f16-49f8-4284-b24d-1c3dc44c9d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580382173 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.580382173 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_key_error/latest

Test location /workspace/coverage/default/6.kmac_long_msg_and_output.4093784422
Short name T681
Test name
Test status
Simulation time 162074309755 ps
CPU time 1574.9 seconds
Started Aug 09 05:53:55 PM PDT 24
Finished Aug 09 06:20:10 PM PDT 24
Peak memory 1762144 kb
Host smart-95f581aa-0cd6-47a1-9461-4f76d009531e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093784422 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_an
d_output.4093784422 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/6.kmac_mubi.908382235
Short name T635
Test name
Test status
Simulation time 16069700655 ps
CPU time 285.4 seconds
Started Aug 09 05:53:52 PM PDT 24
Finished Aug 09 05:58:38 PM PDT 24
Peak memory 318532 kb
Host smart-f31c29d2-fd54-4192-97db-b396dd564033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908382235 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.908382235 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_mubi/latest

Test location /workspace/coverage/default/6.kmac_sideload.3327275135
Short name T221
Test name
Test status
Simulation time 69571231 ps
CPU time 2.86 seconds
Started Aug 09 05:53:52 PM PDT 24
Finished Aug 09 05:53:55 PM PDT 24
Peak memory 221472 kb
Host smart-deb2f15f-ef70-4210-91a7-1406d67b5432
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327275135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.3327275135 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_sideload/latest

Test location /workspace/coverage/default/6.kmac_smoke.1165410931
Short name T427
Test name
Test status
Simulation time 8210505540 ps
CPU time 53.66 seconds
Started Aug 09 05:53:49 PM PDT 24
Finished Aug 09 05:54:43 PM PDT 24
Peak memory 227040 kb
Host smart-763c83b5-8b9a-4323-8ff9-d84392853cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165410931 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.1165410931 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_smoke/latest

Test location /workspace/coverage/default/6.kmac_stress_all.1331212476
Short name T335
Test name
Test status
Simulation time 44672964789 ps
CPU time 743.91 seconds
Started Aug 09 05:53:52 PM PDT 24
Finished Aug 09 06:06:16 PM PDT 24
Peak memory 479000 kb
Host smart-96876bdd-db4d-4f83-982b-7ceed2608ab9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1331212476 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.1331212476 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_stress_all/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_kmac.2673893700
Short name T753
Test name
Test status
Simulation time 544317968 ps
CPU time 6.69 seconds
Started Aug 09 05:54:00 PM PDT 24
Finished Aug 09 05:54:07 PM PDT 24
Peak memory 219752 kb
Host smart-4153da3a-3004-469b-a739-10b4fe2ffdfd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673893700 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.kmac_test_vectors_kmac.2673893700 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_kmac_xof.3001939918
Short name T579
Test name
Test status
Simulation time 703339667 ps
CPU time 5.7 seconds
Started Aug 09 05:53:56 PM PDT 24
Finished Aug 09 05:54:02 PM PDT 24
Peak memory 219812 kb
Host smart-a1c105c8-9735-4221-ad22-5121831e98ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001939918 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.kmac_test_vectors_kmac_xof.3001939918 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_224.805026837
Short name T835
Test name
Test status
Simulation time 271334432986 ps
CPU time 3100.08 seconds
Started Aug 09 05:53:52 PM PDT 24
Finished Aug 09 06:45:32 PM PDT 24
Peak memory 3214740 kb
Host smart-79e5309a-099a-4875-ab16-1f492a89586a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=805026837 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_224.805026837 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_256.3056052434
Short name T418
Test name
Test status
Simulation time 77992943626 ps
CPU time 3247.32 seconds
Started Aug 09 05:53:57 PM PDT 24
Finished Aug 09 06:48:04 PM PDT 24
Peak memory 3109748 kb
Host smart-26ab2f71-8e44-4e23-82c6-e70525696679
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3056052434 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_256.3056052434 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_384.338138121
Short name T147
Test name
Test status
Simulation time 195251063757 ps
CPU time 2128.03 seconds
Started Aug 09 05:53:51 PM PDT 24
Finished Aug 09 06:29:20 PM PDT 24
Peak memory 2357484 kb
Host smart-6a13f8af-15e1-493f-b8a6-4c12fefe9fe7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=338138121 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_384.338138121 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_512.2517728592
Short name T738
Test name
Test status
Simulation time 87882264333 ps
CPU time 1656.06 seconds
Started Aug 09 05:53:53 PM PDT 24
Finished Aug 09 06:21:29 PM PDT 24
Peak memory 1716988 kb
Host smart-7029a4de-42eb-4da3-a891-44c0a4603601
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2517728592 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_512.2517728592 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_shake_128.1189083569
Short name T368
Test name
Test status
Simulation time 240546618354 ps
CPU time 6684.91 seconds
Started Aug 09 05:53:53 PM PDT 24
Finished Aug 09 07:45:19 PM PDT 24
Peak memory 2704152 kb
Host smart-5b4026be-2eec-4914-b3f9-21428dbcd5df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1189083569 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_128.1189083569 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_shake_256.2691669227
Short name T266
Test name
Test status
Simulation time 741265834152 ps
CPU time 9520.67 seconds
Started Aug 09 05:53:53 PM PDT 24
Finished Aug 09 08:32:35 PM PDT 24
Peak memory 6532904 kb
Host smart-6f3cb470-19cc-4d57-8f7e-dce493361307
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2691669227 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_256.2691669227 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/7.kmac_alert_test.1189797954
Short name T519
Test name
Test status
Simulation time 17995736 ps
CPU time 0.84 seconds
Started Aug 09 05:53:52 PM PDT 24
Finished Aug 09 05:53:53 PM PDT 24
Peak memory 218548 kb
Host smart-1a7779ee-d3fe-4439-a977-91691ea9d7f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189797954 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.1189797954 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_alert_test/latest

Test location /workspace/coverage/default/7.kmac_app.3538912019
Short name T889
Test name
Test status
Simulation time 232442408100 ps
CPU time 449.36 seconds
Started Aug 09 05:53:50 PM PDT 24
Finished Aug 09 06:01:20 PM PDT 24
Peak memory 507280 kb
Host smart-93abe141-f608-409f-be63-cacb1316de38
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538912019 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.3538912019 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/7.kmac_app/latest

Test location /workspace/coverage/default/7.kmac_app_with_partial_data.1757014395
Short name T974
Test name
Test status
Simulation time 76369562766 ps
CPU time 447.45 seconds
Started Aug 09 05:53:52 PM PDT 24
Finished Aug 09 06:01:20 PM PDT 24
Peak memory 520472 kb
Host smart-f3810b04-c872-4a88-8b97-8ac8055c8352
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757014395 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_par
tial_data.1757014395 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/7.kmac_burst_write.1413257012
Short name T782
Test name
Test status
Simulation time 111897709736 ps
CPU time 941.99 seconds
Started Aug 09 05:53:54 PM PDT 24
Finished Aug 09 06:09:36 PM PDT 24
Peak memory 256756 kb
Host smart-1db94a03-4fd2-481f-a166-ce9f76179fe1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413257012 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.1413257012
+enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_burst_write/latest

Test location /workspace/coverage/default/7.kmac_edn_timeout_error.4192894785
Short name T665
Test name
Test status
Simulation time 1810749859 ps
CPU time 37.67 seconds
Started Aug 09 05:53:58 PM PDT 24
Finished Aug 09 05:54:36 PM PDT 24
Peak memory 238184 kb
Host smart-3f073e04-0226-4ad5-93fe-aa5792be2e29
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4192894785 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.4192894785 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_mode_error.3351094273
Short name T627
Test name
Test status
Simulation time 16736591 ps
CPU time 0.88 seconds
Started Aug 09 05:53:55 PM PDT 24
Finished Aug 09 05:53:56 PM PDT 24
Peak memory 220532 kb
Host smart-cfd56549-8fae-4d0b-a1df-c985532f82e9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3351094273 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.3351094273 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_ready_error.1337671095
Short name T9
Test name
Test status
Simulation time 6984674935 ps
CPU time 20.08 seconds
Started Aug 09 05:53:52 PM PDT 24
Finished Aug 09 05:54:12 PM PDT 24
Peak memory 220672 kb
Host smart-5dd26118-054e-427e-b003-4aa1b371d7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337671095 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.1337671095 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_refresh.3946277976
Short name T38
Test name
Test status
Simulation time 17585493329 ps
CPU time 294.83 seconds
Started Aug 09 05:53:55 PM PDT 24
Finished Aug 09 05:58:50 PM PDT 24
Peak memory 461040 kb
Host smart-8d6a7721-2f4f-45cc-bb5b-a80a70c1494a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946277976 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.39
46277976 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/7.kmac_error.542474347
Short name T870
Test name
Test status
Simulation time 24925414277 ps
CPU time 435.93 seconds
Started Aug 09 05:53:58 PM PDT 24
Finished Aug 09 06:01:14 PM PDT 24
Peak memory 547256 kb
Host smart-8c73f889-9260-47fa-b18a-db46164e8f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542474347 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.542474347 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_error/latest

Test location /workspace/coverage/default/7.kmac_key_error.361917569
Short name T13
Test name
Test status
Simulation time 804670498 ps
CPU time 5.78 seconds
Started Aug 09 05:53:57 PM PDT 24
Finished Aug 09 05:54:02 PM PDT 24
Peak memory 226660 kb
Host smart-70e89f59-6f10-412d-9057-5bb8cd1327b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361917569 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.361917569 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_key_error/latest

Test location /workspace/coverage/default/7.kmac_lc_escalation.3813254852
Short name T50
Test name
Test status
Simulation time 38854279 ps
CPU time 1.36 seconds
Started Aug 09 05:53:56 PM PDT 24
Finished Aug 09 05:53:58 PM PDT 24
Peak memory 226844 kb
Host smart-da509891-a703-4b60-bf29-c1ffd8b7c9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813254852 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.3813254852 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/7.kmac_lc_escalation/latest

Test location /workspace/coverage/default/7.kmac_long_msg_and_output.1183808964
Short name T349
Test name
Test status
Simulation time 226700121962 ps
CPU time 2226.16 seconds
Started Aug 09 05:53:54 PM PDT 24
Finished Aug 09 06:31:00 PM PDT 24
Peak memory 2209104 kb
Host smart-145aa3e8-5b56-47a1-a23c-bf03087c40f7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183808964 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_an
d_output.1183808964 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/7.kmac_mubi.1866134344
Short name T934
Test name
Test status
Simulation time 5963053579 ps
CPU time 338.63 seconds
Started Aug 09 05:53:53 PM PDT 24
Finished Aug 09 05:59:32 PM PDT 24
Peak memory 341200 kb
Host smart-257117e0-ec9c-4d58-8e1e-4b3180affe1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866134344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.1866134344 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_mubi/latest

Test location /workspace/coverage/default/7.kmac_sideload.2212621101
Short name T145
Test name
Test status
Simulation time 29201010441 ps
CPU time 154.68 seconds
Started Aug 09 05:53:57 PM PDT 24
Finished Aug 09 05:56:32 PM PDT 24
Peak memory 359888 kb
Host smart-5b8259f2-af4c-432b-a05a-721222b42ccd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212621101 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.2212621101 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_sideload/latest

Test location /workspace/coverage/default/7.kmac_smoke.1161407694
Short name T853
Test name
Test status
Simulation time 5883860933 ps
CPU time 72.14 seconds
Started Aug 09 05:53:57 PM PDT 24
Finished Aug 09 05:55:09 PM PDT 24
Peak memory 227776 kb
Host smart-2cf7baea-3c2a-43e1-a8f6-c208b4eb9527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161407694 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.1161407694 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_smoke/latest

Test location /workspace/coverage/default/7.kmac_stress_all.1187267419
Short name T283
Test name
Test status
Simulation time 31032180643 ps
CPU time 348.19 seconds
Started Aug 09 05:53:58 PM PDT 24
Finished Aug 09 05:59:46 PM PDT 24
Peak memory 243364 kb
Host smart-33c08e14-c443-458d-9d98-5b3ba982772a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1187267419 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.1187267419 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_stress_all/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_kmac.2301837037
Short name T248
Test name
Test status
Simulation time 410936395 ps
CPU time 5.64 seconds
Started Aug 09 05:53:51 PM PDT 24
Finished Aug 09 05:53:57 PM PDT 24
Peak memory 218848 kb
Host smart-36f4c83d-7855-40be-8f43-6c3adfde9e2a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301837037 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.kmac_test_vectors_kmac.2301837037 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_kmac_xof.3609163619
Short name T656
Test name
Test status
Simulation time 1175465257 ps
CPU time 6.09 seconds
Started Aug 09 05:53:55 PM PDT 24
Finished Aug 09 05:54:01 PM PDT 24
Peak memory 218860 kb
Host smart-16243c10-2453-42df-9467-5c5e532bc164
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609163619 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.kmac_test_vectors_kmac_xof.3609163619 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_224.2092332898
Short name T517
Test name
Test status
Simulation time 21070100332 ps
CPU time 2363.88 seconds
Started Aug 09 05:53:58 PM PDT 24
Finished Aug 09 06:33:23 PM PDT 24
Peak memory 1173132 kb
Host smart-80e21d31-8784-4d9a-a2fa-e7b5673a6b80
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2092332898 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_224.2092332898 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_256.404348905
Short name T955
Test name
Test status
Simulation time 20987037232 ps
CPU time 2280.01 seconds
Started Aug 09 05:53:58 PM PDT 24
Finished Aug 09 06:31:58 PM PDT 24
Peak memory 1147736 kb
Host smart-244a9754-07de-44a8-9a46-55f6ce00a6a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=404348905 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_256.404348905 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_384.1139256937
Short name T795
Test name
Test status
Simulation time 56892278853 ps
CPU time 1660.43 seconds
Started Aug 09 05:53:59 PM PDT 24
Finished Aug 09 06:21:40 PM PDT 24
Peak memory 935732 kb
Host smart-dbc0943e-38f4-4798-88b5-1d86b8d8968d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1139256937 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_384.1139256937 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_512.3152313009
Short name T274
Test name
Test status
Simulation time 41739107813 ps
CPU time 1705.87 seconds
Started Aug 09 05:53:57 PM PDT 24
Finished Aug 09 06:22:23 PM PDT 24
Peak memory 1687572 kb
Host smart-68561f4e-db60-44d8-ac1c-6912f04bbea8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3152313009 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_512.3152313009 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_shake_128.2481622080
Short name T658
Test name
Test status
Simulation time 549211139552 ps
CPU time 6873.74 seconds
Started Aug 09 05:53:54 PM PDT 24
Finished Aug 09 07:48:28 PM PDT 24
Peak memory 2706772 kb
Host smart-677c0fc6-cf9e-4867-885e-710e52eeb59b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2481622080 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_128.2481622080 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_shake_256.2737496613
Short name T193
Test name
Test status
Simulation time 341114106599 ps
CPU time 9556.45 seconds
Started Aug 09 05:53:52 PM PDT 24
Finished Aug 09 08:33:10 PM PDT 24
Peak memory 6322268 kb
Host smart-2c7da30a-134a-40b4-97cb-0d93f415091e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2737496613 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_256.2737496613 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/8.kmac_alert_test.3168325121
Short name T953
Test name
Test status
Simulation time 55880439 ps
CPU time 0.86 seconds
Started Aug 09 05:54:05 PM PDT 24
Finished Aug 09 05:54:06 PM PDT 24
Peak memory 218532 kb
Host smart-dee81171-5448-478e-ae5c-7d5b49e45dba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168325121 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.3168325121 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_alert_test/latest

Test location /workspace/coverage/default/8.kmac_app.3639388574
Short name T410
Test name
Test status
Simulation time 48504608593 ps
CPU time 353.27 seconds
Started Aug 09 05:54:05 PM PDT 24
Finished Aug 09 05:59:58 PM PDT 24
Peak memory 450096 kb
Host smart-cb47b2d3-268a-4332-9265-8e4c21565d1e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639388574 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.3639388574 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/8.kmac_app/latest

Test location /workspace/coverage/default/8.kmac_app_with_partial_data.1497389308
Short name T586
Test name
Test status
Simulation time 60199258252 ps
CPU time 213.65 seconds
Started Aug 09 05:54:00 PM PDT 24
Finished Aug 09 05:57:34 PM PDT 24
Peak memory 347168 kb
Host smart-86bce273-8286-4376-802b-0f8135caa870
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497389308 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_par
tial_data.1497389308 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/8.kmac_burst_write.2246964326
Short name T450
Test name
Test status
Simulation time 41906184454 ps
CPU time 1065.43 seconds
Started Aug 09 05:53:51 PM PDT 24
Finished Aug 09 06:11:37 PM PDT 24
Peak memory 242528 kb
Host smart-e15d8075-a8c9-40cf-be15-f0bbe443579f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246964326 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.2246964326
+enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_burst_write/latest

Test location /workspace/coverage/default/8.kmac_edn_timeout_error.4024048006
Short name T47
Test name
Test status
Simulation time 67925828 ps
CPU time 0.85 seconds
Started Aug 09 05:54:09 PM PDT 24
Finished Aug 09 05:54:10 PM PDT 24
Peak memory 218440 kb
Host smart-af89d246-8fd7-485a-b897-f1e8f9ec6374
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4024048006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.4024048006 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_mode_error.1983761980
Short name T758
Test name
Test status
Simulation time 21323013 ps
CPU time 0.94 seconds
Started Aug 09 05:54:02 PM PDT 24
Finished Aug 09 05:54:03 PM PDT 24
Peak memory 220524 kb
Host smart-eba7b05f-d560-4bcf-a484-3874e8d28df8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1983761980 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.1983761980 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_ready_error.4065928639
Short name T6
Test name
Test status
Simulation time 3223300376 ps
CPU time 48.93 seconds
Started Aug 09 05:54:03 PM PDT 24
Finished Aug 09 05:54:52 PM PDT 24
Peak memory 223904 kb
Host smart-28be0f07-e8c0-45db-835e-34c74c7a1db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065928639 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.4065928639 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_refresh.4031292373
Short name T466
Test name
Test status
Simulation time 27126751743 ps
CPU time 182.5 seconds
Started Aug 09 05:54:01 PM PDT 24
Finished Aug 09 05:57:03 PM PDT 24
Peak memory 283488 kb
Host smart-2c0cefb5-6708-4a67-aa89-ff170cb94c97
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031292373 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.40
31292373 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/8.kmac_error.2048636649
Short name T768
Test name
Test status
Simulation time 3103569304 ps
CPU time 45.61 seconds
Started Aug 09 05:54:00 PM PDT 24
Finished Aug 09 05:54:45 PM PDT 24
Peak memory 263460 kb
Host smart-c7e7ab83-32f6-4cce-afa7-e43ada4d5492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048636649 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.2048636649 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_error/latest

Test location /workspace/coverage/default/8.kmac_key_error.872306646
Short name T756
Test name
Test status
Simulation time 516675163 ps
CPU time 1.4 seconds
Started Aug 09 05:54:02 PM PDT 24
Finished Aug 09 05:54:04 PM PDT 24
Peak memory 225280 kb
Host smart-001388b9-808f-4ac6-8cdb-474c058073c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872306646 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.872306646 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_key_error/latest

Test location /workspace/coverage/default/8.kmac_lc_escalation.3069225003
Short name T591
Test name
Test status
Simulation time 47491195 ps
CPU time 1.31 seconds
Started Aug 09 05:53:57 PM PDT 24
Finished Aug 09 05:53:58 PM PDT 24
Peak memory 226872 kb
Host smart-d6a06a80-bef2-40cb-87c5-30685e84adb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069225003 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.3069225003 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/8.kmac_lc_escalation/latest

Test location /workspace/coverage/default/8.kmac_long_msg_and_output.1819202697
Short name T742
Test name
Test status
Simulation time 47609461493 ps
CPU time 2432.06 seconds
Started Aug 09 05:53:55 PM PDT 24
Finished Aug 09 06:34:27 PM PDT 24
Peak memory 2354028 kb
Host smart-c617d12b-e8a4-4b58-8f8a-a6ebfaa9a7c0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819202697 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_an
d_output.1819202697 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/8.kmac_mubi.1798158740
Short name T552
Test name
Test status
Simulation time 1541141477 ps
CPU time 99.39 seconds
Started Aug 09 05:53:55 PM PDT 24
Finished Aug 09 05:55:34 PM PDT 24
Peak memory 260792 kb
Host smart-e150365a-a16e-4a0e-9177-829599279044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798158740 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.1798158740 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_mubi/latest

Test location /workspace/coverage/default/8.kmac_sideload.3944556970
Short name T1026
Test name
Test status
Simulation time 79447873702 ps
CPU time 268.77 seconds
Started Aug 09 05:53:57 PM PDT 24
Finished Aug 09 05:58:25 PM PDT 24
Peak memory 423740 kb
Host smart-770c5f22-8310-4f84-8a4e-d7303e3988ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944556970 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.3944556970 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_sideload/latest

Test location /workspace/coverage/default/8.kmac_smoke.3723211518
Short name T214
Test name
Test status
Simulation time 3697113571 ps
CPU time 41.59 seconds
Started Aug 09 05:53:58 PM PDT 24
Finished Aug 09 05:54:40 PM PDT 24
Peak memory 226972 kb
Host smart-cd1da0e0-4ca8-4c81-aa98-02ff0a6744c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723211518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.3723211518 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_smoke/latest

Test location /workspace/coverage/default/8.kmac_stress_all.1889285760
Short name T1013
Test name
Test status
Simulation time 2941400907 ps
CPU time 56.33 seconds
Started Aug 09 05:53:58 PM PDT 24
Finished Aug 09 05:54:55 PM PDT 24
Peak memory 244540 kb
Host smart-e82cba9d-30a9-4938-9a4b-fe0b0f9139eb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1889285760 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.1889285760 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_stress_all/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_kmac.3032567346
Short name T338
Test name
Test status
Simulation time 572134500 ps
CPU time 6.12 seconds
Started Aug 09 05:54:03 PM PDT 24
Finished Aug 09 05:54:09 PM PDT 24
Peak memory 219764 kb
Host smart-c6bef964-e1ea-404c-a72b-64b800dfb71c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032567346 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.kmac_test_vectors_kmac.3032567346 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_kmac_xof.2278230783
Short name T692
Test name
Test status
Simulation time 255087747 ps
CPU time 6.48 seconds
Started Aug 09 05:54:00 PM PDT 24
Finished Aug 09 05:54:07 PM PDT 24
Peak memory 219860 kb
Host smart-4519279d-888e-40b2-af1b-ce02d6ef2526
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278230783 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.kmac_test_vectors_kmac_xof.2278230783 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_224.2121836584
Short name T979
Test name
Test status
Simulation time 192428765978 ps
CPU time 3288.44 seconds
Started Aug 09 05:53:58 PM PDT 24
Finished Aug 09 06:48:47 PM PDT 24
Peak memory 3232088 kb
Host smart-7e184b78-e763-440c-a496-371e89d20228
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2121836584 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_224.2121836584 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_256.2245007796
Short name T761
Test name
Test status
Simulation time 257786606945 ps
CPU time 3372.23 seconds
Started Aug 09 05:53:53 PM PDT 24
Finished Aug 09 06:50:06 PM PDT 24
Peak memory 3037988 kb
Host smart-2c758193-5059-46cd-9604-1ef140e60c50
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2245007796 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_256.2245007796 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_384.1541162360
Short name T557
Test name
Test status
Simulation time 642440196749 ps
CPU time 2571.44 seconds
Started Aug 09 05:53:59 PM PDT 24
Finished Aug 09 06:36:51 PM PDT 24
Peak memory 2367176 kb
Host smart-547e13b9-b169-444b-8577-9728b6e73221
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1541162360 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_384.1541162360 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_512.2392805293
Short name T217
Test name
Test status
Simulation time 40320647446 ps
CPU time 1375.42 seconds
Started Aug 09 05:54:05 PM PDT 24
Finished Aug 09 06:17:01 PM PDT 24
Peak memory 717112 kb
Host smart-4b29e9f2-fd1c-4390-bc62-82b4fdbe4bac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2392805293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_512.2392805293 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_shake_256.425771689
Short name T206
Test name
Test status
Simulation time 242511730723 ps
CPU time 5262.05 seconds
Started Aug 09 05:54:00 PM PDT 24
Finished Aug 09 07:21:43 PM PDT 24
Peak memory 2229972 kb
Host smart-52031480-13d7-4e6e-be6d-37a6199ed382
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=425771689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_256.425771689 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/9.kmac_alert_test.827158083
Short name T479
Test name
Test status
Simulation time 23112150 ps
CPU time 0.82 seconds
Started Aug 09 05:54:05 PM PDT 24
Finished Aug 09 05:54:05 PM PDT 24
Peak memory 218468 kb
Host smart-4b302f23-2e6b-4b44-b44c-64c6115663a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827158083 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.827158083 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/9.kmac_alert_test/latest

Test location /workspace/coverage/default/9.kmac_app.3252778329
Short name T924
Test name
Test status
Simulation time 23821445034 ps
CPU time 190.8 seconds
Started Aug 09 05:54:02 PM PDT 24
Finished Aug 09 05:57:13 PM PDT 24
Peak memory 355784 kb
Host smart-a94e7f30-a7c1-4fd4-8dd0-6d7008d2b116
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252778329 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.3252778329 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/9.kmac_app/latest

Test location /workspace/coverage/default/9.kmac_app_with_partial_data.798888352
Short name T652
Test name
Test status
Simulation time 15560013195 ps
CPU time 236.14 seconds
Started Aug 09 05:54:05 PM PDT 24
Finished Aug 09 05:58:01 PM PDT 24
Peak memory 307140 kb
Host smart-1c3921f5-5a09-449c-9af7-cc4f38f9014f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798888352 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_parti
al_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_part
ial_data.798888352 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/9.kmac_burst_write.4274963870
Short name T416
Test name
Test status
Simulation time 12819836024 ps
CPU time 562.38 seconds
Started Aug 09 05:54:00 PM PDT 24
Finished Aug 09 06:03:22 PM PDT 24
Peak memory 245924 kb
Host smart-95c20e0d-f21a-451c-bf70-9fe4e153ffdb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274963870 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.4274963870
+enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_burst_write/latest

Test location /workspace/coverage/default/9.kmac_edn_timeout_error.4069479980
Short name T701
Test name
Test status
Simulation time 72986838 ps
CPU time 2.71 seconds
Started Aug 09 05:54:06 PM PDT 24
Finished Aug 09 05:54:09 PM PDT 24
Peak memory 221516 kb
Host smart-50212c2a-cfab-4394-b88e-8602d2d23222
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4069479980 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.4069479980 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_mode_error.2488502060
Short name T78
Test name
Test status
Simulation time 33160187 ps
CPU time 1.06 seconds
Started Aug 09 05:54:02 PM PDT 24
Finished Aug 09 05:54:04 PM PDT 24
Peak memory 222100 kb
Host smart-f4ded68d-17be-4dfb-80c0-4b5d4f64f886
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2488502060 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.2488502060 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_ready_error.3907808343
Short name T597
Test name
Test status
Simulation time 30152860273 ps
CPU time 21.22 seconds
Started Aug 09 05:53:58 PM PDT 24
Finished Aug 09 05:54:19 PM PDT 24
Peak memory 221732 kb
Host smart-11beb910-a900-4638-b438-e8703dc0e3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907808343 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.3907808343 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_refresh.1926035217
Short name T783
Test name
Test status
Simulation time 28354430102 ps
CPU time 402.91 seconds
Started Aug 09 05:54:00 PM PDT 24
Finished Aug 09 06:00:43 PM PDT 24
Peak memory 347976 kb
Host smart-cb890775-221a-452a-ae4c-428913c2fd11
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926035217 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.19
26035217 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/9.kmac_error.3399100979
Short name T886
Test name
Test status
Simulation time 5103121266 ps
CPU time 415.89 seconds
Started Aug 09 05:53:59 PM PDT 24
Finished Aug 09 06:00:55 PM PDT 24
Peak memory 357524 kb
Host smart-9793251d-b081-4d35-8cc2-f9f64b6d0b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399100979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.3399100979 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_error/latest

Test location /workspace/coverage/default/9.kmac_key_error.3680273279
Short name T4
Test name
Test status
Simulation time 501610119 ps
CPU time 4.25 seconds
Started Aug 09 05:54:01 PM PDT 24
Finished Aug 09 05:54:05 PM PDT 24
Peak memory 226680 kb
Host smart-f68b48dd-d1cb-45b1-97a7-9f44d55aec2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680273279 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.3680273279 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_key_error/latest

Test location /workspace/coverage/default/9.kmac_lc_escalation.3180509771
Short name T319
Test name
Test status
Simulation time 84749377 ps
CPU time 1.45 seconds
Started Aug 09 05:54:02 PM PDT 24
Finished Aug 09 05:54:04 PM PDT 24
Peak memory 226864 kb
Host smart-f38ebdd7-e4f4-4d09-af8a-d276ab0e167c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180509771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.3180509771 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/9.kmac_lc_escalation/latest

Test location /workspace/coverage/default/9.kmac_mubi.3288783456
Short name T303
Test name
Test status
Simulation time 11319388685 ps
CPU time 66.53 seconds
Started Aug 09 05:54:05 PM PDT 24
Finished Aug 09 05:55:12 PM PDT 24
Peak memory 251960 kb
Host smart-e0872c6a-dcec-4940-9dd6-870c30f4cc64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288783456 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.3288783456 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_mubi/latest

Test location /workspace/coverage/default/9.kmac_sideload.3248466969
Short name T329
Test name
Test status
Simulation time 1525329713 ps
CPU time 48.05 seconds
Started Aug 09 05:54:02 PM PDT 24
Finished Aug 09 05:54:50 PM PDT 24
Peak memory 261132 kb
Host smart-e59072e0-25b9-442e-bed8-6583cc6b8f4e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248466969 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.3248466969 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_sideload/latest

Test location /workspace/coverage/default/9.kmac_smoke.3604124738
Short name T393
Test name
Test status
Simulation time 1484380869 ps
CPU time 25.65 seconds
Started Aug 09 05:54:02 PM PDT 24
Finished Aug 09 05:54:28 PM PDT 24
Peak memory 226852 kb
Host smart-cfbaf286-06a5-4ab5-9ea6-229a3efa5799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604124738 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.3604124738 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_smoke/latest

Test location /workspace/coverage/default/9.kmac_stress_all.3616004754
Short name T1012
Test name
Test status
Simulation time 26800949428 ps
CPU time 921.73 seconds
Started Aug 09 05:53:58 PM PDT 24
Finished Aug 09 06:09:20 PM PDT 24
Peak memory 332688 kb
Host smart-5294611f-5b13-4ae0-bb1f-a19920f31efd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3616004754 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.3616004754 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_stress_all/latest

Test location /workspace/coverage/default/9.kmac_stress_all_with_rand_reset.1991607181
Short name T24
Test name
Test status
Simulation time 337569026032 ps
CPU time 3753.43 seconds
Started Aug 09 05:54:00 PM PDT 24
Finished Aug 09 06:56:34 PM PDT 24
Peak memory 565752 kb
Host smart-ae7984fe-8fed-4a49-bb4d-02ee9da39d04
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1991607181 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all_with_rand_reset.1991607181 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_kmac.3284349851
Short name T964
Test name
Test status
Simulation time 1790820487 ps
CPU time 7.18 seconds
Started Aug 09 05:54:06 PM PDT 24
Finished Aug 09 05:54:13 PM PDT 24
Peak memory 218836 kb
Host smart-0d7bcc91-c7d5-4959-b6b6-38976f27d212
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284349851 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.kmac_test_vectors_kmac.3284349851 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_kmac_xof.2655630116
Short name T858
Test name
Test status
Simulation time 342913810 ps
CPU time 6.6 seconds
Started Aug 09 05:53:59 PM PDT 24
Finished Aug 09 05:54:06 PM PDT 24
Peak memory 218872 kb
Host smart-74e0a10e-31c0-4270-abd0-e8321f7b01c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655630116 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.kmac_test_vectors_kmac_xof.2655630116 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_224.3352992935
Short name T192
Test name
Test status
Simulation time 225746530774 ps
CPU time 3326.17 seconds
Started Aug 09 05:54:05 PM PDT 24
Finished Aug 09 06:49:32 PM PDT 24
Peak memory 3210548 kb
Host smart-df4e7734-99a0-418f-aaaa-7c35a3a6db5a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3352992935 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_224.3352992935 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_256.2319478429
Short name T740
Test name
Test status
Simulation time 92638451151 ps
CPU time 3515 seconds
Started Aug 09 05:53:59 PM PDT 24
Finished Aug 09 06:52:35 PM PDT 24
Peak memory 3043700 kb
Host smart-e576d654-435d-4757-bd36-b14a59b4875e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2319478429 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_256.2319478429 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_384.3512822557
Short name T202
Test name
Test status
Simulation time 69220074920 ps
CPU time 2695.23 seconds
Started Aug 09 05:53:59 PM PDT 24
Finished Aug 09 06:38:55 PM PDT 24
Peak memory 2348452 kb
Host smart-69a2525e-8639-474b-8702-a824e1f8362b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3512822557 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_384.3512822557 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_512.1541841849
Short name T285
Test name
Test status
Simulation time 28329260794 ps
CPU time 1433.45 seconds
Started Aug 09 05:54:05 PM PDT 24
Finished Aug 09 06:17:58 PM PDT 24
Peak memory 716648 kb
Host smart-21b8d22d-0a2d-4287-bb41-940dee00a084
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1541841849 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_512.1541841849 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_shake_128.650373475
Short name T767
Test name
Test status
Simulation time 242910537888 ps
CPU time 6386.93 seconds
Started Aug 09 05:54:05 PM PDT 24
Finished Aug 09 07:40:32 PM PDT 24
Peak memory 2658048 kb
Host smart-c4de3a29-e7ab-4620-a37c-9cf9db031aa3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=650373475 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_128.650373475 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_shake_256.3202844225
Short name T779
Test name
Test status
Simulation time 109674853743 ps
CPU time 5040.34 seconds
Started Aug 09 05:54:05 PM PDT 24
Finished Aug 09 07:18:06 PM PDT 24
Peak memory 2171440 kb
Host smart-8452b81d-7963-45ed-b9f0-fefa3eb6eab5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3202844225 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_256.3202844225 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_shake_256/latest
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