Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	83728088	1			T1	4		T2	10693		T3	221808
all_values[1]	83728088	1			T1	4		T2	10693		T3	221808
all_values[2]	83728088	1			T1	4		T2	10693		T3	221808

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

469547

1

T2

92

T3

6

T34

3274

auto[1]

250714717

1

T1

12

T2

31987

T3

665418

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

249941115

1

T1

12

T2

31800

T3

663681

auto[1]

1243149

1

T2

279

T3

1743

T20

39

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	161415	1			T2	49		T3	1		T21	107
all_values[0]	auto[0]	auto[1]	1989	1			T2	4		T3	2		T21	4
all_values[0]	auto[1]	auto[0]	83152290	1			T1	4		T2	10551		T3	221226
all_values[0]	auto[1]	auto[1]	412394	1			T2	89		T3	579		T20	13
all_values[1]	auto[0]	auto[0]	154568	1			T2	37		T3	1		T34	3272
all_values[1]	auto[0]	auto[1]	1465	1			T2	2		T3	2		T34	2
all_values[1]	auto[1]	auto[0]	83159137	1			T1	4		T2	10563		T3	221226
all_values[1]	auto[1]	auto[1]	412918	1			T2	91		T3	579		T20	13
all_values[2]	auto[0]	auto[0]	148647	1			T36	2		T21	41		T7	319
all_values[2]	auto[0]	auto[1]	1463	1			T36	1		T21	2		T7	2
all_values[2]	auto[1]	auto[0]	83165058	1			T1	4		T2	10600		T3	221227
all_values[2]	auto[1]	auto[1]	412920	1			T2	93		T3	581		T20	13