Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
274892 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
2 |
auto[1] |
289842 |
1 |
|
|
T2 |
130 |
|
T3 |
778 |
|
T20 |
16 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
142258 |
1 |
|
|
T2 |
25 |
|
T3 |
187 |
|
T20 |
8 |
lower_val |
139593 |
1 |
|
|
T1 |
1 |
|
T2 |
34 |
|
T3 |
208 |
zero_val |
1599 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
209458 |
1 |
|
|
T2 |
30 |
|
T3 |
178 |
|
T20 |
4 |
lower_val |
209984 |
1 |
|
|
T1 |
2 |
|
T2 |
34 |
|
T3 |
218 |
zero_val |
145292 |
1 |
|
|
T2 |
68 |
|
T3 |
384 |
|
T20 |
8 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
34526 |
1 |
|
|
T34 |
12 |
|
T36 |
1 |
|
T21 |
14 |
higher_val |
higher_val |
auto[1] |
18217 |
1 |
|
|
T2 |
8 |
|
T3 |
44 |
|
T20 |
1 |
higher_val |
lower_val |
auto[0] |
34657 |
1 |
|
|
T34 |
8 |
|
T21 |
14 |
|
T7 |
21 |
higher_val |
lower_val |
auto[1] |
18335 |
1 |
|
|
T2 |
6 |
|
T3 |
57 |
|
T20 |
4 |
higher_val |
zero_val |
auto[0] |
85 |
1 |
|
|
T11 |
1 |
|
T37 |
1 |
|
T12 |
1 |
higher_val |
zero_val |
auto[1] |
36438 |
1 |
|
|
T2 |
11 |
|
T3 |
86 |
|
T20 |
3 |
lower_val |
higher_val |
auto[0] |
33728 |
1 |
|
|
T34 |
6 |
|
T21 |
8 |
|
T7 |
15 |
lower_val |
higher_val |
auto[1] |
17794 |
1 |
|
|
T2 |
10 |
|
T3 |
45 |
|
T20 |
1 |
lower_val |
lower_val |
auto[0] |
34219 |
1 |
|
|
T1 |
1 |
|
T34 |
6 |
|
T21 |
14 |
lower_val |
lower_val |
auto[1] |
17997 |
1 |
|
|
T2 |
9 |
|
T3 |
62 |
|
T20 |
1 |
lower_val |
zero_val |
auto[0] |
68 |
1 |
|
|
T95 |
1 |
|
T96 |
1 |
|
T198 |
1 |
lower_val |
zero_val |
auto[1] |
35787 |
1 |
|
|
T2 |
15 |
|
T3 |
101 |
|
T20 |
2 |
zero_val |
higher_val |
auto[0] |
513 |
1 |
|
|
T34 |
1 |
|
T36 |
1 |
|
T8 |
1 |
zero_val |
higher_val |
auto[1] |
129 |
1 |
|
|
T96 |
1 |
|
T43 |
3 |
|
T199 |
1 |
zero_val |
lower_val |
auto[0] |
467 |
1 |
|
|
T1 |
1 |
|
T21 |
1 |
|
T7 |
1 |
zero_val |
lower_val |
auto[1] |
96 |
1 |
|
|
T96 |
2 |
|
T198 |
2 |
|
T200 |
1 |
zero_val |
zero_val |
auto[0] |
240 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T20 |
1 |
zero_val |
zero_val |
auto[1] |
154 |
1 |
|
|
T96 |
1 |
|
T200 |
1 |
|
T24 |
1 |