Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	8306	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	7723	1			T3	17		T34	7		T40	10
len_5001_7500	12602	1			T3	17		T34	16		T36	33
len_2501_5000	8239	1			T3	17		T34	6		T36	34
len_1025_2500	4829	1			T3	10		T34	1		T36	20
len_769_1024	5923	1			T2	17		T3	2		T36	4
len_513_768	6198	1			T2	15		T3	2		T36	3
len_257_512	15396	1			T2	23		T3	2		T36	4
len_0_256	206806	1			T2	11		T3	290		T20	9
len_keccak_block_sizes[72]	642	1			T3	2		T36	2		T21	1
len_keccak_block_sizes[104]	547	1			T3	2		T41	2		T42	3
len_keccak_block_sizes[136]	440	1			T3	2		T41	2		T42	3
len_keccak_block_sizes[144]	342	1			T3	2		T41	2		T42	3
len_keccak_block_sizes[168]	240	1			T42	3		T96	3		T46	1
len_1	682	1			T3	2		T36	2		T41	2
len_0	1068	1			T3	2		T34	4		T36	2