Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	83728088	1			T1	4		T2	10693		T3	221808
all_pins[1]	83728088	1			T1	4		T2	10693		T3	221808
all_pins[2]	83728088	1			T1	4		T2	10693		T3	221808

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	250512645	1			T1	12		T2	31990		T3	664845
values[0x1]	671619	1			T2	89		T3	579		T20	13
transitions[0x0=>0x1]	669877	1			T2	89		T3	579		T20	13
transitions[0x1=>0x0]	669901	1			T2	89		T3	579		T20	13

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	83315694	1			T1	4		T2	10604		T3	221229
all_pins[0]	values[0x1]	412394	1			T2	89		T3	579		T20	13
all_pins[0]	transitions[0x0=>0x1]	412378	1			T2	89		T3	579		T20	13
all_pins[0]	transitions[0x1=>0x0]	5443	1			T21	31		T40	27		T45	4
all_pins[1]	values[0x0]	83722629	1			T1	4		T2	10693		T3	221808
all_pins[1]	values[0x1]	5459	1			T21	31		T40	27		T45	4
all_pins[1]	transitions[0x0=>0x1]	5253	1			T21	31		T40	27		T45	4
all_pins[1]	transitions[0x1=>0x0]	253560	1			T46	519		T22	100		T23	593
all_pins[2]	values[0x0]	83474322	1			T1	4		T2	10693		T3	221808
all_pins[2]	values[0x1]	253766	1			T46	519		T22	100		T23	593
all_pins[2]	transitions[0x0=>0x1]	252246	1			T46	519		T22	100		T23	593
all_pins[2]	transitions[0x1=>0x0]	410898	1			T2	89		T3	579		T20	13