Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	565	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	4976	1			T2	10		T34	4		T21	10
len_601_800	11345	1			T2	30		T34	17		T21	15
len_401_600	7514	1			T2	10		T34	8		T21	19
len_201_400	14856	1			T2	8		T34	7		T21	5
len_65_200	55648	1			T2	2		T34	2		T21	3
len_min_for_xof_require_squeeze	757	1			T40	1		T42	10		T96	10
len_keccak_block_sizes[72]	533	1			T42	5		T96	5		T200	5
len_keccak_block_sizes[104]	530	1			T42	5		T96	5		T200	5
len_keccak_block_sizes[136]	543	1			T42	5		T70	1		T96	5
len_keccak_block_sizes[144]	250	1			T42	5		T96	5		T200	5
len_keccak_block_sizes[168]	250	1			T40	1		T42	5		T96	5
len_datapath_width	13810	1			T20	3		T36	246		T7	1
len_2_63	172094	1			T2	4		T3	390		T20	6
len_1	49	1			T201	1		T14	2		T65	1