Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9339795 |
1 |
|
|
T2 |
11260 |
|
T3 |
2730 |
|
T20 |
96 |
auto[1] |
9339731 |
1 |
|
|
T2 |
11260 |
|
T3 |
2730 |
|
T20 |
96 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
18491008 |
1 |
|
|
T2 |
22432 |
|
T3 |
5460 |
|
T20 |
192 |
triple_byte_access |
62586 |
1 |
|
|
T2 |
24 |
|
T34 |
20 |
|
T21 |
32 |
halfword_access |
63256 |
1 |
|
|
T2 |
30 |
|
T34 |
20 |
|
T21 |
16 |
byte_access |
62676 |
1 |
|
|
T2 |
34 |
|
T34 |
14 |
|
T21 |
28 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
9245536 |
1 |
|
|
T2 |
11216 |
|
T3 |
2730 |
|
T20 |
96 |
auto[0] |
triple_byte_access |
31293 |
1 |
|
|
T2 |
12 |
|
T34 |
10 |
|
T21 |
16 |
auto[0] |
halfword_access |
31628 |
1 |
|
|
T2 |
15 |
|
T34 |
10 |
|
T21 |
8 |
auto[0] |
byte_access |
31338 |
1 |
|
|
T2 |
17 |
|
T34 |
7 |
|
T21 |
14 |
auto[1] |
word_access |
9245472 |
1 |
|
|
T2 |
11216 |
|
T3 |
2730 |
|
T20 |
96 |
auto[1] |
triple_byte_access |
31293 |
1 |
|
|
T2 |
12 |
|
T34 |
10 |
|
T21 |
16 |
auto[1] |
halfword_access |
31628 |
1 |
|
|
T2 |
15 |
|
T34 |
10 |
|
T21 |
8 |
auto[1] |
byte_access |
31338 |
1 |
|
|
T2 |
17 |
|
T34 |
7 |
|
T21 |
14 |