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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.51 97.89 92.65 99.89 78.87 95.53 98.89 97.88


Total test records in report: 1208
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T99 /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.3279891892 Aug 10 05:29:38 PM PDT 24 Aug 10 05:29:41 PM PDT 24 172318716 ps
T133 /workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.2562682466 Aug 10 05:29:47 PM PDT 24 Aug 10 05:29:49 PM PDT 24 52115854 ps
T197 /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.3618134296 Aug 10 05:29:39 PM PDT 24 Aug 10 05:29:44 PM PDT 24 220147368 ps
T1056 /workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.3018049959 Aug 10 05:29:32 PM PDT 24 Aug 10 05:29:34 PM PDT 24 190745955 ps
T182 /workspace/coverage/cover_reg_top/9.kmac_intr_test.675312322 Aug 10 05:29:48 PM PDT 24 Aug 10 05:29:49 PM PDT 24 13988943 ps
T171 /workspace/coverage/cover_reg_top/38.kmac_intr_test.2284132635 Aug 10 05:30:03 PM PDT 24 Aug 10 05:30:04 PM PDT 24 35092222 ps
T1057 /workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.768612401 Aug 10 05:29:37 PM PDT 24 Aug 10 05:29:38 PM PDT 24 56065285 ps
T154 /workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.1970324861 Aug 10 05:29:41 PM PDT 24 Aug 10 05:29:43 PM PDT 24 54057400 ps
T137 /workspace/coverage/cover_reg_top/18.kmac_tl_errors.3447536734 Aug 10 05:29:58 PM PDT 24 Aug 10 05:30:00 PM PDT 24 207484471 ps
T166 /workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.3827498658 Aug 10 05:29:38 PM PDT 24 Aug 10 05:29:40 PM PDT 24 191653931 ps
T146 /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.3203538765 Aug 10 05:30:01 PM PDT 24 Aug 10 05:30:04 PM PDT 24 272646286 ps
T183 /workspace/coverage/cover_reg_top/37.kmac_intr_test.1068341701 Aug 10 05:30:04 PM PDT 24 Aug 10 05:30:05 PM PDT 24 16125458 ps
T1058 /workspace/coverage/cover_reg_top/5.kmac_csr_rw.1891917680 Aug 10 05:29:40 PM PDT 24 Aug 10 05:29:42 PM PDT 24 46274426 ps
T167 /workspace/coverage/cover_reg_top/16.kmac_csr_rw.3691866871 Aug 10 05:30:01 PM PDT 24 Aug 10 05:30:03 PM PDT 24 33552567 ps
T168 /workspace/coverage/cover_reg_top/17.kmac_csr_rw.1794118768 Aug 10 05:29:55 PM PDT 24 Aug 10 05:29:56 PM PDT 24 22960105 ps
T172 /workspace/coverage/cover_reg_top/0.kmac_intr_test.578006480 Aug 10 05:29:32 PM PDT 24 Aug 10 05:29:33 PM PDT 24 49801589 ps
T173 /workspace/coverage/cover_reg_top/8.kmac_intr_test.2583254705 Aug 10 05:29:49 PM PDT 24 Aug 10 05:29:51 PM PDT 24 30741131 ps
T138 /workspace/coverage/cover_reg_top/2.kmac_tl_errors.3849929315 Aug 10 05:29:32 PM PDT 24 Aug 10 05:29:34 PM PDT 24 77158881 ps
T100 /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.3324798994 Aug 10 05:29:29 PM PDT 24 Aug 10 05:29:30 PM PDT 24 29796319 ps
T1059 /workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.638123461 Aug 10 05:29:43 PM PDT 24 Aug 10 05:29:44 PM PDT 24 68352870 ps
T135 /workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.675663880 Aug 10 05:29:31 PM PDT 24 Aug 10 05:29:35 PM PDT 24 211851756 ps
T1060 /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.3527089567 Aug 10 05:29:56 PM PDT 24 Aug 10 05:29:58 PM PDT 24 84832518 ps
T102 /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.2960634835 Aug 10 05:29:19 PM PDT 24 Aug 10 05:29:20 PM PDT 24 149555086 ps
T1061 /workspace/coverage/cover_reg_top/15.kmac_csr_rw.1333993113 Aug 10 05:29:57 PM PDT 24 Aug 10 05:29:58 PM PDT 24 16548913 ps
T112 /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.1774822097 Aug 10 05:29:52 PM PDT 24 Aug 10 05:29:54 PM PDT 24 31448765 ps
T1062 /workspace/coverage/cover_reg_top/8.kmac_csr_rw.2798923738 Aug 10 05:29:50 PM PDT 24 Aug 10 05:29:51 PM PDT 24 32094560 ps
T1063 /workspace/coverage/cover_reg_top/28.kmac_intr_test.2015882579 Aug 10 05:30:04 PM PDT 24 Aug 10 05:30:05 PM PDT 24 47172772 ps
T1064 /workspace/coverage/cover_reg_top/1.kmac_csr_rw.3730107470 Aug 10 05:29:32 PM PDT 24 Aug 10 05:29:33 PM PDT 24 73517086 ps
T113 /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.246652726 Aug 10 05:29:41 PM PDT 24 Aug 10 05:29:42 PM PDT 24 53672373 ps
T136 /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.3133476567 Aug 10 05:29:54 PM PDT 24 Aug 10 05:29:57 PM PDT 24 258875305 ps
T1065 /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.2898646475 Aug 10 05:29:58 PM PDT 24 Aug 10 05:29:59 PM PDT 24 42153795 ps
T169 /workspace/coverage/cover_reg_top/13.kmac_csr_rw.2113423447 Aug 10 05:29:48 PM PDT 24 Aug 10 05:29:50 PM PDT 24 114652348 ps
T147 /workspace/coverage/cover_reg_top/15.kmac_tl_errors.1546373016 Aug 10 05:30:02 PM PDT 24 Aug 10 05:30:04 PM PDT 24 290159383 ps
T156 /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.3341599104 Aug 10 05:29:37 PM PDT 24 Aug 10 05:29:39 PM PDT 24 35178692 ps
T1066 /workspace/coverage/cover_reg_top/4.kmac_intr_test.3048174730 Aug 10 05:29:44 PM PDT 24 Aug 10 05:29:45 PM PDT 24 37853524 ps
T157 /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.2357478702 Aug 10 05:29:29 PM PDT 24 Aug 10 05:29:31 PM PDT 24 74718884 ps
T148 /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.202225624 Aug 10 05:29:53 PM PDT 24 Aug 10 05:29:58 PM PDT 24 898350760 ps
T1067 /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.4061023194 Aug 10 05:29:29 PM PDT 24 Aug 10 05:29:38 PM PDT 24 580312508 ps
T139 /workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.3757628820 Aug 10 05:29:37 PM PDT 24 Aug 10 05:29:43 PM PDT 24 906733211 ps
T174 /workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.1306958854 Aug 10 05:29:59 PM PDT 24 Aug 10 05:30:01 PM PDT 24 100572267 ps
T1068 /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.4290654008 Aug 10 05:29:46 PM PDT 24 Aug 10 05:29:47 PM PDT 24 41909923 ps
T1069 /workspace/coverage/cover_reg_top/42.kmac_intr_test.3418925163 Aug 10 05:30:04 PM PDT 24 Aug 10 05:30:05 PM PDT 24 17247961 ps
T192 /workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.3206715239 Aug 10 05:29:48 PM PDT 24 Aug 10 05:29:51 PM PDT 24 389721585 ps
T170 /workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.560446710 Aug 10 05:29:59 PM PDT 24 Aug 10 05:30:01 PM PDT 24 72046807 ps
T134 /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.1992177810 Aug 10 05:29:39 PM PDT 24 Aug 10 05:29:40 PM PDT 24 60279434 ps
T175 /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.1825155046 Aug 10 05:29:48 PM PDT 24 Aug 10 05:29:50 PM PDT 24 72238762 ps
T144 /workspace/coverage/cover_reg_top/5.kmac_tl_errors.3931573361 Aug 10 05:29:39 PM PDT 24 Aug 10 05:29:41 PM PDT 24 137608142 ps
T1070 /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.3602713869 Aug 10 05:29:40 PM PDT 24 Aug 10 05:29:41 PM PDT 24 115806484 ps
T176 /workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.76166084 Aug 10 05:29:47 PM PDT 24 Aug 10 05:29:53 PM PDT 24 1977395074 ps
T1071 /workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.2830495156 Aug 10 05:29:41 PM PDT 24 Aug 10 05:29:42 PM PDT 24 80508715 ps
T189 /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.118934575 Aug 10 05:29:52 PM PDT 24 Aug 10 05:29:55 PM PDT 24 373204074 ps
T1072 /workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.1719206512 Aug 10 05:29:59 PM PDT 24 Aug 10 05:30:00 PM PDT 24 367004050 ps
T103 /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.1788998171 Aug 10 05:29:39 PM PDT 24 Aug 10 05:29:40 PM PDT 24 96635179 ps
T1073 /workspace/coverage/cover_reg_top/17.kmac_intr_test.3142126994 Aug 10 05:30:01 PM PDT 24 Aug 10 05:30:03 PM PDT 24 40926675 ps
T1074 /workspace/coverage/cover_reg_top/18.kmac_intr_test.3905519032 Aug 10 05:29:56 PM PDT 24 Aug 10 05:29:57 PM PDT 24 91213637 ps
T1075 /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.687307922 Aug 10 05:29:50 PM PDT 24 Aug 10 05:29:52 PM PDT 24 94760530 ps
T1076 /workspace/coverage/cover_reg_top/2.kmac_mem_walk.3131100480 Aug 10 05:29:30 PM PDT 24 Aug 10 05:29:31 PM PDT 24 46282175 ps
T1077 /workspace/coverage/cover_reg_top/26.kmac_intr_test.2847204136 Aug 10 05:30:04 PM PDT 24 Aug 10 05:30:05 PM PDT 24 17334057 ps
T1078 /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.1902391258 Aug 10 05:29:40 PM PDT 24 Aug 10 05:29:47 PM PDT 24 3645875441 ps
T1079 /workspace/coverage/cover_reg_top/9.kmac_csr_rw.481925757 Aug 10 05:29:49 PM PDT 24 Aug 10 05:29:50 PM PDT 24 35178960 ps
T158 /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.2470100887 Aug 10 05:29:30 PM PDT 24 Aug 10 05:29:31 PM PDT 24 64318261 ps
T140 /workspace/coverage/cover_reg_top/1.kmac_tl_errors.1557500983 Aug 10 05:29:32 PM PDT 24 Aug 10 05:29:36 PM PDT 24 50386197 ps
T1080 /workspace/coverage/cover_reg_top/19.kmac_tl_errors.2279443524 Aug 10 05:29:57 PM PDT 24 Aug 10 05:30:01 PM PDT 24 185901871 ps
T1081 /workspace/coverage/cover_reg_top/46.kmac_intr_test.2764152533 Aug 10 05:30:04 PM PDT 24 Aug 10 05:30:04 PM PDT 24 13687312 ps
T184 /workspace/coverage/cover_reg_top/4.kmac_tl_errors.178410104 Aug 10 05:29:41 PM PDT 24 Aug 10 05:29:45 PM PDT 24 962517531 ps
T108 /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.100372947 Aug 10 05:29:39 PM PDT 24 Aug 10 05:29:42 PM PDT 24 155983835 ps
T1082 /workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.3315318626 Aug 10 05:29:42 PM PDT 24 Aug 10 05:29:48 PM PDT 24 2350827665 ps
T1083 /workspace/coverage/cover_reg_top/36.kmac_intr_test.683852626 Aug 10 05:30:02 PM PDT 24 Aug 10 05:30:03 PM PDT 24 28416275 ps
T145 /workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.3001028822 Aug 10 05:29:38 PM PDT 24 Aug 10 05:29:41 PM PDT 24 145617142 ps
T1084 /workspace/coverage/cover_reg_top/13.kmac_tl_errors.3441521473 Aug 10 05:29:51 PM PDT 24 Aug 10 05:29:55 PM PDT 24 136869542 ps
T1085 /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.603586050 Aug 10 05:29:30 PM PDT 24 Aug 10 05:29:32 PM PDT 24 31711160 ps
T106 /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.320666940 Aug 10 05:29:39 PM PDT 24 Aug 10 05:29:42 PM PDT 24 1860368020 ps
T1086 /workspace/coverage/cover_reg_top/18.kmac_csr_rw.1972454556 Aug 10 05:29:56 PM PDT 24 Aug 10 05:29:57 PM PDT 24 22834246 ps
T1087 /workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.1871189819 Aug 10 05:29:38 PM PDT 24 Aug 10 05:29:49 PM PDT 24 774450289 ps
T1088 /workspace/coverage/cover_reg_top/23.kmac_intr_test.3800007735 Aug 10 05:30:01 PM PDT 24 Aug 10 05:30:02 PM PDT 24 24764531 ps
T1089 /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.1285078221 Aug 10 05:29:57 PM PDT 24 Aug 10 05:29:59 PM PDT 24 41676532 ps
T1090 /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.1066355252 Aug 10 05:29:31 PM PDT 24 Aug 10 05:29:43 PM PDT 24 3144825995 ps
T1091 /workspace/coverage/cover_reg_top/35.kmac_intr_test.2014605953 Aug 10 05:30:03 PM PDT 24 Aug 10 05:30:04 PM PDT 24 41279215 ps
T1092 /workspace/coverage/cover_reg_top/19.kmac_csr_rw.1428115582 Aug 10 05:29:56 PM PDT 24 Aug 10 05:29:57 PM PDT 24 45554443 ps
T159 /workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.3805174948 Aug 10 05:29:30 PM PDT 24 Aug 10 05:29:31 PM PDT 24 85895742 ps
T1093 /workspace/coverage/cover_reg_top/1.kmac_intr_test.1414846777 Aug 10 05:29:34 PM PDT 24 Aug 10 05:29:35 PM PDT 24 13504627 ps
T1094 /workspace/coverage/cover_reg_top/32.kmac_intr_test.4086598377 Aug 10 05:30:05 PM PDT 24 Aug 10 05:30:06 PM PDT 24 12791227 ps
T1095 /workspace/coverage/cover_reg_top/43.kmac_intr_test.3029911016 Aug 10 05:30:03 PM PDT 24 Aug 10 05:30:04 PM PDT 24 82293371 ps
T1096 /workspace/coverage/cover_reg_top/7.kmac_csr_rw.304281813 Aug 10 05:29:42 PM PDT 24 Aug 10 05:29:43 PM PDT 24 16643352 ps
T193 /workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.1559723769 Aug 10 05:29:39 PM PDT 24 Aug 10 05:29:42 PM PDT 24 144729664 ps
T1097 /workspace/coverage/cover_reg_top/10.kmac_tl_errors.4108884676 Aug 10 05:29:51 PM PDT 24 Aug 10 05:29:53 PM PDT 24 382434944 ps
T1098 /workspace/coverage/cover_reg_top/3.kmac_tl_errors.328410618 Aug 10 05:29:38 PM PDT 24 Aug 10 05:29:40 PM PDT 24 38000374 ps
T107 /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.491665031 Aug 10 05:29:50 PM PDT 24 Aug 10 05:29:53 PM PDT 24 104669893 ps
T1099 /workspace/coverage/cover_reg_top/12.kmac_tl_errors.4102427290 Aug 10 05:29:48 PM PDT 24 Aug 10 05:29:52 PM PDT 24 139210041 ps
T111 /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.2663768816 Aug 10 05:29:48 PM PDT 24 Aug 10 05:29:51 PM PDT 24 138014978 ps
T1100 /workspace/coverage/cover_reg_top/13.kmac_intr_test.4037387365 Aug 10 05:29:53 PM PDT 24 Aug 10 05:29:54 PM PDT 24 80949397 ps
T1101 /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.1161702316 Aug 10 05:29:50 PM PDT 24 Aug 10 05:29:54 PM PDT 24 2124119076 ps
T1102 /workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.3820550262 Aug 10 05:29:40 PM PDT 24 Aug 10 05:29:42 PM PDT 24 49316473 ps
T1103 /workspace/coverage/cover_reg_top/12.kmac_intr_test.361311715 Aug 10 05:29:49 PM PDT 24 Aug 10 05:29:50 PM PDT 24 35975209 ps
T1104 /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.1811410507 Aug 10 05:29:59 PM PDT 24 Aug 10 05:30:01 PM PDT 24 38077845 ps
T1105 /workspace/coverage/cover_reg_top/6.kmac_intr_test.215895195 Aug 10 05:29:41 PM PDT 24 Aug 10 05:29:42 PM PDT 24 36891796 ps
T1106 /workspace/coverage/cover_reg_top/7.kmac_intr_test.1168889669 Aug 10 05:29:44 PM PDT 24 Aug 10 05:29:45 PM PDT 24 31364931 ps
T1107 /workspace/coverage/cover_reg_top/4.kmac_mem_walk.2438168884 Aug 10 05:29:37 PM PDT 24 Aug 10 05:29:38 PM PDT 24 11653688 ps
T194 /workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.1516433061 Aug 10 05:29:38 PM PDT 24 Aug 10 05:29:44 PM PDT 24 972364106 ps
T1108 /workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.4198231325 Aug 10 05:29:40 PM PDT 24 Aug 10 05:29:42 PM PDT 24 322839020 ps
T195 /workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.1164056752 Aug 10 05:30:01 PM PDT 24 Aug 10 05:30:07 PM PDT 24 757715147 ps
T1109 /workspace/coverage/cover_reg_top/11.kmac_tl_errors.2279505594 Aug 10 05:29:50 PM PDT 24 Aug 10 05:29:54 PM PDT 24 58351105 ps
T1110 /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.3721276684 Aug 10 05:29:48 PM PDT 24 Aug 10 05:29:49 PM PDT 24 91731186 ps
T1111 /workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.4259740729 Aug 10 05:29:40 PM PDT 24 Aug 10 05:29:41 PM PDT 24 46181167 ps
T1112 /workspace/coverage/cover_reg_top/1.kmac_mem_walk.2298175575 Aug 10 05:29:30 PM PDT 24 Aug 10 05:29:31 PM PDT 24 40020840 ps
T1113 /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.986309590 Aug 10 05:29:37 PM PDT 24 Aug 10 05:29:39 PM PDT 24 23228036 ps
T191 /workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.4279777533 Aug 10 05:29:46 PM PDT 24 Aug 10 05:29:48 PM PDT 24 198577889 ps
T1114 /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.3712392581 Aug 10 05:29:48 PM PDT 24 Aug 10 05:29:51 PM PDT 24 108925921 ps
T1115 /workspace/coverage/cover_reg_top/49.kmac_intr_test.1978897969 Aug 10 05:30:15 PM PDT 24 Aug 10 05:30:16 PM PDT 24 45598984 ps
T1116 /workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.3232651850 Aug 10 05:29:30 PM PDT 24 Aug 10 05:29:49 PM PDT 24 1100628863 ps
T1117 /workspace/coverage/cover_reg_top/16.kmac_tl_errors.233223741 Aug 10 05:29:59 PM PDT 24 Aug 10 05:30:03 PM PDT 24 204201744 ps
T1118 /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.2173693346 Aug 10 05:29:37 PM PDT 24 Aug 10 05:29:39 PM PDT 24 89827225 ps
T1119 /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.3048755918 Aug 10 05:29:59 PM PDT 24 Aug 10 05:30:01 PM PDT 24 165142906 ps
T1120 /workspace/coverage/cover_reg_top/3.kmac_csr_rw.2438344962 Aug 10 05:29:40 PM PDT 24 Aug 10 05:29:41 PM PDT 24 83816820 ps
T1121 /workspace/coverage/cover_reg_top/39.kmac_intr_test.1405369315 Aug 10 05:30:03 PM PDT 24 Aug 10 05:30:04 PM PDT 24 14703392 ps
T1122 /workspace/coverage/cover_reg_top/14.kmac_intr_test.1120260945 Aug 10 05:29:49 PM PDT 24 Aug 10 05:29:51 PM PDT 24 41225999 ps
T1123 /workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.3536319835 Aug 10 05:29:42 PM PDT 24 Aug 10 05:29:45 PM PDT 24 251826700 ps
T1124 /workspace/coverage/cover_reg_top/11.kmac_csr_rw.712963210 Aug 10 05:29:51 PM PDT 24 Aug 10 05:29:53 PM PDT 24 23002557 ps
T1125 /workspace/coverage/cover_reg_top/34.kmac_intr_test.2224997113 Aug 10 05:30:03 PM PDT 24 Aug 10 05:30:03 PM PDT 24 34022964 ps
T1126 /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.180056630 Aug 10 05:29:53 PM PDT 24 Aug 10 05:29:55 PM PDT 24 158609713 ps
T1127 /workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.212484921 Aug 10 05:29:36 PM PDT 24 Aug 10 05:29:41 PM PDT 24 89172781 ps
T1128 /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.2490132108 Aug 10 05:29:56 PM PDT 24 Aug 10 05:29:58 PM PDT 24 68684498 ps
T1129 /workspace/coverage/cover_reg_top/7.kmac_tl_errors.2680456770 Aug 10 05:29:39 PM PDT 24 Aug 10 05:29:42 PM PDT 24 223921451 ps
T1130 /workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.3188802096 Aug 10 05:29:39 PM PDT 24 Aug 10 05:29:41 PM PDT 24 326326658 ps
T1131 /workspace/coverage/cover_reg_top/31.kmac_intr_test.3784310669 Aug 10 05:30:05 PM PDT 24 Aug 10 05:30:06 PM PDT 24 16208441 ps
T110 /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.3772597755 Aug 10 05:29:54 PM PDT 24 Aug 10 05:29:57 PM PDT 24 136842448 ps
T1132 /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.2124793749 Aug 10 05:29:30 PM PDT 24 Aug 10 05:29:32 PM PDT 24 156551708 ps
T1133 /workspace/coverage/cover_reg_top/45.kmac_intr_test.1619597213 Aug 10 05:30:03 PM PDT 24 Aug 10 05:30:04 PM PDT 24 29460128 ps
T1134 /workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.2445920634 Aug 10 05:29:47 PM PDT 24 Aug 10 05:29:49 PM PDT 24 25397876 ps
T1135 /workspace/coverage/cover_reg_top/24.kmac_intr_test.3517236651 Aug 10 05:30:06 PM PDT 24 Aug 10 05:30:07 PM PDT 24 39646848 ps
T1136 /workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.1262980639 Aug 10 05:29:42 PM PDT 24 Aug 10 05:29:44 PM PDT 24 36522423 ps
T1137 /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.3125995212 Aug 10 05:29:46 PM PDT 24 Aug 10 05:29:49 PM PDT 24 249200111 ps
T1138 /workspace/coverage/cover_reg_top/6.kmac_tl_errors.569276423 Aug 10 05:29:41 PM PDT 24 Aug 10 05:29:44 PM PDT 24 413531458 ps
T1139 /workspace/coverage/cover_reg_top/6.kmac_csr_rw.129374996 Aug 10 05:29:40 PM PDT 24 Aug 10 05:29:41 PM PDT 24 100890093 ps
T1140 /workspace/coverage/cover_reg_top/30.kmac_intr_test.1708638125 Aug 10 05:30:06 PM PDT 24 Aug 10 05:30:07 PM PDT 24 25782269 ps
T1141 /workspace/coverage/cover_reg_top/3.kmac_intr_test.976286086 Aug 10 05:29:43 PM PDT 24 Aug 10 05:29:44 PM PDT 24 80519912 ps
T1142 /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.4080042902 Aug 10 05:29:36 PM PDT 24 Aug 10 05:29:37 PM PDT 24 30470368 ps
T1143 /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.1912701597 Aug 10 05:29:39 PM PDT 24 Aug 10 05:29:41 PM PDT 24 60226644 ps
T190 /workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.868018335 Aug 10 05:29:31 PM PDT 24 Aug 10 05:29:34 PM PDT 24 207028071 ps
T1144 /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.597825008 Aug 10 05:29:44 PM PDT 24 Aug 10 05:29:47 PM PDT 24 171247685 ps
T104 /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.477382132 Aug 10 05:29:56 PM PDT 24 Aug 10 05:29:59 PM PDT 24 178151295 ps
T1145 /workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.2086173531 Aug 10 05:29:49 PM PDT 24 Aug 10 05:29:52 PM PDT 24 133270802 ps
T1146 /workspace/coverage/cover_reg_top/19.kmac_intr_test.2815079188 Aug 10 05:29:55 PM PDT 24 Aug 10 05:29:56 PM PDT 24 24277482 ps
T1147 /workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.3639027385 Aug 10 05:29:40 PM PDT 24 Aug 10 05:29:42 PM PDT 24 146291413 ps
T1148 /workspace/coverage/cover_reg_top/44.kmac_intr_test.1430851587 Aug 10 05:30:02 PM PDT 24 Aug 10 05:30:03 PM PDT 24 16235471 ps
T1149 /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.94684829 Aug 10 05:29:31 PM PDT 24 Aug 10 05:29:32 PM PDT 24 56209892 ps
T1150 /workspace/coverage/cover_reg_top/4.kmac_csr_rw.1175845491 Aug 10 05:29:41 PM PDT 24 Aug 10 05:29:42 PM PDT 24 39964784 ps
T1151 /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.1409516059 Aug 10 05:29:50 PM PDT 24 Aug 10 05:29:53 PM PDT 24 1137013090 ps
T1152 /workspace/coverage/cover_reg_top/0.kmac_tl_errors.3514200924 Aug 10 05:29:31 PM PDT 24 Aug 10 05:29:35 PM PDT 24 212360240 ps
T1153 /workspace/coverage/cover_reg_top/25.kmac_intr_test.676742381 Aug 10 05:30:04 PM PDT 24 Aug 10 05:30:05 PM PDT 24 80749476 ps
T1154 /workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.2301047098 Aug 10 05:29:29 PM PDT 24 Aug 10 05:29:31 PM PDT 24 381036425 ps
T1155 /workspace/coverage/cover_reg_top/21.kmac_intr_test.2525498592 Aug 10 05:30:02 PM PDT 24 Aug 10 05:30:03 PM PDT 24 36629763 ps
T1156 /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.4467983 Aug 10 05:29:40 PM PDT 24 Aug 10 05:29:43 PM PDT 24 36372615 ps
T1157 /workspace/coverage/cover_reg_top/11.kmac_intr_test.417274201 Aug 10 05:29:47 PM PDT 24 Aug 10 05:29:48 PM PDT 24 38084704 ps
T1158 /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.2603510743 Aug 10 05:29:49 PM PDT 24 Aug 10 05:29:50 PM PDT 24 52357208 ps
T1159 /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.2924879589 Aug 10 05:29:56 PM PDT 24 Aug 10 05:29:58 PM PDT 24 49137489 ps
T1160 /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.2332615303 Aug 10 05:29:58 PM PDT 24 Aug 10 05:29:59 PM PDT 24 81683963 ps
T1161 /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.845735868 Aug 10 05:29:59 PM PDT 24 Aug 10 05:30:02 PM PDT 24 174432845 ps
T1162 /workspace/coverage/cover_reg_top/9.kmac_tl_errors.3254183170 Aug 10 05:29:52 PM PDT 24 Aug 10 05:29:56 PM PDT 24 555487181 ps
T1163 /workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.3694685194 Aug 10 05:29:59 PM PDT 24 Aug 10 05:30:01 PM PDT 24 390711930 ps
T1164 /workspace/coverage/cover_reg_top/17.kmac_tl_errors.1611156117 Aug 10 05:29:57 PM PDT 24 Aug 10 05:29:59 PM PDT 24 42055666 ps
T109 /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.570062406 Aug 10 05:29:40 PM PDT 24 Aug 10 05:29:41 PM PDT 24 216952258 ps
T1165 /workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.1459068042 Aug 10 05:29:41 PM PDT 24 Aug 10 05:29:43 PM PDT 24 61920603 ps
T1166 /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.1855643231 Aug 10 05:29:47 PM PDT 24 Aug 10 05:29:48 PM PDT 24 76530423 ps
T188 /workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.1036517999 Aug 10 05:30:01 PM PDT 24 Aug 10 05:30:05 PM PDT 24 472121620 ps
T1167 /workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.1410118773 Aug 10 05:29:33 PM PDT 24 Aug 10 05:29:35 PM PDT 24 62162397 ps
T1168 /workspace/coverage/cover_reg_top/33.kmac_intr_test.4187070894 Aug 10 05:30:02 PM PDT 24 Aug 10 05:30:03 PM PDT 24 18444272 ps
T1169 /workspace/coverage/cover_reg_top/10.kmac_csr_rw.2277163801 Aug 10 05:29:51 PM PDT 24 Aug 10 05:29:53 PM PDT 24 56216793 ps
T1170 /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.676201040 Aug 10 05:29:57 PM PDT 24 Aug 10 05:29:59 PM PDT 24 48056177 ps
T1171 /workspace/coverage/cover_reg_top/27.kmac_intr_test.1006557402 Aug 10 05:30:02 PM PDT 24 Aug 10 05:30:03 PM PDT 24 222141657 ps
T1172 /workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.3435972256 Aug 10 05:29:52 PM PDT 24 Aug 10 05:29:55 PM PDT 24 36772979 ps
T1173 /workspace/coverage/cover_reg_top/0.kmac_mem_walk.1346790078 Aug 10 05:29:31 PM PDT 24 Aug 10 05:29:32 PM PDT 24 12427408 ps
T1174 /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.476797844 Aug 10 05:29:48 PM PDT 24 Aug 10 05:29:50 PM PDT 24 1166709969 ps
T1175 /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.1551366422 Aug 10 05:29:37 PM PDT 24 Aug 10 05:29:47 PM PDT 24 1957074185 ps
T1176 /workspace/coverage/cover_reg_top/5.kmac_intr_test.611269538 Aug 10 05:29:37 PM PDT 24 Aug 10 05:29:38 PM PDT 24 40837837 ps
T1177 /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.89840983 Aug 10 05:29:56 PM PDT 24 Aug 10 05:29:57 PM PDT 24 73695191 ps
T1178 /workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.391177714 Aug 10 05:29:37 PM PDT 24 Aug 10 05:29:38 PM PDT 24 21455184 ps
T1179 /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.1266293290 Aug 10 05:29:49 PM PDT 24 Aug 10 05:29:51 PM PDT 24 97468944 ps
T105 /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.3847879234 Aug 10 05:29:47 PM PDT 24 Aug 10 05:29:50 PM PDT 24 52879327 ps
T1180 /workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.3934597638 Aug 10 05:29:40 PM PDT 24 Aug 10 05:29:50 PM PDT 24 459180664 ps
T1181 /workspace/coverage/cover_reg_top/41.kmac_intr_test.4037198218 Aug 10 05:30:05 PM PDT 24 Aug 10 05:30:06 PM PDT 24 13989483 ps
T1182 /workspace/coverage/cover_reg_top/2.kmac_intr_test.849298789 Aug 10 05:29:32 PM PDT 24 Aug 10 05:29:33 PM PDT 24 41400220 ps
T1183 /workspace/coverage/cover_reg_top/47.kmac_intr_test.131221543 Aug 10 05:30:12 PM PDT 24 Aug 10 05:30:12 PM PDT 24 44845551 ps
T1184 /workspace/coverage/cover_reg_top/0.kmac_csr_rw.2564422881 Aug 10 05:29:34 PM PDT 24 Aug 10 05:29:35 PM PDT 24 23051681 ps
T1185 /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.2757424177 Aug 10 05:29:55 PM PDT 24 Aug 10 05:29:59 PM PDT 24 204404628 ps
T1186 /workspace/coverage/cover_reg_top/10.kmac_intr_test.2287872715 Aug 10 05:29:51 PM PDT 24 Aug 10 05:29:52 PM PDT 24 70490811 ps
T1187 /workspace/coverage/cover_reg_top/8.kmac_tl_errors.2210215912 Aug 10 05:29:43 PM PDT 24 Aug 10 05:29:47 PM PDT 24 805365968 ps
T1188 /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.3622503447 Aug 10 05:29:31 PM PDT 24 Aug 10 05:29:33 PM PDT 24 90720179 ps
T1189 /workspace/coverage/cover_reg_top/20.kmac_intr_test.3387827079 Aug 10 05:29:54 PM PDT 24 Aug 10 05:29:55 PM PDT 24 72701671 ps
T1190 /workspace/coverage/cover_reg_top/14.kmac_tl_errors.2219446698 Aug 10 05:29:48 PM PDT 24 Aug 10 05:29:49 PM PDT 24 39173467 ps
T1191 /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.3343279808 Aug 10 05:29:47 PM PDT 24 Aug 10 05:29:49 PM PDT 24 152870928 ps
T1192 /workspace/coverage/cover_reg_top/3.kmac_mem_walk.923072117 Aug 10 05:29:38 PM PDT 24 Aug 10 05:29:39 PM PDT 24 18943046 ps
T1193 /workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.2029195309 Aug 10 05:29:41 PM PDT 24 Aug 10 05:29:43 PM PDT 24 305153363 ps
T1194 /workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.74830960 Aug 10 05:29:50 PM PDT 24 Aug 10 05:29:52 PM PDT 24 73582091 ps
T1195 /workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.1422054889 Aug 10 05:29:30 PM PDT 24 Aug 10 05:29:33 PM PDT 24 268211199 ps
T1196 /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.3157183490 Aug 10 05:29:48 PM PDT 24 Aug 10 05:29:50 PM PDT 24 182585673 ps
T1197 /workspace/coverage/cover_reg_top/15.kmac_intr_test.130059162 Aug 10 05:30:02 PM PDT 24 Aug 10 05:30:03 PM PDT 24 49874995 ps
T1198 /workspace/coverage/cover_reg_top/40.kmac_intr_test.2685333438 Aug 10 05:30:04 PM PDT 24 Aug 10 05:30:04 PM PDT 24 29394686 ps
T1199 /workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.2648104655 Aug 10 05:29:57 PM PDT 24 Aug 10 05:29:59 PM PDT 24 62605346 ps
T1200 /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.3258254206 Aug 10 05:29:49 PM PDT 24 Aug 10 05:29:52 PM PDT 24 29923630 ps
T1201 /workspace/coverage/cover_reg_top/12.kmac_csr_rw.3529689143 Aug 10 05:29:47 PM PDT 24 Aug 10 05:29:48 PM PDT 24 71146671 ps
T1202 /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.24299502 Aug 10 05:29:55 PM PDT 24 Aug 10 05:29:58 PM PDT 24 68228171 ps
T1203 /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.1878736247 Aug 10 05:29:55 PM PDT 24 Aug 10 05:29:56 PM PDT 24 26569872 ps
T1204 /workspace/coverage/cover_reg_top/14.kmac_csr_rw.3001496869 Aug 10 05:29:52 PM PDT 24 Aug 10 05:29:53 PM PDT 24 58768392 ps
T1205 /workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.3189911230 Aug 10 05:29:52 PM PDT 24 Aug 10 05:29:54 PM PDT 24 58915444 ps
T1206 /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.1601378963 Aug 10 05:29:55 PM PDT 24 Aug 10 05:29:56 PM PDT 24 107772963 ps
T1207 /workspace/coverage/cover_reg_top/16.kmac_intr_test.1328939582 Aug 10 05:30:01 PM PDT 24 Aug 10 05:30:02 PM PDT 24 32535453 ps
T1208 /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.3802747609 Aug 10 05:29:31 PM PDT 24 Aug 10 05:29:41 PM PDT 24 7497889706 ps

Test location /workspace/coverage/default/38.kmac_entropy_refresh.3708919734
Short name T7
Test name
Test status
Simulation time 12778883830 ps
CPU time 145.23 seconds
Started Aug 10 06:50:06 PM PDT 24
Finished Aug 10 06:52:31 PM PDT 24
Peak memory 335464 kb
Host smart-4c4f9cd8-f316-4496-86d3-468e53cbe806
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708919734 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.3
708919734 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_entropy_refresh/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.1452527853
Short name T101
Test name
Test status
Simulation time 708711569 ps
CPU time 5.03 seconds
Started Aug 10 05:30:02 PM PDT 24
Finished Aug 10 05:30:07 PM PDT 24
Peak memory 216588 kb
Host smart-5c03c572-dfe1-43ba-b934-5a9b3232789b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452527853 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.1452
527853 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/12.kmac_lc_escalation.969048937
Short name T12
Test name
Test status
Simulation time 152677672 ps
CPU time 1.25 seconds
Started Aug 10 06:33:53 PM PDT 24
Finished Aug 10 06:33:54 PM PDT 24
Peak memory 226972 kb
Host smart-7c8703ae-0d32-4331-ba69-caaf5ec6afba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969048937 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.969048937 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/12.kmac_lc_escalation/latest

Test location /workspace/coverage/default/2.kmac_stress_all_with_rand_reset.2451938530
Short name T15
Test name
Test status
Simulation time 46753849175 ps
CPU time 833.13 seconds
Started Aug 10 06:29:36 PM PDT 24
Finished Aug 10 06:43:29 PM PDT 24
Peak memory 402752 kb
Host smart-56c26d5a-b4c2-4bb3-b310-faa2d1ad677e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2451938530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all_with_rand_reset.2451938530 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.kmac_error.4057823871
Short name T22
Test name
Test status
Simulation time 1771369655 ps
CPU time 46.32 seconds
Started Aug 10 06:53:01 PM PDT 24
Finished Aug 10 06:53:47 PM PDT 24
Peak memory 251620 kb
Host smart-3d9ee5d9-f9ae-4492-ba21-a8e1e52357af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057823871 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.4057823871 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_error/latest

Test location /workspace/coverage/default/1.kmac_sec_cm.484687996
Short name T30
Test name
Test status
Simulation time 8370700909 ps
CPU time 101.1 seconds
Started Aug 10 06:29:13 PM PDT 24
Finished Aug 10 06:30:54 PM PDT 24
Peak memory 283008 kb
Host smart-c43dc393-26b7-4743-ae17-ef70595a5183
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484687996 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.484687996 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/1.kmac_sec_cm/latest

Test location /workspace/coverage/default/28.kmac_key_error.3324242855
Short name T13
Test name
Test status
Simulation time 4451789686 ps
CPU time 9.78 seconds
Started Aug 10 06:43:33 PM PDT 24
Finished Aug 10 06:43:43 PM PDT 24
Peak memory 226820 kb
Host smart-7eb67c00-0ae0-46a3-8b07-2b4f55edde06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324242855 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.3324242855 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_key_error/latest

Test location /workspace/coverage/default/33.kmac_lc_escalation.1201834373
Short name T49
Test name
Test status
Simulation time 111775045 ps
CPU time 1.64 seconds
Started Aug 10 06:47:06 PM PDT 24
Finished Aug 10 06:47:08 PM PDT 24
Peak memory 226904 kb
Host smart-aff051f8-1d2e-41a3-b0bb-0f3c978b0496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201834373 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.1201834373 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/33.kmac_lc_escalation/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_shake_256.1062818993
Short name T96
Test name
Test status
Simulation time 124903278800 ps
CPU time 4942.51 seconds
Started Aug 10 06:34:39 PM PDT 24
Finished Aug 10 07:57:02 PM PDT 24
Peak memory 2211144 kb
Host smart-94ac0a57-d597-4317-9573-548d6cb33c34
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1062818993 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_256.1062818993 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.320666940
Short name T106
Test name
Test status
Simulation time 1860368020 ps
CPU time 3.23 seconds
Started Aug 10 05:29:39 PM PDT 24
Finished Aug 10 05:29:42 PM PDT 24
Peak memory 218960 kb
Host smart-97fe0f47-696c-4223-8955-ce1aff2c5f5b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320666940 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_
shadow_reg_errors_with_csr_rw.320666940 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.kmac_entropy_ready_error.2227137102
Short name T5
Test name
Test status
Simulation time 8187131351 ps
CPU time 20.73 seconds
Started Aug 10 06:28:45 PM PDT 24
Finished Aug 10 06:29:06 PM PDT 24
Peak memory 220496 kb
Host smart-eda79643-d73d-43e8-a611-3194242b858d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227137102 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.2227137102 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_ready_error/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_intr_test.578006480
Short name T172
Test name
Test status
Simulation time 49801589 ps
CPU time 0.79 seconds
Started Aug 10 05:29:32 PM PDT 24
Finished Aug 10 05:29:33 PM PDT 24
Peak memory 216348 kb
Host smart-b288c537-fd05-4f18-abb1-96f8fc32d99d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578006480 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.578006480 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/0.kmac_intr_test/latest

Test location /workspace/coverage/default/0.kmac_edn_timeout_error.2661669318
Short name T60
Test name
Test status
Simulation time 41004325 ps
CPU time 1.16 seconds
Started Aug 10 06:28:46 PM PDT 24
Finished Aug 10 06:28:47 PM PDT 24
Peak memory 218724 kb
Host smart-ba203f2c-46f1-49de-a52e-fa53ec47f84c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2661669318 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.2661669318 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/29.kmac_lc_escalation.887340036
Short name T72
Test name
Test status
Simulation time 1006513946 ps
CPU time 26.43 seconds
Started Aug 10 06:44:18 PM PDT 24
Finished Aug 10 06:44:44 PM PDT 24
Peak memory 240632 kb
Host smart-71100d9f-f509-4387-97f0-c0ed8a48368d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887340036 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.887340036 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/29.kmac_lc_escalation/latest

Test location /workspace/coverage/default/25.kmac_error.1287888656
Short name T24
Test name
Test status
Simulation time 11776891194 ps
CPU time 501.49 seconds
Started Aug 10 06:41:14 PM PDT 24
Finished Aug 10 06:49:36 PM PDT 24
Peak memory 393468 kb
Host smart-d8f3308d-1b3c-42d8-a0f0-691e6e2a12fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287888656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_error.1287888656 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_error/latest

Test location /workspace/coverage/default/10.kmac_entropy_mode_error.2616879640
Short name T66
Test name
Test status
Simulation time 62326584 ps
CPU time 1.14 seconds
Started Aug 10 06:33:06 PM PDT 24
Finished Aug 10 06:33:07 PM PDT 24
Peak memory 218688 kb
Host smart-51b1e9e7-809f-4112-aa9a-feb935c915dc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2616879640 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.2616879640 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/49.kmac_stress_all.2210384896
Short name T65
Test name
Test status
Simulation time 10507705571 ps
CPU time 917.01 seconds
Started Aug 10 06:57:10 PM PDT 24
Finished Aug 10 07:12:27 PM PDT 24
Peak memory 600484 kb
Host smart-2ca26010-ae3c-4c81-bc1d-8431c95f326e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2210384896 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.2210384896 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_stress_all/latest

Test location /workspace/coverage/default/11.kmac_lc_escalation.2722880784
Short name T290
Test name
Test status
Simulation time 75052607 ps
CPU time 1.67 seconds
Started Aug 10 06:33:24 PM PDT 24
Finished Aug 10 06:33:26 PM PDT 24
Peak memory 226840 kb
Host smart-6fd7d6da-4b13-44ff-a546-cfeee9b051b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722880784 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.2722880784 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/11.kmac_lc_escalation/latest

Test location /workspace/coverage/default/6.kmac_lc_escalation.3705022223
Short name T47
Test name
Test status
Simulation time 47423838 ps
CPU time 1.38 seconds
Started Aug 10 06:31:25 PM PDT 24
Finished Aug 10 06:31:27 PM PDT 24
Peak memory 226928 kb
Host smart-d0dbdaf0-7c11-4233-8799-160d23143346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705022223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.3705022223 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/6.kmac_lc_escalation/latest

Test location /workspace/coverage/default/38.kmac_lc_escalation.3011007165
Short name T54
Test name
Test status
Simulation time 1017845950 ps
CPU time 32.84 seconds
Started Aug 10 06:50:17 PM PDT 24
Finished Aug 10 06:50:50 PM PDT 24
Peak memory 243632 kb
Host smart-dad55cac-f59c-48a7-84c6-797e67dd798f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011007165 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.3011007165 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/38.kmac_lc_escalation/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.2357478702
Short name T157
Test name
Test status
Simulation time 74718884 ps
CPU time 1.5 seconds
Started Aug 10 05:29:29 PM PDT 24
Finished Aug 10 05:29:31 PM PDT 24
Peak memory 216564 kb
Host smart-7b3d798b-d756-4d8e-a7ee-641edf1dcb47
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357478702 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partia
l_access.2357478702 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.477382132
Short name T104
Test name
Test status
Simulation time 178151295 ps
CPU time 2.76 seconds
Started Aug 10 05:29:56 PM PDT 24
Finished Aug 10 05:29:59 PM PDT 24
Peak memory 220080 kb
Host smart-d1c61c51-d684-420b-8a1a-18567091d986
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477382132 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac
_shadow_reg_errors_with_csr_rw.477382132 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/15.kmac_lc_escalation.3862818276
Short name T958
Test name
Test status
Simulation time 170728081 ps
CPU time 1.48 seconds
Started Aug 10 06:35:30 PM PDT 24
Finished Aug 10 06:35:31 PM PDT 24
Peak memory 226960 kb
Host smart-3e6f4294-1e95-4226-8528-fac9338f0eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862818276 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.3862818276 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/15.kmac_lc_escalation/latest

Test location /workspace/coverage/default/18.kmac_lc_escalation.1593752969
Short name T77
Test name
Test status
Simulation time 40384011 ps
CPU time 1.26 seconds
Started Aug 10 06:37:29 PM PDT 24
Finished Aug 10 06:37:30 PM PDT 24
Peak memory 226944 kb
Host smart-978f2b32-b499-4ab8-b55e-2892fcb35921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593752969 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.1593752969 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/18.kmac_lc_escalation/latest

Test location /workspace/coverage/default/10.kmac_alert_test.3672667414
Short name T88
Test name
Test status
Simulation time 24911210 ps
CPU time 0.81 seconds
Started Aug 10 06:33:02 PM PDT 24
Finished Aug 10 06:33:03 PM PDT 24
Peak memory 218568 kb
Host smart-e37eb646-9fb1-497d-8fe0-bf47523df72a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672667414 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.3672667414 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.4290654008
Short name T1068
Test name
Test status
Simulation time 41909923 ps
CPU time 0.95 seconds
Started Aug 10 05:29:46 PM PDT 24
Finished Aug 10 05:29:47 PM PDT 24
Peak memory 216572 kb
Host smart-ecefdc43-678d-46c3-8004-2e320d37fc29
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290654008 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg
_errors.4290654008 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.3001028822
Short name T145
Test name
Test status
Simulation time 145617142 ps
CPU time 2.97 seconds
Started Aug 10 05:29:38 PM PDT 24
Finished Aug 10 05:29:41 PM PDT 24
Peak memory 216512 kb
Host smart-003b6a74-4028-4acc-aaad-96e82b53784e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001028822 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.30010
28822 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/3.kmac_sec_cm.2327525131
Short name T32
Test name
Test status
Simulation time 9195377697 ps
CPU time 122.32 seconds
Started Aug 10 06:30:09 PM PDT 24
Finished Aug 10 06:32:12 PM PDT 24
Peak memory 308384 kb
Host smart-6bd8a9b6-6b64-4180-80a5-d6304ec6bb03
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327525131 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.2327525131 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspace/3.kmac_sec_cm/latest

Test location /workspace/coverage/default/34.kmac_stress_all.3250431052
Short name T2
Test name
Test status
Simulation time 12895421712 ps
CPU time 190.88 seconds
Started Aug 10 06:47:37 PM PDT 24
Finished Aug 10 06:50:48 PM PDT 24
Peak memory 375380 kb
Host smart-1beea95c-ae60-4513-ac4c-7908b0fe2c49
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3250431052 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.3250431052 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_stress_all/latest

Test location /workspace/coverage/default/15.kmac_entropy_refresh.1090719013
Short name T634
Test name
Test status
Simulation time 10202573294 ps
CPU time 273.46 seconds
Started Aug 10 06:35:23 PM PDT 24
Finished Aug 10 06:39:57 PM PDT 24
Peak memory 441044 kb
Host smart-184689fb-4e96-4747-9489-29a96e6524d7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090719013 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.1
090719013 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_entropy_refresh/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.76166084
Short name T176
Test name
Test status
Simulation time 1977395074 ps
CPU time 5.38 seconds
Started Aug 10 05:29:47 PM PDT 24
Finished Aug 10 05:29:53 PM PDT 24
Peak memory 216592 kb
Host smart-f9af1e63-60f1-40e0-a573-28d395d25ba4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76166084 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.761660
84 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_intr_test.3142126994
Short name T1073
Test name
Test status
Simulation time 40926675 ps
CPU time 0.83 seconds
Started Aug 10 05:30:01 PM PDT 24
Finished Aug 10 05:30:03 PM PDT 24
Peak memory 216316 kb
Host smart-6b10c5fa-e73d-442a-89bd-5a77c384f3aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142126994 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.3142126994 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.2960634835
Short name T102
Test name
Test status
Simulation time 149555086 ps
CPU time 1.64 seconds
Started Aug 10 05:29:19 PM PDT 24
Finished Aug 10 05:29:20 PM PDT 24
Peak memory 216572 kb
Host smart-570d4e61-ae06-4553-b4ec-7d7fd52fc3ac
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960634835 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac
_shadow_reg_errors_with_csr_rw.2960634835 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/15.kmac_error.184066050
Short name T26
Test name
Test status
Simulation time 24696914539 ps
CPU time 554.85 seconds
Started Aug 10 06:35:23 PM PDT 24
Finished Aug 10 06:44:38 PM PDT 24
Peak memory 635768 kb
Host smart-af46a727-931c-4203-90ed-de9bf91c5f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184066050 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.184066050 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_error/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.1410118773
Short name T1167
Test name
Test status
Simulation time 62162397 ps
CPU time 2.4 seconds
Started Aug 10 05:29:33 PM PDT 24
Finished Aug 10 05:29:35 PM PDT 24
Peak memory 216488 kb
Host smart-4847b6f8-079d-4d6e-ae87-2bc957f1cf1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410118773 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.14101
18773 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_intr_test.1414846777
Short name T1093
Test name
Test status
Simulation time 13504627 ps
CPU time 0.76 seconds
Started Aug 10 05:29:34 PM PDT 24
Finished Aug 10 05:29:35 PM PDT 24
Peak memory 216280 kb
Host smart-6c4b292e-6b16-47af-a21a-97f31c817f8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414846777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.1414846777 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.118934575
Short name T189
Test name
Test status
Simulation time 373204074 ps
CPU time 2.75 seconds
Started Aug 10 05:29:52 PM PDT 24
Finished Aug 10 05:29:55 PM PDT 24
Peak memory 216556 kb
Host smart-7adbff79-f7fd-4b7e-b3d5-8fa7c09e7734
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118934575 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.11893
4575 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/1.kmac_mubi.1691829576
Short name T83
Test name
Test status
Simulation time 2528195884 ps
CPU time 175.55 seconds
Started Aug 10 06:29:07 PM PDT 24
Finished Aug 10 06:32:03 PM PDT 24
Peak memory 286816 kb
Host smart-37b51a5d-c7ee-4b0e-a576-722d1ac96c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691829576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.1691829576 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_mubi/latest

Test location /workspace/coverage/default/15.kmac_app.341025954
Short name T457
Test name
Test status
Simulation time 9234092504 ps
CPU time 312.62 seconds
Started Aug 10 06:35:24 PM PDT 24
Finished Aug 10 06:40:37 PM PDT 24
Peak memory 322716 kb
Host smart-cdfee201-3dca-4e78-85ca-5b544c72257d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341025954 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.341025954 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/15.kmac_app/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.3757628820
Short name T139
Test name
Test status
Simulation time 906733211 ps
CPU time 5.09 seconds
Started Aug 10 05:29:37 PM PDT 24
Finished Aug 10 05:29:43 PM PDT 24
Peak memory 216460 kb
Host smart-87121b70-ec51-4ec7-9634-367b7c92d5b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757628820 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.37576
28820 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.kmac_mubi.2863316529
Short name T80
Test name
Test status
Simulation time 55084683208 ps
CPU time 482.9 seconds
Started Aug 10 06:28:47 PM PDT 24
Finished Aug 10 06:36:50 PM PDT 24
Peak memory 552740 kb
Host smart-9f52aab1-5aca-49c1-9aaf-b0b1875c862f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863316529 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.2863316529 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_mubi/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.212484921
Short name T1127
Test name
Test status
Simulation time 89172781 ps
CPU time 4.4 seconds
Started Aug 10 05:29:36 PM PDT 24
Finished Aug 10 05:29:41 PM PDT 24
Peak memory 216488 kb
Host smart-d3c81f7b-5d46-4674-b661-d374e6d55f39
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212484921 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.21248492
1 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.1066355252
Short name T1090
Test name
Test status
Simulation time 3144825995 ps
CPU time 11.65 seconds
Started Aug 10 05:29:31 PM PDT 24
Finished Aug 10 05:29:43 PM PDT 24
Peak memory 216528 kb
Host smart-f45ecac7-6494-4fe3-85cf-6666d742caf1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066355252 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.1066355
252 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.1649712663
Short name T143
Test name
Test status
Simulation time 54123975 ps
CPU time 1.14 seconds
Started Aug 10 05:29:31 PM PDT 24
Finished Aug 10 05:29:32 PM PDT 24
Peak memory 216548 kb
Host smart-5a7e29c8-95a4-4cef-bf13-471024bca32d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649712663 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.1649712
663 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.2124793749
Short name T1132
Test name
Test status
Simulation time 156551708 ps
CPU time 1.65 seconds
Started Aug 10 05:29:30 PM PDT 24
Finished Aug 10 05:29:32 PM PDT 24
Peak memory 221192 kb
Host smart-be005a11-9683-4aad-bab3-67ab8ed2b2aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124793749 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.kmac_csr_mem_rw_with_rand_reset.2124793749 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_rw.2564422881
Short name T1184
Test name
Test status
Simulation time 23051681 ps
CPU time 0.99 seconds
Started Aug 10 05:29:34 PM PDT 24
Finished Aug 10 05:29:35 PM PDT 24
Peak memory 216224 kb
Host smart-b38ebd3b-e795-47d1-9f92-56518f7d24a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564422881 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.2564422881 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.2470100887
Short name T158
Test name
Test status
Simulation time 64318261 ps
CPU time 1.41 seconds
Started Aug 10 05:29:30 PM PDT 24
Finished Aug 10 05:29:31 PM PDT 24
Peak memory 216572 kb
Host smart-cac93c7e-c565-41fb-8210-0c626d988617
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470100887 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partia
l_access.2470100887 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_mem_walk.1346790078
Short name T1173
Test name
Test status
Simulation time 12427408 ps
CPU time 0.77 seconds
Started Aug 10 05:29:31 PM PDT 24
Finished Aug 10 05:29:32 PM PDT 24
Peak memory 216332 kb
Host smart-db4b4f36-460c-4569-b2fd-0819fefe35c0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346790078 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.1346790078
+enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.2301047098
Short name T1154
Test name
Test status
Simulation time 381036425 ps
CPU time 2.29 seconds
Started Aug 10 05:29:29 PM PDT 24
Finished Aug 10 05:29:31 PM PDT 24
Peak memory 216600 kb
Host smart-542b71eb-a7a1-4759-8b91-b54b349c2e25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301047098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr
_outstanding.2301047098 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.3324798994
Short name T100
Test name
Test status
Simulation time 29796319 ps
CPU time 0.92 seconds
Started Aug 10 05:29:29 PM PDT 24
Finished Aug 10 05:29:30 PM PDT 24
Peak memory 216668 kb
Host smart-dd275031-4bc1-4c4b-815e-ca607802d06c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324798994 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_
errors.3324798994 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_tl_errors.3514200924
Short name T1152
Test name
Test status
Simulation time 212360240 ps
CPU time 3.19 seconds
Started Aug 10 05:29:31 PM PDT 24
Finished Aug 10 05:29:35 PM PDT 24
Peak memory 216624 kb
Host smart-d0657788-85c2-4d8f-8be2-af9b124b3977
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514200924 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.3514200924 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.3802747609
Short name T1208
Test name
Test status
Simulation time 7497889706 ps
CPU time 9.48 seconds
Started Aug 10 05:29:31 PM PDT 24
Finished Aug 10 05:29:41 PM PDT 24
Peak memory 216568 kb
Host smart-03108bd6-33f8-43c7-b3c4-223a599a8d9f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802747609 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.3802747
609 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.4061023194
Short name T1067
Test name
Test status
Simulation time 580312508 ps
CPU time 8.58 seconds
Started Aug 10 05:29:29 PM PDT 24
Finished Aug 10 05:29:38 PM PDT 24
Peak memory 216460 kb
Host smart-35e013f2-6f02-4291-b3fd-5a2ce43ccfa5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061023194 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.4061023
194 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.603586050
Short name T1085
Test name
Test status
Simulation time 31711160 ps
CPU time 1.13 seconds
Started Aug 10 05:29:30 PM PDT 24
Finished Aug 10 05:29:32 PM PDT 24
Peak memory 216480 kb
Host smart-57ccf3cb-607a-44d7-84af-b3ee38fd09e1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603586050 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.60358605
0 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.1422054889
Short name T1195
Test name
Test status
Simulation time 268211199 ps
CPU time 2.31 seconds
Started Aug 10 05:29:30 PM PDT 24
Finished Aug 10 05:29:33 PM PDT 24
Peak memory 220872 kb
Host smart-1ff46cc7-27e8-43e3-8634-97ab3174515b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422054889 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.kmac_csr_mem_rw_with_rand_reset.1422054889 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_rw.3730107470
Short name T1064
Test name
Test status
Simulation time 73517086 ps
CPU time 1 seconds
Started Aug 10 05:29:32 PM PDT 24
Finished Aug 10 05:29:33 PM PDT 24
Peak memory 216332 kb
Host smart-bd47ce5f-4e0f-495f-87d6-48ab7e970f63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730107470 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.3730107470 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_mem_walk.2298175575
Short name T1112
Test name
Test status
Simulation time 40020840 ps
CPU time 0.74 seconds
Started Aug 10 05:29:30 PM PDT 24
Finished Aug 10 05:29:31 PM PDT 24
Peak memory 216316 kb
Host smart-4e8e91c4-995c-4535-9399-b1cc1d02c295
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298175575 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.2298175575
+enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.3018049959
Short name T1056
Test name
Test status
Simulation time 190745955 ps
CPU time 1.64 seconds
Started Aug 10 05:29:32 PM PDT 24
Finished Aug 10 05:29:34 PM PDT 24
Peak memory 216464 kb
Host smart-520dd898-0577-42ed-875f-98c23cfc693b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018049959 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr
_outstanding.3018049959 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.94684829
Short name T1149
Test name
Test status
Simulation time 56209892 ps
CPU time 1.27 seconds
Started Aug 10 05:29:31 PM PDT 24
Finished Aug 10 05:29:32 PM PDT 24
Peak memory 217704 kb
Host smart-7867fb42-becc-4977-9b74-87e241120fb4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94684829 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_er
rors.94684829 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.2173693346
Short name T1118
Test name
Test status
Simulation time 89827225 ps
CPU time 2.4 seconds
Started Aug 10 05:29:37 PM PDT 24
Finished Aug 10 05:29:39 PM PDT 24
Peak memory 219320 kb
Host smart-1ce2f641-c55f-44c7-8bb9-d7648e6bdd14
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173693346 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac
_shadow_reg_errors_with_csr_rw.2173693346 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_tl_errors.1557500983
Short name T140
Test name
Test status
Simulation time 50386197 ps
CPU time 3.21 seconds
Started Aug 10 05:29:32 PM PDT 24
Finished Aug 10 05:29:36 PM PDT 24
Peak memory 216696 kb
Host smart-3fae0d5c-06bd-4812-9ce9-dd268e0e33b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557500983 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.1557500983 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.868018335
Short name T190
Test name
Test status
Simulation time 207028071 ps
CPU time 2.63 seconds
Started Aug 10 05:29:31 PM PDT 24
Finished Aug 10 05:29:34 PM PDT 24
Peak memory 216584 kb
Host smart-d4ec7395-825f-4660-b511-5a2f590c5b17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868018335 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.868018
335 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.2562682466
Short name T133
Test name
Test status
Simulation time 52115854 ps
CPU time 1.76 seconds
Started Aug 10 05:29:47 PM PDT 24
Finished Aug 10 05:29:49 PM PDT 24
Peak memory 220688 kb
Host smart-d0a47f2a-fb60-46fc-9c5d-ed14ee68e1cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562682466 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.kmac_csr_mem_rw_with_rand_reset.2562682466 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_csr_rw.2277163801
Short name T1169
Test name
Test status
Simulation time 56216793 ps
CPU time 1.18 seconds
Started Aug 10 05:29:51 PM PDT 24
Finished Aug 10 05:29:53 PM PDT 24
Peak memory 216408 kb
Host smart-5f1ba892-639b-4652-925e-70d881eac0e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277163801 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.2277163801 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_intr_test.2287872715
Short name T1186
Test name
Test status
Simulation time 70490811 ps
CPU time 0.81 seconds
Started Aug 10 05:29:51 PM PDT 24
Finished Aug 10 05:29:52 PM PDT 24
Peak memory 216432 kb
Host smart-9d26eff6-d601-4d92-9abc-c59ca0359e46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287872715 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.2287872715 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.1409516059
Short name T1151
Test name
Test status
Simulation time 1137013090 ps
CPU time 2.71 seconds
Started Aug 10 05:29:50 PM PDT 24
Finished Aug 10 05:29:53 PM PDT 24
Peak memory 216556 kb
Host smart-7a6715b7-fbd2-41d2-b622-b161f1175203
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409516059 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_cs
r_outstanding.1409516059 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.1266293290
Short name T1179
Test name
Test status
Simulation time 97468944 ps
CPU time 1.77 seconds
Started Aug 10 05:29:49 PM PDT 24
Finished Aug 10 05:29:51 PM PDT 24
Peak memory 216836 kb
Host smart-c2267db5-1a1d-4c48-8773-f48ef36474f7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266293290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kma
c_shadow_reg_errors_with_csr_rw.1266293290 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_tl_errors.4108884676
Short name T1097
Test name
Test status
Simulation time 382434944 ps
CPU time 2.48 seconds
Started Aug 10 05:29:51 PM PDT 24
Finished Aug 10 05:29:53 PM PDT 24
Peak memory 216676 kb
Host smart-57d2044b-e8b8-4a0b-95bd-15fe022c3746
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108884676 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.4108884676 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.687307922
Short name T1075
Test name
Test status
Simulation time 94760530 ps
CPU time 1.76 seconds
Started Aug 10 05:29:50 PM PDT 24
Finished Aug 10 05:29:52 PM PDT 24
Peak memory 220808 kb
Host smart-75f33bce-c7c8-428a-995e-22cec2605292
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687307922 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.kmac_csr_mem_rw_with_rand_reset.687307922 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_csr_rw.712963210
Short name T1124
Test name
Test status
Simulation time 23002557 ps
CPU time 0.94 seconds
Started Aug 10 05:29:51 PM PDT 24
Finished Aug 10 05:29:53 PM PDT 24
Peak memory 216228 kb
Host smart-dec80b2a-6cfc-4e49-9c7b-17aca39a56ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712963210 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.712963210 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/11.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_intr_test.417274201
Short name T1157
Test name
Test status
Simulation time 38084704 ps
CPU time 0.83 seconds
Started Aug 10 05:29:47 PM PDT 24
Finished Aug 10 05:29:48 PM PDT 24
Peak memory 216356 kb
Host smart-6e1006fb-0cf9-410c-9b1d-4916c75722ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417274201 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.417274201 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/11.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.2445920634
Short name T1134
Test name
Test status
Simulation time 25397876 ps
CPU time 1.46 seconds
Started Aug 10 05:29:47 PM PDT 24
Finished Aug 10 05:29:49 PM PDT 24
Peak memory 216500 kb
Host smart-20c8e5a9-3d07-456c-9f6b-32837f51bbcf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445920634 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_cs
r_outstanding.2445920634 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.3721276684
Short name T1110
Test name
Test status
Simulation time 91731186 ps
CPU time 0.88 seconds
Started Aug 10 05:29:48 PM PDT 24
Finished Aug 10 05:29:49 PM PDT 24
Peak memory 216300 kb
Host smart-41b2b8cf-a74d-4d03-a877-fcd1eb791b33
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721276684 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg
_errors.3721276684 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.2663768816
Short name T111
Test name
Test status
Simulation time 138014978 ps
CPU time 2.79 seconds
Started Aug 10 05:29:48 PM PDT 24
Finished Aug 10 05:29:51 PM PDT 24
Peak memory 219248 kb
Host smart-a0e33a06-d7f2-4b22-b336-05da6a192618
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663768816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kma
c_shadow_reg_errors_with_csr_rw.2663768816 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_tl_errors.2279505594
Short name T1109
Test name
Test status
Simulation time 58351105 ps
CPU time 3.61 seconds
Started Aug 10 05:29:50 PM PDT 24
Finished Aug 10 05:29:54 PM PDT 24
Peak memory 216628 kb
Host smart-fe0e2900-fe7f-47d0-9b3f-ad8e232440a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279505594 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.2279505594 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.3125995212
Short name T1137
Test name
Test status
Simulation time 249200111 ps
CPU time 2.87 seconds
Started Aug 10 05:29:46 PM PDT 24
Finished Aug 10 05:29:49 PM PDT 24
Peak memory 216372 kb
Host smart-d7327792-031a-46ed-80fa-883f340a3457
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125995212 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.3125
995212 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.2086173531
Short name T1145
Test name
Test status
Simulation time 133270802 ps
CPU time 2.28 seconds
Started Aug 10 05:29:49 PM PDT 24
Finished Aug 10 05:29:52 PM PDT 24
Peak memory 220996 kb
Host smart-389ae518-3d7b-431a-8567-32d777f29370
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086173531 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.kmac_csr_mem_rw_with_rand_reset.2086173531 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_csr_rw.3529689143
Short name T1201
Test name
Test status
Simulation time 71146671 ps
CPU time 1.21 seconds
Started Aug 10 05:29:47 PM PDT 24
Finished Aug 10 05:29:48 PM PDT 24
Peak memory 216492 kb
Host smart-e8816f18-3fd5-4274-aa72-ae036fd881d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529689143 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.3529689143 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_intr_test.361311715
Short name T1103
Test name
Test status
Simulation time 35975209 ps
CPU time 0.79 seconds
Started Aug 10 05:29:49 PM PDT 24
Finished Aug 10 05:29:50 PM PDT 24
Peak memory 216236 kb
Host smart-c4cca72e-f438-4787-9082-4daa0165281c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361311715 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.361311715 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/12.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.180056630
Short name T1126
Test name
Test status
Simulation time 158609713 ps
CPU time 2.29 seconds
Started Aug 10 05:29:53 PM PDT 24
Finished Aug 10 05:29:55 PM PDT 24
Peak memory 216624 kb
Host smart-d4ba7704-86a3-4b1d-877b-76e6285cbca8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180056630 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_csr
_outstanding.180056630 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.2603510743
Short name T1158
Test name
Test status
Simulation time 52357208 ps
CPU time 1.05 seconds
Started Aug 10 05:29:49 PM PDT 24
Finished Aug 10 05:29:50 PM PDT 24
Peak memory 216540 kb
Host smart-b7ac4dc7-4c53-463f-838f-b95006d97133
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603510743 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg
_errors.2603510743 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.3847879234
Short name T105
Test name
Test status
Simulation time 52879327 ps
CPU time 2.26 seconds
Started Aug 10 05:29:47 PM PDT 24
Finished Aug 10 05:29:50 PM PDT 24
Peak memory 216512 kb
Host smart-d1c1416a-8140-4a7c-ac9d-441a66785f5a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847879234 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kma
c_shadow_reg_errors_with_csr_rw.3847879234 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_tl_errors.4102427290
Short name T1099
Test name
Test status
Simulation time 139210041 ps
CPU time 3.77 seconds
Started Aug 10 05:29:48 PM PDT 24
Finished Aug 10 05:29:52 PM PDT 24
Peak memory 216520 kb
Host smart-3b49c65e-d58a-4531-bf93-4b15aa60a397
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102427290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.4102427290 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.3206715239
Short name T192
Test name
Test status
Simulation time 389721585 ps
CPU time 2.88 seconds
Started Aug 10 05:29:48 PM PDT 24
Finished Aug 10 05:29:51 PM PDT 24
Peak memory 216620 kb
Host smart-21d2d384-431f-437e-8af6-98ea21144893
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206715239 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.3206
715239 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.3435972256
Short name T1172
Test name
Test status
Simulation time 36772979 ps
CPU time 2.3 seconds
Started Aug 10 05:29:52 PM PDT 24
Finished Aug 10 05:29:55 PM PDT 24
Peak memory 222004 kb
Host smart-c937f70f-7f4d-4bc4-9156-723ddd846441
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435972256 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.kmac_csr_mem_rw_with_rand_reset.3435972256 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_csr_rw.2113423447
Short name T169
Test name
Test status
Simulation time 114652348 ps
CPU time 1.01 seconds
Started Aug 10 05:29:48 PM PDT 24
Finished Aug 10 05:29:50 PM PDT 24
Peak memory 216120 kb
Host smart-1b614b56-a3e2-49c9-81f8-e13181502949
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113423447 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.2113423447 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_intr_test.4037387365
Short name T1100
Test name
Test status
Simulation time 80949397 ps
CPU time 0.81 seconds
Started Aug 10 05:29:53 PM PDT 24
Finished Aug 10 05:29:54 PM PDT 24
Peak memory 216332 kb
Host smart-8026631b-2215-4933-b8e8-edd772e48212
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037387365 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.4037387365 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.3258254206
Short name T1200
Test name
Test status
Simulation time 29923630 ps
CPU time 1.54 seconds
Started Aug 10 05:29:49 PM PDT 24
Finished Aug 10 05:29:52 PM PDT 24
Peak memory 216560 kb
Host smart-aaeea13e-2249-4ad2-986c-517ff76ce8b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258254206 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_cs
r_outstanding.3258254206 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.1774822097
Short name T112
Test name
Test status
Simulation time 31448765 ps
CPU time 1.08 seconds
Started Aug 10 05:29:52 PM PDT 24
Finished Aug 10 05:29:54 PM PDT 24
Peak memory 216824 kb
Host smart-881465df-638d-4dfc-a2d4-d57a25a81a03
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774822097 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg
_errors.1774822097 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.476797844
Short name T1174
Test name
Test status
Simulation time 1166709969 ps
CPU time 2.27 seconds
Started Aug 10 05:29:48 PM PDT 24
Finished Aug 10 05:29:50 PM PDT 24
Peak memory 219128 kb
Host smart-e8fcfdf4-e567-43a1-9418-1021e5105eff
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476797844 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac
_shadow_reg_errors_with_csr_rw.476797844 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_tl_errors.3441521473
Short name T1084
Test name
Test status
Simulation time 136869542 ps
CPU time 3.44 seconds
Started Aug 10 05:29:51 PM PDT 24
Finished Aug 10 05:29:55 PM PDT 24
Peak memory 216728 kb
Host smart-56e1b29e-4b87-449a-b39b-5249d4c31305
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441521473 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.3441521473 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.1719206512
Short name T1072
Test name
Test status
Simulation time 367004050 ps
CPU time 1.56 seconds
Started Aug 10 05:29:59 PM PDT 24
Finished Aug 10 05:30:00 PM PDT 24
Peak memory 217832 kb
Host smart-cd633f9e-d337-4787-a64a-5df3c6d80ad7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719206512 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.kmac_csr_mem_rw_with_rand_reset.1719206512 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_csr_rw.3001496869
Short name T1204
Test name
Test status
Simulation time 58768392 ps
CPU time 0.96 seconds
Started Aug 10 05:29:52 PM PDT 24
Finished Aug 10 05:29:53 PM PDT 24
Peak memory 216292 kb
Host smart-41a0fd62-fd1b-479b-8591-f0ee1184d2df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001496869 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.3001496869 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_intr_test.1120260945
Short name T1122
Test name
Test status
Simulation time 41225999 ps
CPU time 0.78 seconds
Started Aug 10 05:29:49 PM PDT 24
Finished Aug 10 05:29:51 PM PDT 24
Peak memory 216296 kb
Host smart-f535e773-d244-4369-b39a-9ae97f68e745
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120260945 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.1120260945 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.2490132108
Short name T1128
Test name
Test status
Simulation time 68684498 ps
CPU time 1.79 seconds
Started Aug 10 05:29:56 PM PDT 24
Finished Aug 10 05:29:58 PM PDT 24
Peak memory 216572 kb
Host smart-65bd9a01-eb7c-4e22-b471-ae4d37aa070b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490132108 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_cs
r_outstanding.2490132108 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.1855643231
Short name T1166
Test name
Test status
Simulation time 76530423 ps
CPU time 0.97 seconds
Started Aug 10 05:29:47 PM PDT 24
Finished Aug 10 05:29:48 PM PDT 24
Peak memory 216280 kb
Host smart-37cb8092-f542-4192-8919-f05dba579ecf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855643231 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg
_errors.1855643231 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.491665031
Short name T107
Test name
Test status
Simulation time 104669893 ps
CPU time 2.78 seconds
Started Aug 10 05:29:50 PM PDT 24
Finished Aug 10 05:29:53 PM PDT 24
Peak memory 219212 kb
Host smart-b66ad3c6-17c3-4512-9f16-7b9895e586ab
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491665031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac
_shadow_reg_errors_with_csr_rw.491665031 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_tl_errors.2219446698
Short name T1190
Test name
Test status
Simulation time 39173467 ps
CPU time 1.32 seconds
Started Aug 10 05:29:48 PM PDT 24
Finished Aug 10 05:29:49 PM PDT 24
Peak memory 216704 kb
Host smart-818368ab-907d-41fe-87e7-3f1788d55649
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219446698 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.2219446698 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.3712392581
Short name T1114
Test name
Test status
Simulation time 108925921 ps
CPU time 2.37 seconds
Started Aug 10 05:29:48 PM PDT 24
Finished Aug 10 05:29:51 PM PDT 24
Peak memory 216596 kb
Host smart-75fb5875-aa6f-4ba1-84ad-bf560a3e6f14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712392581 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.3712
392581 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.1285078221
Short name T1089
Test name
Test status
Simulation time 41676532 ps
CPU time 1.61 seconds
Started Aug 10 05:29:57 PM PDT 24
Finished Aug 10 05:29:59 PM PDT 24
Peak memory 217656 kb
Host smart-bf4844ec-382c-4c9f-891a-524c1d36f4d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285078221 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.kmac_csr_mem_rw_with_rand_reset.1285078221 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_csr_rw.1333993113
Short name T1061
Test name
Test status
Simulation time 16548913 ps
CPU time 0.98 seconds
Started Aug 10 05:29:57 PM PDT 24
Finished Aug 10 05:29:58 PM PDT 24
Peak memory 216292 kb
Host smart-ed37e297-2abe-4210-999f-a4998acc0734
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333993113 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.1333993113 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_intr_test.130059162
Short name T1197
Test name
Test status
Simulation time 49874995 ps
CPU time 0.93 seconds
Started Aug 10 05:30:02 PM PDT 24
Finished Aug 10 05:30:03 PM PDT 24
Peak memory 216388 kb
Host smart-a1122cc5-fe37-4b17-a055-a1b4b153419a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130059162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.130059162 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/15.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.2332615303
Short name T1160
Test name
Test status
Simulation time 81683963 ps
CPU time 1.43 seconds
Started Aug 10 05:29:58 PM PDT 24
Finished Aug 10 05:29:59 PM PDT 24
Peak memory 216572 kb
Host smart-3fa12153-d393-45e4-8a2b-176856275c5c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332615303 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_cs
r_outstanding.2332615303 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.2924879589
Short name T1159
Test name
Test status
Simulation time 49137489 ps
CPU time 0.96 seconds
Started Aug 10 05:29:56 PM PDT 24
Finished Aug 10 05:29:58 PM PDT 24
Peak memory 216316 kb
Host smart-eb602068-b94d-4aaf-8a9b-c78fca46d7e6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924879589 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg
_errors.2924879589 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.89840983
Short name T1177
Test name
Test status
Simulation time 73695191 ps
CPU time 1.52 seconds
Started Aug 10 05:29:56 PM PDT 24
Finished Aug 10 05:29:57 PM PDT 24
Peak memory 216616 kb
Host smart-ea9f97f5-b858-4636-946f-ff219a5c40b1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89840983 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_
shadow_reg_errors_with_csr_rw.89840983 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_tl_errors.1546373016
Short name T147
Test name
Test status
Simulation time 290159383 ps
CPU time 2.58 seconds
Started Aug 10 05:30:02 PM PDT 24
Finished Aug 10 05:30:04 PM PDT 24
Peak memory 216700 kb
Host smart-b9b35846-2edc-4196-810a-0e4a83429ce1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546373016 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.1546373016 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.24299502
Short name T1202
Test name
Test status
Simulation time 68228171 ps
CPU time 2.41 seconds
Started Aug 10 05:29:55 PM PDT 24
Finished Aug 10 05:29:58 PM PDT 24
Peak memory 219928 kb
Host smart-fa0f1e98-6526-44f4-b305-80d8c2ee3b88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24299502 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.kmac_csr_mem_rw_with_rand_reset.24299502 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_csr_rw.3691866871
Short name T167
Test name
Test status
Simulation time 33552567 ps
CPU time 1.15 seconds
Started Aug 10 05:30:01 PM PDT 24
Finished Aug 10 05:30:03 PM PDT 24
Peak memory 216428 kb
Host smart-83efc05c-fa7d-495c-afac-85eb5e543173
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691866871 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.3691866871 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_intr_test.1328939582
Short name T1207
Test name
Test status
Simulation time 32535453 ps
CPU time 0.88 seconds
Started Aug 10 05:30:01 PM PDT 24
Finished Aug 10 05:30:02 PM PDT 24
Peak memory 216396 kb
Host smart-42e96958-f381-4526-a671-b22ff607b1ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328939582 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.1328939582 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.3527089567
Short name T1060
Test name
Test status
Simulation time 84832518 ps
CPU time 2.36 seconds
Started Aug 10 05:29:56 PM PDT 24
Finished Aug 10 05:29:58 PM PDT 24
Peak memory 216348 kb
Host smart-90472349-022d-462b-8f48-675e4d03e98e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527089567 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_cs
r_outstanding.3527089567 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.1601378963
Short name T1206
Test name
Test status
Simulation time 107772963 ps
CPU time 1.18 seconds
Started Aug 10 05:29:55 PM PDT 24
Finished Aug 10 05:29:56 PM PDT 24
Peak memory 217932 kb
Host smart-6aa4a26e-6949-418d-8da3-d806beef9845
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601378963 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg
_errors.1601378963 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.3772597755
Short name T110
Test name
Test status
Simulation time 136842448 ps
CPU time 2.81 seconds
Started Aug 10 05:29:54 PM PDT 24
Finished Aug 10 05:29:57 PM PDT 24
Peak memory 218864 kb
Host smart-3515e266-4f90-42c2-bf39-183b389ba1b9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772597755 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kma
c_shadow_reg_errors_with_csr_rw.3772597755 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_tl_errors.233223741
Short name T1117
Test name
Test status
Simulation time 204201744 ps
CPU time 3.31 seconds
Started Aug 10 05:29:59 PM PDT 24
Finished Aug 10 05:30:03 PM PDT 24
Peak memory 216660 kb
Host smart-c83b1f45-9621-4dd5-b488-27340af11c07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233223741 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.233223741 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/16.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.2757424177
Short name T1185
Test name
Test status
Simulation time 204404628 ps
CPU time 4.4 seconds
Started Aug 10 05:29:55 PM PDT 24
Finished Aug 10 05:29:59 PM PDT 24
Peak memory 216488 kb
Host smart-4c0f8564-3a4d-4023-917f-967b54cc15c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757424177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.2757
424177 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.3203538765
Short name T146
Test name
Test status
Simulation time 272646286 ps
CPU time 2.42 seconds
Started Aug 10 05:30:01 PM PDT 24
Finished Aug 10 05:30:04 PM PDT 24
Peak memory 220732 kb
Host smart-df9ce5dd-00b1-4ae8-83ab-84219843c21e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203538765 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.kmac_csr_mem_rw_with_rand_reset.3203538765 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_csr_rw.1794118768
Short name T168
Test name
Test status
Simulation time 22960105 ps
CPU time 1.02 seconds
Started Aug 10 05:29:55 PM PDT 24
Finished Aug 10 05:29:56 PM PDT 24
Peak memory 216240 kb
Host smart-8ab8ffb6-96f6-4c24-b727-e4294289ab33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794118768 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.1794118768 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.560446710
Short name T170
Test name
Test status
Simulation time 72046807 ps
CPU time 1.77 seconds
Started Aug 10 05:29:59 PM PDT 24
Finished Aug 10 05:30:01 PM PDT 24
Peak memory 216592 kb
Host smart-35a7636a-e377-432c-8e18-3cd782ccc78e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560446710 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_csr
_outstanding.560446710 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.1878736247
Short name T1203
Test name
Test status
Simulation time 26569872 ps
CPU time 0.98 seconds
Started Aug 10 05:29:55 PM PDT 24
Finished Aug 10 05:29:56 PM PDT 24
Peak memory 216420 kb
Host smart-94be4e85-d75a-4093-8a8b-eccbb4112f80
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878736247 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg
_errors.1878736247 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.1811410507
Short name T1104
Test name
Test status
Simulation time 38077845 ps
CPU time 1.64 seconds
Started Aug 10 05:29:59 PM PDT 24
Finished Aug 10 05:30:01 PM PDT 24
Peak memory 218496 kb
Host smart-f655414f-36e0-4fc9-8bb5-f0232f67efaf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811410507 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kma
c_shadow_reg_errors_with_csr_rw.1811410507 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_tl_errors.1611156117
Short name T1164
Test name
Test status
Simulation time 42055666 ps
CPU time 2.37 seconds
Started Aug 10 05:29:57 PM PDT 24
Finished Aug 10 05:29:59 PM PDT 24
Peak memory 216760 kb
Host smart-5abdd90e-30b6-407a-aef8-75a99806c7ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611156117 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.1611156117 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.3133476567
Short name T136
Test name
Test status
Simulation time 258875305 ps
CPU time 2.83 seconds
Started Aug 10 05:29:54 PM PDT 24
Finished Aug 10 05:29:57 PM PDT 24
Peak memory 216600 kb
Host smart-58325472-ca90-4731-b0cf-c13a06c24630
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133476567 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.3133
476567 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.3048755918
Short name T1119
Test name
Test status
Simulation time 165142906 ps
CPU time 2.46 seconds
Started Aug 10 05:29:59 PM PDT 24
Finished Aug 10 05:30:01 PM PDT 24
Peak memory 221360 kb
Host smart-1eb6090b-ba5e-4333-b69c-212af5e79245
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048755918 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.kmac_csr_mem_rw_with_rand_reset.3048755918 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_csr_rw.1972454556
Short name T1086
Test name
Test status
Simulation time 22834246 ps
CPU time 0.9 seconds
Started Aug 10 05:29:56 PM PDT 24
Finished Aug 10 05:29:57 PM PDT 24
Peak memory 216192 kb
Host smart-4ecf7fc6-7e3d-4567-b177-7af0efa648d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972454556 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.1972454556 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_intr_test.3905519032
Short name T1074
Test name
Test status
Simulation time 91213637 ps
CPU time 0.8 seconds
Started Aug 10 05:29:56 PM PDT 24
Finished Aug 10 05:29:57 PM PDT 24
Peak memory 216292 kb
Host smart-e0fccec7-e1b1-4d80-9889-dee89919c074
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905519032 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.3905519032 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.2648104655
Short name T1199
Test name
Test status
Simulation time 62605346 ps
CPU time 1.59 seconds
Started Aug 10 05:29:57 PM PDT 24
Finished Aug 10 05:29:59 PM PDT 24
Peak memory 216596 kb
Host smart-766242f5-06e9-4236-aaeb-c26d02e2cf53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648104655 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_cs
r_outstanding.2648104655 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.676201040
Short name T1170
Test name
Test status
Simulation time 48056177 ps
CPU time 1.31 seconds
Started Aug 10 05:29:57 PM PDT 24
Finished Aug 10 05:29:59 PM PDT 24
Peak memory 216852 kb
Host smart-3d336c8d-cfc2-400e-b3da-325e1f4c1383
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676201040 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_
errors.676201040 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_tl_errors.3447536734
Short name T137
Test name
Test status
Simulation time 207484471 ps
CPU time 1.64 seconds
Started Aug 10 05:29:58 PM PDT 24
Finished Aug 10 05:30:00 PM PDT 24
Peak memory 216732 kb
Host smart-6cad180c-90b4-4615-a2c9-e858ce9bbc1a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447536734 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.3447536734 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.1036517999
Short name T188
Test name
Test status
Simulation time 472121620 ps
CPU time 3.03 seconds
Started Aug 10 05:30:01 PM PDT 24
Finished Aug 10 05:30:05 PM PDT 24
Peak memory 216556 kb
Host smart-69d77c0c-d13d-40b3-8f9a-86e78bca3c1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036517999 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.1036
517999 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.3694685194
Short name T1163
Test name
Test status
Simulation time 390711930 ps
CPU time 2.49 seconds
Started Aug 10 05:29:59 PM PDT 24
Finished Aug 10 05:30:01 PM PDT 24
Peak memory 221408 kb
Host smart-b481f67e-d578-4bb6-82a9-27efa7f982e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694685194 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.kmac_csr_mem_rw_with_rand_reset.3694685194 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_csr_rw.1428115582
Short name T1092
Test name
Test status
Simulation time 45554443 ps
CPU time 1.15 seconds
Started Aug 10 05:29:56 PM PDT 24
Finished Aug 10 05:29:57 PM PDT 24
Peak memory 216308 kb
Host smart-b2c6e9d2-8595-4841-b4b2-9c3b54d0369b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428115582 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.1428115582 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_intr_test.2815079188
Short name T1146
Test name
Test status
Simulation time 24277482 ps
CPU time 0.88 seconds
Started Aug 10 05:29:55 PM PDT 24
Finished Aug 10 05:29:56 PM PDT 24
Peak memory 216360 kb
Host smart-2837373a-b6ba-4100-9fd6-19b9ca0cb89f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815079188 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.2815079188 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.1306958854
Short name T174
Test name
Test status
Simulation time 100572267 ps
CPU time 2.41 seconds
Started Aug 10 05:29:59 PM PDT 24
Finished Aug 10 05:30:01 PM PDT 24
Peak memory 216420 kb
Host smart-d42e2533-7d1f-4d43-90d0-2c0695a93230
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306958854 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_cs
r_outstanding.1306958854 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.2898646475
Short name T1065
Test name
Test status
Simulation time 42153795 ps
CPU time 0.86 seconds
Started Aug 10 05:29:58 PM PDT 24
Finished Aug 10 05:29:59 PM PDT 24
Peak memory 216128 kb
Host smart-82e77afd-510a-4c3a-964e-b087c2646519
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898646475 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg
_errors.2898646475 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.845735868
Short name T1161
Test name
Test status
Simulation time 174432845 ps
CPU time 2.38 seconds
Started Aug 10 05:29:59 PM PDT 24
Finished Aug 10 05:30:02 PM PDT 24
Peak memory 219288 kb
Host smart-dbb5355e-b42c-4c12-9372-f33cab719e06
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845735868 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac
_shadow_reg_errors_with_csr_rw.845735868 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_tl_errors.2279443524
Short name T1080
Test name
Test status
Simulation time 185901871 ps
CPU time 4.23 seconds
Started Aug 10 05:29:57 PM PDT 24
Finished Aug 10 05:30:01 PM PDT 24
Peak memory 216584 kb
Host smart-14ad056d-4a31-47b4-968f-77a47f59116a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279443524 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.2279443524 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.1164056752
Short name T195
Test name
Test status
Simulation time 757715147 ps
CPU time 5.09 seconds
Started Aug 10 05:30:01 PM PDT 24
Finished Aug 10 05:30:07 PM PDT 24
Peak memory 216584 kb
Host smart-751af49f-8700-419c-a102-aafc310302eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164056752 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.1164
056752 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.1902391258
Short name T1078
Test name
Test status
Simulation time 3645875441 ps
CPU time 6.24 seconds
Started Aug 10 05:29:40 PM PDT 24
Finished Aug 10 05:29:47 PM PDT 24
Peak memory 216528 kb
Host smart-6936e993-df18-4391-99fe-e7cfadd915b3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902391258 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.1902391
258 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.3232651850
Short name T1116
Test name
Test status
Simulation time 1100628863 ps
CPU time 18.49 seconds
Started Aug 10 05:29:30 PM PDT 24
Finished Aug 10 05:29:49 PM PDT 24
Peak memory 216300 kb
Host smart-e39a6bce-e616-4585-bfd6-d8eddeb6f155
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232651850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.3232651
850 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.391177714
Short name T1178
Test name
Test status
Simulation time 21455184 ps
CPU time 1.01 seconds
Started Aug 10 05:29:37 PM PDT 24
Finished Aug 10 05:29:38 PM PDT 24
Peak memory 216304 kb
Host smart-d3e0a954-ce67-4047-9f0b-4748f76dd21f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391177714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.39117771
4 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.4259740729
Short name T1111
Test name
Test status
Simulation time 46181167 ps
CPU time 1.68 seconds
Started Aug 10 05:29:40 PM PDT 24
Finished Aug 10 05:29:41 PM PDT 24
Peak memory 217612 kb
Host smart-f52d2ed8-29b2-4a14-93da-17fa4b1b46a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259740729 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.kmac_csr_mem_rw_with_rand_reset.4259740729 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_rw.2867621268
Short name T196
Test name
Test status
Simulation time 26373933 ps
CPU time 0.9 seconds
Started Aug 10 05:29:31 PM PDT 24
Finished Aug 10 05:29:32 PM PDT 24
Peak memory 216288 kb
Host smart-1c7f37ad-2525-4540-a200-db04807b8e60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867621268 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.2867621268 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_intr_test.849298789
Short name T1182
Test name
Test status
Simulation time 41400220 ps
CPU time 0.83 seconds
Started Aug 10 05:29:32 PM PDT 24
Finished Aug 10 05:29:33 PM PDT 24
Peak memory 216392 kb
Host smart-7aae5fa5-01ce-4d33-b45c-f1f72cb1ab40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849298789 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.849298789 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/2.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.3805174948
Short name T159
Test name
Test status
Simulation time 85895742 ps
CPU time 1.5 seconds
Started Aug 10 05:29:30 PM PDT 24
Finished Aug 10 05:29:31 PM PDT 24
Peak memory 216548 kb
Host smart-eab41ae7-e33f-4cd4-a8d4-d22503f00323
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805174948 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partia
l_access.3805174948 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_mem_walk.3131100480
Short name T1076
Test name
Test status
Simulation time 46282175 ps
CPU time 0.78 seconds
Started Aug 10 05:29:30 PM PDT 24
Finished Aug 10 05:29:31 PM PDT 24
Peak memory 216284 kb
Host smart-53651519-471a-4e4a-bd46-234d37293a67
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131100480 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.3131100480
+enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.3820550262
Short name T1102
Test name
Test status
Simulation time 49316473 ps
CPU time 1.63 seconds
Started Aug 10 05:29:40 PM PDT 24
Finished Aug 10 05:29:42 PM PDT 24
Peak memory 216608 kb
Host smart-d2554324-39df-4113-b587-eeebaca081e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820550262 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr
_outstanding.3820550262 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.4080042902
Short name T1142
Test name
Test status
Simulation time 30470368 ps
CPU time 1.15 seconds
Started Aug 10 05:29:36 PM PDT 24
Finished Aug 10 05:29:37 PM PDT 24
Peak memory 216788 kb
Host smart-5eb89c02-455b-4d94-8613-6d1f0a91d772
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080042902 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_
errors.4080042902 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.3622503447
Short name T1188
Test name
Test status
Simulation time 90720179 ps
CPU time 2.49 seconds
Started Aug 10 05:29:31 PM PDT 24
Finished Aug 10 05:29:33 PM PDT 24
Peak memory 219428 kb
Host smart-77035514-e3d0-4e94-b67d-35035b875643
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622503447 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac
_shadow_reg_errors_with_csr_rw.3622503447 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_tl_errors.3849929315
Short name T138
Test name
Test status
Simulation time 77158881 ps
CPU time 1.42 seconds
Started Aug 10 05:29:32 PM PDT 24
Finished Aug 10 05:29:34 PM PDT 24
Peak memory 216692 kb
Host smart-e98704ae-2c81-4098-aa21-2b2381dd531d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849929315 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.3849929315 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.675663880
Short name T135
Test name
Test status
Simulation time 211851756 ps
CPU time 4.44 seconds
Started Aug 10 05:29:31 PM PDT 24
Finished Aug 10 05:29:35 PM PDT 24
Peak memory 216544 kb
Host smart-4a0862f4-2d44-4bb3-a7d3-6d64e5a2a47b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675663880 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.675663
880 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.kmac_intr_test.3387827079
Short name T1189
Test name
Test status
Simulation time 72701671 ps
CPU time 0.86 seconds
Started Aug 10 05:29:54 PM PDT 24
Finished Aug 10 05:29:55 PM PDT 24
Peak memory 216344 kb
Host smart-e9656770-3ec6-4af9-a730-365515d47a89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387827079 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.3387827079 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.kmac_intr_test.2525498592
Short name T1155
Test name
Test status
Simulation time 36629763 ps
CPU time 0.84 seconds
Started Aug 10 05:30:02 PM PDT 24
Finished Aug 10 05:30:03 PM PDT 24
Peak memory 216252 kb
Host smart-62b681dc-8155-4447-b876-888993d128a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525498592 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.2525498592 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.kmac_intr_test.4176884249
Short name T141
Test name
Test status
Simulation time 15067430 ps
CPU time 0.83 seconds
Started Aug 10 05:30:04 PM PDT 24
Finished Aug 10 05:30:05 PM PDT 24
Peak memory 216372 kb
Host smart-3255171e-2506-4e28-8345-a1f2a8173d42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176884249 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.4176884249 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.kmac_intr_test.3800007735
Short name T1088
Test name
Test status
Simulation time 24764531 ps
CPU time 0.83 seconds
Started Aug 10 05:30:01 PM PDT 24
Finished Aug 10 05:30:02 PM PDT 24
Peak memory 216404 kb
Host smart-198b187c-73ce-43d6-8e28-87cfe30679df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800007735 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.3800007735 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.kmac_intr_test.3517236651
Short name T1135
Test name
Test status
Simulation time 39646848 ps
CPU time 0.78 seconds
Started Aug 10 05:30:06 PM PDT 24
Finished Aug 10 05:30:07 PM PDT 24
Peak memory 216328 kb
Host smart-a0bbe05d-053d-497d-8e09-b2e51afd4657
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517236651 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.3517236651 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.kmac_intr_test.676742381
Short name T1153
Test name
Test status
Simulation time 80749476 ps
CPU time 0.87 seconds
Started Aug 10 05:30:04 PM PDT 24
Finished Aug 10 05:30:05 PM PDT 24
Peak memory 216316 kb
Host smart-a8f8419a-6440-4dce-b7d6-142806e1189c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676742381 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.676742381 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/25.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.kmac_intr_test.2847204136
Short name T1077
Test name
Test status
Simulation time 17334057 ps
CPU time 0.78 seconds
Started Aug 10 05:30:04 PM PDT 24
Finished Aug 10 05:30:05 PM PDT 24
Peak memory 216236 kb
Host smart-6a863775-7968-4bc4-8d64-c28f5edcdf91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847204136 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.2847204136 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.kmac_intr_test.1006557402
Short name T1171
Test name
Test status
Simulation time 222141657 ps
CPU time 0.81 seconds
Started Aug 10 05:30:02 PM PDT 24
Finished Aug 10 05:30:03 PM PDT 24
Peak memory 216272 kb
Host smart-23d592ba-cc88-46c5-a1e5-9e6562a19752
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006557402 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.1006557402 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.kmac_intr_test.2015882579
Short name T1063
Test name
Test status
Simulation time 47172772 ps
CPU time 0.76 seconds
Started Aug 10 05:30:04 PM PDT 24
Finished Aug 10 05:30:05 PM PDT 24
Peak memory 216132 kb
Host smart-75b600d7-f4a8-4bf7-8817-afa40a349740
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015882579 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.2015882579 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.kmac_intr_test.1393962093
Short name T181
Test name
Test status
Simulation time 11699506 ps
CPU time 0.76 seconds
Started Aug 10 05:30:05 PM PDT 24
Finished Aug 10 05:30:06 PM PDT 24
Peak memory 216428 kb
Host smart-345079c0-b570-49e7-881a-effd83e8c9b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393962093 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.1393962093 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.3934597638
Short name T1180
Test name
Test status
Simulation time 459180664 ps
CPU time 9.41 seconds
Started Aug 10 05:29:40 PM PDT 24
Finished Aug 10 05:29:50 PM PDT 24
Peak memory 216412 kb
Host smart-4e0272f1-8c3e-42d8-9070-5ca94a270ec9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934597638 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.3934597
638 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.1551366422
Short name T1175
Test name
Test status
Simulation time 1957074185 ps
CPU time 9.64 seconds
Started Aug 10 05:29:37 PM PDT 24
Finished Aug 10 05:29:47 PM PDT 24
Peak memory 216464 kb
Host smart-ec474750-2763-4937-b487-04e5bfb0061d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551366422 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.1551366
422 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.768612401
Short name T1057
Test name
Test status
Simulation time 56065285 ps
CPU time 1.1 seconds
Started Aug 10 05:29:37 PM PDT 24
Finished Aug 10 05:29:38 PM PDT 24
Peak memory 216452 kb
Host smart-3955da6a-6981-406a-a186-dc38413344bf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768612401 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.76861240
1 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.1970324861
Short name T154
Test name
Test status
Simulation time 54057400 ps
CPU time 1.79 seconds
Started Aug 10 05:29:41 PM PDT 24
Finished Aug 10 05:29:43 PM PDT 24
Peak memory 220996 kb
Host smart-afc82046-5f38-480a-a563-b85801785c73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970324861 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.kmac_csr_mem_rw_with_rand_reset.1970324861 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_rw.2438344962
Short name T1120
Test name
Test status
Simulation time 83816820 ps
CPU time 1.11 seconds
Started Aug 10 05:29:40 PM PDT 24
Finished Aug 10 05:29:41 PM PDT 24
Peak memory 216516 kb
Host smart-6b33a02b-ced6-441c-9a29-a67c9f217c06
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438344962 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.2438344962 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_intr_test.976286086
Short name T1141
Test name
Test status
Simulation time 80519912 ps
CPU time 0.77 seconds
Started Aug 10 05:29:43 PM PDT 24
Finished Aug 10 05:29:44 PM PDT 24
Peak memory 216416 kb
Host smart-3596ee5d-9e31-4513-bd18-7160acf86042
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976286086 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.976286086 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/3.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.3341599104
Short name T156
Test name
Test status
Simulation time 35178692 ps
CPU time 1.39 seconds
Started Aug 10 05:29:37 PM PDT 24
Finished Aug 10 05:29:39 PM PDT 24
Peak memory 216536 kb
Host smart-01ebc81d-baa7-435a-b083-faadc6265766
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341599104 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partia
l_access.3341599104 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_mem_walk.923072117
Short name T1192
Test name
Test status
Simulation time 18943046 ps
CPU time 0.76 seconds
Started Aug 10 05:29:38 PM PDT 24
Finished Aug 10 05:29:39 PM PDT 24
Peak memory 216396 kb
Host smart-0b54d862-af78-4528-a725-274aeb37f9b0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923072117 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.923072117 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.1459068042
Short name T1165
Test name
Test status
Simulation time 61920603 ps
CPU time 1.74 seconds
Started Aug 10 05:29:41 PM PDT 24
Finished Aug 10 05:29:43 PM PDT 24
Peak memory 216412 kb
Host smart-7c074851-a0ec-45d2-9766-ff4a9207e699
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459068042 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr
_outstanding.1459068042 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.570062406
Short name T109
Test name
Test status
Simulation time 216952258 ps
CPU time 1.19 seconds
Started Aug 10 05:29:40 PM PDT 24
Finished Aug 10 05:29:41 PM PDT 24
Peak memory 217804 kb
Host smart-3f6b4cce-adb2-4c6f-a9b5-f3b6dc73d49c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570062406 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_e
rrors.570062406 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_tl_errors.328410618
Short name T1098
Test name
Test status
Simulation time 38000374 ps
CPU time 1.75 seconds
Started Aug 10 05:29:38 PM PDT 24
Finished Aug 10 05:29:40 PM PDT 24
Peak memory 216676 kb
Host smart-5d45c5e4-1ab8-4351-89aa-6db568467999
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328410618 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.328410618 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/3.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.kmac_intr_test.1708638125
Short name T1140
Test name
Test status
Simulation time 25782269 ps
CPU time 0.82 seconds
Started Aug 10 05:30:06 PM PDT 24
Finished Aug 10 05:30:07 PM PDT 24
Peak memory 216328 kb
Host smart-7b715497-8ee1-47f0-a495-c13a5c80ea1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708638125 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.1708638125 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.kmac_intr_test.3784310669
Short name T1131
Test name
Test status
Simulation time 16208441 ps
CPU time 0.85 seconds
Started Aug 10 05:30:05 PM PDT 24
Finished Aug 10 05:30:06 PM PDT 24
Peak memory 216148 kb
Host smart-b6cf5c64-8202-40d2-b3a7-89d6293e9a2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784310669 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.3784310669 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.kmac_intr_test.4086598377
Short name T1094
Test name
Test status
Simulation time 12791227 ps
CPU time 0.86 seconds
Started Aug 10 05:30:05 PM PDT 24
Finished Aug 10 05:30:06 PM PDT 24
Peak memory 216400 kb
Host smart-81c3160c-fdde-4e56-91b5-d81a6473060b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086598377 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.4086598377 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.kmac_intr_test.4187070894
Short name T1168
Test name
Test status
Simulation time 18444272 ps
CPU time 0.84 seconds
Started Aug 10 05:30:02 PM PDT 24
Finished Aug 10 05:30:03 PM PDT 24
Peak memory 216312 kb
Host smart-03ad6126-b0c9-4955-9f85-a2109bfd1b0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187070894 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.4187070894 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.kmac_intr_test.2224997113
Short name T1125
Test name
Test status
Simulation time 34022964 ps
CPU time 0.79 seconds
Started Aug 10 05:30:03 PM PDT 24
Finished Aug 10 05:30:03 PM PDT 24
Peak memory 216312 kb
Host smart-7e98e542-1ff3-4c50-ac2d-73dd4a2358b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224997113 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.2224997113 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.kmac_intr_test.2014605953
Short name T1091
Test name
Test status
Simulation time 41279215 ps
CPU time 0.81 seconds
Started Aug 10 05:30:03 PM PDT 24
Finished Aug 10 05:30:04 PM PDT 24
Peak memory 216304 kb
Host smart-d4de7c04-60e9-4ca0-859f-0fbca58dee15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014605953 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.2014605953 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.kmac_intr_test.683852626
Short name T1083
Test name
Test status
Simulation time 28416275 ps
CPU time 0.91 seconds
Started Aug 10 05:30:02 PM PDT 24
Finished Aug 10 05:30:03 PM PDT 24
Peak memory 216276 kb
Host smart-447ebaa0-9265-4ca7-bdf8-c0df35ba2288
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683852626 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.683852626 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/36.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.kmac_intr_test.1068341701
Short name T183
Test name
Test status
Simulation time 16125458 ps
CPU time 0.8 seconds
Started Aug 10 05:30:04 PM PDT 24
Finished Aug 10 05:30:05 PM PDT 24
Peak memory 216180 kb
Host smart-3d7f539d-9da6-4ad5-a411-75eed4721994
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068341701 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.1068341701 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.kmac_intr_test.2284132635
Short name T171
Test name
Test status
Simulation time 35092222 ps
CPU time 0.8 seconds
Started Aug 10 05:30:03 PM PDT 24
Finished Aug 10 05:30:04 PM PDT 24
Peak memory 216404 kb
Host smart-c3e7387b-3e74-4462-ab33-ab55061c9c04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284132635 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.2284132635 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.kmac_intr_test.1405369315
Short name T1121
Test name
Test status
Simulation time 14703392 ps
CPU time 0.8 seconds
Started Aug 10 05:30:03 PM PDT 24
Finished Aug 10 05:30:04 PM PDT 24
Peak memory 216332 kb
Host smart-ab3c20e5-9414-4441-87ff-b63f9b389677
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405369315 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.1405369315 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.3618134296
Short name T197
Test name
Test status
Simulation time 220147368 ps
CPU time 5.07 seconds
Started Aug 10 05:29:39 PM PDT 24
Finished Aug 10 05:29:44 PM PDT 24
Peak memory 216396 kb
Host smart-e8f6ffe9-4a9a-4e10-a86f-964c5eec285d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618134296 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.3618134
296 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.1871189819
Short name T1087
Test name
Test status
Simulation time 774450289 ps
CPU time 10.7 seconds
Started Aug 10 05:29:38 PM PDT 24
Finished Aug 10 05:29:49 PM PDT 24
Peak memory 216436 kb
Host smart-ec82b0f4-bd4b-4ec7-8b67-b189af73855a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871189819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.1871189
819 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.1262980639
Short name T1136
Test name
Test status
Simulation time 36522423 ps
CPU time 1 seconds
Started Aug 10 05:29:42 PM PDT 24
Finished Aug 10 05:29:44 PM PDT 24
Peak memory 216452 kb
Host smart-ed3dbce8-f389-4bd0-afa1-185f14a5cb03
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262980639 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.1262980
639 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.3188802096
Short name T1130
Test name
Test status
Simulation time 326326658 ps
CPU time 2.44 seconds
Started Aug 10 05:29:39 PM PDT 24
Finished Aug 10 05:29:41 PM PDT 24
Peak memory 221444 kb
Host smart-5e4a5165-7845-451f-b5ca-6859f4f0411a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188802096 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.kmac_csr_mem_rw_with_rand_reset.3188802096 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_rw.1175845491
Short name T1150
Test name
Test status
Simulation time 39964784 ps
CPU time 0.93 seconds
Started Aug 10 05:29:41 PM PDT 24
Finished Aug 10 05:29:42 PM PDT 24
Peak memory 216124 kb
Host smart-9a02ea1f-9c19-47df-b7bd-6b1e0bd0ca91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175845491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.1175845491 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_intr_test.3048174730
Short name T1066
Test name
Test status
Simulation time 37853524 ps
CPU time 0.81 seconds
Started Aug 10 05:29:44 PM PDT 24
Finished Aug 10 05:29:45 PM PDT 24
Peak memory 216372 kb
Host smart-a4f56a3b-775f-454c-a272-e5c42d61c25c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048174730 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.3048174730 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.638123461
Short name T1059
Test name
Test status
Simulation time 68352870 ps
CPU time 1.5 seconds
Started Aug 10 05:29:43 PM PDT 24
Finished Aug 10 05:29:44 PM PDT 24
Peak memory 216564 kb
Host smart-ae9110b4-1741-4817-ad5a-19a305ade0bd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638123461 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partial
_access.638123461 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_mem_walk.2438168884
Short name T1107
Test name
Test status
Simulation time 11653688 ps
CPU time 0.8 seconds
Started Aug 10 05:29:37 PM PDT 24
Finished Aug 10 05:29:38 PM PDT 24
Peak memory 216088 kb
Host smart-31201f31-54e1-4221-8dd3-dc69d241d0a3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438168884 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.2438168884
+enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.3827498658
Short name T166
Test name
Test status
Simulation time 191653931 ps
CPU time 1.44 seconds
Started Aug 10 05:29:38 PM PDT 24
Finished Aug 10 05:29:40 PM PDT 24
Peak memory 216424 kb
Host smart-99de45d6-996a-4ccf-b45d-fafdacfb52ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827498658 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr
_outstanding.3827498658 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.1788998171
Short name T103
Test name
Test status
Simulation time 96635179 ps
CPU time 1.09 seconds
Started Aug 10 05:29:39 PM PDT 24
Finished Aug 10 05:29:40 PM PDT 24
Peak memory 217076 kb
Host smart-404c9be7-1372-4d81-abe4-2d1752de8142
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788998171 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_
errors.1788998171 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.100372947
Short name T108
Test name
Test status
Simulation time 155983835 ps
CPU time 2.76 seconds
Started Aug 10 05:29:39 PM PDT 24
Finished Aug 10 05:29:42 PM PDT 24
Peak memory 220048 kb
Host smart-1f76cd56-4452-49fb-a112-ad4e2fcdcc9e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100372947 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_
shadow_reg_errors_with_csr_rw.100372947 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_tl_errors.178410104
Short name T184
Test name
Test status
Simulation time 962517531 ps
CPU time 3.86 seconds
Started Aug 10 05:29:41 PM PDT 24
Finished Aug 10 05:29:45 PM PDT 24
Peak memory 216708 kb
Host smart-5a1cad63-46b7-465a-a81e-f6c2bca42049
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178410104 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.178410104 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/4.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.kmac_intr_test.2685333438
Short name T1198
Test name
Test status
Simulation time 29394686 ps
CPU time 0.83 seconds
Started Aug 10 05:30:04 PM PDT 24
Finished Aug 10 05:30:04 PM PDT 24
Peak memory 216388 kb
Host smart-65d813a5-b2be-4cf0-a88e-49db42a823b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685333438 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.2685333438 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.kmac_intr_test.4037198218
Short name T1181
Test name
Test status
Simulation time 13989483 ps
CPU time 0.79 seconds
Started Aug 10 05:30:05 PM PDT 24
Finished Aug 10 05:30:06 PM PDT 24
Peak memory 216412 kb
Host smart-1cd4d547-eb73-4d31-86e5-923bcd768f81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037198218 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.4037198218 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.kmac_intr_test.3418925163
Short name T1069
Test name
Test status
Simulation time 17247961 ps
CPU time 0.87 seconds
Started Aug 10 05:30:04 PM PDT 24
Finished Aug 10 05:30:05 PM PDT 24
Peak memory 216340 kb
Host smart-b82a70e8-0282-4745-be9d-38e911bb8c2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418925163 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.3418925163 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.kmac_intr_test.3029911016
Short name T1095
Test name
Test status
Simulation time 82293371 ps
CPU time 0.82 seconds
Started Aug 10 05:30:03 PM PDT 24
Finished Aug 10 05:30:04 PM PDT 24
Peak memory 216372 kb
Host smart-96116a9f-1b3d-48d1-b524-60932231c549
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029911016 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.3029911016 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.kmac_intr_test.1430851587
Short name T1148
Test name
Test status
Simulation time 16235471 ps
CPU time 0.82 seconds
Started Aug 10 05:30:02 PM PDT 24
Finished Aug 10 05:30:03 PM PDT 24
Peak memory 216168 kb
Host smart-eb1bdec1-4d28-438e-9d2d-9cad345dcc6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430851587 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.1430851587 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.kmac_intr_test.1619597213
Short name T1133
Test name
Test status
Simulation time 29460128 ps
CPU time 0.8 seconds
Started Aug 10 05:30:03 PM PDT 24
Finished Aug 10 05:30:04 PM PDT 24
Peak memory 216380 kb
Host smart-416ea7b5-b83b-4cd9-b8ce-47e6340c4c62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619597213 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.1619597213 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.kmac_intr_test.2764152533
Short name T1081
Test name
Test status
Simulation time 13687312 ps
CPU time 0.76 seconds
Started Aug 10 05:30:04 PM PDT 24
Finished Aug 10 05:30:04 PM PDT 24
Peak memory 216312 kb
Host smart-7af1709c-cebe-4141-8b30-d622082e69a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764152533 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.2764152533 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.kmac_intr_test.131221543
Short name T1183
Test name
Test status
Simulation time 44845551 ps
CPU time 0.81 seconds
Started Aug 10 05:30:12 PM PDT 24
Finished Aug 10 05:30:12 PM PDT 24
Peak memory 216384 kb
Host smart-35068b70-4d6c-4115-9adf-641f4cb11575
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131221543 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.131221543 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/47.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.kmac_intr_test.1337624047
Short name T142
Test name
Test status
Simulation time 24367117 ps
CPU time 0.79 seconds
Started Aug 10 05:30:12 PM PDT 24
Finished Aug 10 05:30:13 PM PDT 24
Peak memory 216304 kb
Host smart-e2a9b15d-239a-4664-993c-53e45c4775e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337624047 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.1337624047 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.kmac_intr_test.1978897969
Short name T1115
Test name
Test status
Simulation time 45598984 ps
CPU time 0.81 seconds
Started Aug 10 05:30:15 PM PDT 24
Finished Aug 10 05:30:16 PM PDT 24
Peak memory 216396 kb
Host smart-f7d61ebc-6c08-4930-9c98-fc3653919f61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978897969 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.1978897969 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.2029195309
Short name T1193
Test name
Test status
Simulation time 305153363 ps
CPU time 2.43 seconds
Started Aug 10 05:29:41 PM PDT 24
Finished Aug 10 05:29:43 PM PDT 24
Peak memory 222412 kb
Host smart-397a2f88-4f9e-4eda-b1eb-2e8774a6013d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029195309 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.kmac_csr_mem_rw_with_rand_reset.2029195309 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_csr_rw.1891917680
Short name T1058
Test name
Test status
Simulation time 46274426 ps
CPU time 1.15 seconds
Started Aug 10 05:29:40 PM PDT 24
Finished Aug 10 05:29:42 PM PDT 24
Peak memory 216536 kb
Host smart-c5da5a19-78dc-469f-b12b-d968d82102d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891917680 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.1891917680 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_intr_test.611269538
Short name T1176
Test name
Test status
Simulation time 40837837 ps
CPU time 0.76 seconds
Started Aug 10 05:29:37 PM PDT 24
Finished Aug 10 05:29:38 PM PDT 24
Peak memory 216324 kb
Host smart-d0b49ab5-0dc6-4791-9d39-5c6936011b49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611269538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.611269538 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/5.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.3639027385
Short name T1147
Test name
Test status
Simulation time 146291413 ps
CPU time 2.25 seconds
Started Aug 10 05:29:40 PM PDT 24
Finished Aug 10 05:29:42 PM PDT 24
Peak memory 216532 kb
Host smart-b5a55cd9-6fee-4b2b-a71d-4d90e72c0863
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639027385 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr
_outstanding.3639027385 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.246652726
Short name T113
Test name
Test status
Simulation time 53672373 ps
CPU time 1.32 seconds
Started Aug 10 05:29:41 PM PDT 24
Finished Aug 10 05:29:42 PM PDT 24
Peak memory 216972 kb
Host smart-665bacbc-c918-4aa4-a4d2-61e6c504fe28
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246652726 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_e
rrors.246652726 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.3279891892
Short name T99
Test name
Test status
Simulation time 172318716 ps
CPU time 2.54 seconds
Started Aug 10 05:29:38 PM PDT 24
Finished Aug 10 05:29:41 PM PDT 24
Peak memory 220208 kb
Host smart-37dad568-2f25-4031-9695-a203e7cbc67f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279891892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac
_shadow_reg_errors_with_csr_rw.3279891892 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_tl_errors.3931573361
Short name T144
Test name
Test status
Simulation time 137608142 ps
CPU time 1.93 seconds
Started Aug 10 05:29:39 PM PDT 24
Finished Aug 10 05:29:41 PM PDT 24
Peak memory 216732 kb
Host smart-96fd72ba-1686-44fb-895e-7d887bd75d6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931573361 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.3931573361 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.1516433061
Short name T194
Test name
Test status
Simulation time 972364106 ps
CPU time 5.2 seconds
Started Aug 10 05:29:38 PM PDT 24
Finished Aug 10 05:29:44 PM PDT 24
Peak memory 216428 kb
Host smart-c4c6659e-3f3c-430d-ad0d-db85a6e872a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516433061 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.15164
33061 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.4467983
Short name T1156
Test name
Test status
Simulation time 36372615 ps
CPU time 2.61 seconds
Started Aug 10 05:29:40 PM PDT 24
Finished Aug 10 05:29:43 PM PDT 24
Peak memory 221268 kb
Host smart-2271a6f2-7456-4500-901e-5a9edfb7ed2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4467983 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.kmac_csr_mem_rw_with_rand_reset.4467983 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_csr_rw.129374996
Short name T1139
Test name
Test status
Simulation time 100890093 ps
CPU time 1.13 seconds
Started Aug 10 05:29:40 PM PDT 24
Finished Aug 10 05:29:41 PM PDT 24
Peak memory 216352 kb
Host smart-58e4f012-8842-49f8-b8cb-26180232720b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129374996 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.129374996 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/6.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_intr_test.215895195
Short name T1105
Test name
Test status
Simulation time 36891796 ps
CPU time 0.79 seconds
Started Aug 10 05:29:41 PM PDT 24
Finished Aug 10 05:29:42 PM PDT 24
Peak memory 216348 kb
Host smart-16fb31be-cd39-4b6f-8267-fd81c1dccefd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215895195 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.215895195 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/6.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.4198231325
Short name T1108
Test name
Test status
Simulation time 322839020 ps
CPU time 1.81 seconds
Started Aug 10 05:29:40 PM PDT 24
Finished Aug 10 05:29:42 PM PDT 24
Peak memory 216580 kb
Host smart-5efe04c4-0630-4bf4-a2eb-63f9795a66dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198231325 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr
_outstanding.4198231325 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.1992177810
Short name T134
Test name
Test status
Simulation time 60279434 ps
CPU time 0.84 seconds
Started Aug 10 05:29:39 PM PDT 24
Finished Aug 10 05:29:40 PM PDT 24
Peak memory 216276 kb
Host smart-1a5aaba0-fbbf-4607-95a5-ed01ac0edd74
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992177810 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_
errors.1992177810 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.986309590
Short name T1113
Test name
Test status
Simulation time 23228036 ps
CPU time 1.51 seconds
Started Aug 10 05:29:37 PM PDT 24
Finished Aug 10 05:29:39 PM PDT 24
Peak memory 216496 kb
Host smart-a2971fdd-b5ed-4912-8eb8-7fd86ee1e542
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986309590 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_
shadow_reg_errors_with_csr_rw.986309590 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_tl_errors.569276423
Short name T1138
Test name
Test status
Simulation time 413531458 ps
CPU time 2.81 seconds
Started Aug 10 05:29:41 PM PDT 24
Finished Aug 10 05:29:44 PM PDT 24
Peak memory 216652 kb
Host smart-82e8fbf7-b1ab-489b-8847-7948fe8fcf83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569276423 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.569276423 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/6.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.1559723769
Short name T193
Test name
Test status
Simulation time 144729664 ps
CPU time 2.71 seconds
Started Aug 10 05:29:39 PM PDT 24
Finished Aug 10 05:29:42 PM PDT 24
Peak memory 216484 kb
Host smart-c6b1112c-e9aa-4ee3-82a1-45ba4552359c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559723769 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.15597
23769 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.3536319835
Short name T1123
Test name
Test status
Simulation time 251826700 ps
CPU time 2.25 seconds
Started Aug 10 05:29:42 PM PDT 24
Finished Aug 10 05:29:45 PM PDT 24
Peak memory 221700 kb
Host smart-b885c02a-08c5-4547-8ed4-ef55bbc7da6c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536319835 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.kmac_csr_mem_rw_with_rand_reset.3536319835 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_csr_rw.304281813
Short name T1096
Test name
Test status
Simulation time 16643352 ps
CPU time 0.95 seconds
Started Aug 10 05:29:42 PM PDT 24
Finished Aug 10 05:29:43 PM PDT 24
Peak memory 216296 kb
Host smart-9242c2c5-dca1-447d-9a95-13bbd2c8ea8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304281813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.304281813 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/7.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_intr_test.1168889669
Short name T1106
Test name
Test status
Simulation time 31364931 ps
CPU time 0.81 seconds
Started Aug 10 05:29:44 PM PDT 24
Finished Aug 10 05:29:45 PM PDT 24
Peak memory 216348 kb
Host smart-4053842b-3b2b-43e3-8696-2ac903cd6875
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168889669 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.1168889669 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.2830495156
Short name T1071
Test name
Test status
Simulation time 80508715 ps
CPU time 1.47 seconds
Started Aug 10 05:29:41 PM PDT 24
Finished Aug 10 05:29:42 PM PDT 24
Peak memory 216552 kb
Host smart-3d95339f-da71-4e7a-b6d5-05baf2ae1ad5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830495156 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr
_outstanding.2830495156 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.3602713869
Short name T1070
Test name
Test status
Simulation time 115806484 ps
CPU time 1.03 seconds
Started Aug 10 05:29:40 PM PDT 24
Finished Aug 10 05:29:41 PM PDT 24
Peak memory 216548 kb
Host smart-13a0d718-ef23-432a-9352-bc39f0dd6cdb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602713869 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_
errors.3602713869 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.1912701597
Short name T1143
Test name
Test status
Simulation time 60226644 ps
CPU time 1.86 seconds
Started Aug 10 05:29:39 PM PDT 24
Finished Aug 10 05:29:41 PM PDT 24
Peak memory 219252 kb
Host smart-996c46cc-f2c9-4b3d-bf55-ba65a9325a9e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912701597 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac
_shadow_reg_errors_with_csr_rw.1912701597 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_tl_errors.2680456770
Short name T1129
Test name
Test status
Simulation time 223921451 ps
CPU time 3.02 seconds
Started Aug 10 05:29:39 PM PDT 24
Finished Aug 10 05:29:42 PM PDT 24
Peak memory 216680 kb
Host smart-cb980539-8749-44ac-b365-411868dc92ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680456770 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.2680456770 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.3315318626
Short name T1082
Test name
Test status
Simulation time 2350827665 ps
CPU time 5.02 seconds
Started Aug 10 05:29:42 PM PDT 24
Finished Aug 10 05:29:48 PM PDT 24
Peak memory 216832 kb
Host smart-133fc6da-3223-4e9a-b006-d17a4757b05d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315318626 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.33153
18626 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.74830960
Short name T1194
Test name
Test status
Simulation time 73582091 ps
CPU time 1.61 seconds
Started Aug 10 05:29:50 PM PDT 24
Finished Aug 10 05:29:52 PM PDT 24
Peak memory 219716 kb
Host smart-ed3bd803-3a64-40fe-b920-3af467bb9307
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74830960 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.kmac_csr_mem_rw_with_rand_reset.74830960 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_csr_rw.2798923738
Short name T1062
Test name
Test status
Simulation time 32094560 ps
CPU time 1.2 seconds
Started Aug 10 05:29:50 PM PDT 24
Finished Aug 10 05:29:51 PM PDT 24
Peak memory 216568 kb
Host smart-252e83e2-6f4f-4ad1-91c8-a45d7671443b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798923738 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.2798923738 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_intr_test.2583254705
Short name T173
Test name
Test status
Simulation time 30741131 ps
CPU time 0.83 seconds
Started Aug 10 05:29:49 PM PDT 24
Finished Aug 10 05:29:51 PM PDT 24
Peak memory 216396 kb
Host smart-7bb95871-38bc-4395-ba7c-3fe1bfec2100
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583254705 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.2583254705 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.3189911230
Short name T1205
Test name
Test status
Simulation time 58915444 ps
CPU time 2.18 seconds
Started Aug 10 05:29:52 PM PDT 24
Finished Aug 10 05:29:54 PM PDT 24
Peak memory 216600 kb
Host smart-dc39738e-6dda-495f-958a-66febd5079b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189911230 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr
_outstanding.3189911230 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.3537753033
Short name T98
Test name
Test status
Simulation time 82446596 ps
CPU time 1.13 seconds
Started Aug 10 05:29:44 PM PDT 24
Finished Aug 10 05:29:46 PM PDT 24
Peak memory 216812 kb
Host smart-83607b67-920e-4009-931c-515e19438b10
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537753033 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_
errors.3537753033 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.597825008
Short name T1144
Test name
Test status
Simulation time 171247685 ps
CPU time 2.54 seconds
Started Aug 10 05:29:44 PM PDT 24
Finished Aug 10 05:29:47 PM PDT 24
Peak memory 219976 kb
Host smart-ab9aafc9-495d-45c1-a79c-f6988bb7b962
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597825008 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_
shadow_reg_errors_with_csr_rw.597825008 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_tl_errors.2210215912
Short name T1187
Test name
Test status
Simulation time 805365968 ps
CPU time 4.24 seconds
Started Aug 10 05:29:43 PM PDT 24
Finished Aug 10 05:29:47 PM PDT 24
Peak memory 216640 kb
Host smart-7d4c4158-fe50-48a8-9f3a-842a073709cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210215912 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.2210215912 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.4279777533
Short name T191
Test name
Test status
Simulation time 198577889 ps
CPU time 2.65 seconds
Started Aug 10 05:29:46 PM PDT 24
Finished Aug 10 05:29:48 PM PDT 24
Peak memory 216576 kb
Host smart-42ff01f3-2431-4c5f-b66b-7f4dd4449b6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279777533 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.42797
77533 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.3343279808
Short name T1191
Test name
Test status
Simulation time 152870928 ps
CPU time 1.66 seconds
Started Aug 10 05:29:47 PM PDT 24
Finished Aug 10 05:29:49 PM PDT 24
Peak memory 219896 kb
Host smart-8c606658-53b6-47a2-867e-05a6b5ee09e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343279808 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.kmac_csr_mem_rw_with_rand_reset.3343279808 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_csr_rw.481925757
Short name T1079
Test name
Test status
Simulation time 35178960 ps
CPU time 1 seconds
Started Aug 10 05:29:49 PM PDT 24
Finished Aug 10 05:29:50 PM PDT 24
Peak memory 216316 kb
Host smart-9b4de1c9-d2f4-48b9-9e8a-d941951e0af7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481925757 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.481925757 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/9.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_intr_test.675312322
Short name T182
Test name
Test status
Simulation time 13988943 ps
CPU time 0.79 seconds
Started Aug 10 05:29:48 PM PDT 24
Finished Aug 10 05:29:49 PM PDT 24
Peak memory 216392 kb
Host smart-2d2a1a42-c818-472c-9e1c-b40cf413b28f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675312322 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.675312322 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/9.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.1161702316
Short name T1101
Test name
Test status
Simulation time 2124119076 ps
CPU time 3.41 seconds
Started Aug 10 05:29:50 PM PDT 24
Finished Aug 10 05:29:54 PM PDT 24
Peak memory 216404 kb
Host smart-da9001bc-a9df-4232-9beb-d2b56bb53af2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161702316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr
_outstanding.1161702316 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.1825155046
Short name T175
Test name
Test status
Simulation time 72238762 ps
CPU time 1 seconds
Started Aug 10 05:29:48 PM PDT 24
Finished Aug 10 05:29:50 PM PDT 24
Peak memory 216488 kb
Host smart-9c2b7dc8-6622-4c2a-b896-76f525bfd7a9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825155046 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_
errors.1825155046 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.3157183490
Short name T1196
Test name
Test status
Simulation time 182585673 ps
CPU time 2.54 seconds
Started Aug 10 05:29:48 PM PDT 24
Finished Aug 10 05:29:50 PM PDT 24
Peak memory 219492 kb
Host smart-ea13a99d-9ca0-4bc7-9557-bcd87faa3e1b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157183490 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac
_shadow_reg_errors_with_csr_rw.3157183490 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_tl_errors.3254183170
Short name T1162
Test name
Test status
Simulation time 555487181 ps
CPU time 3.39 seconds
Started Aug 10 05:29:52 PM PDT 24
Finished Aug 10 05:29:56 PM PDT 24
Peak memory 216716 kb
Host smart-42d796a8-d95a-470a-8086-dd833547b479
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254183170 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.3254183170 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.202225624
Short name T148
Test name
Test status
Simulation time 898350760 ps
CPU time 5.19 seconds
Started Aug 10 05:29:53 PM PDT 24
Finished Aug 10 05:29:58 PM PDT 24
Peak memory 216552 kb
Host smart-5fc0be85-6b45-4f88-924b-8a60fff26518
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202225624 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.202225
624 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.kmac_alert_test.3845121715
Short name T797
Test name
Test status
Simulation time 188943601 ps
CPU time 0.95 seconds
Started Aug 10 06:28:57 PM PDT 24
Finished Aug 10 06:28:58 PM PDT 24
Peak memory 218556 kb
Host smart-f238f61e-cce5-496e-a67b-e34de5740fe6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845121715 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.3845121715 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_alert_test/latest

Test location /workspace/coverage/default/0.kmac_app.3804239802
Short name T130
Test name
Test status
Simulation time 2799767124 ps
CPU time 150.41 seconds
Started Aug 10 06:28:48 PM PDT 24
Finished Aug 10 06:31:18 PM PDT 24
Peak memory 277076 kb
Host smart-6df213ed-da14-4c0d-a65a-b6166b98c53d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804239802 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.3804239802 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/0.kmac_app/latest

Test location /workspace/coverage/default/0.kmac_app_with_partial_data.101440848
Short name T911
Test name
Test status
Simulation time 9407407070 ps
CPU time 347.88 seconds
Started Aug 10 06:28:47 PM PDT 24
Finished Aug 10 06:34:35 PM PDT 24
Peak memory 334360 kb
Host smart-6c35a1eb-6a6b-45eb-9926-22bbe52e851d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101440848 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_parti
al_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_part
ial_data.101440848 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/0.kmac_burst_write.946624860
Short name T296
Test name
Test status
Simulation time 34629919464 ps
CPU time 505.58 seconds
Started Aug 10 06:28:36 PM PDT 24
Finished Aug 10 06:37:02 PM PDT 24
Peak memory 241372 kb
Host smart-90651abf-a975-4f90-be00-ba3a272e49c4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946624860 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.946624860 +
enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_burst_write/latest

Test location /workspace/coverage/default/0.kmac_entropy_mode_error.100245841
Short name T1025
Test name
Test status
Simulation time 29727446 ps
CPU time 1.21 seconds
Started Aug 10 06:28:47 PM PDT 24
Finished Aug 10 06:28:48 PM PDT 24
Peak memory 222092 kb
Host smart-83a7572f-d22b-46c8-8654-1903654d0515
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=100245841 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.100245841 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_refresh.667124916
Short name T490
Test name
Test status
Simulation time 91421574 ps
CPU time 4.7 seconds
Started Aug 10 06:28:49 PM PDT 24
Finished Aug 10 06:28:54 PM PDT 24
Peak memory 224704 kb
Host smart-3c836769-daed-4623-8ccb-3a6c6a8ef6f9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667124916 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.667
124916 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/0.kmac_error.2300939836
Short name T25
Test name
Test status
Simulation time 15134945639 ps
CPU time 108.09 seconds
Started Aug 10 06:28:46 PM PDT 24
Finished Aug 10 06:30:34 PM PDT 24
Peak memory 308128 kb
Host smart-a6225116-8f37-4d03-951c-f2b40b60a988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300939836 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.2300939836 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_error/latest

Test location /workspace/coverage/default/0.kmac_key_error.237455579
Short name T999
Test name
Test status
Simulation time 2011935111 ps
CPU time 8.8 seconds
Started Aug 10 06:28:46 PM PDT 24
Finished Aug 10 06:28:55 PM PDT 24
Peak memory 226760 kb
Host smart-33707613-78b5-48fb-a0d5-d5a2026c7a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237455579 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.237455579 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_key_error/latest

Test location /workspace/coverage/default/0.kmac_lc_escalation.3573380340
Short name T591
Test name
Test status
Simulation time 294958986 ps
CPU time 1.5 seconds
Started Aug 10 06:28:47 PM PDT 24
Finished Aug 10 06:28:49 PM PDT 24
Peak memory 226876 kb
Host smart-88b2e3ab-f0b4-4c50-91db-3815e084ffc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573380340 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.3573380340 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/0.kmac_lc_escalation/latest

Test location /workspace/coverage/default/0.kmac_long_msg_and_output.3801808795
Short name T448
Test name
Test status
Simulation time 60641802270 ps
CPU time 624.65 seconds
Started Aug 10 06:28:37 PM PDT 24
Finished Aug 10 06:39:02 PM PDT 24
Peak memory 904120 kb
Host smart-15ee1d85-994e-4451-a97b-539fb28e3e2a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801808795 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_an
d_output.3801808795 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/0.kmac_sec_cm.4057163531
Short name T124
Test name
Test status
Simulation time 106482240616 ps
CPU time 100.34 seconds
Started Aug 10 06:28:56 PM PDT 24
Finished Aug 10 06:30:36 PM PDT 24
Peak memory 290472 kb
Host smart-f03585a6-d227-447e-834d-9eea19597880
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057163531 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.4057163531 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspace/0.kmac_sec_cm/latest

Test location /workspace/coverage/default/0.kmac_sideload.2656079828
Short name T21
Test name
Test status
Simulation time 3484889163 ps
CPU time 152.84 seconds
Started Aug 10 06:28:37 PM PDT 24
Finished Aug 10 06:31:10 PM PDT 24
Peak memory 273044 kb
Host smart-21cfd7ad-8e0c-4404-b55d-a64fb88a5680
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656079828 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.2656079828 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_sideload/latest

Test location /workspace/coverage/default/0.kmac_smoke.621376668
Short name T1010
Test name
Test status
Simulation time 2728251853 ps
CPU time 9.53 seconds
Started Aug 10 06:28:26 PM PDT 24
Finished Aug 10 06:28:36 PM PDT 24
Peak memory 226808 kb
Host smart-45655543-98b5-4b2b-9695-687d2ab546f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621376668 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.621376668 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_smoke/latest

Test location /workspace/coverage/default/0.kmac_stress_all.3275350058
Short name T1015
Test name
Test status
Simulation time 17826994064 ps
CPU time 1605.77 seconds
Started Aug 10 06:28:47 PM PDT 24
Finished Aug 10 06:55:33 PM PDT 24
Peak memory 673860 kb
Host smart-434dc297-1c3b-4263-bfb8-396420debc33
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3275350058 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.3275350058 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_stress_all/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_kmac.605407817
Short name T425
Test name
Test status
Simulation time 513485870 ps
CPU time 6.82 seconds
Started Aug 10 06:28:46 PM PDT 24
Finished Aug 10 06:28:53 PM PDT 24
Peak memory 220176 kb
Host smart-516615c5-96db-4956-bb6b-e22b95eb36ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605407817 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.kmac_test_vectors_kmac.605407817 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_kmac_xof.46067501
Short name T854
Test name
Test status
Simulation time 133914544 ps
CPU time 6.51 seconds
Started Aug 10 06:28:46 PM PDT 24
Finished Aug 10 06:28:53 PM PDT 24
Peak memory 218892 kb
Host smart-bd6bb5b3-0112-4565-97c0-c030e8fa8f33
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46067501 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.kmac_test_vectors_kmac_xof.46067501 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_224.2746867875
Short name T822
Test name
Test status
Simulation time 148966518457 ps
CPU time 3096.44 seconds
Started Aug 10 06:28:37 PM PDT 24
Finished Aug 10 07:20:14 PM PDT 24
Peak memory 3140372 kb
Host smart-0fb3c358-aa2f-4e44-8f73-737d38a83de2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2746867875 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.2746867875 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_256.3599872481
Short name T386
Test name
Test status
Simulation time 192988741176 ps
CPU time 3471.52 seconds
Started Aug 10 06:28:49 PM PDT 24
Finished Aug 10 07:26:41 PM PDT 24
Peak memory 3041416 kb
Host smart-1fb8590a-45d3-4ce3-96b2-aeec259912b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3599872481 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.3599872481 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_384.3116879947
Short name T330
Test name
Test status
Simulation time 60527628573 ps
CPU time 1594.34 seconds
Started Aug 10 06:28:47 PM PDT 24
Finished Aug 10 06:55:21 PM PDT 24
Peak memory 931964 kb
Host smart-4ee660cc-5547-461b-a6cc-b835264211d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3116879947 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.3116879947 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_512.2315504976
Short name T36
Test name
Test status
Simulation time 101378599500 ps
CPU time 1752.59 seconds
Started Aug 10 06:28:46 PM PDT 24
Finished Aug 10 06:57:59 PM PDT 24
Peak memory 1716752 kb
Host smart-a35a6b8d-2a03-4d82-a550-3194186aadf3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2315504976 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.2315504976 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_shake_128.1815546063
Short name T861
Test name
Test status
Simulation time 189795687756 ps
CPU time 10772.5 seconds
Started Aug 10 06:28:45 PM PDT 24
Finished Aug 10 09:28:19 PM PDT 24
Peak memory 7655844 kb
Host smart-dd82eb69-f916-4ca9-8d3b-da934fe7883a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1815546063 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.1815546063 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_shake_256.3989548631
Short name T931
Test name
Test status
Simulation time 1001366192818 ps
CPU time 10338.1 seconds
Started Aug 10 06:28:47 PM PDT 24
Finished Aug 10 09:21:06 PM PDT 24
Peak memory 6386320 kb
Host smart-bcd13dc5-2b52-4dba-90d3-57c8f29a9f8d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3989548631 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.3989548631 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/1.kmac_alert_test.682872201
Short name T644
Test name
Test status
Simulation time 58531615 ps
CPU time 0.88 seconds
Started Aug 10 06:29:14 PM PDT 24
Finished Aug 10 06:29:15 PM PDT 24
Peak memory 218552 kb
Host smart-7f30ff63-b588-4ed8-8514-4c9b422f80fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682872201 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.682872201 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/1.kmac_alert_test/latest

Test location /workspace/coverage/default/1.kmac_app.949191498
Short name T768
Test name
Test status
Simulation time 14387778541 ps
CPU time 409.18 seconds
Started Aug 10 06:29:04 PM PDT 24
Finished Aug 10 06:35:54 PM PDT 24
Peak memory 509316 kb
Host smart-db63ac5a-bcf6-49cf-8b71-70d1419d6824
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949191498 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.949191498 +enable_masking=1
+sw_key_masked=0
Directory /workspace/1.kmac_app/latest

Test location /workspace/coverage/default/1.kmac_app_with_partial_data.3525975589
Short name T665
Test name
Test status
Simulation time 11243549658 ps
CPU time 72.8 seconds
Started Aug 10 06:29:05 PM PDT 24
Finished Aug 10 06:30:18 PM PDT 24
Peak memory 245364 kb
Host smart-4a7362b1-5929-4507-80ac-ee3525778c5d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525975589 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_par
tial_data.3525975589 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/1.kmac_burst_write.1188486737
Short name T486
Test name
Test status
Simulation time 12938231059 ps
CPU time 667.13 seconds
Started Aug 10 06:28:56 PM PDT 24
Finished Aug 10 06:40:04 PM PDT 24
Peak memory 248636 kb
Host smart-142bf7c6-4d3b-4d76-b522-c615fc842e36
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188486737 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.1188486737
+enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_burst_write/latest

Test location /workspace/coverage/default/1.kmac_edn_timeout_error.3198142612
Short name T633
Test name
Test status
Simulation time 38388729 ps
CPU time 1.16 seconds
Started Aug 10 06:29:14 PM PDT 24
Finished Aug 10 06:29:15 PM PDT 24
Peak memory 218680 kb
Host smart-6a8a11bb-c0d5-4e4f-93a8-ccfd5b6ee49e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3198142612 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.3198142612 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_mode_error.601554100
Short name T791
Test name
Test status
Simulation time 26661422 ps
CPU time 0.93 seconds
Started Aug 10 06:29:17 PM PDT 24
Finished Aug 10 06:29:19 PM PDT 24
Peak memory 219832 kb
Host smart-6a9419fc-2a2c-4d7b-86c9-c1a9b5ce8edb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=601554100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.601554100 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_ready_error.58935968
Short name T809
Test name
Test status
Simulation time 1650800806 ps
CPU time 18.1 seconds
Started Aug 10 06:29:14 PM PDT 24
Finished Aug 10 06:29:32 PM PDT 24
Peak memory 226992 kb
Host smart-e9d69aa4-04c5-44e3-ad0e-9484cd676f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58935968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.58935968 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_refresh.48309568
Short name T796
Test name
Test status
Simulation time 2032006491 ps
CPU time 17.36 seconds
Started Aug 10 06:29:06 PM PDT 24
Finished Aug 10 06:29:23 PM PDT 24
Peak memory 229052 kb
Host smart-d325a342-cd55-4db5-ab18-ec778335fa56
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48309568 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.4830
9568 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/1.kmac_error.2986565842
Short name T241
Test name
Test status
Simulation time 15101256297 ps
CPU time 201.25 seconds
Started Aug 10 06:29:06 PM PDT 24
Finished Aug 10 06:32:27 PM PDT 24
Peak memory 396348 kb
Host smart-7d8b929e-ee0b-4b36-b9bc-6d6cbc23c153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986565842 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.2986565842 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_error/latest

Test location /workspace/coverage/default/1.kmac_key_error.109087642
Short name T841
Test name
Test status
Simulation time 2812178427 ps
CPU time 5.62 seconds
Started Aug 10 06:29:08 PM PDT 24
Finished Aug 10 06:29:13 PM PDT 24
Peak memory 226836 kb
Host smart-d0b0bbca-4fde-49bb-9f4a-08baf891fb11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109087642 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.109087642 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_key_error/latest

Test location /workspace/coverage/default/1.kmac_lc_escalation.1419777824
Short name T73
Test name
Test status
Simulation time 653062563 ps
CPU time 38.19 seconds
Started Aug 10 06:29:14 PM PDT 24
Finished Aug 10 06:29:53 PM PDT 24
Peak memory 244508 kb
Host smart-c7e7b184-83d0-4119-ad93-8209df90bf5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419777824 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.1419777824 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/1.kmac_lc_escalation/latest

Test location /workspace/coverage/default/1.kmac_long_msg_and_output.1903243676
Short name T222
Test name
Test status
Simulation time 409733503351 ps
CPU time 4386.02 seconds
Started Aug 10 06:28:55 PM PDT 24
Finished Aug 10 07:42:02 PM PDT 24
Peak memory 3463052 kb
Host smart-d1a6ab84-da90-452a-a04f-b9719883123c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903243676 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_an
d_output.1903243676 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/1.kmac_sideload.762980795
Short name T812
Test name
Test status
Simulation time 1892273347 ps
CPU time 163.67 seconds
Started Aug 10 06:28:56 PM PDT 24
Finished Aug 10 06:31:39 PM PDT 24
Peak memory 279808 kb
Host smart-4e95da71-d641-4408-b1ea-39356f531ed1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762980795 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.762980795 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_sideload/latest

Test location /workspace/coverage/default/1.kmac_smoke.3024727348
Short name T994
Test name
Test status
Simulation time 1892141530 ps
CPU time 41.66 seconds
Started Aug 10 06:28:56 PM PDT 24
Finished Aug 10 06:29:38 PM PDT 24
Peak memory 226964 kb
Host smart-71950f44-9040-406b-b038-21d7090c0c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024727348 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.3024727348 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_smoke/latest

Test location /workspace/coverage/default/1.kmac_stress_all.690925674
Short name T280
Test name
Test status
Simulation time 3545884754 ps
CPU time 312.88 seconds
Started Aug 10 06:29:14 PM PDT 24
Finished Aug 10 06:34:27 PM PDT 24
Peak memory 276144 kb
Host smart-aa822341-fbc9-4b3e-9945-a6cce290c9ae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=690925674 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.690925674 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_stress_all/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_kmac.1370522149
Short name T716
Test name
Test status
Simulation time 279062494 ps
CPU time 6.31 seconds
Started Aug 10 06:29:05 PM PDT 24
Finished Aug 10 06:29:11 PM PDT 24
Peak memory 219808 kb
Host smart-e9bd38e2-601a-431a-aaea-6743f0366730
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370522149 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.kmac_test_vectors_kmac.1370522149 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_kmac_xof.3447170737
Short name T311
Test name
Test status
Simulation time 254107358 ps
CPU time 5.92 seconds
Started Aug 10 06:29:08 PM PDT 24
Finished Aug 10 06:29:14 PM PDT 24
Peak memory 218996 kb
Host smart-4f47479a-8857-45a4-bcf2-ec07389a799f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447170737 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.kmac_test_vectors_kmac_xof.3447170737 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_224.4236978687
Short name T253
Test name
Test status
Simulation time 191825635741 ps
CPU time 3717.01 seconds
Started Aug 10 06:28:56 PM PDT 24
Finished Aug 10 07:30:53 PM PDT 24
Peak memory 3183460 kb
Host smart-dca1d676-3bd1-4123-a5fd-7a786bd7317b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4236978687 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.4236978687 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_256.270167123
Short name T365
Test name
Test status
Simulation time 97676052041 ps
CPU time 3628.05 seconds
Started Aug 10 06:28:54 PM PDT 24
Finished Aug 10 07:29:23 PM PDT 24
Peak memory 3101676 kb
Host smart-44e3a946-c4d4-4817-8b91-c950d5fb5e8b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=270167123 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.270167123 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_384.795804051
Short name T289
Test name
Test status
Simulation time 61748156978 ps
CPU time 1601.22 seconds
Started Aug 10 06:28:55 PM PDT 24
Finished Aug 10 06:55:37 PM PDT 24
Peak memory 908884 kb
Host smart-2f484e00-2cd4-4624-9e5a-a988fc064a85
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=795804051 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.795804051 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_512.4288186095
Short name T371
Test name
Test status
Simulation time 178590306349 ps
CPU time 1600.98 seconds
Started Aug 10 06:28:55 PM PDT 24
Finished Aug 10 06:55:37 PM PDT 24
Peak memory 1738732 kb
Host smart-9192825c-16a9-408f-b81a-d5bc300b5ec6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4288186095 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.4288186095 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_shake_128.1093189234
Short name T935
Test name
Test status
Simulation time 219926740863 ps
CPU time 6362.97 seconds
Started Aug 10 06:28:57 PM PDT 24
Finished Aug 10 08:15:00 PM PDT 24
Peak memory 2660952 kb
Host smart-94febfca-4000-4950-8466-d36862dcc4ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1093189234 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_128.1093189234 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_shake_256.3429600019
Short name T391
Test name
Test status
Simulation time 63051270738 ps
CPU time 5057.39 seconds
Started Aug 10 06:29:05 PM PDT 24
Finished Aug 10 07:53:23 PM PDT 24
Peak memory 2238356 kb
Host smart-91d211e6-db5b-4b9c-88df-6793b5f5d32c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3429600019 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.3429600019 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/10.kmac_app.1917637097
Short name T1037
Test name
Test status
Simulation time 11782452865 ps
CPU time 87.49 seconds
Started Aug 10 06:32:46 PM PDT 24
Finished Aug 10 06:34:14 PM PDT 24
Peak memory 278268 kb
Host smart-3c7f4336-7335-49ae-8966-5b5f110527d5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917637097 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.1917637097 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/10.kmac_app/latest

Test location /workspace/coverage/default/10.kmac_burst_write.3367825176
Short name T252
Test name
Test status
Simulation time 30726111513 ps
CPU time 687.55 seconds
Started Aug 10 06:32:41 PM PDT 24
Finished Aug 10 06:44:09 PM PDT 24
Peak memory 247260 kb
Host smart-f586375a-731e-473d-8b67-4b50ac23d19c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367825176 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.336782517
6 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_burst_write/latest

Test location /workspace/coverage/default/10.kmac_edn_timeout_error.3404729834
Short name T944
Test name
Test status
Simulation time 962879849 ps
CPU time 20.54 seconds
Started Aug 10 06:33:03 PM PDT 24
Finished Aug 10 06:33:24 PM PDT 24
Peak memory 226964 kb
Host smart-1a43bc65-f7df-4f2a-9bb4-3e7d543083f7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3404729834 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.3404729834 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/10.kmac_entropy_refresh.1783787299
Short name T62
Test name
Test status
Simulation time 4267175416 ps
CPU time 51.06 seconds
Started Aug 10 06:32:47 PM PDT 24
Finished Aug 10 06:33:38 PM PDT 24
Peak memory 261104 kb
Host smart-a4059a92-997e-4812-aefa-e7e752dca243
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783787299 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.1
783787299 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/10.kmac_error.3842159803
Short name T412
Test name
Test status
Simulation time 12887810385 ps
CPU time 370.83 seconds
Started Aug 10 06:32:55 PM PDT 24
Finished Aug 10 06:39:06 PM PDT 24
Peak memory 511332 kb
Host smart-f45ec1fc-0e43-4820-8259-020bc81755e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842159803 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.3842159803 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_error/latest

Test location /workspace/coverage/default/10.kmac_key_error.3906287991
Short name T789
Test name
Test status
Simulation time 5144620274 ps
CPU time 9.46 seconds
Started Aug 10 06:32:57 PM PDT 24
Finished Aug 10 06:33:07 PM PDT 24
Peak memory 226820 kb
Host smart-f20dcc85-8b58-459e-bea9-847aba4764ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906287991 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.3906287991 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_key_error/latest

Test location /workspace/coverage/default/10.kmac_lc_escalation.2898761550
Short name T411
Test name
Test status
Simulation time 137403962 ps
CPU time 1.38 seconds
Started Aug 10 06:33:02 PM PDT 24
Finished Aug 10 06:33:03 PM PDT 24
Peak memory 226908 kb
Host smart-171f623d-ff7d-4dae-a3d4-3b87b83566a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898761550 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.2898761550 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/10.kmac_lc_escalation/latest

Test location /workspace/coverage/default/10.kmac_long_msg_and_output.4031718346
Short name T473
Test name
Test status
Simulation time 11592419562 ps
CPU time 1267.72 seconds
Started Aug 10 06:32:33 PM PDT 24
Finished Aug 10 06:53:41 PM PDT 24
Peak memory 902864 kb
Host smart-032580ce-7c82-4d3d-96cb-fd1ea2a9227f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031718346 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_a
nd_output.4031718346 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/10.kmac_sideload.3194159736
Short name T274
Test name
Test status
Simulation time 181708442309 ps
CPU time 524.9 seconds
Started Aug 10 06:32:33 PM PDT 24
Finished Aug 10 06:41:18 PM PDT 24
Peak memory 576396 kb
Host smart-5f0c24c4-8209-4813-842a-3533afb2c3be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194159736 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.3194159736 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_sideload/latest

Test location /workspace/coverage/default/10.kmac_smoke.2866398784
Short name T892
Test name
Test status
Simulation time 2513560312 ps
CPU time 31.63 seconds
Started Aug 10 06:32:34 PM PDT 24
Finished Aug 10 06:33:05 PM PDT 24
Peak memory 226996 kb
Host smart-12eee711-6f6d-4b15-8314-326d34f92a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866398784 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.2866398784 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_smoke/latest

Test location /workspace/coverage/default/10.kmac_stress_all.700232422
Short name T653
Test name
Test status
Simulation time 18731099390 ps
CPU time 870.53 seconds
Started Aug 10 06:33:02 PM PDT 24
Finished Aug 10 06:47:33 PM PDT 24
Peak memory 334164 kb
Host smart-0eddf66d-50b2-4668-b0fc-f339a9cf4948
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=700232422 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.700232422 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_stress_all/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_kmac.2213867261
Short name T963
Test name
Test status
Simulation time 2193502724 ps
CPU time 6.63 seconds
Started Aug 10 06:32:49 PM PDT 24
Finished Aug 10 06:32:56 PM PDT 24
Peak memory 219892 kb
Host smart-e04ee404-801d-4c15-bd0c-8c0141b9ce4b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213867261 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.kmac_test_vectors_kmac.2213867261 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_kmac_xof.539512823
Short name T588
Test name
Test status
Simulation time 239496254 ps
CPU time 6.57 seconds
Started Aug 10 06:32:49 PM PDT 24
Finished Aug 10 06:32:55 PM PDT 24
Peak memory 219816 kb
Host smart-a954b8c3-aabe-4b61-b0d5-142d4ad7c3d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539512823 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.kmac_test_vectors_kmac_xof.539512823 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_224.2734112579
Short name T319
Test name
Test status
Simulation time 69076701382 ps
CPU time 3031.26 seconds
Started Aug 10 06:32:42 PM PDT 24
Finished Aug 10 07:23:14 PM PDT 24
Peak memory 3276308 kb
Host smart-0740f759-5a79-477c-aead-14b46f7b43f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2734112579 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_224.2734112579 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_256.3587487443
Short name T347
Test name
Test status
Simulation time 76691874331 ps
CPU time 2072.76 seconds
Started Aug 10 06:32:41 PM PDT 24
Finished Aug 10 07:07:14 PM PDT 24
Peak memory 1139476 kb
Host smart-d292830b-9917-48d8-89ce-b7fede57a000
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3587487443 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_256.3587487443 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_384.2113953197
Short name T339
Test name
Test status
Simulation time 308267090392 ps
CPU time 2520.67 seconds
Started Aug 10 06:32:41 PM PDT 24
Finished Aug 10 07:14:42 PM PDT 24
Peak memory 2403280 kb
Host smart-f0c3b8d6-af44-4687-8d73-5552fc453fa2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2113953197 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_384.2113953197 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_512.2183289792
Short name T978
Test name
Test status
Simulation time 10709226210 ps
CPU time 1292.45 seconds
Started Aug 10 06:32:40 PM PDT 24
Finished Aug 10 06:54:13 PM PDT 24
Peak memory 707668 kb
Host smart-0fc8a738-ab96-481e-ba04-e105fa3b5497
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2183289792 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_512.2183289792 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_shake_256.1101473100
Short name T293
Test name
Test status
Simulation time 197261187710 ps
CPU time 9646.82 seconds
Started Aug 10 06:32:47 PM PDT 24
Finished Aug 10 09:13:35 PM PDT 24
Peak memory 6322240 kb
Host smart-24ab6ab2-2c93-4259-90b1-8095b8e6b02b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1101473100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_shake_256.1101473100 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/11.kmac_alert_test.2299079448
Short name T759
Test name
Test status
Simulation time 20567275 ps
CPU time 0.84 seconds
Started Aug 10 06:33:23 PM PDT 24
Finished Aug 10 06:33:24 PM PDT 24
Peak memory 218564 kb
Host smart-d6d33271-1ee5-4add-806d-d35330bb780c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299079448 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.2299079448 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_alert_test/latest

Test location /workspace/coverage/default/11.kmac_app.632779069
Short name T364
Test name
Test status
Simulation time 4615972695 ps
CPU time 347.46 seconds
Started Aug 10 06:33:16 PM PDT 24
Finished Aug 10 06:39:04 PM PDT 24
Peak memory 329232 kb
Host smart-991c506b-8c4b-4546-9785-9ee207e11225
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632779069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.632779069 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/11.kmac_app/latest

Test location /workspace/coverage/default/11.kmac_burst_write.3533250077
Short name T638
Test name
Test status
Simulation time 27664267598 ps
CPU time 435.81 seconds
Started Aug 10 06:33:02 PM PDT 24
Finished Aug 10 06:40:18 PM PDT 24
Peak memory 243460 kb
Host smart-e6077245-4fc5-4874-8bc3-0674808dfff2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533250077 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.353325007
7 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_burst_write/latest

Test location /workspace/coverage/default/11.kmac_edn_timeout_error.2173584800
Short name T981
Test name
Test status
Simulation time 319344069 ps
CPU time 7.56 seconds
Started Aug 10 06:33:23 PM PDT 24
Finished Aug 10 06:33:31 PM PDT 24
Peak memory 236652 kb
Host smart-787251a9-5abc-4df0-8a24-91adc3b3295d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2173584800 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.2173584800 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/11.kmac_entropy_mode_error.439224256
Short name T67
Test name
Test status
Simulation time 42317434 ps
CPU time 1.29 seconds
Started Aug 10 06:33:26 PM PDT 24
Finished Aug 10 06:33:28 PM PDT 24
Peak memory 222528 kb
Host smart-bff81729-51fa-4356-aa91-0f4c462c7658
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=439224256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.439224256 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/11.kmac_entropy_refresh.3573557467
Short name T860
Test name
Test status
Simulation time 29071527743 ps
CPU time 359.76 seconds
Started Aug 10 06:33:15 PM PDT 24
Finished Aug 10 06:39:15 PM PDT 24
Peak memory 484636 kb
Host smart-46531dd0-c4d3-474f-a8e1-180e1c1e8993
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573557467 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.3
573557467 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/11.kmac_error.1384188721
Short name T967
Test name
Test status
Simulation time 40791164714 ps
CPU time 369.09 seconds
Started Aug 10 06:33:24 PM PDT 24
Finished Aug 10 06:39:33 PM PDT 24
Peak memory 511640 kb
Host smart-51e5c082-b415-466a-b8a6-d6764f139752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384188721 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.1384188721 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_error/latest

Test location /workspace/coverage/default/11.kmac_key_error.1129339282
Short name T331
Test name
Test status
Simulation time 3358689496 ps
CPU time 6.65 seconds
Started Aug 10 06:33:24 PM PDT 24
Finished Aug 10 06:33:31 PM PDT 24
Peak memory 226772 kb
Host smart-bcdf7635-81ee-4150-bbc7-141894228d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129339282 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.1129339282 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_key_error/latest

Test location /workspace/coverage/default/11.kmac_long_msg_and_output.1079062306
Short name T149
Test name
Test status
Simulation time 32952614880 ps
CPU time 1545.38 seconds
Started Aug 10 06:33:06 PM PDT 24
Finished Aug 10 06:58:51 PM PDT 24
Peak memory 1715556 kb
Host smart-16387093-dfa6-40a7-9eff-a164b777c785
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079062306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_a
nd_output.1079062306 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/11.kmac_sideload.2898109054
Short name T476
Test name
Test status
Simulation time 46288780430 ps
CPU time 236.74 seconds
Started Aug 10 06:33:01 PM PDT 24
Finished Aug 10 06:36:58 PM PDT 24
Peak memory 408624 kb
Host smart-c936a940-519d-4f4a-a1fa-1cb366cf00bb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898109054 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.2898109054 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_sideload/latest

Test location /workspace/coverage/default/11.kmac_smoke.1906472761
Short name T268
Test name
Test status
Simulation time 10272690040 ps
CPU time 57.89 seconds
Started Aug 10 06:33:07 PM PDT 24
Finished Aug 10 06:34:05 PM PDT 24
Peak memory 227124 kb
Host smart-1ec39e0f-36da-4306-9dfc-c93f5432f220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906472761 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.1906472761 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_smoke/latest

Test location /workspace/coverage/default/11.kmac_stress_all.383483941
Short name T477
Test name
Test status
Simulation time 3372110414 ps
CPU time 165.5 seconds
Started Aug 10 06:33:24 PM PDT 24
Finished Aug 10 06:36:09 PM PDT 24
Peak memory 282136 kb
Host smart-599549e6-121f-469f-bfc8-cec707fc2e9b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=383483941 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.383483941 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_stress_all/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_kmac.3740183553
Short name T129
Test name
Test status
Simulation time 110570469 ps
CPU time 5.67 seconds
Started Aug 10 06:33:16 PM PDT 24
Finished Aug 10 06:33:22 PM PDT 24
Peak memory 218896 kb
Host smart-a0d9723e-9c86-48c9-8603-3024de205659
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740183553 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.kmac_test_vectors_kmac.3740183553 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_kmac_xof.2454666099
Short name T554
Test name
Test status
Simulation time 547029623 ps
CPU time 5.71 seconds
Started Aug 10 06:33:18 PM PDT 24
Finished Aug 10 06:33:24 PM PDT 24
Peak memory 218972 kb
Host smart-5ad60d3c-684d-4b07-9344-3d0eec01a9ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454666099 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.kmac_test_vectors_kmac_xof.2454666099 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_224.875069547
Short name T3
Test name
Test status
Simulation time 80256160538 ps
CPU time 2028.13 seconds
Started Aug 10 06:33:09 PM PDT 24
Finished Aug 10 07:06:57 PM PDT 24
Peak memory 1187900 kb
Host smart-ee4d6d46-1541-40ad-a6a9-c2c90c34485b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=875069547 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_224.875069547 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_256.833995432
Short name T333
Test name
Test status
Simulation time 68242802100 ps
CPU time 2222.89 seconds
Started Aug 10 06:33:10 PM PDT 24
Finished Aug 10 07:10:14 PM PDT 24
Peak memory 1131840 kb
Host smart-e01ca3c0-0ed8-4f87-aa29-fd73b92be7d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=833995432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_256.833995432 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_384.629427024
Short name T281
Test name
Test status
Simulation time 133774994005 ps
CPU time 2450.8 seconds
Started Aug 10 06:33:09 PM PDT 24
Finished Aug 10 07:14:00 PM PDT 24
Peak memory 2448868 kb
Host smart-c1e015e9-5145-4304-bf18-f10a8e402a60
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=629427024 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_384.629427024 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_512.1626844795
Short name T418
Test name
Test status
Simulation time 89071012103 ps
CPU time 1766.36 seconds
Started Aug 10 06:33:09 PM PDT 24
Finished Aug 10 07:02:36 PM PDT 24
Peak memory 1719196 kb
Host smart-3c88996e-002f-43c3-a65e-115989a54abe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1626844795 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_512.1626844795 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_shake_128.1471527508
Short name T299
Test name
Test status
Simulation time 62924544732 ps
CPU time 6217.52 seconds
Started Aug 10 06:33:09 PM PDT 24
Finished Aug 10 08:16:47 PM PDT 24
Peak memory 2700344 kb
Host smart-080aa844-0f82-469b-8aea-c49b99a82393
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1471527508 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_128.1471527508 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_shake_256.2134029248
Short name T266
Test name
Test status
Simulation time 227921857709 ps
CPU time 5321.95 seconds
Started Aug 10 06:33:09 PM PDT 24
Finished Aug 10 08:01:52 PM PDT 24
Peak memory 2229432 kb
Host smart-e6b70464-ca1b-460e-9b07-a10fd5fd671f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2134029248 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_256.2134029248 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/12.kmac_alert_test.709337041
Short name T538
Test name
Test status
Simulation time 27680425 ps
CPU time 0.81 seconds
Started Aug 10 06:34:00 PM PDT 24
Finished Aug 10 06:34:01 PM PDT 24
Peak memory 218592 kb
Host smart-aee3d98c-074d-4ca7-9353-79fa56e2081d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709337041 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.709337041 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/12.kmac_alert_test/latest

Test location /workspace/coverage/default/12.kmac_app.3644087032
Short name T256
Test name
Test status
Simulation time 684450032 ps
CPU time 29.95 seconds
Started Aug 10 06:33:43 PM PDT 24
Finished Aug 10 06:34:13 PM PDT 24
Peak memory 235152 kb
Host smart-6ac8d578-bcb2-421d-8a21-57576e40be30
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644087032 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.3644087032 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/12.kmac_app/latest

Test location /workspace/coverage/default/12.kmac_burst_write.1496057417
Short name T395
Test name
Test status
Simulation time 168567768168 ps
CPU time 563.43 seconds
Started Aug 10 06:33:28 PM PDT 24
Finished Aug 10 06:42:52 PM PDT 24
Peak memory 244244 kb
Host smart-9d4399f3-f5de-42f1-9dec-f9269285c623
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496057417 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.149605741
7 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_burst_write/latest

Test location /workspace/coverage/default/12.kmac_edn_timeout_error.3045207913
Short name T557
Test name
Test status
Simulation time 189718842 ps
CPU time 15.48 seconds
Started Aug 10 06:33:44 PM PDT 24
Finished Aug 10 06:34:00 PM PDT 24
Peak memory 226748 kb
Host smart-c0c89332-3363-42d9-8f91-b78eaa3e722a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3045207913 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.3045207913 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/12.kmac_entropy_mode_error.576646164
Short name T905
Test name
Test status
Simulation time 681130413 ps
CPU time 49.65 seconds
Started Aug 10 06:33:46 PM PDT 24
Finished Aug 10 06:34:36 PM PDT 24
Peak memory 226764 kb
Host smart-f2641f29-01fb-4027-b24b-5fc39057b7d2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=576646164 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.576646164 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/12.kmac_entropy_refresh.3171719640
Short name T269
Test name
Test status
Simulation time 19452018644 ps
CPU time 226.07 seconds
Started Aug 10 06:33:44 PM PDT 24
Finished Aug 10 06:37:30 PM PDT 24
Peak memory 292280 kb
Host smart-7d8f1a89-a72c-4e60-9fe9-1d75db619a3f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171719640 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.3
171719640 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/12.kmac_error.1132977922
Short name T265
Test name
Test status
Simulation time 42892885442 ps
CPU time 326.24 seconds
Started Aug 10 06:33:43 PM PDT 24
Finished Aug 10 06:39:09 PM PDT 24
Peak memory 475132 kb
Host smart-536812e8-1ae7-493d-9015-f39647fcc73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132977922 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.1132977922 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_error/latest

Test location /workspace/coverage/default/12.kmac_key_error.222652647
Short name T790
Test name
Test status
Simulation time 7001246844 ps
CPU time 13.35 seconds
Started Aug 10 06:33:45 PM PDT 24
Finished Aug 10 06:33:58 PM PDT 24
Peak memory 226852 kb
Host smart-6b005fa6-8dbc-4661-9aad-847dc2ef9bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222652647 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.222652647 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_key_error/latest

Test location /workspace/coverage/default/12.kmac_long_msg_and_output.3225274948
Short name T565
Test name
Test status
Simulation time 173776141414 ps
CPU time 3489.41 seconds
Started Aug 10 06:33:29 PM PDT 24
Finished Aug 10 07:31:39 PM PDT 24
Peak memory 3031024 kb
Host smart-8dd15c5a-205c-4d5d-ab3d-3d88b4178ec6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225274948 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_a
nd_output.3225274948 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/12.kmac_sideload.1979638653
Short name T396
Test name
Test status
Simulation time 11591545855 ps
CPU time 479.94 seconds
Started Aug 10 06:33:29 PM PDT 24
Finished Aug 10 06:41:29 PM PDT 24
Peak memory 382172 kb
Host smart-95a7f345-1d8e-4a55-a800-2a0b13c0d79b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979638653 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.1979638653 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_sideload/latest

Test location /workspace/coverage/default/12.kmac_smoke.3128928008
Short name T329
Test name
Test status
Simulation time 1321007685 ps
CPU time 12.32 seconds
Started Aug 10 06:33:23 PM PDT 24
Finished Aug 10 06:33:35 PM PDT 24
Peak memory 226904 kb
Host smart-a0b7405f-7bfa-49a7-9a52-c12ce2a4e463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128928008 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.3128928008 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_smoke/latest

Test location /workspace/coverage/default/12.kmac_stress_all.1530079795
Short name T735
Test name
Test status
Simulation time 27024343022 ps
CPU time 302.35 seconds
Started Aug 10 06:34:00 PM PDT 24
Finished Aug 10 06:39:02 PM PDT 24
Peak memory 305524 kb
Host smart-591b8bea-45e8-49da-90cd-4c20b3c52508
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1530079795 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.1530079795 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_stress_all/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_kmac.4109123391
Short name T950
Test name
Test status
Simulation time 253761629 ps
CPU time 6.52 seconds
Started Aug 10 06:33:42 PM PDT 24
Finished Aug 10 06:33:49 PM PDT 24
Peak memory 218852 kb
Host smart-f75f849c-4aad-4429-ae65-ecb963f93cd8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109123391 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.kmac_test_vectors_kmac.4109123391 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_kmac_xof.1727608018
Short name T152
Test name
Test status
Simulation time 2021235147 ps
CPU time 6.29 seconds
Started Aug 10 06:33:44 PM PDT 24
Finished Aug 10 06:33:50 PM PDT 24
Peak memory 219764 kb
Host smart-d13a0c22-c161-4b17-b0b1-43120ef6fa39
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727608018 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.kmac_test_vectors_kmac_xof.1727608018 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_224.516081382
Short name T699
Test name
Test status
Simulation time 398381365244 ps
CPU time 3988.51 seconds
Started Aug 10 06:33:37 PM PDT 24
Finished Aug 10 07:40:06 PM PDT 24
Peak memory 3155260 kb
Host smart-c2a43cd5-292d-4c40-9f68-44162da7f10a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=516081382 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_224.516081382 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_256.1173264873
Short name T632
Test name
Test status
Simulation time 41023907780 ps
CPU time 2099.02 seconds
Started Aug 10 06:33:37 PM PDT 24
Finished Aug 10 07:08:36 PM PDT 24
Peak memory 1151188 kb
Host smart-ca01a720-6cd9-48fb-a270-de88293058a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1173264873 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_256.1173264873 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_384.2062967445
Short name T162
Test name
Test status
Simulation time 254018994186 ps
CPU time 2626.13 seconds
Started Aug 10 06:33:43 PM PDT 24
Finished Aug 10 07:17:29 PM PDT 24
Peak memory 2381192 kb
Host smart-71427f6d-b489-4651-8ddf-b14c555355c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2062967445 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_384.2062967445 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_512.4000719567
Short name T618
Test name
Test status
Simulation time 203554526524 ps
CPU time 1853.44 seconds
Started Aug 10 06:33:46 PM PDT 24
Finished Aug 10 07:04:40 PM PDT 24
Peak memory 1712588 kb
Host smart-5d6517d3-ea45-4b4c-8d14-d441ec8f2cc8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4000719567 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_512.4000719567 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_shake_256.2228069689
Short name T360
Test name
Test status
Simulation time 161725188945 ps
CPU time 9104.24 seconds
Started Aug 10 06:33:42 PM PDT 24
Finished Aug 10 09:05:27 PM PDT 24
Peak memory 6478260 kb
Host smart-baac144f-f2bc-45af-ac2c-f424ee5791fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2228069689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_256.2228069689 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/13.kmac_alert_test.3866307576
Short name T1005
Test name
Test status
Simulation time 18122887 ps
CPU time 0.86 seconds
Started Aug 10 06:34:26 PM PDT 24
Finished Aug 10 06:34:27 PM PDT 24
Peak memory 218532 kb
Host smart-a087f3b3-0d9b-4122-9424-028b4b8a098d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866307576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.3866307576 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_alert_test/latest

Test location /workspace/coverage/default/13.kmac_app.3817127000
Short name T1036
Test name
Test status
Simulation time 8778466172 ps
CPU time 196.34 seconds
Started Aug 10 06:34:12 PM PDT 24
Finished Aug 10 06:37:28 PM PDT 24
Peak memory 361836 kb
Host smart-5e5c25d4-c48d-4dc7-b230-74d7e47d807b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817127000 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.3817127000 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/13.kmac_app/latest

Test location /workspace/coverage/default/13.kmac_burst_write.2051529665
Short name T897
Test name
Test status
Simulation time 14315327129 ps
CPU time 346.24 seconds
Started Aug 10 06:33:59 PM PDT 24
Finished Aug 10 06:39:46 PM PDT 24
Peak memory 242568 kb
Host smart-1f112a4b-1630-48b6-8231-3f1fc0705b25
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051529665 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.205152966
5 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_burst_write/latest

Test location /workspace/coverage/default/13.kmac_edn_timeout_error.788254306
Short name T570
Test name
Test status
Simulation time 1364754943 ps
CPU time 26.99 seconds
Started Aug 10 06:34:13 PM PDT 24
Finished Aug 10 06:34:40 PM PDT 24
Peak memory 226756 kb
Host smart-684c356e-37e6-434b-aaae-8e2abadee636
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=788254306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.788254306 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/13.kmac_entropy_mode_error.4162517429
Short name T1029
Test name
Test status
Simulation time 138710450 ps
CPU time 1.07 seconds
Started Aug 10 06:34:12 PM PDT 24
Finished Aug 10 06:34:13 PM PDT 24
Peak memory 222124 kb
Host smart-85d28724-eb86-4683-95f7-4a127f4ca79d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4162517429 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.4162517429 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/13.kmac_entropy_refresh.3354187895
Short name T785
Test name
Test status
Simulation time 7657914756 ps
CPU time 358.13 seconds
Started Aug 10 06:34:12 PM PDT 24
Finished Aug 10 06:40:10 PM PDT 24
Peak memory 333640 kb
Host smart-1267a455-02d1-480c-81c8-45f22f80598f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354187895 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.3
354187895 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/13.kmac_error.1445610571
Short name T23
Test name
Test status
Simulation time 12937617174 ps
CPU time 278.04 seconds
Started Aug 10 06:34:12 PM PDT 24
Finished Aug 10 06:38:50 PM PDT 24
Peak memory 315168 kb
Host smart-b97e6ea0-91f4-46ec-bc2b-db073e6de847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445610571 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.1445610571 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_error/latest

Test location /workspace/coverage/default/13.kmac_key_error.457659934
Short name T356
Test name
Test status
Simulation time 6454788412 ps
CPU time 12.22 seconds
Started Aug 10 06:34:12 PM PDT 24
Finished Aug 10 06:34:24 PM PDT 24
Peak memory 226856 kb
Host smart-b1f7fabf-1e46-43aa-b81e-4993bbc543df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457659934 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.457659934 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_key_error/latest

Test location /workspace/coverage/default/13.kmac_lc_escalation.3890581678
Short name T946
Test name
Test status
Simulation time 255692738 ps
CPU time 1.38 seconds
Started Aug 10 06:34:25 PM PDT 24
Finished Aug 10 06:34:26 PM PDT 24
Peak memory 226908 kb
Host smart-17bfca7a-ef29-4b7a-8c82-c53a37ace948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890581678 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.3890581678 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/13.kmac_lc_escalation/latest

Test location /workspace/coverage/default/13.kmac_long_msg_and_output.2818482917
Short name T344
Test name
Test status
Simulation time 5890785058 ps
CPU time 670.33 seconds
Started Aug 10 06:34:00 PM PDT 24
Finished Aug 10 06:45:11 PM PDT 24
Peak memory 573560 kb
Host smart-58ad286a-1a74-4683-903a-ae1843524f6c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818482917 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_a
nd_output.2818482917 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/13.kmac_sideload.122829854
Short name T366
Test name
Test status
Simulation time 1306684946 ps
CPU time 120.2 seconds
Started Aug 10 06:34:00 PM PDT 24
Finished Aug 10 06:36:00 PM PDT 24
Peak memory 264408 kb
Host smart-10450707-02ba-4b88-ba6f-c013904d8f86
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122829854 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.122829854 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_sideload/latest

Test location /workspace/coverage/default/13.kmac_smoke.3788723507
Short name T600
Test name
Test status
Simulation time 2216553160 ps
CPU time 80.11 seconds
Started Aug 10 06:34:00 PM PDT 24
Finished Aug 10 06:35:20 PM PDT 24
Peak memory 227008 kb
Host smart-d8d57677-fb0f-4642-997d-73bd7f58b7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788723507 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.3788723507 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_smoke/latest

Test location /workspace/coverage/default/13.kmac_stress_all.2441144773
Short name T84
Test name
Test status
Simulation time 44975515787 ps
CPU time 1466.22 seconds
Started Aug 10 06:34:27 PM PDT 24
Finished Aug 10 06:58:53 PM PDT 24
Peak memory 953924 kb
Host smart-3cd5aecf-e686-4177-bdfa-46b2ad28ac1e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2441144773 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.2441144773 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_stress_all/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_kmac.674057909
Short name T405
Test name
Test status
Simulation time 557288692 ps
CPU time 5.47 seconds
Started Aug 10 06:34:14 PM PDT 24
Finished Aug 10 06:34:19 PM PDT 24
Peak memory 218908 kb
Host smart-959db132-52b0-48ff-85bf-c2fc91a984ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674057909 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.kmac_test_vectors_kmac.674057909 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_kmac_xof.3555492284
Short name T620
Test name
Test status
Simulation time 245855573 ps
CPU time 6.41 seconds
Started Aug 10 06:34:12 PM PDT 24
Finished Aug 10 06:34:19 PM PDT 24
Peak memory 219836 kb
Host smart-f7bd4ff7-0a12-499a-813a-7efe1b042d72
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555492284 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.kmac_test_vectors_kmac_xof.3555492284 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_224.4109999734
Short name T205
Test name
Test status
Simulation time 40450820127 ps
CPU time 2072.35 seconds
Started Aug 10 06:34:06 PM PDT 24
Finished Aug 10 07:08:39 PM PDT 24
Peak memory 1165156 kb
Host smart-4c583909-ac75-41d1-9cb7-698365849296
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4109999734 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_224.4109999734 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_256.1768322394
Short name T992
Test name
Test status
Simulation time 314389176011 ps
CPU time 3048.49 seconds
Started Aug 10 06:34:07 PM PDT 24
Finished Aug 10 07:24:56 PM PDT 24
Peak memory 3116116 kb
Host smart-5ac46711-92a0-4db4-92d6-cc755fee4357
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1768322394 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_256.1768322394 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_384.1623721624
Short name T888
Test name
Test status
Simulation time 79919010849 ps
CPU time 1770.93 seconds
Started Aug 10 06:34:04 PM PDT 24
Finished Aug 10 07:03:35 PM PDT 24
Peak memory 892192 kb
Host smart-d6eccec2-2372-47ad-a7da-b38f468275fe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1623721624 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_384.1623721624 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_512.3880606192
Short name T788
Test name
Test status
Simulation time 119327500086 ps
CPU time 1292.94 seconds
Started Aug 10 06:34:05 PM PDT 24
Finished Aug 10 06:55:38 PM PDT 24
Peak memory 706864 kb
Host smart-7a9bd74e-11cb-4f5a-baab-11375f28e87e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3880606192 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_512.3880606192 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_shake_256.2900899524
Short name T471
Test name
Test status
Simulation time 744654380009 ps
CPU time 9243.55 seconds
Started Aug 10 06:34:06 PM PDT 24
Finished Aug 10 09:08:11 PM PDT 24
Peak memory 6298372 kb
Host smart-00c42e44-0baa-43d7-b30e-babcb1222afc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2900899524 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_256.2900899524 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/14.kmac_alert_test.2675698796
Short name T623
Test name
Test status
Simulation time 55564619 ps
CPU time 0.88 seconds
Started Aug 10 06:34:54 PM PDT 24
Finished Aug 10 06:34:55 PM PDT 24
Peak memory 218528 kb
Host smart-9c91a9c9-fbc1-4f4e-bfad-56a8212ec233
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675698796 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.2675698796 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_alert_test/latest

Test location /workspace/coverage/default/14.kmac_app.894910078
Short name T432
Test name
Test status
Simulation time 21622512822 ps
CPU time 277.14 seconds
Started Aug 10 06:34:40 PM PDT 24
Finished Aug 10 06:39:17 PM PDT 24
Peak memory 457792 kb
Host smart-0dd0447f-61bb-4311-badb-ad40f6d0971e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894910078 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.894910078 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/14.kmac_app/latest

Test location /workspace/coverage/default/14.kmac_burst_write.1243566598
Short name T894
Test name
Test status
Simulation time 28014249832 ps
CPU time 650.19 seconds
Started Aug 10 06:34:32 PM PDT 24
Finished Aug 10 06:45:22 PM PDT 24
Peak memory 244836 kb
Host smart-150ec7bf-af66-4b58-a10f-a33eaf305ead
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243566598 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.124356659
8 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_burst_write/latest

Test location /workspace/coverage/default/14.kmac_edn_timeout_error.613442989
Short name T776
Test name
Test status
Simulation time 26805567 ps
CPU time 0.99 seconds
Started Aug 10 06:34:54 PM PDT 24
Finished Aug 10 06:34:55 PM PDT 24
Peak memory 218504 kb
Host smart-a2c3a9c1-355b-4e18-9c8b-e46a29cec5c0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=613442989 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.613442989 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/14.kmac_entropy_mode_error.2075916573
Short name T727
Test name
Test status
Simulation time 403760491 ps
CPU time 26.21 seconds
Started Aug 10 06:34:54 PM PDT 24
Finished Aug 10 06:35:20 PM PDT 24
Peak memory 226812 kb
Host smart-ce002b08-676d-4ec2-aac5-3acb6c0afd21
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2075916573 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.2075916573 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/14.kmac_entropy_refresh.2286376013
Short name T505
Test name
Test status
Simulation time 8118743581 ps
CPU time 107.34 seconds
Started Aug 10 06:34:48 PM PDT 24
Finished Aug 10 06:36:36 PM PDT 24
Peak memory 259840 kb
Host smart-fd86b10a-8dc3-4489-93df-c19dfbf1960a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286376013 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.2
286376013 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/14.kmac_error.516490780
Short name T509
Test name
Test status
Simulation time 48318023106 ps
CPU time 399.12 seconds
Started Aug 10 06:34:47 PM PDT 24
Finished Aug 10 06:41:26 PM PDT 24
Peak memory 514468 kb
Host smart-7d1777bd-a74a-4b8b-86a8-9a10916d0b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516490780 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.516490780 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_error/latest

Test location /workspace/coverage/default/14.kmac_key_error.3629014945
Short name T869
Test name
Test status
Simulation time 4661079280 ps
CPU time 9.1 seconds
Started Aug 10 06:34:48 PM PDT 24
Finished Aug 10 06:34:57 PM PDT 24
Peak memory 226800 kb
Host smart-6f428c7e-75a4-47a6-b4bc-c888b7f9bc21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629014945 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.3629014945 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_key_error/latest

Test location /workspace/coverage/default/14.kmac_lc_escalation.376041040
Short name T76
Test name
Test status
Simulation time 395265036 ps
CPU time 1.41 seconds
Started Aug 10 06:34:54 PM PDT 24
Finished Aug 10 06:34:55 PM PDT 24
Peak memory 226936 kb
Host smart-7e591802-a376-4ac9-931e-fcaff0a0fccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376041040 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.376041040 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/14.kmac_lc_escalation/latest

Test location /workspace/coverage/default/14.kmac_long_msg_and_output.2721991972
Short name T237
Test name
Test status
Simulation time 78733835452 ps
CPU time 1361 seconds
Started Aug 10 06:34:26 PM PDT 24
Finished Aug 10 06:57:07 PM PDT 24
Peak memory 841908 kb
Host smart-f2cc1c18-dea4-402d-95d0-0e4cbd9e733e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721991972 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_a
nd_output.2721991972 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/14.kmac_sideload.1536335658
Short name T780
Test name
Test status
Simulation time 12934685482 ps
CPU time 406.31 seconds
Started Aug 10 06:34:31 PM PDT 24
Finished Aug 10 06:41:17 PM PDT 24
Peak memory 352272 kb
Host smart-ebd67103-b5cd-4a50-95fe-6d31d6c2724d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536335658 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.1536335658 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_sideload/latest

Test location /workspace/coverage/default/14.kmac_smoke.2697968686
Short name T693
Test name
Test status
Simulation time 5256497190 ps
CPU time 37.45 seconds
Started Aug 10 06:34:25 PM PDT 24
Finished Aug 10 06:35:03 PM PDT 24
Peak memory 227028 kb
Host smart-c61677a6-8540-4597-bd6f-c76725c72302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697968686 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.2697968686 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_smoke/latest

Test location /workspace/coverage/default/14.kmac_stress_all.111619833
Short name T542
Test name
Test status
Simulation time 16152132587 ps
CPU time 327.71 seconds
Started Aug 10 06:34:55 PM PDT 24
Finished Aug 10 06:40:23 PM PDT 24
Peak memory 349416 kb
Host smart-b452c1f3-e1dc-44d2-ae3b-2b9fdd0a7253
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=111619833 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.111619833 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_stress_all/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_kmac.973219649
Short name T388
Test name
Test status
Simulation time 283344276 ps
CPU time 6.35 seconds
Started Aug 10 06:34:39 PM PDT 24
Finished Aug 10 06:34:45 PM PDT 24
Peak memory 219832 kb
Host smart-15f0b647-af9e-4f33-9db0-f41fb4b77ce8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973219649 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.kmac_test_vectors_kmac.973219649 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_kmac_xof.833610314
Short name T987
Test name
Test status
Simulation time 1116388229 ps
CPU time 7.29 seconds
Started Aug 10 06:34:40 PM PDT 24
Finished Aug 10 06:34:48 PM PDT 24
Peak memory 220004 kb
Host smart-565c6a88-4171-4931-a52f-11a5a8e72b51
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833610314 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.kmac_test_vectors_kmac_xof.833610314 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_224.3046068474
Short name T965
Test name
Test status
Simulation time 163580029833 ps
CPU time 3383.44 seconds
Started Aug 10 06:34:32 PM PDT 24
Finished Aug 10 07:30:56 PM PDT 24
Peak memory 3248108 kb
Host smart-2c5f8cfc-7698-4bea-aeb9-66b9e129a799
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3046068474 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_224.3046068474 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_256.1005150471
Short name T1006
Test name
Test status
Simulation time 878437357677 ps
CPU time 3372.17 seconds
Started Aug 10 06:34:31 PM PDT 24
Finished Aug 10 07:30:44 PM PDT 24
Peak memory 3037500 kb
Host smart-33ff5d83-7049-4433-8a50-ebf0bbbc1f53
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1005150471 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_256.1005150471 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_384.3669060108
Short name T848
Test name
Test status
Simulation time 14863130612 ps
CPU time 1671.3 seconds
Started Aug 10 06:34:40 PM PDT 24
Finished Aug 10 07:02:31 PM PDT 24
Peak memory 922624 kb
Host smart-04967397-03c0-4a35-887b-2f2f7e7718a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3669060108 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_384.3669060108 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_512.933720735
Short name T904
Test name
Test status
Simulation time 90619622296 ps
CPU time 1441.03 seconds
Started Aug 10 06:34:40 PM PDT 24
Finished Aug 10 06:58:41 PM PDT 24
Peak memory 1643852 kb
Host smart-487c65e2-8268-4535-82dc-392c713cedb4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=933720735 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_512.933720735 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/15.kmac_alert_test.3722286266
Short name T925
Test name
Test status
Simulation time 13968621 ps
CPU time 0.76 seconds
Started Aug 10 06:35:36 PM PDT 24
Finished Aug 10 06:35:37 PM PDT 24
Peak memory 218600 kb
Host smart-a8bf6dc4-17b3-4502-a377-e68c79192f8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722286266 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.3722286266 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_alert_test/latest

Test location /workspace/coverage/default/15.kmac_burst_write.3999247220
Short name T278
Test name
Test status
Simulation time 46451858259 ps
CPU time 715.85 seconds
Started Aug 10 06:35:03 PM PDT 24
Finished Aug 10 06:46:59 PM PDT 24
Peak memory 244368 kb
Host smart-d59c1dd9-bee5-499a-80b4-f5c9a70c5c0f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999247220 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.399924722
0 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_burst_write/latest

Test location /workspace/coverage/default/15.kmac_edn_timeout_error.458258946
Short name T38
Test name
Test status
Simulation time 7013389738 ps
CPU time 48.23 seconds
Started Aug 10 06:35:30 PM PDT 24
Finished Aug 10 06:36:18 PM PDT 24
Peak memory 228436 kb
Host smart-4a7a7b16-7456-4e70-af85-527f9455ac24
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=458258946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.458258946 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/15.kmac_entropy_mode_error.3343868893
Short name T373
Test name
Test status
Simulation time 30142879 ps
CPU time 0.92 seconds
Started Aug 10 06:35:29 PM PDT 24
Finished Aug 10 06:35:30 PM PDT 24
Peak memory 218540 kb
Host smart-277ebb66-fd4e-4122-959b-3a54429b5670
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3343868893 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.3343868893 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/15.kmac_key_error.1471467936
Short name T984
Test name
Test status
Simulation time 19629344255 ps
CPU time 9.9 seconds
Started Aug 10 06:35:23 PM PDT 24
Finished Aug 10 06:35:33 PM PDT 24
Peak memory 226812 kb
Host smart-751642cc-2d5d-45fe-a915-17513b32eeca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471467936 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.1471467936 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_key_error/latest

Test location /workspace/coverage/default/15.kmac_long_msg_and_output.1477644472
Short name T501
Test name
Test status
Simulation time 72794187898 ps
CPU time 2430.74 seconds
Started Aug 10 06:35:07 PM PDT 24
Finished Aug 10 07:15:38 PM PDT 24
Peak memory 2402088 kb
Host smart-e7ffdd78-ad5d-4306-bb16-7bc8367715ed
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477644472 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_a
nd_output.1477644472 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/15.kmac_sideload.173910829
Short name T90
Test name
Test status
Simulation time 4498782429 ps
CPU time 63.13 seconds
Started Aug 10 06:35:07 PM PDT 24
Finished Aug 10 06:36:10 PM PDT 24
Peak memory 271996 kb
Host smart-317a69f5-35f8-4565-81be-ad2f2bca56c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173910829 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.173910829 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_sideload/latest

Test location /workspace/coverage/default/15.kmac_smoke.449538070
Short name T960
Test name
Test status
Simulation time 2432441812 ps
CPU time 42.99 seconds
Started Aug 10 06:35:02 PM PDT 24
Finished Aug 10 06:35:45 PM PDT 24
Peak memory 227020 kb
Host smart-568ade05-c936-4831-bd29-2c637b4aaf3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449538070 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.449538070 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_smoke/latest

Test location /workspace/coverage/default/15.kmac_stress_all.1579497227
Short name T82
Test name
Test status
Simulation time 11667683132 ps
CPU time 1127.61 seconds
Started Aug 10 06:35:37 PM PDT 24
Finished Aug 10 06:54:25 PM PDT 24
Peak memory 396692 kb
Host smart-0b6cfceb-0fdb-4c07-936c-f42a214eed87
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1579497227 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.1579497227 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_stress_all/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_kmac.2603399147
Short name T744
Test name
Test status
Simulation time 974056432 ps
CPU time 6.94 seconds
Started Aug 10 06:35:16 PM PDT 24
Finished Aug 10 06:35:23 PM PDT 24
Peak memory 219848 kb
Host smart-60c1346c-7bc8-4184-8542-b6fd058611ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603399147 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.kmac_test_vectors_kmac.2603399147 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_kmac_xof.1874435650
Short name T525
Test name
Test status
Simulation time 215747818 ps
CPU time 6.01 seconds
Started Aug 10 06:35:14 PM PDT 24
Finished Aug 10 06:35:20 PM PDT 24
Peak memory 219828 kb
Host smart-55efaab2-dfc7-407f-a4fd-3f439331433b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874435650 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.kmac_test_vectors_kmac_xof.1874435650 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_224.812303353
Short name T291
Test name
Test status
Simulation time 287155804434 ps
CPU time 3430.39 seconds
Started Aug 10 06:35:07 PM PDT 24
Finished Aug 10 07:32:18 PM PDT 24
Peak memory 3262912 kb
Host smart-08f8eb55-e882-482a-a795-07028c202a7e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=812303353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_224.812303353 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_256.285070508
Short name T334
Test name
Test status
Simulation time 19961115459 ps
CPU time 2112.54 seconds
Started Aug 10 06:35:02 PM PDT 24
Finished Aug 10 07:10:15 PM PDT 24
Peak memory 1189844 kb
Host smart-3b7a7ed1-730b-4498-9692-145f04c4c682
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=285070508 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_256.285070508 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_384.2037047868
Short name T516
Test name
Test status
Simulation time 189141649475 ps
CPU time 2218.33 seconds
Started Aug 10 06:35:10 PM PDT 24
Finished Aug 10 07:12:08 PM PDT 24
Peak memory 2374728 kb
Host smart-30218828-bdcc-4e19-8c97-eeaa1e9ccb17
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2037047868 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_384.2037047868 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_512.597367791
Short name T1013
Test name
Test status
Simulation time 38901355237 ps
CPU time 1304.73 seconds
Started Aug 10 06:35:08 PM PDT 24
Finished Aug 10 06:56:53 PM PDT 24
Peak memory 710348 kb
Host smart-b3945b9f-670b-43b0-b31a-ada85b8e9c87
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=597367791 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_512.597367791 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_shake_128.3916382369
Short name T881
Test name
Test status
Simulation time 237404708835 ps
CPU time 6578.06 seconds
Started Aug 10 06:35:09 PM PDT 24
Finished Aug 10 08:24:48 PM PDT 24
Peak memory 2653460 kb
Host smart-84b1696f-55f7-4b9e-9cd1-499296705b59
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3916382369 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_128.3916382369 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_shake_256.10440864
Short name T375
Test name
Test status
Simulation time 204101407713 ps
CPU time 5331.49 seconds
Started Aug 10 06:35:16 PM PDT 24
Finished Aug 10 08:04:08 PM PDT 24
Peak memory 2220688 kb
Host smart-0f1b2125-da7a-41c4-88a4-cec29fbbb15b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=10440864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_256.10440864 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/16.kmac_alert_test.3107391400
Short name T901
Test name
Test status
Simulation time 17078947 ps
CPU time 0.8 seconds
Started Aug 10 06:36:23 PM PDT 24
Finished Aug 10 06:36:24 PM PDT 24
Peak memory 218564 kb
Host smart-f1659b5c-434d-48d3-8b68-0f299b2a5eb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107391400 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.3107391400 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_alert_test/latest

Test location /workspace/coverage/default/16.kmac_app.765983182
Short name T887
Test name
Test status
Simulation time 17299845951 ps
CPU time 275.62 seconds
Started Aug 10 06:36:10 PM PDT 24
Finished Aug 10 06:40:46 PM PDT 24
Peak memory 411408 kb
Host smart-c44c1d8a-8691-4feb-b1c6-5fed8faf04f2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765983182 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.765983182 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/16.kmac_app/latest

Test location /workspace/coverage/default/16.kmac_edn_timeout_error.3257115692
Short name T218
Test name
Test status
Simulation time 1434854943 ps
CPU time 42.73 seconds
Started Aug 10 06:36:10 PM PDT 24
Finished Aug 10 06:36:53 PM PDT 24
Peak memory 227572 kb
Host smart-318d65f3-ff0d-40d8-b94f-16e3880b55c6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3257115692 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.3257115692 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/16.kmac_entropy_mode_error.3825357864
Short name T949
Test name
Test status
Simulation time 47281759 ps
CPU time 0.98 seconds
Started Aug 10 06:36:16 PM PDT 24
Finished Aug 10 06:36:17 PM PDT 24
Peak memory 218444 kb
Host smart-191dc674-8fe8-494a-a55a-42e2e404b71c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3825357864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.3825357864 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/16.kmac_error.4106365562
Short name T446
Test name
Test status
Simulation time 8052445559 ps
CPU time 210.97 seconds
Started Aug 10 06:36:12 PM PDT 24
Finished Aug 10 06:39:43 PM PDT 24
Peak memory 399776 kb
Host smart-8eed3afd-279b-4ad5-ad53-bc014828e0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106365562 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.4106365562 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_error/latest

Test location /workspace/coverage/default/16.kmac_key_error.1826096402
Short name T552
Test name
Test status
Simulation time 1293458504 ps
CPU time 9.74 seconds
Started Aug 10 06:36:12 PM PDT 24
Finished Aug 10 06:36:22 PM PDT 24
Peak memory 226752 kb
Host smart-c5df6267-896e-4f45-953b-ed595a72ef0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826096402 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.1826096402 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_key_error/latest

Test location /workspace/coverage/default/16.kmac_lc_escalation.870140809
Short name T51
Test name
Test status
Simulation time 62490504 ps
CPU time 1.64 seconds
Started Aug 10 06:36:16 PM PDT 24
Finished Aug 10 06:36:18 PM PDT 24
Peak memory 226896 kb
Host smart-9ac56359-4e16-44a2-8f35-915bbe5dc0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870140809 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.870140809 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/16.kmac_lc_escalation/latest

Test location /workspace/coverage/default/16.kmac_long_msg_and_output.1515651967
Short name T922
Test name
Test status
Simulation time 145489760344 ps
CPU time 4281.13 seconds
Started Aug 10 06:35:37 PM PDT 24
Finished Aug 10 07:46:59 PM PDT 24
Peak memory 3596324 kb
Host smart-31fa6017-8f36-4a8e-a51d-de8f76109820
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515651967 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_a
nd_output.1515651967 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/16.kmac_sideload.206496824
Short name T368
Test name
Test status
Simulation time 236936762 ps
CPU time 9.23 seconds
Started Aug 10 06:35:46 PM PDT 24
Finished Aug 10 06:35:56 PM PDT 24
Peak memory 237272 kb
Host smart-5574b10e-fe01-44fc-8b80-10095bf92180
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206496824 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.206496824 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_sideload/latest

Test location /workspace/coverage/default/16.kmac_smoke.3759898210
Short name T891
Test name
Test status
Simulation time 18761595265 ps
CPU time 45.08 seconds
Started Aug 10 06:35:37 PM PDT 24
Finished Aug 10 06:36:22 PM PDT 24
Peak memory 225248 kb
Host smart-b1eecc94-4bb4-46b3-accb-cb9f67a530fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759898210 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.3759898210 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_smoke/latest

Test location /workspace/coverage/default/16.kmac_stress_all.1025720331
Short name T810
Test name
Test status
Simulation time 7284423567 ps
CPU time 620.07 seconds
Started Aug 10 06:36:17 PM PDT 24
Finished Aug 10 06:46:37 PM PDT 24
Peak memory 317056 kb
Host smart-91ed1cc4-8423-42ca-870b-529579dafede
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1025720331 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all.1025720331 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_stress_all/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_kmac.4147903600
Short name T853
Test name
Test status
Simulation time 193431386 ps
CPU time 5.97 seconds
Started Aug 10 06:36:09 PM PDT 24
Finished Aug 10 06:36:15 PM PDT 24
Peak memory 218896 kb
Host smart-e7a50d4a-91d7-47d6-9c36-0f8a4bb3c280
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147903600 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.kmac_test_vectors_kmac.4147903600 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_kmac_xof.163057984
Short name T782
Test name
Test status
Simulation time 570063825 ps
CPU time 5.66 seconds
Started Aug 10 06:36:08 PM PDT 24
Finished Aug 10 06:36:13 PM PDT 24
Peak memory 219852 kb
Host smart-697584a9-9a7b-442a-849b-ec5604a7ef8f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163057984 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.kmac_test_vectors_kmac_xof.163057984 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_224.3730447304
Short name T972
Test name
Test status
Simulation time 22979905858 ps
CPU time 2305.03 seconds
Started Aug 10 06:36:02 PM PDT 24
Finished Aug 10 07:14:27 PM PDT 24
Peak memory 1196952 kb
Host smart-0f64d68e-d3e3-4772-a46f-58263c2b0319
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3730447304 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_224.3730447304 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_256.3255391298
Short name T397
Test name
Test status
Simulation time 120583072781 ps
CPU time 2880.97 seconds
Started Aug 10 06:36:01 PM PDT 24
Finished Aug 10 07:24:03 PM PDT 24
Peak memory 2982204 kb
Host smart-659b3752-88aa-4347-ae84-937a5c357667
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3255391298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_256.3255391298 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_384.2485266080
Short name T258
Test name
Test status
Simulation time 68997713856 ps
CPU time 2558.59 seconds
Started Aug 10 06:36:02 PM PDT 24
Finished Aug 10 07:18:41 PM PDT 24
Peak memory 2345316 kb
Host smart-d8634d23-dbd1-4b3c-a0b5-89868ae5600d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2485266080 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_384.2485266080 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_512.3276624034
Short name T818
Test name
Test status
Simulation time 12020786684 ps
CPU time 1129.07 seconds
Started Aug 10 06:36:01 PM PDT 24
Finished Aug 10 06:54:51 PM PDT 24
Peak memory 707404 kb
Host smart-811694f4-90bb-4f01-a2d2-86ade632bbb4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3276624034 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_512.3276624034 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_shake_128.1009085754
Short name T569
Test name
Test status
Simulation time 122584342382 ps
CPU time 6588.03 seconds
Started Aug 10 06:36:02 PM PDT 24
Finished Aug 10 08:25:51 PM PDT 24
Peak memory 2717812 kb
Host smart-7f4e3fc2-d35d-419e-8a29-242a5871d2d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1009085754 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_128.1009085754 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_shake_256.1414774684
Short name T487
Test name
Test status
Simulation time 795830887937 ps
CPU time 9391.1 seconds
Started Aug 10 06:36:03 PM PDT 24
Finished Aug 10 09:12:36 PM PDT 24
Peak memory 6474680 kb
Host smart-07bff890-547f-40a3-8e20-0ef07e481aed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1414774684 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_256.1414774684 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/17.kmac_alert_test.2192593541
Short name T885
Test name
Test status
Simulation time 29694236 ps
CPU time 0.84 seconds
Started Aug 10 06:36:51 PM PDT 24
Finished Aug 10 06:36:52 PM PDT 24
Peak memory 218612 kb
Host smart-f25bf9ad-0aa7-452b-8b35-f3a7aa5dd2e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192593541 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.2192593541 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_alert_test/latest

Test location /workspace/coverage/default/17.kmac_app.2959096440
Short name T573
Test name
Test status
Simulation time 35043973446 ps
CPU time 462.14 seconds
Started Aug 10 06:36:45 PM PDT 24
Finished Aug 10 06:44:28 PM PDT 24
Peak memory 554512 kb
Host smart-1461227c-9cb1-4526-a017-3d94bcfd0072
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959096440 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.2959096440 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/17.kmac_app/latest

Test location /workspace/coverage/default/17.kmac_burst_write.3403292730
Short name T803
Test name
Test status
Simulation time 38603341501 ps
CPU time 940.41 seconds
Started Aug 10 06:36:33 PM PDT 24
Finished Aug 10 06:52:14 PM PDT 24
Peak memory 241192 kb
Host smart-3fc55e19-4b79-43b9-b4e6-b9ff6eddeaf9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403292730 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.340329273
0 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_burst_write/latest

Test location /workspace/coverage/default/17.kmac_edn_timeout_error.2141751281
Short name T875
Test name
Test status
Simulation time 664864811 ps
CPU time 12.38 seconds
Started Aug 10 06:36:49 PM PDT 24
Finished Aug 10 06:37:01 PM PDT 24
Peak memory 225892 kb
Host smart-08f34fdf-ca60-4408-a867-0460bd9f2b46
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2141751281 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.2141751281 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/17.kmac_entropy_mode_error.1124080152
Short name T990
Test name
Test status
Simulation time 1496642376 ps
CPU time 44.45 seconds
Started Aug 10 06:36:51 PM PDT 24
Finished Aug 10 06:37:35 PM PDT 24
Peak memory 227292 kb
Host smart-527bf542-aaa6-484f-bf95-823bc5ad0517
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1124080152 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.1124080152 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/17.kmac_entropy_refresh.1361001532
Short name T1035
Test name
Test status
Simulation time 8292795676 ps
CPU time 60.42 seconds
Started Aug 10 06:36:47 PM PDT 24
Finished Aug 10 06:37:47 PM PDT 24
Peak memory 265720 kb
Host smart-5c3bc874-b5be-4cda-b3e6-675937ad10cc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361001532 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.1
361001532 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/17.kmac_error.2617179889
Short name T180
Test name
Test status
Simulation time 13261947251 ps
CPU time 474.32 seconds
Started Aug 10 06:36:49 PM PDT 24
Finished Aug 10 06:44:43 PM PDT 24
Peak memory 600008 kb
Host smart-aa930969-2d39-45d1-89dc-36995d5db122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617179889 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.2617179889 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_error/latest

Test location /workspace/coverage/default/17.kmac_key_error.583018946
Short name T468
Test name
Test status
Simulation time 2187720414 ps
CPU time 9.82 seconds
Started Aug 10 06:36:45 PM PDT 24
Finished Aug 10 06:36:55 PM PDT 24
Peak memory 226804 kb
Host smart-4ecb696a-a149-436d-9e99-9332521dbc6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583018946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.583018946 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_key_error/latest

Test location /workspace/coverage/default/17.kmac_lc_escalation.902062181
Short name T53
Test name
Test status
Simulation time 112458900 ps
CPU time 1.36 seconds
Started Aug 10 06:36:51 PM PDT 24
Finished Aug 10 06:36:53 PM PDT 24
Peak memory 226912 kb
Host smart-cff01e20-d262-406b-94ad-c5af910b9381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902062181 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.902062181 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/17.kmac_lc_escalation/latest

Test location /workspace/coverage/default/17.kmac_long_msg_and_output.2268536828
Short name T128
Test name
Test status
Simulation time 14237628527 ps
CPU time 784.72 seconds
Started Aug 10 06:36:23 PM PDT 24
Finished Aug 10 06:49:28 PM PDT 24
Peak memory 620540 kb
Host smart-7f5f241b-bb2a-4f62-9117-b32b04816c03
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268536828 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_a
nd_output.2268536828 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/17.kmac_sideload.2570700004
Short name T387
Test name
Test status
Simulation time 4725568366 ps
CPU time 95.79 seconds
Started Aug 10 06:36:23 PM PDT 24
Finished Aug 10 06:37:59 PM PDT 24
Peak memory 293212 kb
Host smart-cacb4591-4ddd-4f11-839b-18cd93d5048f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570700004 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.2570700004 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_sideload/latest

Test location /workspace/coverage/default/17.kmac_smoke.984268280
Short name T865
Test name
Test status
Simulation time 8297450641 ps
CPU time 81.89 seconds
Started Aug 10 06:36:22 PM PDT 24
Finished Aug 10 06:37:44 PM PDT 24
Peak memory 227812 kb
Host smart-6b7a8069-ebce-4c42-b4f2-da0bbbc0306e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984268280 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.984268280 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_smoke/latest

Test location /workspace/coverage/default/17.kmac_stress_all.1592740408
Short name T929
Test name
Test status
Simulation time 97653380095 ps
CPU time 851.89 seconds
Started Aug 10 06:36:52 PM PDT 24
Finished Aug 10 06:51:04 PM PDT 24
Peak memory 536292 kb
Host smart-e8410cb2-aa55-4e0c-a12d-a73884f251d4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1592740408 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.1592740408 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_stress_all/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_kmac.4173596863
Short name T646
Test name
Test status
Simulation time 391787617 ps
CPU time 6.12 seconds
Started Aug 10 06:36:39 PM PDT 24
Finished Aug 10 06:36:45 PM PDT 24
Peak memory 219764 kb
Host smart-650a6218-4857-4217-920e-04d17065e788
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173596863 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.kmac_test_vectors_kmac.4173596863 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_kmac_xof.1157452567
Short name T730
Test name
Test status
Simulation time 1327077109 ps
CPU time 7.38 seconds
Started Aug 10 06:36:45 PM PDT 24
Finished Aug 10 06:36:53 PM PDT 24
Peak memory 219820 kb
Host smart-4bc4f933-c024-4c49-8529-c1263cd4d248
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157452567 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.kmac_test_vectors_kmac_xof.1157452567 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_224.4093498187
Short name T832
Test name
Test status
Simulation time 83391401956 ps
CPU time 2258.37 seconds
Started Aug 10 06:36:30 PM PDT 24
Finished Aug 10 07:14:09 PM PDT 24
Peak memory 1228248 kb
Host smart-d206f1f3-877f-487f-8f08-b1ae825208bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4093498187 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_224.4093498187 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_256.450253337
Short name T561
Test name
Test status
Simulation time 81759860087 ps
CPU time 2108.08 seconds
Started Aug 10 06:36:30 PM PDT 24
Finished Aug 10 07:11:39 PM PDT 24
Peak memory 1163632 kb
Host smart-cd0ad10b-ce8a-4c7b-9e6a-d53ceab05db2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=450253337 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_256.450253337 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_384.1258550245
Short name T786
Test name
Test status
Simulation time 318449976637 ps
CPU time 2753.21 seconds
Started Aug 10 06:36:30 PM PDT 24
Finished Aug 10 07:22:24 PM PDT 24
Peak memory 2373340 kb
Host smart-4a5fe665-12cf-4e34-9f28-9c63e27fc23b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1258550245 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_384.1258550245 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_512.1882776548
Short name T341
Test name
Test status
Simulation time 33082772029 ps
CPU time 1596.47 seconds
Started Aug 10 06:36:31 PM PDT 24
Finished Aug 10 07:03:07 PM PDT 24
Peak memory 1699784 kb
Host smart-41e5d266-6e53-4ed1-9d7a-af22c782d1d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1882776548 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_512.1882776548 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/18.kmac_alert_test.2645982069
Short name T117
Test name
Test status
Simulation time 22848152 ps
CPU time 0.8 seconds
Started Aug 10 06:37:34 PM PDT 24
Finished Aug 10 06:37:35 PM PDT 24
Peak memory 218556 kb
Host smart-a6eb5dcc-e97b-4f32-b288-95facb929e1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645982069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.2645982069 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_alert_test/latest

Test location /workspace/coverage/default/18.kmac_app.776187587
Short name T233
Test name
Test status
Simulation time 18420114942 ps
CPU time 107.04 seconds
Started Aug 10 06:37:19 PM PDT 24
Finished Aug 10 06:39:06 PM PDT 24
Peak memory 295020 kb
Host smart-f2454160-1db3-4c7f-ab7b-ccb9c7f9c5b9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776187587 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.776187587 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/18.kmac_app/latest

Test location /workspace/coverage/default/18.kmac_burst_write.3432890232
Short name T753
Test name
Test status
Simulation time 30514654282 ps
CPU time 1476.3 seconds
Started Aug 10 06:36:58 PM PDT 24
Finished Aug 10 07:01:34 PM PDT 24
Peak memory 249440 kb
Host smart-91cd8e88-5535-4cdb-9398-1ad2ce98ee8c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432890232 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.343289023
2 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_burst_write/latest

Test location /workspace/coverage/default/18.kmac_edn_timeout_error.1100619547
Short name T649
Test name
Test status
Simulation time 20727267 ps
CPU time 0.83 seconds
Started Aug 10 06:37:25 PM PDT 24
Finished Aug 10 06:37:26 PM PDT 24
Peak memory 218496 kb
Host smart-2af01dc3-0471-415c-a052-3d7ace34ccaa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1100619547 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.1100619547 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/18.kmac_entropy_mode_error.432706862
Short name T537
Test name
Test status
Simulation time 226967210 ps
CPU time 0.83 seconds
Started Aug 10 06:37:29 PM PDT 24
Finished Aug 10 06:37:30 PM PDT 24
Peak memory 220816 kb
Host smart-a1d1997d-b344-424a-80fe-61acc03591b8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=432706862 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.432706862 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/18.kmac_entropy_refresh.3639001327
Short name T540
Test name
Test status
Simulation time 33301731374 ps
CPU time 103.67 seconds
Started Aug 10 06:37:28 PM PDT 24
Finished Aug 10 06:39:12 PM PDT 24
Peak memory 296660 kb
Host smart-ae206085-bc9a-4f05-b7ec-c3c21403d0fe
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639001327 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.3
639001327 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/18.kmac_error.2888007710
Short name T69
Test name
Test status
Simulation time 5426476541 ps
CPU time 187.58 seconds
Started Aug 10 06:37:25 PM PDT 24
Finished Aug 10 06:40:32 PM PDT 24
Peak memory 373280 kb
Host smart-91577404-2ce6-4d7d-ba62-9498a6dff1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888007710 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.2888007710 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_error/latest

Test location /workspace/coverage/default/18.kmac_key_error.944487576
Short name T374
Test name
Test status
Simulation time 996426713 ps
CPU time 6.71 seconds
Started Aug 10 06:37:29 PM PDT 24
Finished Aug 10 06:37:36 PM PDT 24
Peak memory 218692 kb
Host smart-403cc299-7165-4c41-94e2-3b104e344153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944487576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.944487576 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_key_error/latest

Test location /workspace/coverage/default/18.kmac_long_msg_and_output.4070103119
Short name T1049
Test name
Test status
Simulation time 48486995614 ps
CPU time 2506.33 seconds
Started Aug 10 06:36:58 PM PDT 24
Finished Aug 10 07:18:44 PM PDT 24
Peak memory 2492860 kb
Host smart-344307ff-6c25-4757-8a25-cd61118fcf92
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070103119 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_a
nd_output.4070103119 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/18.kmac_sideload.3000392766
Short name T611
Test name
Test status
Simulation time 363778271 ps
CPU time 29.1 seconds
Started Aug 10 06:36:59 PM PDT 24
Finished Aug 10 06:37:28 PM PDT 24
Peak memory 228104 kb
Host smart-f303c778-1b30-43f3-8b7e-ba09cf2f0e98
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000392766 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.3000392766 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_sideload/latest

Test location /workspace/coverage/default/18.kmac_smoke.3612372342
Short name T943
Test name
Test status
Simulation time 2238454541 ps
CPU time 67.45 seconds
Started Aug 10 06:36:54 PM PDT 24
Finished Aug 10 06:38:01 PM PDT 24
Peak memory 227132 kb
Host smart-35a54955-751c-48f4-b71a-b6b1d95f0359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612372342 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.3612372342 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_smoke/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_kmac.676597486
Short name T772
Test name
Test status
Simulation time 274876313 ps
CPU time 7.6 seconds
Started Aug 10 06:37:18 PM PDT 24
Finished Aug 10 06:37:26 PM PDT 24
Peak memory 219816 kb
Host smart-3ac3b909-0351-4fbf-a09c-09eb620f45f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676597486 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.kmac_test_vectors_kmac.676597486 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_kmac_xof.4189492031
Short name T672
Test name
Test status
Simulation time 213491343 ps
CPU time 6.25 seconds
Started Aug 10 06:37:19 PM PDT 24
Finished Aug 10 06:37:26 PM PDT 24
Peak memory 219800 kb
Host smart-0cd13267-e4c3-40d2-9bda-b7527963dcbb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189492031 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.kmac_test_vectors_kmac_xof.4189492031 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_224.584038942
Short name T836
Test name
Test status
Simulation time 27737633920 ps
CPU time 2208.58 seconds
Started Aug 10 06:36:58 PM PDT 24
Finished Aug 10 07:13:47 PM PDT 24
Peak memory 1211100 kb
Host smart-22fc6493-b05b-4695-a4a1-67cae5189d1a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=584038942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_224.584038942 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_256.3380939524
Short name T203
Test name
Test status
Simulation time 153715708201 ps
CPU time 3196.21 seconds
Started Aug 10 06:37:07 PM PDT 24
Finished Aug 10 07:30:24 PM PDT 24
Peak memory 3021724 kb
Host smart-b6d998ea-b240-4537-9957-7bf6b658d569
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3380939524 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_256.3380939524 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_384.1233972714
Short name T529
Test name
Test status
Simulation time 125707263077 ps
CPU time 2402.31 seconds
Started Aug 10 06:37:07 PM PDT 24
Finished Aug 10 07:17:10 PM PDT 24
Peak memory 2393760 kb
Host smart-416651ae-5d5e-4595-9fb0-ebcdb7313676
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1233972714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_384.1233972714 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_512.2904287547
Short name T450
Test name
Test status
Simulation time 66187165440 ps
CPU time 1580.1 seconds
Started Aug 10 06:37:05 PM PDT 24
Finished Aug 10 07:03:26 PM PDT 24
Peak memory 1748504 kb
Host smart-b1a99f32-51d9-4d94-95db-bdfec1bf0eab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2904287547 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_512.2904287547 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_shake_128.3550199418
Short name T938
Test name
Test status
Simulation time 714380825091 ps
CPU time 9304.14 seconds
Started Aug 10 06:37:14 PM PDT 24
Finished Aug 10 09:12:20 PM PDT 24
Peak memory 7706084 kb
Host smart-80e7ae5d-714c-4b2a-a399-128a62da21f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3550199418 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_128.3550199418 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_shake_256.1379128917
Short name T778
Test name
Test status
Simulation time 60691570688 ps
CPU time 5237.99 seconds
Started Aug 10 06:37:19 PM PDT 24
Finished Aug 10 08:04:38 PM PDT 24
Peak memory 2193348 kb
Host smart-fe4b9ba9-cfb1-4bae-81f1-db1e751c5a40
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1379128917 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_256.1379128917 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/19.kmac_alert_test.3500845285
Short name T469
Test name
Test status
Simulation time 45982650 ps
CPU time 0.83 seconds
Started Aug 10 06:38:01 PM PDT 24
Finished Aug 10 06:38:02 PM PDT 24
Peak memory 218604 kb
Host smart-eb5a7881-9595-44bf-8187-513c9c177aa8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500845285 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.3500845285 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_alert_test/latest

Test location /workspace/coverage/default/19.kmac_app.3837482720
Short name T807
Test name
Test status
Simulation time 11323097468 ps
CPU time 172.11 seconds
Started Aug 10 06:37:48 PM PDT 24
Finished Aug 10 06:40:40 PM PDT 24
Peak memory 349728 kb
Host smart-b4490bbc-bd7c-42ac-a66b-1d6755929ebb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837482720 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.3837482720 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/19.kmac_app/latest

Test location /workspace/coverage/default/19.kmac_burst_write.3499788603
Short name T87
Test name
Test status
Simulation time 30503530150 ps
CPU time 1255.75 seconds
Started Aug 10 06:37:35 PM PDT 24
Finished Aug 10 06:58:31 PM PDT 24
Peak memory 264856 kb
Host smart-9fcea9d1-8f4f-4cd3-ad64-ace542e14edf
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499788603 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.349978860
3 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_burst_write/latest

Test location /workspace/coverage/default/19.kmac_edn_timeout_error.3355719739
Short name T879
Test name
Test status
Simulation time 12963301 ps
CPU time 0.84 seconds
Started Aug 10 06:38:02 PM PDT 24
Finished Aug 10 06:38:03 PM PDT 24
Peak memory 218472 kb
Host smart-ca4b26a4-c356-428e-afd0-91f48041262a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3355719739 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.3355719739 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/19.kmac_entropy_mode_error.4048155688
Short name T534
Test name
Test status
Simulation time 74524592 ps
CPU time 1.18 seconds
Started Aug 10 06:38:01 PM PDT 24
Finished Aug 10 06:38:03 PM PDT 24
Peak memory 218636 kb
Host smart-04cbb1f1-aa5e-49c5-b2db-99a859871078
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4048155688 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.4048155688 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/19.kmac_entropy_refresh.3374700269
Short name T275
Test name
Test status
Simulation time 23564423423 ps
CPU time 222.92 seconds
Started Aug 10 06:37:51 PM PDT 24
Finished Aug 10 06:41:34 PM PDT 24
Peak memory 399580 kb
Host smart-38eacc29-c2ea-43c7-b6cf-41d09dcbfddb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374700269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.3
374700269 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/19.kmac_error.441548700
Short name T277
Test name
Test status
Simulation time 4327801114 ps
CPU time 161.38 seconds
Started Aug 10 06:37:56 PM PDT 24
Finished Aug 10 06:40:37 PM PDT 24
Peak memory 288072 kb
Host smart-2427087c-2520-4a72-9a8e-a4b2bb51084d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441548700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.441548700 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_error/latest

Test location /workspace/coverage/default/19.kmac_key_error.456181755
Short name T1031
Test name
Test status
Simulation time 9077359662 ps
CPU time 7.02 seconds
Started Aug 10 06:37:56 PM PDT 24
Finished Aug 10 06:38:03 PM PDT 24
Peak memory 226820 kb
Host smart-2700ab79-9819-4425-ba1f-117a44c3fa4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456181755 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.456181755 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_key_error/latest

Test location /workspace/coverage/default/19.kmac_lc_escalation.2043364404
Short name T971
Test name
Test status
Simulation time 52717524 ps
CPU time 1.56 seconds
Started Aug 10 06:38:02 PM PDT 24
Finished Aug 10 06:38:04 PM PDT 24
Peak memory 227000 kb
Host smart-9f748e57-7aef-4ae3-ba15-127da8159ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043364404 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.2043364404 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/19.kmac_lc_escalation/latest

Test location /workspace/coverage/default/19.kmac_long_msg_and_output.2373124219
Short name T482
Test name
Test status
Simulation time 75746644695 ps
CPU time 3607.48 seconds
Started Aug 10 06:37:34 PM PDT 24
Finished Aug 10 07:37:42 PM PDT 24
Peak memory 2961064 kb
Host smart-fe0ff9b2-4aab-4cae-aa94-5e33090b5e4b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373124219 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_a
nd_output.2373124219 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/19.kmac_sideload.833680580
Short name T514
Test name
Test status
Simulation time 7522124717 ps
CPU time 45.47 seconds
Started Aug 10 06:37:34 PM PDT 24
Finished Aug 10 06:38:20 PM PDT 24
Peak memory 258156 kb
Host smart-b029100b-7cbf-4078-91be-11fe4168b2ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833680580 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.833680580 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_sideload/latest

Test location /workspace/coverage/default/19.kmac_smoke.2067466062
Short name T572
Test name
Test status
Simulation time 791814601 ps
CPU time 26.92 seconds
Started Aug 10 06:37:36 PM PDT 24
Finished Aug 10 06:38:03 PM PDT 24
Peak memory 226908 kb
Host smart-e2ec10e9-1eff-49aa-ba3e-5e75674ed695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067466062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.2067466062 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_smoke/latest

Test location /workspace/coverage/default/19.kmac_stress_all.1662198556
Short name T43
Test name
Test status
Simulation time 7325770634 ps
CPU time 674.18 seconds
Started Aug 10 06:38:01 PM PDT 24
Finished Aug 10 06:49:16 PM PDT 24
Peak memory 308860 kb
Host smart-50600417-ef27-40a9-bec1-3040e62269e8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1662198556 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.1662198556 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_stress_all/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_kmac.301597173
Short name T758
Test name
Test status
Simulation time 203041316 ps
CPU time 6.52 seconds
Started Aug 10 06:37:37 PM PDT 24
Finished Aug 10 06:37:43 PM PDT 24
Peak memory 219880 kb
Host smart-2d601650-e003-44df-a99d-a9716856dc0d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301597173 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.kmac_test_vectors_kmac.301597173 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_kmac_xof.3434168354
Short name T876
Test name
Test status
Simulation time 369270829 ps
CPU time 6.05 seconds
Started Aug 10 06:37:42 PM PDT 24
Finished Aug 10 06:37:48 PM PDT 24
Peak memory 218960 kb
Host smart-e1a35a9c-0012-4611-893d-542355192dd8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434168354 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.kmac_test_vectors_kmac_xof.3434168354 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_224.1934489480
Short name T512
Test name
Test status
Simulation time 33015926357 ps
CPU time 2218.3 seconds
Started Aug 10 06:37:35 PM PDT 24
Finished Aug 10 07:14:33 PM PDT 24
Peak memory 1219352 kb
Host smart-0d5f4bbb-7d3e-4caf-a370-ece044762b24
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1934489480 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_224.1934489480 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_256.832708739
Short name T736
Test name
Test status
Simulation time 190147184686 ps
CPU time 3535.79 seconds
Started Aug 10 06:37:36 PM PDT 24
Finished Aug 10 07:36:32 PM PDT 24
Peak memory 3003124 kb
Host smart-e4d4bba6-4462-441f-bdcc-ef90d2c5a233
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=832708739 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_256.832708739 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_384.1648142203
Short name T843
Test name
Test status
Simulation time 83061379648 ps
CPU time 1508.88 seconds
Started Aug 10 06:37:34 PM PDT 24
Finished Aug 10 07:02:43 PM PDT 24
Peak memory 926744 kb
Host smart-92b7780d-fa2f-4b00-aa0b-a1aef9a97c11
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1648142203 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_384.1648142203 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_512.2223727281
Short name T407
Test name
Test status
Simulation time 35587450356 ps
CPU time 1642.6 seconds
Started Aug 10 06:37:38 PM PDT 24
Finished Aug 10 07:05:00 PM PDT 24
Peak memory 1777616 kb
Host smart-3111732e-eedd-4c98-9436-cc858b8c543f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2223727281 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_512.2223727281 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_shake_128.1094278451
Short name T417
Test name
Test status
Simulation time 253621559747 ps
CPU time 6451.8 seconds
Started Aug 10 06:37:36 PM PDT 24
Finished Aug 10 08:25:10 PM PDT 24
Peak memory 2701016 kb
Host smart-38a1a4af-14e5-41c4-ac9a-f6b995e768e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1094278451 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_128.1094278451 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_shake_256.3534925227
Short name T42
Test name
Test status
Simulation time 590788464567 ps
CPU time 8743.02 seconds
Started Aug 10 06:37:37 PM PDT 24
Finished Aug 10 09:03:21 PM PDT 24
Peak memory 6272856 kb
Host smart-968e5d96-f919-4fb5-a18b-5c861d688bb9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3534925227 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_256.3534925227 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/2.kmac_alert_test.1979753883
Short name T996
Test name
Test status
Simulation time 15446599 ps
CPU time 0.87 seconds
Started Aug 10 06:29:44 PM PDT 24
Finished Aug 10 06:29:45 PM PDT 24
Peak memory 218536 kb
Host smart-7a0b0c84-a651-44c3-853d-b5e722bfd651
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979753883 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.1979753883 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_alert_test/latest

Test location /workspace/coverage/default/2.kmac_app.4008508542
Short name T308
Test name
Test status
Simulation time 5952251059 ps
CPU time 80.82 seconds
Started Aug 10 06:29:23 PM PDT 24
Finished Aug 10 06:30:44 PM PDT 24
Peak memory 246960 kb
Host smart-b9ffb480-84ca-405c-8209-35b66d0747fa
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008508542 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.4008508542 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/2.kmac_app/latest

Test location /workspace/coverage/default/2.kmac_app_with_partial_data.53340025
Short name T762
Test name
Test status
Simulation time 33737710430 ps
CPU time 393.54 seconds
Started Aug 10 06:29:24 PM PDT 24
Finished Aug 10 06:35:58 PM PDT 24
Peak memory 340764 kb
Host smart-9050e939-903f-43be-a1b5-4b9b572a5962
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53340025 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partia
l_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_parti
al_data.53340025 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/2.kmac_burst_write.693060704
Short name T685
Test name
Test status
Simulation time 3116564602 ps
CPU time 87.28 seconds
Started Aug 10 06:29:13 PM PDT 24
Finished Aug 10 06:30:41 PM PDT 24
Peak memory 227100 kb
Host smart-007650ef-93d4-4f62-8286-f42b5a5b8602
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693060704 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.693060704 +
enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_burst_write/latest

Test location /workspace/coverage/default/2.kmac_edn_timeout_error.352077981
Short name T57
Test name
Test status
Simulation time 17699692 ps
CPU time 0.91 seconds
Started Aug 10 06:29:31 PM PDT 24
Finished Aug 10 06:29:32 PM PDT 24
Peak memory 218456 kb
Host smart-132f3fe2-a83e-4acb-8d68-1a32dca72ec1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=352077981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.352077981 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_mode_error.1439245679
Short name T729
Test name
Test status
Simulation time 41115797 ps
CPU time 1.02 seconds
Started Aug 10 06:29:31 PM PDT 24
Finished Aug 10 06:29:32 PM PDT 24
Peak memory 222016 kb
Host smart-12d776b3-e7e2-4da3-9ece-18195d009d7f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1439245679 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.1439245679 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_ready_error.3826016256
Short name T857
Test name
Test status
Simulation time 323342165 ps
CPU time 3.37 seconds
Started Aug 10 06:29:33 PM PDT 24
Finished Aug 10 06:29:36 PM PDT 24
Peak memory 224544 kb
Host smart-bf462434-9f75-4416-af4b-8eacf607e538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826016256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.3826016256 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_refresh.980600860
Short name T578
Test name
Test status
Simulation time 275275203406 ps
CPU time 377.44 seconds
Started Aug 10 06:29:23 PM PDT 24
Finished Aug 10 06:35:41 PM PDT 24
Peak memory 473552 kb
Host smart-a2eaf71a-0f9e-43cc-9894-9f2f1cf622a8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980600860 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.980
600860 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/2.kmac_error.2983505917
Short name T918
Test name
Test status
Simulation time 22591069706 ps
CPU time 221.74 seconds
Started Aug 10 06:29:33 PM PDT 24
Finished Aug 10 06:33:15 PM PDT 24
Peak memory 300548 kb
Host smart-4d29e754-fa8f-435f-b7ab-d419f945c3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983505917 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.2983505917 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_error/latest

Test location /workspace/coverage/default/2.kmac_key_error.1792140952
Short name T443
Test name
Test status
Simulation time 1509424434 ps
CPU time 11.4 seconds
Started Aug 10 06:29:32 PM PDT 24
Finished Aug 10 06:29:44 PM PDT 24
Peak memory 226684 kb
Host smart-30bc6979-b4e5-4bbf-815a-8bb2bd01e58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792140952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.1792140952 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_key_error/latest

Test location /workspace/coverage/default/2.kmac_lc_escalation.2213398891
Short name T465
Test name
Test status
Simulation time 40630821 ps
CPU time 1.48 seconds
Started Aug 10 06:29:32 PM PDT 24
Finished Aug 10 06:29:33 PM PDT 24
Peak memory 226868 kb
Host smart-9d129433-3b35-4cc2-a928-6575fe969068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213398891 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.2213398891 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/2.kmac_lc_escalation/latest

Test location /workspace/coverage/default/2.kmac_long_msg_and_output.807463802
Short name T34
Test name
Test status
Simulation time 16191245080 ps
CPU time 663.89 seconds
Started Aug 10 06:29:17 PM PDT 24
Finished Aug 10 06:40:21 PM PDT 24
Peak memory 944456 kb
Host smart-86fce8e3-b01c-4484-9bcf-da36c60c8a9a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807463802 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_and
_output.807463802 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/2.kmac_mubi.3002201253
Short name T1007
Test name
Test status
Simulation time 546937133 ps
CPU time 42.85 seconds
Started Aug 10 06:29:31 PM PDT 24
Finished Aug 10 06:30:14 PM PDT 24
Peak memory 235908 kb
Host smart-cd77ed27-5e83-4456-9f03-21cb140b31c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002201253 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.3002201253 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_mubi/latest

Test location /workspace/coverage/default/2.kmac_sec_cm.3071664361
Short name T125
Test name
Test status
Simulation time 13501317589 ps
CPU time 103.51 seconds
Started Aug 10 06:29:35 PM PDT 24
Finished Aug 10 06:31:19 PM PDT 24
Peak memory 278204 kb
Host smart-c00d9dd8-ae14-47b3-8a03-84e9b9cfc367
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071664361 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.3071664361 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspace/2.kmac_sec_cm/latest

Test location /workspace/coverage/default/2.kmac_sideload.1293987100
Short name T213
Test name
Test status
Simulation time 3311662717 ps
CPU time 90.31 seconds
Started Aug 10 06:29:15 PM PDT 24
Finished Aug 10 06:30:45 PM PDT 24
Peak memory 296080 kb
Host smart-045c09b3-2b3d-450d-b80d-b0884e35e17a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293987100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.1293987100 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_sideload/latest

Test location /workspace/coverage/default/2.kmac_smoke.104056316
Short name T354
Test name
Test status
Simulation time 501828205 ps
CPU time 16.22 seconds
Started Aug 10 06:29:18 PM PDT 24
Finished Aug 10 06:29:34 PM PDT 24
Peak memory 226992 kb
Host smart-1e903817-416d-4d81-b15f-c0004ac54e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104056316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.104056316 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_smoke/latest

Test location /workspace/coverage/default/2.kmac_stress_all.1801580994
Short name T859
Test name
Test status
Simulation time 55410300075 ps
CPU time 266.89 seconds
Started Aug 10 06:29:35 PM PDT 24
Finished Aug 10 06:34:02 PM PDT 24
Peak memory 289480 kb
Host smart-9b2ef270-b71e-433a-9147-f4432baf4917
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1801580994 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.1801580994 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_stress_all/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_kmac.971849523
Short name T688
Test name
Test status
Simulation time 552338012 ps
CPU time 6.72 seconds
Started Aug 10 06:29:23 PM PDT 24
Finished Aug 10 06:29:30 PM PDT 24
Peak memory 219916 kb
Host smart-b93a6b19-2355-4d31-a692-21cc29f7bfff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971849523 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.kmac_test_vectors_kmac.971849523 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_kmac_xof.101702198
Short name T1019
Test name
Test status
Simulation time 948264868 ps
CPU time 6.43 seconds
Started Aug 10 06:29:23 PM PDT 24
Finished Aug 10 06:29:29 PM PDT 24
Peak memory 219808 kb
Host smart-4bad199f-729a-490f-8486-4e21878334a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101702198 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.kmac_test_vectors_kmac_xof.101702198 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_224.2338607798
Short name T704
Test name
Test status
Simulation time 119597681400 ps
CPU time 2138.47 seconds
Started Aug 10 06:29:14 PM PDT 24
Finished Aug 10 07:04:52 PM PDT 24
Peak memory 1200528 kb
Host smart-8f87066b-b271-49b5-86d1-069889123115
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2338607798 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.2338607798 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_256.2739561658
Short name T831
Test name
Test status
Simulation time 764046618771 ps
CPU time 3347 seconds
Started Aug 10 06:29:24 PM PDT 24
Finished Aug 10 07:25:12 PM PDT 24
Peak memory 3020556 kb
Host smart-53f9c8ef-d4b3-400c-b7f3-95fca9f8e001
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2739561658 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.2739561658 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_384.3268424879
Short name T383
Test name
Test status
Simulation time 142356502838 ps
CPU time 2610.07 seconds
Started Aug 10 06:29:23 PM PDT 24
Finished Aug 10 07:12:53 PM PDT 24
Peak memory 2414328 kb
Host smart-5f691015-2779-466e-b9d1-2e1455abd999
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3268424879 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.3268424879 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_512.2613337265
Short name T215
Test name
Test status
Simulation time 52559534704 ps
CPU time 1765.96 seconds
Started Aug 10 06:29:22 PM PDT 24
Finished Aug 10 06:58:49 PM PDT 24
Peak memory 1745512 kb
Host smart-f4c441e1-95ee-4c2f-bd52-ce2ec6501bd6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2613337265 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.2613337265 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_shake_128.1895715814
Short name T995
Test name
Test status
Simulation time 859576329480 ps
CPU time 6648.17 seconds
Started Aug 10 06:29:23 PM PDT 24
Finished Aug 10 08:20:12 PM PDT 24
Peak memory 2658716 kb
Host smart-ef0ff36b-02e6-4785-93dd-8ee72f4fbd7a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1895715814 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.1895715814 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_shake_256.977188540
Short name T989
Test name
Test status
Simulation time 208994425284 ps
CPU time 5696.27 seconds
Started Aug 10 06:29:24 PM PDT 24
Finished Aug 10 08:04:21 PM PDT 24
Peak memory 2226264 kb
Host smart-f9adb3ae-9397-431a-b237-3a7ec2f3fbc6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=977188540 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.977188540 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/20.kmac_alert_test.1262218388
Short name T358
Test name
Test status
Simulation time 81432203 ps
CPU time 0.89 seconds
Started Aug 10 06:38:34 PM PDT 24
Finished Aug 10 06:38:35 PM PDT 24
Peak memory 218604 kb
Host smart-ebb1ebcd-083e-4983-ae96-9ca5df47b08d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262218388 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.1262218388 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_alert_test/latest

Test location /workspace/coverage/default/20.kmac_app.2359480989
Short name T351
Test name
Test status
Simulation time 15125297316 ps
CPU time 210.28 seconds
Started Aug 10 06:38:21 PM PDT 24
Finished Aug 10 06:41:51 PM PDT 24
Peak memory 382544 kb
Host smart-626b8b6f-172b-4f14-b1b7-58b36f703b34
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359480989 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.2359480989 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/20.kmac_app/latest

Test location /workspace/coverage/default/20.kmac_burst_write.3627558456
Short name T714
Test name
Test status
Simulation time 177673016570 ps
CPU time 1553.41 seconds
Started Aug 10 06:38:07 PM PDT 24
Finished Aug 10 07:04:01 PM PDT 24
Peak memory 247036 kb
Host smart-ca3f7ff4-8e3b-425d-88bb-b6f30a89f66f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627558456 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.362755845
6 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_burst_write/latest

Test location /workspace/coverage/default/20.kmac_entropy_refresh.2236630537
Short name T227
Test name
Test status
Simulation time 16927349480 ps
CPU time 69.34 seconds
Started Aug 10 06:38:21 PM PDT 24
Finished Aug 10 06:39:31 PM PDT 24
Peak memory 268204 kb
Host smart-b34202b5-00e4-4c2b-a295-730dc355e70c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236630537 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.2
236630537 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/20.kmac_error.2733506950
Short name T924
Test name
Test status
Simulation time 37007333885 ps
CPU time 165.29 seconds
Started Aug 10 06:38:21 PM PDT 24
Finished Aug 10 06:41:06 PM PDT 24
Peak memory 360632 kb
Host smart-8db9a2be-349d-467a-8391-a932d0224277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733506950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.2733506950 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_error/latest

Test location /workspace/coverage/default/20.kmac_key_error.2031502792
Short name T6
Test name
Test status
Simulation time 1064212611 ps
CPU time 8.42 seconds
Started Aug 10 06:38:22 PM PDT 24
Finished Aug 10 06:38:30 PM PDT 24
Peak memory 226756 kb
Host smart-4211fc71-29a0-4bdd-aa11-5216f7ba46db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031502792 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.2031502792 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_key_error/latest

Test location /workspace/coverage/default/20.kmac_lc_escalation.126100075
Short name T29
Test name
Test status
Simulation time 130368184 ps
CPU time 1.34 seconds
Started Aug 10 06:38:25 PM PDT 24
Finished Aug 10 06:38:27 PM PDT 24
Peak memory 227012 kb
Host smart-6af4319a-e852-4f4b-93fb-3e30a35af3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126100075 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.126100075 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/20.kmac_lc_escalation/latest

Test location /workspace/coverage/default/20.kmac_long_msg_and_output.1085657512
Short name T45
Test name
Test status
Simulation time 5783138829 ps
CPU time 145.52 seconds
Started Aug 10 06:38:07 PM PDT 24
Finished Aug 10 06:40:32 PM PDT 24
Peak memory 299888 kb
Host smart-642f290f-42e0-4ca6-a005-ed7db138e86a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085657512 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_a
nd_output.1085657512 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/20.kmac_sideload.3846238220
Short name T643
Test name
Test status
Simulation time 6077687205 ps
CPU time 263.61 seconds
Started Aug 10 06:38:07 PM PDT 24
Finished Aug 10 06:42:31 PM PDT 24
Peak memory 311392 kb
Host smart-753604db-52de-4055-8c27-76842c890c0e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846238220 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.3846238220 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_sideload/latest

Test location /workspace/coverage/default/20.kmac_smoke.485812418
Short name T325
Test name
Test status
Simulation time 15788213836 ps
CPU time 50.59 seconds
Started Aug 10 06:38:07 PM PDT 24
Finished Aug 10 06:38:58 PM PDT 24
Peak memory 222600 kb
Host smart-b411fda2-720a-4002-a433-f3495e68dc7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485812418 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.485812418 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_smoke/latest

Test location /workspace/coverage/default/20.kmac_stress_all.2963989886
Short name T343
Test name
Test status
Simulation time 26918035786 ps
CPU time 848.29 seconds
Started Aug 10 06:38:26 PM PDT 24
Finished Aug 10 06:52:34 PM PDT 24
Peak memory 600468 kb
Host smart-46eaa8b7-6d59-4766-a093-99969e5377d5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2963989886 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.2963989886 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_stress_all/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_kmac.4293150250
Short name T1045
Test name
Test status
Simulation time 406762359 ps
CPU time 6.48 seconds
Started Aug 10 06:38:23 PM PDT 24
Finished Aug 10 06:38:29 PM PDT 24
Peak memory 218972 kb
Host smart-7cfaadf0-fed9-47a5-bf78-f14144902570
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293150250 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.kmac_test_vectors_kmac.4293150250 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_kmac_xof.2563413228
Short name T511
Test name
Test status
Simulation time 442693534 ps
CPU time 5.94 seconds
Started Aug 10 06:38:23 PM PDT 24
Finished Aug 10 06:38:29 PM PDT 24
Peak memory 218952 kb
Host smart-a671daf1-3d79-430f-940f-e2f36ffb4e2a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563413228 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.kmac_test_vectors_kmac_xof.2563413228 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_224.3696042765
Short name T526
Test name
Test status
Simulation time 252915297625 ps
CPU time 3022.76 seconds
Started Aug 10 06:38:08 PM PDT 24
Finished Aug 10 07:28:31 PM PDT 24
Peak memory 3250588 kb
Host smart-e082b253-f3bf-4102-bfe8-90f5ee0b1926
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3696042765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_224.3696042765 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_256.822765552
Short name T1023
Test name
Test status
Simulation time 87877116840 ps
CPU time 2033.33 seconds
Started Aug 10 06:38:08 PM PDT 24
Finished Aug 10 07:12:01 PM PDT 24
Peak memory 1151376 kb
Host smart-a85637f2-3372-41b0-a46a-4f2f7219909d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=822765552 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_256.822765552 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_384.447090513
Short name T220
Test name
Test status
Simulation time 28607879597 ps
CPU time 1701.04 seconds
Started Aug 10 06:38:13 PM PDT 24
Finished Aug 10 07:06:34 PM PDT 24
Peak memory 919904 kb
Host smart-7a941d9b-e561-41d0-b3da-fb112aa1cd0b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=447090513 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_384.447090513 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_512.340835037
Short name T1048
Test name
Test status
Simulation time 43989884604 ps
CPU time 1386.24 seconds
Started Aug 10 06:38:13 PM PDT 24
Finished Aug 10 07:01:19 PM PDT 24
Peak memory 702332 kb
Host smart-9a4a9845-eccc-4236-a665-eb6c587ff8da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=340835037 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_512.340835037 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_shake_128.2804268174
Short name T567
Test name
Test status
Simulation time 139942818919 ps
CPU time 6568.42 seconds
Started Aug 10 06:38:16 PM PDT 24
Finished Aug 10 08:27:45 PM PDT 24
Peak memory 2640300 kb
Host smart-c6fea3a7-c208-4adc-96ab-4a6daf62dace
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2804268174 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_128.2804268174 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_shake_256.3338202502
Short name T248
Test name
Test status
Simulation time 152952917703 ps
CPU time 9144.82 seconds
Started Aug 10 06:38:14 PM PDT 24
Finished Aug 10 09:10:40 PM PDT 24
Peak memory 6515548 kb
Host smart-36c324c7-0c42-4f43-87fb-4b252b5cece3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3338202502 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_256.3338202502 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/21.kmac_alert_test.4174007106
Short name T1027
Test name
Test status
Simulation time 51273912 ps
CPU time 0.85 seconds
Started Aug 10 06:39:06 PM PDT 24
Finished Aug 10 06:39:07 PM PDT 24
Peak memory 218592 kb
Host smart-ce4c3a7c-0943-44a5-9ba9-7622653b9cea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174007106 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.4174007106 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_alert_test/latest

Test location /workspace/coverage/default/21.kmac_app.369098019
Short name T441
Test name
Test status
Simulation time 26261895998 ps
CPU time 211.6 seconds
Started Aug 10 06:39:00 PM PDT 24
Finished Aug 10 06:42:32 PM PDT 24
Peak memory 400700 kb
Host smart-23380d53-f2cd-4078-bdf3-ba256b0f33d9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369098019 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.369098019 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/21.kmac_app/latest

Test location /workspace/coverage/default/21.kmac_burst_write.241171032
Short name T774
Test name
Test status
Simulation time 12468552462 ps
CPU time 1207.58 seconds
Started Aug 10 06:38:39 PM PDT 24
Finished Aug 10 06:58:47 PM PDT 24
Peak memory 245744 kb
Host smart-41648d51-6d19-4b13-b3f2-c1fe7c3bf8a4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241171032 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.241171032
+enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_burst_write/latest

Test location /workspace/coverage/default/21.kmac_entropy_refresh.1012165431
Short name T915
Test name
Test status
Simulation time 66495692963 ps
CPU time 426.31 seconds
Started Aug 10 06:39:00 PM PDT 24
Finished Aug 10 06:46:06 PM PDT 24
Peak memory 515636 kb
Host smart-1fcdfdfb-225c-4c14-8a24-390d388d7652
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012165431 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_entropy_refresh.1
012165431 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/21.kmac_error.3289351925
Short name T927
Test name
Test status
Simulation time 14414738810 ps
CPU time 518.08 seconds
Started Aug 10 06:39:08 PM PDT 24
Finished Aug 10 06:47:47 PM PDT 24
Peak memory 603056 kb
Host smart-81149a08-f910-49ee-97a9-ec63df59c77e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289351925 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_error.3289351925 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_error/latest

Test location /workspace/coverage/default/21.kmac_key_error.2305908194
Short name T1043
Test name
Test status
Simulation time 673491289 ps
CPU time 2.79 seconds
Started Aug 10 06:39:09 PM PDT 24
Finished Aug 10 06:39:12 PM PDT 24
Peak memory 226632 kb
Host smart-bc586c39-485b-4d59-a208-b77038a464bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305908194 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.2305908194 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_key_error/latest

Test location /workspace/coverage/default/21.kmac_lc_escalation.780376205
Short name T1003
Test name
Test status
Simulation time 67281155 ps
CPU time 1.36 seconds
Started Aug 10 06:39:06 PM PDT 24
Finished Aug 10 06:39:08 PM PDT 24
Peak memory 226900 kb
Host smart-c921984b-62a4-4463-ae80-1bdfdce0511c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780376205 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.780376205 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/21.kmac_lc_escalation/latest

Test location /workspace/coverage/default/21.kmac_long_msg_and_output.342285033
Short name T254
Test name
Test status
Simulation time 55547660259 ps
CPU time 645.55 seconds
Started Aug 10 06:38:38 PM PDT 24
Finished Aug 10 06:49:24 PM PDT 24
Peak memory 921140 kb
Host smart-7f49bba1-fe82-43a2-a4c6-0517a377d2ed
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342285033 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_an
d_output.342285033 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/21.kmac_sideload.589284007
Short name T97
Test name
Test status
Simulation time 14984937501 ps
CPU time 441.92 seconds
Started Aug 10 06:38:38 PM PDT 24
Finished Aug 10 06:46:00 PM PDT 24
Peak memory 558748 kb
Host smart-d445c923-4a36-4b23-bafd-bc09bc21c7db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589284007 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.589284007 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_sideload/latest

Test location /workspace/coverage/default/21.kmac_smoke.3655146778
Short name T756
Test name
Test status
Simulation time 15024796443 ps
CPU time 90.72 seconds
Started Aug 10 06:38:31 PM PDT 24
Finished Aug 10 06:40:02 PM PDT 24
Peak memory 229608 kb
Host smart-59bd2d0f-8863-473f-854c-caa69fd44e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655146778 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.3655146778 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_smoke/latest

Test location /workspace/coverage/default/21.kmac_stress_all.2280809220
Short name T663
Test name
Test status
Simulation time 2446576087 ps
CPU time 65.39 seconds
Started Aug 10 06:39:09 PM PDT 24
Finished Aug 10 06:40:14 PM PDT 24
Peak memory 270968 kb
Host smart-4aba1cb1-ec39-41c5-bc5c-5789187de652
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2280809220 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.2280809220 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_stress_all/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_kmac.3483619777
Short name T493
Test name
Test status
Simulation time 557290867 ps
CPU time 6.45 seconds
Started Aug 10 06:38:37 PM PDT 24
Finished Aug 10 06:38:44 PM PDT 24
Peak memory 219808 kb
Host smart-6b0743c3-cd23-4be9-88c0-eda8e535cb35
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483619777 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.kmac_test_vectors_kmac.3483619777 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_kmac_xof.2705112133
Short name T404
Test name
Test status
Simulation time 351546874 ps
CPU time 5.7 seconds
Started Aug 10 06:38:54 PM PDT 24
Finished Aug 10 06:39:00 PM PDT 24
Peak memory 219828 kb
Host smart-32c001ec-e8f7-4877-bce2-a511272f11dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705112133 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.kmac_test_vectors_kmac_xof.2705112133 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_224.499299052
Short name T91
Test name
Test status
Simulation time 99706577430 ps
CPU time 3789.42 seconds
Started Aug 10 06:38:37 PM PDT 24
Finished Aug 10 07:41:47 PM PDT 24
Peak memory 3315788 kb
Host smart-8b25b8b4-0357-4bb6-a1af-95ff78ed7311
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=499299052 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_224.499299052 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_256.4243868206
Short name T847
Test name
Test status
Simulation time 250966444241 ps
CPU time 3044.54 seconds
Started Aug 10 06:38:39 PM PDT 24
Finished Aug 10 07:29:24 PM PDT 24
Peak memory 2983132 kb
Host smart-4712ca74-09af-46ae-8f24-3a0d75ca147d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4243868206 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_256.4243868206 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_384.3023228212
Short name T613
Test name
Test status
Simulation time 947616648595 ps
CPU time 2304.85 seconds
Started Aug 10 06:38:39 PM PDT 24
Finished Aug 10 07:17:05 PM PDT 24
Peak memory 2381296 kb
Host smart-1c2edb3a-2aa9-4d35-99c3-636115cacdda
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3023228212 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_384.3023228212 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_512.2381026736
Short name T952
Test name
Test status
Simulation time 86972227191 ps
CPU time 1579.11 seconds
Started Aug 10 06:38:39 PM PDT 24
Finished Aug 10 07:04:58 PM PDT 24
Peak memory 1743432 kb
Host smart-a864e254-336a-40f6-8435-6d94cb24edfe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2381026736 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_512.2381026736 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_shake_128.3950405339
Short name T263
Test name
Test status
Simulation time 602723103284 ps
CPU time 6631.81 seconds
Started Aug 10 06:38:38 PM PDT 24
Finished Aug 10 08:29:10 PM PDT 24
Peak memory 2732972 kb
Host smart-64d5fed1-1040-4f14-89d9-94b5583b6c10
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3950405339 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_128.3950405339 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_shake_256.285683069
Short name T683
Test name
Test status
Simulation time 579985578249 ps
CPU time 5545.1 seconds
Started Aug 10 06:38:37 PM PDT 24
Finished Aug 10 08:11:03 PM PDT 24
Peak memory 2227780 kb
Host smart-654eb8cc-495d-4d1e-95d9-b61d5539a181
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=285683069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_256.285683069 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/22.kmac_alert_test.2743772090
Short name T783
Test name
Test status
Simulation time 38779750 ps
CPU time 0.8 seconds
Started Aug 10 06:39:49 PM PDT 24
Finished Aug 10 06:39:50 PM PDT 24
Peak memory 218564 kb
Host smart-65d7b59f-13d5-40de-b2be-845e183fb7be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743772090 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.2743772090 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_alert_test/latest

Test location /workspace/coverage/default/22.kmac_app.1099485027
Short name T282
Test name
Test status
Simulation time 3271303076 ps
CPU time 82.13 seconds
Started Aug 10 06:39:44 PM PDT 24
Finished Aug 10 06:41:06 PM PDT 24
Peak memory 255040 kb
Host smart-73963e39-2725-48f0-8fac-7fed4cb23885
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099485027 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.1099485027 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/22.kmac_app/latest

Test location /workspace/coverage/default/22.kmac_burst_write.3678536333
Short name T315
Test name
Test status
Simulation time 109039780709 ps
CPU time 1253.09 seconds
Started Aug 10 06:39:18 PM PDT 24
Finished Aug 10 07:00:12 PM PDT 24
Peak memory 261324 kb
Host smart-444f34af-0b11-4691-891c-6a207c9f26bf
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678536333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.367853633
3 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_burst_write/latest

Test location /workspace/coverage/default/22.kmac_entropy_refresh.4137904598
Short name T827
Test name
Test status
Simulation time 6054821704 ps
CPU time 97.92 seconds
Started Aug 10 06:39:42 PM PDT 24
Finished Aug 10 06:41:20 PM PDT 24
Peak memory 289316 kb
Host smart-4a6edca5-06d8-4756-8743-d4c4fe4242cd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137904598 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.4
137904598 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/22.kmac_error.1072822538
Short name T359
Test name
Test status
Simulation time 9602012450 ps
CPU time 163.01 seconds
Started Aug 10 06:39:43 PM PDT 24
Finished Aug 10 06:42:26 PM PDT 24
Peak memory 340732 kb
Host smart-ab174c59-7953-46b6-9914-5a68bed21703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072822538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.1072822538 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_error/latest

Test location /workspace/coverage/default/22.kmac_key_error.2674576170
Short name T310
Test name
Test status
Simulation time 18279913414 ps
CPU time 8.49 seconds
Started Aug 10 06:39:42 PM PDT 24
Finished Aug 10 06:39:51 PM PDT 24
Peak memory 226688 kb
Host smart-2abce9bd-815e-4ffe-8962-5767575b6800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674576170 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.2674576170 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_key_error/latest

Test location /workspace/coverage/default/22.kmac_lc_escalation.2206966808
Short name T571
Test name
Test status
Simulation time 237197226 ps
CPU time 1.45 seconds
Started Aug 10 06:39:46 PM PDT 24
Finished Aug 10 06:39:47 PM PDT 24
Peak memory 226960 kb
Host smart-556a3f63-b87b-44b9-b8e5-1ef9aac0ccb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206966808 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.2206966808 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/22.kmac_lc_escalation/latest

Test location /workspace/coverage/default/22.kmac_long_msg_and_output.422057871
Short name T332
Test name
Test status
Simulation time 32460443526 ps
CPU time 1228.15 seconds
Started Aug 10 06:39:13 PM PDT 24
Finished Aug 10 06:59:42 PM PDT 24
Peak memory 787304 kb
Host smart-3a6f4860-5d6a-46da-a654-74f407bd63a5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422057871 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_an
d_output.422057871 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/22.kmac_sideload.3663579331
Short name T766
Test name
Test status
Simulation time 14579392992 ps
CPU time 358.11 seconds
Started Aug 10 06:39:17 PM PDT 24
Finished Aug 10 06:45:15 PM PDT 24
Peak memory 332620 kb
Host smart-80c6650e-18f9-4594-9279-c469e9d25a83
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663579331 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.3663579331 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_sideload/latest

Test location /workspace/coverage/default/22.kmac_smoke.2364318108
Short name T228
Test name
Test status
Simulation time 2501369139 ps
CPU time 63.55 seconds
Started Aug 10 06:39:15 PM PDT 24
Finished Aug 10 06:40:19 PM PDT 24
Peak memory 227004 kb
Host smart-592a0f30-60b9-4812-bd99-eccfdd5bf4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364318108 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.2364318108 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_smoke/latest

Test location /workspace/coverage/default/22.kmac_stress_all.763877857
Short name T394
Test name
Test status
Simulation time 19611483506 ps
CPU time 1782.18 seconds
Started Aug 10 06:39:42 PM PDT 24
Finished Aug 10 07:09:24 PM PDT 24
Peak memory 864528 kb
Host smart-9b98a2bd-4e1f-4050-a88e-26a87cd33d34
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=763877857 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.763877857 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_stress_all/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_kmac.1050711310
Short name T37
Test name
Test status
Simulation time 281716341 ps
CPU time 6.7 seconds
Started Aug 10 06:39:36 PM PDT 24
Finished Aug 10 06:39:43 PM PDT 24
Peak memory 219888 kb
Host smart-f4686064-c583-4d9f-ab27-e4dd6ca21ab9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050711310 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.kmac_test_vectors_kmac.1050711310 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_kmac_xof.3029447450
Short name T547
Test name
Test status
Simulation time 207671193 ps
CPU time 6.09 seconds
Started Aug 10 06:39:46 PM PDT 24
Finished Aug 10 06:39:52 PM PDT 24
Peak memory 219900 kb
Host smart-df4d0b70-b275-4b10-a553-143bed702a88
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029447450 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.kmac_test_vectors_kmac_xof.3029447450 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_224.4120946567
Short name T1018
Test name
Test status
Simulation time 21902910188 ps
CPU time 2255.55 seconds
Started Aug 10 06:39:20 PM PDT 24
Finished Aug 10 07:16:56 PM PDT 24
Peak memory 1223128 kb
Host smart-075ef783-b8d3-4039-9a40-873092a99495
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4120946567 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_224.4120946567 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_256.1094457545
Short name T150
Test name
Test status
Simulation time 19681377257 ps
CPU time 2117.9 seconds
Started Aug 10 06:39:24 PM PDT 24
Finished Aug 10 07:14:42 PM PDT 24
Peak memory 1136100 kb
Host smart-1f0f63eb-7ef7-4304-93aa-9df295c9d4c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1094457545 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_256.1094457545 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_384.2187688315
Short name T899
Test name
Test status
Simulation time 306384530084 ps
CPU time 2703.59 seconds
Started Aug 10 06:39:25 PM PDT 24
Finished Aug 10 07:24:28 PM PDT 24
Peak memory 2447756 kb
Host smart-e5c25cb1-6421-480a-9ada-7bdd71b9726f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2187688315 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_384.2187688315 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_512.2734777615
Short name T608
Test name
Test status
Simulation time 50977396576 ps
CPU time 1203.26 seconds
Started Aug 10 06:39:40 PM PDT 24
Finished Aug 10 06:59:44 PM PDT 24
Peak memory 712332 kb
Host smart-dfdb3045-4834-41be-9d2e-d612c0807829
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2734777615 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_512.2734777615 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_shake_256.2440497309
Short name T463
Test name
Test status
Simulation time 144810307593 ps
CPU time 4984.23 seconds
Started Aug 10 06:39:36 PM PDT 24
Finished Aug 10 08:02:41 PM PDT 24
Peak memory 2240156 kb
Host smart-64f40a96-9124-4381-8d98-413148045fa1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2440497309 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_256.2440497309 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/23.kmac_alert_test.2739514701
Short name T116
Test name
Test status
Simulation time 38110005 ps
CPU time 0.79 seconds
Started Aug 10 06:40:27 PM PDT 24
Finished Aug 10 06:40:27 PM PDT 24
Peak memory 218508 kb
Host smart-c3742975-6eee-43e9-9c89-201bbaa6eca8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739514701 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.2739514701 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_alert_test/latest

Test location /workspace/coverage/default/23.kmac_app.2867670863
Short name T186
Test name
Test status
Simulation time 7033625599 ps
CPU time 198.67 seconds
Started Aug 10 06:40:22 PM PDT 24
Finished Aug 10 06:43:40 PM PDT 24
Peak memory 284472 kb
Host smart-96d60865-5f84-41f3-995f-a60e7ab0c9fa
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867670863 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.2867670863 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/23.kmac_app/latest

Test location /workspace/coverage/default/23.kmac_burst_write.1469821263
Short name T913
Test name
Test status
Simulation time 180596116194 ps
CPU time 1457.6 seconds
Started Aug 10 06:39:55 PM PDT 24
Finished Aug 10 07:04:13 PM PDT 24
Peak memory 264060 kb
Host smart-45bc27fd-9388-47d2-b65f-4f976035f4fa
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469821263 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.146982126
3 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_burst_write/latest

Test location /workspace/coverage/default/23.kmac_entropy_refresh.2674589891
Short name T636
Test name
Test status
Simulation time 28249101857 ps
CPU time 316.94 seconds
Started Aug 10 06:40:22 PM PDT 24
Finished Aug 10 06:45:39 PM PDT 24
Peak memory 324624 kb
Host smart-d101ebbe-0397-4fa2-9d55-e69d761faa2b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674589891 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.2
674589891 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/23.kmac_error.1140755505
Short name T1052
Test name
Test status
Simulation time 49301898924 ps
CPU time 412.84 seconds
Started Aug 10 06:40:22 PM PDT 24
Finished Aug 10 06:47:15 PM PDT 24
Peak memory 551612 kb
Host smart-9be8ade8-4aed-4223-a02e-44ce954aba98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140755505 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.1140755505 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_error/latest

Test location /workspace/coverage/default/23.kmac_key_error.2150913420
Short name T991
Test name
Test status
Simulation time 17007056091 ps
CPU time 13.79 seconds
Started Aug 10 06:40:27 PM PDT 24
Finished Aug 10 06:40:41 PM PDT 24
Peak memory 226684 kb
Host smart-b9d84c9a-e1f0-4df9-9c6c-0431fc305e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150913420 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.2150913420 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_key_error/latest

Test location /workspace/coverage/default/23.kmac_lc_escalation.1714462766
Short name T120
Test name
Test status
Simulation time 189602961 ps
CPU time 1.54 seconds
Started Aug 10 06:40:27 PM PDT 24
Finished Aug 10 06:40:29 PM PDT 24
Peak memory 226908 kb
Host smart-e5547dbd-5c6d-4091-a15b-eee5cea2dfd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714462766 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.1714462766 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/23.kmac_lc_escalation/latest

Test location /workspace/coverage/default/23.kmac_long_msg_and_output.2587621632
Short name T651
Test name
Test status
Simulation time 2467294663 ps
CPU time 24.75 seconds
Started Aug 10 06:39:51 PM PDT 24
Finished Aug 10 06:40:16 PM PDT 24
Peak memory 259776 kb
Host smart-d154ff23-d3e1-43c1-b00d-aae2024f8707
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587621632 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_a
nd_output.2587621632 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/23.kmac_sideload.4240534066
Short name T746
Test name
Test status
Simulation time 4432596730 ps
CPU time 346.29 seconds
Started Aug 10 06:39:55 PM PDT 24
Finished Aug 10 06:45:42 PM PDT 24
Peak memory 332416 kb
Host smart-0c1c718e-f020-4d3a-92fb-00c52a3aad49
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240534066 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.4240534066 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_sideload/latest

Test location /workspace/coverage/default/23.kmac_smoke.3609578756
Short name T624
Test name
Test status
Simulation time 6005032140 ps
CPU time 33.64 seconds
Started Aug 10 06:39:49 PM PDT 24
Finished Aug 10 06:40:22 PM PDT 24
Peak memory 223836 kb
Host smart-7ffa21d0-d3d7-4564-ae78-b9868e118268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609578756 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.3609578756 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_smoke/latest

Test location /workspace/coverage/default/23.kmac_stress_all.2489529509
Short name T737
Test name
Test status
Simulation time 17962300645 ps
CPU time 665.07 seconds
Started Aug 10 06:40:27 PM PDT 24
Finished Aug 10 06:51:33 PM PDT 24
Peak memory 834232 kb
Host smart-20ffa06e-e2a3-4e12-a0d3-cd5a37adaa57
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2489529509 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.2489529509 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_stress_all/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_kmac.3515533155
Short name T408
Test name
Test status
Simulation time 145054612 ps
CPU time 5.58 seconds
Started Aug 10 06:40:22 PM PDT 24
Finished Aug 10 06:40:27 PM PDT 24
Peak memory 219716 kb
Host smart-70d316b8-9339-4282-97f0-b8a62fcfabeb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515533155 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.kmac_test_vectors_kmac.3515533155 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_kmac_xof.3568836813
Short name T792
Test name
Test status
Simulation time 498005219 ps
CPU time 5.92 seconds
Started Aug 10 06:40:20 PM PDT 24
Finished Aug 10 06:40:25 PM PDT 24
Peak memory 219044 kb
Host smart-259cfc6f-6c8b-485e-bbd9-806646113a45
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568836813 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.kmac_test_vectors_kmac_xof.3568836813 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_224.1876074568
Short name T224
Test name
Test status
Simulation time 131965172700 ps
CPU time 3126.23 seconds
Started Aug 10 06:39:54 PM PDT 24
Finished Aug 10 07:32:01 PM PDT 24
Peak memory 3194032 kb
Host smart-19986d05-69cd-45ad-867b-2998214ecda8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1876074568 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_224.1876074568 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_256.2988559820
Short name T403
Test name
Test status
Simulation time 512853017250 ps
CPU time 3049.75 seconds
Started Aug 10 06:39:54 PM PDT 24
Finished Aug 10 07:30:45 PM PDT 24
Peak memory 3032068 kb
Host smart-aa46d19e-14c8-48f3-a957-bcffaef9c79d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2988559820 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_256.2988559820 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_384.1371449515
Short name T260
Test name
Test status
Simulation time 286382949317 ps
CPU time 2689.65 seconds
Started Aug 10 06:40:03 PM PDT 24
Finished Aug 10 07:24:53 PM PDT 24
Peak memory 2412692 kb
Host smart-caa7cc63-3766-4f16-81a5-b89d5453cf0b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1371449515 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_384.1371449515 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_512.2689481358
Short name T817
Test name
Test status
Simulation time 248400553168 ps
CPU time 1790.73 seconds
Started Aug 10 06:40:06 PM PDT 24
Finished Aug 10 07:09:57 PM PDT 24
Peak memory 1734512 kb
Host smart-45198bde-82da-497c-ab67-a84aab15d268
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2689481358 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_512.2689481358 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_shake_256.1736119456
Short name T416
Test name
Test status
Simulation time 872945668241 ps
CPU time 9776.59 seconds
Started Aug 10 06:40:13 PM PDT 24
Finished Aug 10 09:23:11 PM PDT 24
Peak memory 6406748 kb
Host smart-757449fb-1890-4bdb-86cd-1a9d6752996b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1736119456 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_256.1736119456 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/24.kmac_alert_test.2648758410
Short name T926
Test name
Test status
Simulation time 56290762 ps
CPU time 0.82 seconds
Started Aug 10 06:40:57 PM PDT 24
Finished Aug 10 06:40:58 PM PDT 24
Peak memory 218624 kb
Host smart-e550f3f5-aba5-48cd-8f01-c11c850bc563
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648758410 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.2648758410 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_alert_test/latest

Test location /workspace/coverage/default/24.kmac_app.3042090986
Short name T243
Test name
Test status
Simulation time 78324111426 ps
CPU time 278.63 seconds
Started Aug 10 06:40:38 PM PDT 24
Finished Aug 10 06:45:17 PM PDT 24
Peak memory 429688 kb
Host smart-09d4a592-64b7-4e6c-b191-3f07138c9cee
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042090986 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.3042090986 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/24.kmac_app/latest

Test location /workspace/coverage/default/24.kmac_burst_write.843928534
Short name T631
Test name
Test status
Simulation time 15747157628 ps
CPU time 120.5 seconds
Started Aug 10 06:40:32 PM PDT 24
Finished Aug 10 06:42:32 PM PDT 24
Peak memory 243392 kb
Host smart-da9290bb-0381-41e0-bc02-ecd984f02fe8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843928534 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.843928534
+enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_burst_write/latest

Test location /workspace/coverage/default/24.kmac_entropy_refresh.984944729
Short name T456
Test name
Test status
Simulation time 15533621448 ps
CPU time 362.54 seconds
Started Aug 10 06:40:44 PM PDT 24
Finished Aug 10 06:46:47 PM PDT 24
Peak memory 342520 kb
Host smart-918d0d30-2ab3-4bf8-90ec-0e1db2a3ac13
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984944729 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.98
4944729 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/24.kmac_error.2067564978
Short name T577
Test name
Test status
Simulation time 30872581363 ps
CPU time 526.68 seconds
Started Aug 10 06:40:51 PM PDT 24
Finished Aug 10 06:49:38 PM PDT 24
Peak memory 626420 kb
Host smart-673a5fa9-b2a3-4645-97ac-511d70d5a7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067564978 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.2067564978 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_error/latest

Test location /workspace/coverage/default/24.kmac_key_error.3958223810
Short name T982
Test name
Test status
Simulation time 2150489961 ps
CPU time 7.5 seconds
Started Aug 10 06:40:50 PM PDT 24
Finished Aug 10 06:40:58 PM PDT 24
Peak memory 226616 kb
Host smart-76d09782-d6b1-49ff-88c5-06a98b980eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958223810 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.3958223810 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_key_error/latest

Test location /workspace/coverage/default/24.kmac_lc_escalation.1146515698
Short name T748
Test name
Test status
Simulation time 194827436 ps
CPU time 1.8 seconds
Started Aug 10 06:40:56 PM PDT 24
Finished Aug 10 06:40:58 PM PDT 24
Peak memory 226864 kb
Host smart-805c462b-90e0-451d-aee5-925ee53b27cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146515698 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.1146515698 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/24.kmac_lc_escalation/latest

Test location /workspace/coverage/default/24.kmac_long_msg_and_output.2074437728
Short name T697
Test name
Test status
Simulation time 11973666495 ps
CPU time 1284.45 seconds
Started Aug 10 06:40:27 PM PDT 24
Finished Aug 10 07:01:52 PM PDT 24
Peak memory 931772 kb
Host smart-88f91144-4c28-4c7e-bb7a-10ef28a1ec24
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074437728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_a
nd_output.2074437728 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/24.kmac_sideload.1122457562
Short name T207
Test name
Test status
Simulation time 39885294274 ps
CPU time 383.73 seconds
Started Aug 10 06:40:28 PM PDT 24
Finished Aug 10 06:46:52 PM PDT 24
Peak memory 503556 kb
Host smart-0704c879-4cb2-4204-a8f7-1189c6c208e9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122457562 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.1122457562 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_sideload/latest

Test location /workspace/coverage/default/24.kmac_smoke.3119195034
Short name T211
Test name
Test status
Simulation time 5238044842 ps
CPU time 95.34 seconds
Started Aug 10 06:40:27 PM PDT 24
Finished Aug 10 06:42:03 PM PDT 24
Peak memory 229564 kb
Host smart-7a061649-68da-48e1-b26b-6c0fb0dad70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119195034 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.3119195034 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_smoke/latest

Test location /workspace/coverage/default/24.kmac_stress_all.739407729
Short name T398
Test name
Test status
Simulation time 48442086696 ps
CPU time 1633.26 seconds
Started Aug 10 06:40:55 PM PDT 24
Finished Aug 10 07:08:09 PM PDT 24
Peak memory 1272236 kb
Host smart-97230c23-9b64-4865-bf22-4c0096cc2c07
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=739407729 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.739407729 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_stress_all/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_kmac.3990927189
Short name T707
Test name
Test status
Simulation time 1568402488 ps
CPU time 6.4 seconds
Started Aug 10 06:40:39 PM PDT 24
Finished Aug 10 06:40:46 PM PDT 24
Peak memory 218988 kb
Host smart-4ed13b98-c323-4c77-91b7-f01e6d8ce02c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990927189 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.kmac_test_vectors_kmac.3990927189 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_kmac_xof.874918530
Short name T326
Test name
Test status
Simulation time 158668628 ps
CPU time 5.84 seconds
Started Aug 10 06:40:38 PM PDT 24
Finished Aug 10 06:40:44 PM PDT 24
Peak memory 219844 kb
Host smart-e6c98144-2240-465b-bab4-bc537f241164
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874918530 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.kmac_test_vectors_kmac_xof.874918530 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_224.2703921765
Short name T530
Test name
Test status
Simulation time 282165026375 ps
CPU time 3561.5 seconds
Started Aug 10 06:40:31 PM PDT 24
Finished Aug 10 07:39:54 PM PDT 24
Peak memory 3307132 kb
Host smart-341a5539-80b2-4af1-88db-ac0049085011
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2703921765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_224.2703921765 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_256.3208030796
Short name T212
Test name
Test status
Simulation time 91598753434 ps
CPU time 3286.06 seconds
Started Aug 10 06:40:32 PM PDT 24
Finished Aug 10 07:35:19 PM PDT 24
Peak memory 3059824 kb
Host smart-3bb93dd2-7c7f-42db-9a09-8012eea7602d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3208030796 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_256.3208030796 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_384.375353481
Short name T345
Test name
Test status
Simulation time 48391644265 ps
CPU time 2090.5 seconds
Started Aug 10 06:40:32 PM PDT 24
Finished Aug 10 07:15:23 PM PDT 24
Peak memory 2334236 kb
Host smart-bb9e2712-4d45-46a3-b622-8b58976fe9bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=375353481 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_384.375353481 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_512.2370672210
Short name T305
Test name
Test status
Simulation time 45932988196 ps
CPU time 1103.12 seconds
Started Aug 10 06:40:32 PM PDT 24
Finished Aug 10 06:58:55 PM PDT 24
Peak memory 682628 kb
Host smart-3bb30abf-5263-4e8d-97a0-bf8611d97fc9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2370672210 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_512.2370672210 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_shake_128.3519465746
Short name T312
Test name
Test status
Simulation time 362499180218 ps
CPU time 10675.5 seconds
Started Aug 10 06:40:31 PM PDT 24
Finished Aug 10 09:38:28 PM PDT 24
Peak memory 7755800 kb
Host smart-0c6f4357-77b6-4573-99f0-e0ef63284e9d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3519465746 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_128.3519465746 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_shake_256.1217562413
Short name T720
Test name
Test status
Simulation time 201547909429 ps
CPU time 9598.61 seconds
Started Aug 10 06:40:39 PM PDT 24
Finished Aug 10 09:20:39 PM PDT 24
Peak memory 6397500 kb
Host smart-3b11e670-fb4d-4937-99c6-a491931fd4f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1217562413 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_256.1217562413 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/25.kmac_alert_test.662968126
Short name T115
Test name
Test status
Simulation time 60442205 ps
CPU time 0.81 seconds
Started Aug 10 06:41:20 PM PDT 24
Finished Aug 10 06:41:21 PM PDT 24
Peak memory 218536 kb
Host smart-e9583ec6-fcdc-4dc1-9e02-64d97cedaabd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662968126 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.662968126 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/25.kmac_alert_test/latest

Test location /workspace/coverage/default/25.kmac_app.3774383149
Short name T286
Test name
Test status
Simulation time 32882631264 ps
CPU time 79.96 seconds
Started Aug 10 06:41:15 PM PDT 24
Finished Aug 10 06:42:35 PM PDT 24
Peak memory 277724 kb
Host smart-20abcc2a-05f5-4fcb-a686-3cddae463bdc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774383149 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.3774383149 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/25.kmac_app/latest

Test location /workspace/coverage/default/25.kmac_burst_write.1414854768
Short name T155
Test name
Test status
Simulation time 145495559147 ps
CPU time 1673.59 seconds
Started Aug 10 06:41:03 PM PDT 24
Finished Aug 10 07:08:56 PM PDT 24
Peak memory 268412 kb
Host smart-a5805d9d-5e6b-47f2-9d93-d6ca02b3cafd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414854768 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.141485476
8 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_burst_write/latest

Test location /workspace/coverage/default/25.kmac_entropy_refresh.3185861652
Short name T19
Test name
Test status
Simulation time 71690731341 ps
CPU time 382.77 seconds
Started Aug 10 06:41:17 PM PDT 24
Finished Aug 10 06:47:40 PM PDT 24
Peak memory 480664 kb
Host smart-d52fae81-27b8-4d95-9527-ffebacd52ce0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185861652 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.3
185861652 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/25.kmac_key_error.2082940694
Short name T760
Test name
Test status
Simulation time 4248345072 ps
CPU time 10.71 seconds
Started Aug 10 06:41:17 PM PDT 24
Finished Aug 10 06:41:28 PM PDT 24
Peak memory 226744 kb
Host smart-999f7f51-5d66-40ed-a4e2-a1b5d726fbe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082940694 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.2082940694 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_key_error/latest

Test location /workspace/coverage/default/25.kmac_lc_escalation.877617460
Short name T933
Test name
Test status
Simulation time 40863847 ps
CPU time 1.33 seconds
Started Aug 10 06:41:17 PM PDT 24
Finished Aug 10 06:41:19 PM PDT 24
Peak memory 226884 kb
Host smart-392e3637-6415-4cfa-bec0-ee872340d8bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877617460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.877617460 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/25.kmac_lc_escalation/latest

Test location /workspace/coverage/default/25.kmac_long_msg_and_output.1128936148
Short name T1017
Test name
Test status
Simulation time 255040133524 ps
CPU time 1935.36 seconds
Started Aug 10 06:40:55 PM PDT 24
Finished Aug 10 07:13:11 PM PDT 24
Peak memory 1944760 kb
Host smart-633e7be7-2543-48ee-a6eb-eccf3a68f2ef
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128936148 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_a
nd_output.1128936148 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/25.kmac_sideload.307302427
Short name T961
Test name
Test status
Simulation time 27757515407 ps
CPU time 325.16 seconds
Started Aug 10 06:41:02 PM PDT 24
Finished Aug 10 06:46:27 PM PDT 24
Peak memory 339796 kb
Host smart-a02cea82-0fa7-4fae-967b-85b2a68ea05a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307302427 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.307302427 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_sideload/latest

Test location /workspace/coverage/default/25.kmac_smoke.3012912188
Short name T761
Test name
Test status
Simulation time 10108892767 ps
CPU time 39.44 seconds
Started Aug 10 06:40:56 PM PDT 24
Finished Aug 10 06:41:36 PM PDT 24
Peak memory 223156 kb
Host smart-7edec1a9-7df7-4832-911b-9db2169bef73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012912188 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.3012912188 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_smoke/latest

Test location /workspace/coverage/default/25.kmac_stress_all.3423994103
Short name T794
Test name
Test status
Simulation time 6500484237 ps
CPU time 714.73 seconds
Started Aug 10 06:41:24 PM PDT 24
Finished Aug 10 06:53:19 PM PDT 24
Peak memory 601552 kb
Host smart-a7b47082-8286-4306-af81-d2d1c797b539
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3423994103 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.3423994103 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_stress_all/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_kmac.2947966668
Short name T769
Test name
Test status
Simulation time 1782573896 ps
CPU time 6.32 seconds
Started Aug 10 06:41:08 PM PDT 24
Finished Aug 10 06:41:14 PM PDT 24
Peak memory 219812 kb
Host smart-b36d790a-c955-4fbc-8a15-8052abf4240a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947966668 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.kmac_test_vectors_kmac.2947966668 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_kmac_xof.3533644007
Short name T298
Test name
Test status
Simulation time 627361007 ps
CPU time 6.05 seconds
Started Aug 10 06:41:14 PM PDT 24
Finished Aug 10 06:41:20 PM PDT 24
Peak memory 218828 kb
Host smart-899fa67d-7090-476a-a011-810e723789bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533644007 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.kmac_test_vectors_kmac_xof.3533644007 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_224.1482830404
Short name T658
Test name
Test status
Simulation time 408123462588 ps
CPU time 3235.82 seconds
Started Aug 10 06:41:03 PM PDT 24
Finished Aug 10 07:34:59 PM PDT 24
Peak memory 3219748 kb
Host smart-bd4e90df-3478-43a9-9b10-9014f8239ce8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1482830404 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_224.1482830404 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_256.2311663485
Short name T1012
Test name
Test status
Simulation time 198815993649 ps
CPU time 2185.07 seconds
Started Aug 10 06:41:02 PM PDT 24
Finished Aug 10 07:17:27 PM PDT 24
Peak memory 1153076 kb
Host smart-8b7b2bcb-54b7-4fb5-b38e-b6f33a9f9fb9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2311663485 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_256.2311663485 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_384.460855469
Short name T521
Test name
Test status
Simulation time 15985899000 ps
CPU time 1597.47 seconds
Started Aug 10 06:41:03 PM PDT 24
Finished Aug 10 07:07:41 PM PDT 24
Peak memory 942588 kb
Host smart-a866cdd4-c884-4df7-b84d-36f5159a643b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=460855469 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_384.460855469 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_512.276449234
Short name T682
Test name
Test status
Simulation time 10784516463 ps
CPU time 1165.68 seconds
Started Aug 10 06:41:09 PM PDT 24
Finished Aug 10 07:00:35 PM PDT 24
Peak memory 705656 kb
Host smart-fc8e52c6-072e-424e-93b7-7f45f5612f68
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=276449234 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_512.276449234 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_shake_128.990229492
Short name T709
Test name
Test status
Simulation time 254607296059 ps
CPU time 6900.31 seconds
Started Aug 10 06:41:09 PM PDT 24
Finished Aug 10 08:36:10 PM PDT 24
Peak memory 2720884 kb
Host smart-c1ce48b3-7e39-45d5-ba1e-3ba41423e81e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=990229492 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_128.990229492 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_shake_256.3885008806
Short name T855
Test name
Test status
Simulation time 179463175884 ps
CPU time 9623.61 seconds
Started Aug 10 06:41:10 PM PDT 24
Finished Aug 10 09:21:35 PM PDT 24
Peak memory 6494808 kb
Host smart-a71dbdce-bf90-4739-a2d4-e2c655646579
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3885008806 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_256.3885008806 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/26.kmac_alert_test.1172463070
Short name T974
Test name
Test status
Simulation time 22226503 ps
CPU time 0.83 seconds
Started Aug 10 06:41:57 PM PDT 24
Finished Aug 10 06:41:58 PM PDT 24
Peak memory 218572 kb
Host smart-8db58f63-85a0-40d8-bfe6-8df75a1951fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172463070 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.1172463070 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_alert_test/latest

Test location /workspace/coverage/default/26.kmac_app.1921575139
Short name T255
Test name
Test status
Simulation time 17770349340 ps
CPU time 111.86 seconds
Started Aug 10 06:41:51 PM PDT 24
Finished Aug 10 06:43:43 PM PDT 24
Peak memory 301412 kb
Host smart-03f28b21-416a-477d-9620-acdd85aae766
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921575139 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.1921575139 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/26.kmac_app/latest

Test location /workspace/coverage/default/26.kmac_burst_write.4219528627
Short name T856
Test name
Test status
Simulation time 72674713701 ps
CPU time 537.57 seconds
Started Aug 10 06:41:27 PM PDT 24
Finished Aug 10 06:50:25 PM PDT 24
Peak memory 240876 kb
Host smart-47dfbbdb-f4df-4e49-b178-4b0d02d585cc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219528627 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.421952862
7 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_burst_write/latest

Test location /workspace/coverage/default/26.kmac_entropy_refresh.3185955649
Short name T491
Test name
Test status
Simulation time 10896528955 ps
CPU time 307.49 seconds
Started Aug 10 06:41:49 PM PDT 24
Finished Aug 10 06:46:57 PM PDT 24
Peak memory 327692 kb
Host smart-3c9830b0-0b4b-45fd-b5ce-e91c23b02621
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185955649 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.3
185955649 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/26.kmac_error.188933016
Short name T659
Test name
Test status
Simulation time 2720425939 ps
CPU time 209.3 seconds
Started Aug 10 06:41:57 PM PDT 24
Finished Aug 10 06:45:26 PM PDT 24
Peak memory 297808 kb
Host smart-0c5f597c-d8a2-4480-bbc3-36cc26cd522b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188933016 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.188933016 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_error/latest

Test location /workspace/coverage/default/26.kmac_key_error.3809602450
Short name T1044
Test name
Test status
Simulation time 108417898 ps
CPU time 1.45 seconds
Started Aug 10 06:41:56 PM PDT 24
Finished Aug 10 06:41:58 PM PDT 24
Peak memory 226292 kb
Host smart-a76f7dfd-b735-4ef0-82fe-3766e9f746c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809602450 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.3809602450 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_key_error/latest

Test location /workspace/coverage/default/26.kmac_lc_escalation.742489719
Short name T52
Test name
Test status
Simulation time 100867656 ps
CPU time 1.41 seconds
Started Aug 10 06:41:55 PM PDT 24
Finished Aug 10 06:41:56 PM PDT 24
Peak memory 226936 kb
Host smart-e3798aa4-9948-48b8-9a85-e670eecfd8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742489719 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.742489719 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/26.kmac_lc_escalation/latest

Test location /workspace/coverage/default/26.kmac_long_msg_and_output.148204694
Short name T40
Test name
Test status
Simulation time 12925316706 ps
CPU time 959.97 seconds
Started Aug 10 06:41:20 PM PDT 24
Finished Aug 10 06:57:21 PM PDT 24
Peak memory 717808 kb
Host smart-fc535a66-16ae-4a73-aac9-a2f4cd08f7f0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148204694 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_an
d_output.148204694 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/26.kmac_sideload.2327967482
Short name T400
Test name
Test status
Simulation time 7895095024 ps
CPU time 154.52 seconds
Started Aug 10 06:41:20 PM PDT 24
Finished Aug 10 06:43:55 PM PDT 24
Peak memory 281224 kb
Host smart-772d210b-bb10-43fa-9897-f35fb0db4a34
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327967482 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.2327967482 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_sideload/latest

Test location /workspace/coverage/default/26.kmac_smoke.496466622
Short name T449
Test name
Test status
Simulation time 115309949 ps
CPU time 3.3 seconds
Started Aug 10 06:41:20 PM PDT 24
Finished Aug 10 06:41:23 PM PDT 24
Peak memory 226864 kb
Host smart-bb5cc4ea-7410-42d0-92e7-7d17bf062d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496466622 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.496466622 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_smoke/latest

Test location /workspace/coverage/default/26.kmac_stress_all.585893978
Short name T472
Test name
Test status
Simulation time 12951531264 ps
CPU time 595.53 seconds
Started Aug 10 06:41:57 PM PDT 24
Finished Aug 10 06:51:53 PM PDT 24
Peak memory 540056 kb
Host smart-254b9627-17e7-4abf-9862-5f5c04bb6940
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=585893978 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.585893978 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_stress_all/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_kmac.1415471238
Short name T916
Test name
Test status
Simulation time 104845401 ps
CPU time 5.32 seconds
Started Aug 10 06:41:51 PM PDT 24
Finished Aug 10 06:41:57 PM PDT 24
Peak memory 218964 kb
Host smart-5ac68762-e7fb-49e7-9477-f7d3fe215fe2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415471238 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.kmac_test_vectors_kmac.1415471238 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_kmac_xof.3254756209
Short name T423
Test name
Test status
Simulation time 118074792 ps
CPU time 5.36 seconds
Started Aug 10 06:41:50 PM PDT 24
Finished Aug 10 06:41:56 PM PDT 24
Peak memory 219784 kb
Host smart-1a4bf812-9bd1-40ab-bfa0-18b001c24a8a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254756209 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.kmac_test_vectors_kmac_xof.3254756209 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_224.3132292049
Short name T303
Test name
Test status
Simulation time 469716343557 ps
CPU time 3423.44 seconds
Started Aug 10 06:41:34 PM PDT 24
Finished Aug 10 07:38:38 PM PDT 24
Peak memory 3243492 kb
Host smart-30758619-c675-4424-a4ec-5ab0eb5265bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3132292049 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_224.3132292049 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_256.165808136
Short name T1051
Test name
Test status
Simulation time 104618916289 ps
CPU time 2087.17 seconds
Started Aug 10 06:41:32 PM PDT 24
Finished Aug 10 07:16:20 PM PDT 24
Peak memory 1173620 kb
Host smart-9415a469-e081-479d-b351-4ad22bc2c823
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=165808136 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_256.165808136 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_384.3726383203
Short name T199
Test name
Test status
Simulation time 190398353789 ps
CPU time 2143.58 seconds
Started Aug 10 06:41:32 PM PDT 24
Finished Aug 10 07:17:16 PM PDT 24
Peak memory 2384244 kb
Host smart-ee470b8c-5114-4fdd-91a7-581abcb3f46b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3726383203 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_384.3726383203 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_512.2442752455
Short name T1021
Test name
Test status
Simulation time 38958095382 ps
CPU time 1527.03 seconds
Started Aug 10 06:41:38 PM PDT 24
Finished Aug 10 07:07:05 PM PDT 24
Peak memory 1713900 kb
Host smart-dd8770c4-49f9-482a-8454-d0813e345331
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2442752455 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_512.2442752455 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_shake_128.516927553
Short name T393
Test name
Test status
Simulation time 67298827255 ps
CPU time 6325.4 seconds
Started Aug 10 06:41:45 PM PDT 24
Finished Aug 10 08:27:12 PM PDT 24
Peak memory 2728988 kb
Host smart-31f55f67-9b36-4f0f-a9eb-a2467c68c109
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=516927553 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_128.516927553 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_shake_256.1881150660
Short name T666
Test name
Test status
Simulation time 320385207282 ps
CPU time 8943.05 seconds
Started Aug 10 06:41:44 PM PDT 24
Finished Aug 10 09:10:49 PM PDT 24
Peak memory 6403680 kb
Host smart-c907e891-d9c8-4e0f-8816-1863604dbbed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1881150660 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_256.1881150660 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/27.kmac_alert_test.868601607
Short name T908
Test name
Test status
Simulation time 76746534 ps
CPU time 0.83 seconds
Started Aug 10 06:43:03 PM PDT 24
Finished Aug 10 06:43:04 PM PDT 24
Peak memory 218560 kb
Host smart-46bd412a-7b02-4bf0-8d1d-4ad3b5e20af6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868601607 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.868601607 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/27.kmac_alert_test/latest

Test location /workspace/coverage/default/27.kmac_app.1178223279
Short name T185
Test name
Test status
Simulation time 96195211245 ps
CPU time 359.63 seconds
Started Aug 10 06:42:33 PM PDT 24
Finished Aug 10 06:48:33 PM PDT 24
Peak memory 479672 kb
Host smart-47384982-ecb7-42bd-9160-99209be6f6d0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178223279 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.1178223279 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/27.kmac_app/latest

Test location /workspace/coverage/default/27.kmac_burst_write.2619663055
Short name T164
Test name
Test status
Simulation time 152979754425 ps
CPU time 1813.29 seconds
Started Aug 10 06:42:05 PM PDT 24
Finished Aug 10 07:12:18 PM PDT 24
Peak memory 269344 kb
Host smart-1ece79a5-65ba-4f5a-828e-db5057aaaf41
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619663055 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.261966305
5 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_burst_write/latest

Test location /workspace/coverage/default/27.kmac_entropy_refresh.1745498491
Short name T458
Test name
Test status
Simulation time 3799975095 ps
CPU time 138.54 seconds
Started Aug 10 06:42:33 PM PDT 24
Finished Aug 10 06:44:52 PM PDT 24
Peak memory 263912 kb
Host smart-971f1792-11c3-41ce-9284-93314544897a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745498491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.1
745498491 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/27.kmac_error.303528174
Short name T849
Test name
Test status
Simulation time 54320653058 ps
CPU time 477.17 seconds
Started Aug 10 06:42:33 PM PDT 24
Finished Aug 10 06:50:31 PM PDT 24
Peak memory 590640 kb
Host smart-5cf32388-6e2e-4bd8-9e23-95622c0f70e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303528174 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.303528174 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_error/latest

Test location /workspace/coverage/default/27.kmac_key_error.763252769
Short name T379
Test name
Test status
Simulation time 2448922201 ps
CPU time 13.35 seconds
Started Aug 10 06:42:40 PM PDT 24
Finished Aug 10 06:42:53 PM PDT 24
Peak memory 226816 kb
Host smart-4428b728-933b-424c-8285-bf1549e6f906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763252769 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.763252769 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_key_error/latest

Test location /workspace/coverage/default/27.kmac_lc_escalation.3830645771
Short name T48
Test name
Test status
Simulation time 47163043 ps
CPU time 1.49 seconds
Started Aug 10 06:42:58 PM PDT 24
Finished Aug 10 06:42:59 PM PDT 24
Peak memory 226780 kb
Host smart-3c7f4cb9-14d5-48a8-ab9a-6e8eee857271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830645771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.3830645771 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/27.kmac_lc_escalation/latest

Test location /workspace/coverage/default/27.kmac_long_msg_and_output.2488423383
Short name T650
Test name
Test status
Simulation time 36576682671 ps
CPU time 2320.96 seconds
Started Aug 10 06:42:03 PM PDT 24
Finished Aug 10 07:20:44 PM PDT 24
Peak memory 1312188 kb
Host smart-ec6d2fac-cf6d-45e2-a44b-e37f4b90cb36
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488423383 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_a
nd_output.2488423383 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/27.kmac_sideload.1323465762
Short name T342
Test name
Test status
Simulation time 5659014934 ps
CPU time 32.07 seconds
Started Aug 10 06:42:05 PM PDT 24
Finished Aug 10 06:42:37 PM PDT 24
Peak memory 248880 kb
Host smart-412a2aee-828a-4105-84ef-76ebb4cd695d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323465762 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.1323465762 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_sideload/latest

Test location /workspace/coverage/default/27.kmac_smoke.3816069599
Short name T603
Test name
Test status
Simulation time 555438893 ps
CPU time 3.23 seconds
Started Aug 10 06:41:57 PM PDT 24
Finished Aug 10 06:42:01 PM PDT 24
Peak memory 221484 kb
Host smart-176047e4-b3fc-4354-a2ab-4d5732f222a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816069599 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.3816069599 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_smoke/latest

Test location /workspace/coverage/default/27.kmac_stress_all.2021194439
Short name T662
Test name
Test status
Simulation time 246471141538 ps
CPU time 3627.92 seconds
Started Aug 10 06:42:57 PM PDT 24
Finished Aug 10 07:43:26 PM PDT 24
Peak memory 1450172 kb
Host smart-076c4504-0065-43e6-b908-83ed11a24f7c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2021194439 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all.2021194439 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_stress_all/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_kmac.1110034231
Short name T433
Test name
Test status
Simulation time 511263488 ps
CPU time 5.86 seconds
Started Aug 10 06:42:34 PM PDT 24
Finished Aug 10 06:42:40 PM PDT 24
Peak memory 218820 kb
Host smart-5189e4c2-117e-427e-a4bd-442c1888739b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110034231 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.kmac_test_vectors_kmac.1110034231 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_kmac_xof.3180501258
Short name T883
Test name
Test status
Simulation time 1514144767 ps
CPU time 6.86 seconds
Started Aug 10 06:42:34 PM PDT 24
Finished Aug 10 06:42:41 PM PDT 24
Peak memory 219916 kb
Host smart-e63d6ddb-6c9a-4d9d-8235-ac3429cf2011
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180501258 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.kmac_test_vectors_kmac_xof.3180501258 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_224.954389505
Short name T889
Test name
Test status
Simulation time 352894567327 ps
CPU time 3949.63 seconds
Started Aug 10 06:42:11 PM PDT 24
Finished Aug 10 07:48:01 PM PDT 24
Peak memory 3286552 kb
Host smart-bcf28732-5472-440b-bccd-e452262d4f91
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=954389505 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_224.954389505 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_256.1601502128
Short name T336
Test name
Test status
Simulation time 19705422296 ps
CPU time 2052.47 seconds
Started Aug 10 06:42:08 PM PDT 24
Finished Aug 10 07:16:21 PM PDT 24
Peak memory 1122548 kb
Host smart-404ad80d-5248-46e0-9c39-4bd3f95b6d83
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1601502128 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_256.1601502128 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_384.245343493
Short name T864
Test name
Test status
Simulation time 346088662160 ps
CPU time 2443.11 seconds
Started Aug 10 06:42:08 PM PDT 24
Finished Aug 10 07:22:52 PM PDT 24
Peak memory 2427744 kb
Host smart-607492f5-f423-49dc-ab3b-aa142338d482
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=245343493 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_384.245343493 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_512.2914212442
Short name T654
Test name
Test status
Simulation time 216649030858 ps
CPU time 1887.38 seconds
Started Aug 10 06:42:15 PM PDT 24
Finished Aug 10 07:13:43 PM PDT 24
Peak memory 1748928 kb
Host smart-ab245da9-3a78-41ae-8eff-4453e43a7112
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2914212442 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_512.2914212442 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_shake_128.229433514
Short name T235
Test name
Test status
Simulation time 251188318335 ps
CPU time 5966.43 seconds
Started Aug 10 06:42:30 PM PDT 24
Finished Aug 10 08:21:57 PM PDT 24
Peak memory 2648576 kb
Host smart-8404aff2-4640-4c2b-a73a-34694e3dfeae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=229433514 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_128.229433514 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_shake_256.1373463115
Short name T648
Test name
Test status
Simulation time 67953020142 ps
CPU time 5396.29 seconds
Started Aug 10 06:42:29 PM PDT 24
Finished Aug 10 08:12:26 PM PDT 24
Peak memory 2222508 kb
Host smart-b5f318e1-8a5e-4e39-a680-a0f13d2d9f49
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1373463115 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_256.1373463115 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/28.kmac_alert_test.3208833331
Short name T802
Test name
Test status
Simulation time 15877863 ps
CPU time 0.83 seconds
Started Aug 10 06:43:38 PM PDT 24
Finished Aug 10 06:43:39 PM PDT 24
Peak memory 218608 kb
Host smart-b0dc45a6-8798-49ef-a9eb-226768b870b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208833331 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.3208833331 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_alert_test/latest

Test location /workspace/coverage/default/28.kmac_app.3350470019
Short name T917
Test name
Test status
Simulation time 3383553148 ps
CPU time 221.77 seconds
Started Aug 10 06:43:29 PM PDT 24
Finished Aug 10 06:47:11 PM PDT 24
Peak memory 297016 kb
Host smart-d976d582-1cd0-4bc8-9dd0-953450235ff4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350470019 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.3350470019 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/28.kmac_app/latest

Test location /workspace/coverage/default/28.kmac_burst_write.740006472
Short name T835
Test name
Test status
Simulation time 3757585380 ps
CPU time 369.55 seconds
Started Aug 10 06:43:08 PM PDT 24
Finished Aug 10 06:49:18 PM PDT 24
Peak memory 232096 kb
Host smart-ee4c6653-7949-4fc5-b76d-92ff1a510f85
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740006472 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.740006472
+enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_burst_write/latest

Test location /workspace/coverage/default/28.kmac_entropy_refresh.151988282
Short name T429
Test name
Test status
Simulation time 9448736493 ps
CPU time 181.6 seconds
Started Aug 10 06:43:30 PM PDT 24
Finished Aug 10 06:46:32 PM PDT 24
Peak memory 288676 kb
Host smart-35dc5d86-8888-486c-a99c-7fec96ade2e9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151988282 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_entropy_refresh.15
1988282 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/28.kmac_error.1432488274
Short name T750
Test name
Test status
Simulation time 7506300243 ps
CPU time 108.86 seconds
Started Aug 10 06:43:28 PM PDT 24
Finished Aug 10 06:45:17 PM PDT 24
Peak memory 312004 kb
Host smart-e30d4d1d-1332-4e84-8745-040e5a79bf09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432488274 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.1432488274 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_error/latest

Test location /workspace/coverage/default/28.kmac_lc_escalation.2802675821
Short name T824
Test name
Test status
Simulation time 41588555 ps
CPU time 1.39 seconds
Started Aug 10 06:43:33 PM PDT 24
Finished Aug 10 06:43:34 PM PDT 24
Peak memory 226920 kb
Host smart-7129fc64-9f3e-4c52-8cec-f834ac3dfe85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802675821 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.2802675821 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/28.kmac_lc_escalation/latest

Test location /workspace/coverage/default/28.kmac_long_msg_and_output.3568133685
Short name T921
Test name
Test status
Simulation time 5920893456 ps
CPU time 57.77 seconds
Started Aug 10 06:43:09 PM PDT 24
Finished Aug 10 06:44:07 PM PDT 24
Peak memory 279172 kb
Host smart-3c85bde4-2fb9-4040-8394-a0a520c4bfde
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568133685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_a
nd_output.3568133685 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/28.kmac_sideload.4271523107
Short name T679
Test name
Test status
Simulation time 84363118006 ps
CPU time 395 seconds
Started Aug 10 06:43:11 PM PDT 24
Finished Aug 10 06:49:47 PM PDT 24
Peak memory 549592 kb
Host smart-06ee7753-5a02-4800-beb4-8c600ae22bb7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271523107 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.4271523107 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_sideload/latest

Test location /workspace/coverage/default/28.kmac_smoke.556590215
Short name T556
Test name
Test status
Simulation time 3518981867 ps
CPU time 77.88 seconds
Started Aug 10 06:43:02 PM PDT 24
Finished Aug 10 06:44:20 PM PDT 24
Peak memory 227756 kb
Host smart-8a99bc59-1a92-43bf-8f10-801d1c18c570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556590215 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.556590215 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_smoke/latest

Test location /workspace/coverage/default/28.kmac_stress_all.2059747651
Short name T440
Test name
Test status
Simulation time 66954157433 ps
CPU time 740.78 seconds
Started Aug 10 06:43:38 PM PDT 24
Finished Aug 10 06:55:59 PM PDT 24
Peak memory 439368 kb
Host smart-016e63c3-9ce9-40eb-88ec-3151adb3744b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2059747651 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.2059747651 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_stress_all/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_kmac.3254890811
Short name T725
Test name
Test status
Simulation time 1955609451 ps
CPU time 6.43 seconds
Started Aug 10 06:43:21 PM PDT 24
Finished Aug 10 06:43:28 PM PDT 24
Peak memory 219860 kb
Host smart-49fb4e8b-aa2d-40e3-9743-b0fc4bace0dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254890811 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.kmac_test_vectors_kmac.3254890811 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_kmac_xof.2565213148
Short name T784
Test name
Test status
Simulation time 1018834511 ps
CPU time 6.95 seconds
Started Aug 10 06:43:29 PM PDT 24
Finished Aug 10 06:43:36 PM PDT 24
Peak memory 219900 kb
Host smart-9558273f-684f-443c-a7b3-a1cad4315538
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565213148 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.kmac_test_vectors_kmac_xof.2565213148 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_224.4032640895
Short name T721
Test name
Test status
Simulation time 272470648716 ps
CPU time 3104.61 seconds
Started Aug 10 06:43:12 PM PDT 24
Finished Aug 10 07:34:57 PM PDT 24
Peak memory 3232212 kb
Host smart-d1a71d2e-164a-4d9d-9e37-373192eed641
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4032640895 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_224.4032640895 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_256.3913072315
Short name T420
Test name
Test status
Simulation time 119282757169 ps
CPU time 3130.96 seconds
Started Aug 10 06:43:10 PM PDT 24
Finished Aug 10 07:35:21 PM PDT 24
Peak memory 2986268 kb
Host smart-d661fe5f-4d51-459e-9386-3ed4187d29ee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3913072315 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_256.3913072315 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_384.469398171
Short name T410
Test name
Test status
Simulation time 14600326076 ps
CPU time 1701.94 seconds
Started Aug 10 06:43:18 PM PDT 24
Finished Aug 10 07:11:40 PM PDT 24
Peak memory 909728 kb
Host smart-c42863fb-5551-4509-9eb9-7036d5076ac1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=469398171 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_384.469398171 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_512.1196354980
Short name T877
Test name
Test status
Simulation time 324363767091 ps
CPU time 1616.51 seconds
Started Aug 10 06:43:15 PM PDT 24
Finished Aug 10 07:10:12 PM PDT 24
Peak memory 1708444 kb
Host smart-edd6c73a-20e0-4b40-bb38-ff7985e92deb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1196354980 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_512.1196354980 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_shake_256.384195592
Short name T823
Test name
Test status
Simulation time 77311885596 ps
CPU time 5316.75 seconds
Started Aug 10 06:43:20 PM PDT 24
Finished Aug 10 08:11:58 PM PDT 24
Peak memory 2214732 kb
Host smart-5b07e03e-6e10-4165-af01-b4377b549c4a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=384195592 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_256.384195592 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/29.kmac_alert_test.1920532292
Short name T532
Test name
Test status
Simulation time 29825342 ps
CPU time 0.94 seconds
Started Aug 10 06:44:33 PM PDT 24
Finished Aug 10 06:44:34 PM PDT 24
Peak memory 218616 kb
Host smart-cabd4233-94cf-42e1-8f13-bf1a94696fa8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920532292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.1920532292 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_alert_test/latest

Test location /workspace/coverage/default/29.kmac_app.1130342301
Short name T964
Test name
Test status
Simulation time 52352167375 ps
CPU time 138.47 seconds
Started Aug 10 06:44:12 PM PDT 24
Finished Aug 10 06:46:30 PM PDT 24
Peak memory 320028 kb
Host smart-9f7dfbf4-40c4-41f9-a681-90c3f2bc6f50
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130342301 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.1130342301 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/29.kmac_app/latest

Test location /workspace/coverage/default/29.kmac_burst_write.4000474494
Short name T896
Test name
Test status
Simulation time 14219167819 ps
CPU time 186.86 seconds
Started Aug 10 06:44:07 PM PDT 24
Finished Aug 10 06:47:14 PM PDT 24
Peak memory 239496 kb
Host smart-500ced55-6c70-4f81-aaae-aeac904a03ae
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000474494 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.400047449
4 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_burst_write/latest

Test location /workspace/coverage/default/29.kmac_entropy_refresh.1701650653
Short name T59
Test name
Test status
Simulation time 11110553370 ps
CPU time 135.03 seconds
Started Aug 10 06:44:19 PM PDT 24
Finished Aug 10 06:46:34 PM PDT 24
Peak memory 264540 kb
Host smart-be973c61-c161-4a6f-8600-d0e39b31a2d8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701650653 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.1
701650653 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/29.kmac_error.2545938063
Short name T1053
Test name
Test status
Simulation time 22019637747 ps
CPU time 438.46 seconds
Started Aug 10 06:44:19 PM PDT 24
Finished Aug 10 06:51:37 PM PDT 24
Peak memory 513800 kb
Host smart-64a22d97-605c-41ff-8351-9505cfc8783c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545938063 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.2545938063 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_error/latest

Test location /workspace/coverage/default/29.kmac_key_error.2740299605
Short name T455
Test name
Test status
Simulation time 441195858 ps
CPU time 1.47 seconds
Started Aug 10 06:44:18 PM PDT 24
Finished Aug 10 06:44:19 PM PDT 24
Peak memory 225336 kb
Host smart-318349a4-4dfe-49ef-8329-a26c11aaeb9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740299605 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.2740299605 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_key_error/latest

Test location /workspace/coverage/default/29.kmac_long_msg_and_output.3083449728
Short name T492
Test name
Test status
Simulation time 84347390649 ps
CPU time 2953.95 seconds
Started Aug 10 06:43:51 PM PDT 24
Finished Aug 10 07:33:05 PM PDT 24
Peak memory 1506904 kb
Host smart-a9e66a25-f0fb-4b0b-b88d-cabb083002cf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083449728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_a
nd_output.3083449728 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/29.kmac_sideload.960806657
Short name T362
Test name
Test status
Simulation time 10360733243 ps
CPU time 412.95 seconds
Started Aug 10 06:44:07 PM PDT 24
Finished Aug 10 06:51:01 PM PDT 24
Peak memory 506152 kb
Host smart-0f84204a-ec83-4e0a-9fa7-26274109dc0f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960806657 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.960806657 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_sideload/latest

Test location /workspace/coverage/default/29.kmac_smoke.1259869525
Short name T355
Test name
Test status
Simulation time 7769463268 ps
CPU time 81.47 seconds
Started Aug 10 06:43:44 PM PDT 24
Finished Aug 10 06:45:06 PM PDT 24
Peak memory 222276 kb
Host smart-a7e0efa7-3114-490d-9d77-74a2787e8711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259869525 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.1259869525 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_smoke/latest

Test location /workspace/coverage/default/29.kmac_stress_all.3878788291
Short name T706
Test name
Test status
Simulation time 13528997090 ps
CPU time 1006.42 seconds
Started Aug 10 06:44:24 PM PDT 24
Finished Aug 10 07:01:11 PM PDT 24
Peak memory 561844 kb
Host smart-32bcd153-56a8-4839-a07c-3e10d6f80d84
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3878788291 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.3878788291 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_stress_all/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_kmac.1935769241
Short name T381
Test name
Test status
Simulation time 270529921 ps
CPU time 5.93 seconds
Started Aug 10 06:44:13 PM PDT 24
Finished Aug 10 06:44:19 PM PDT 24
Peak memory 219708 kb
Host smart-042505be-e829-4467-b903-8bf231ecb05b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935769241 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.kmac_test_vectors_kmac.1935769241 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_kmac_xof.1225240975
Short name T519
Test name
Test status
Simulation time 443465710 ps
CPU time 4.74 seconds
Started Aug 10 06:44:12 PM PDT 24
Finished Aug 10 06:44:17 PM PDT 24
Peak memory 218904 kb
Host smart-813d5125-fc11-483a-8090-9178d38d848f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225240975 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.kmac_test_vectors_kmac_xof.1225240975 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_224.3646082642
Short name T198
Test name
Test status
Simulation time 382191959597 ps
CPU time 3836.44 seconds
Started Aug 10 06:44:06 PM PDT 24
Finished Aug 10 07:48:03 PM PDT 24
Peak memory 3176196 kb
Host smart-f1cb52d8-b8ef-4b68-b2a1-45194d87dd00
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3646082642 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_224.3646082642 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_256.96639064
Short name T770
Test name
Test status
Simulation time 49650110670 ps
CPU time 2182.61 seconds
Started Aug 10 06:44:06 PM PDT 24
Finished Aug 10 07:20:29 PM PDT 24
Peak memory 1108028 kb
Host smart-7ed1dc20-d906-4b22-a686-d16857da5c2f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=96639064 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_256.96639064 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_384.1430506500
Short name T871
Test name
Test status
Simulation time 48654627103 ps
CPU time 1560.51 seconds
Started Aug 10 06:44:05 PM PDT 24
Finished Aug 10 07:10:06 PM PDT 24
Peak memory 916276 kb
Host smart-580a9975-721d-4a8f-883a-c50f66ec4b65
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1430506500 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_384.1430506500 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_512.2005489201
Short name T206
Test name
Test status
Simulation time 51162855957 ps
CPU time 1784.13 seconds
Started Aug 10 06:44:11 PM PDT 24
Finished Aug 10 07:13:56 PM PDT 24
Peak memory 1726956 kb
Host smart-bae461b0-c1d5-40f7-bd1b-a23fab74a185
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2005489201 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_512.2005489201 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_shake_128.1280004934
Short name T225
Test name
Test status
Simulation time 120868609983 ps
CPU time 6363.52 seconds
Started Aug 10 06:44:13 PM PDT 24
Finished Aug 10 08:30:17 PM PDT 24
Peak memory 2710316 kb
Host smart-48fef0e4-0125-41b5-a442-d9f53305afbc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1280004934 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_128.1280004934 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_shake_256.3092292364
Short name T579
Test name
Test status
Simulation time 110571600061 ps
CPU time 5492.6 seconds
Started Aug 10 06:44:14 PM PDT 24
Finished Aug 10 08:15:47 PM PDT 24
Peak memory 2225356 kb
Host smart-2c4e2f99-939e-4d4a-9f6a-adf215094b66
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3092292364 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_256.3092292364 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/3.kmac_alert_test.3740784439
Short name T597
Test name
Test status
Simulation time 114302794 ps
CPU time 0.84 seconds
Started Aug 10 06:30:08 PM PDT 24
Finished Aug 10 06:30:09 PM PDT 24
Peak memory 218620 kb
Host smart-be005e13-6b54-4bfc-b2a3-530afe7b3812
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740784439 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.3740784439 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_alert_test/latest

Test location /workspace/coverage/default/3.kmac_app.452790555
Short name T692
Test name
Test status
Simulation time 4494545771 ps
CPU time 238.94 seconds
Started Aug 10 06:29:57 PM PDT 24
Finished Aug 10 06:33:56 PM PDT 24
Peak memory 297056 kb
Host smart-2af76ec6-99fd-4f0f-92fb-b3e3131a25a8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452790555 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.452790555 +enable_masking=1
+sw_key_masked=0
Directory /workspace/3.kmac_app/latest

Test location /workspace/coverage/default/3.kmac_app_with_partial_data.3384030734
Short name T595
Test name
Test status
Simulation time 2535009843 ps
CPU time 97.6 seconds
Started Aug 10 06:29:55 PM PDT 24
Finished Aug 10 06:31:33 PM PDT 24
Peak memory 257836 kb
Host smart-3bcae233-2ec9-4ca8-ba10-2f01d90aca44
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384030734 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_par
tial_data.3384030734 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/3.kmac_burst_write.3247296498
Short name T622
Test name
Test status
Simulation time 24674332073 ps
CPU time 1024.2 seconds
Started Aug 10 06:29:44 PM PDT 24
Finished Aug 10 06:46:48 PM PDT 24
Peak memory 254684 kb
Host smart-b7e79329-f79e-4499-a9ad-7917d513dcc5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247296498 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.3247296498
+enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_burst_write/latest

Test location /workspace/coverage/default/3.kmac_edn_timeout_error.232336909
Short name T497
Test name
Test status
Simulation time 183191935 ps
CPU time 1.08 seconds
Started Aug 10 06:29:56 PM PDT 24
Finished Aug 10 06:29:57 PM PDT 24
Peak memory 218480 kb
Host smart-73fb828f-1f97-4476-8ef6-5322bf20ff73
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=232336909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.232336909 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_mode_error.1952994233
Short name T942
Test name
Test status
Simulation time 53669672 ps
CPU time 1.05 seconds
Started Aug 10 06:29:55 PM PDT 24
Finished Aug 10 06:29:56 PM PDT 24
Peak memory 218488 kb
Host smart-65fc1043-e14d-40ef-af71-b9887d2490df
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1952994233 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.1952994233 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_ready_error.2706045744
Short name T302
Test name
Test status
Simulation time 3845390975 ps
CPU time 45.86 seconds
Started Aug 10 06:29:57 PM PDT 24
Finished Aug 10 06:30:43 PM PDT 24
Peak memory 226984 kb
Host smart-00698c46-25e4-4bdb-84b9-42a2bce5a02a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706045744 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.2706045744 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_refresh.3174165598
Short name T801
Test name
Test status
Simulation time 1582793498 ps
CPU time 25.5 seconds
Started Aug 10 06:29:56 PM PDT 24
Finished Aug 10 06:30:21 PM PDT 24
Peak memory 228024 kb
Host smart-deb19804-95c9-4372-9d68-ac8d8d5f1ceb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174165598 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.31
74165598 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/3.kmac_error.2792545201
Short name T1054
Test name
Test status
Simulation time 7766059115 ps
CPU time 174.23 seconds
Started Aug 10 06:29:55 PM PDT 24
Finished Aug 10 06:32:49 PM PDT 24
Peak memory 289556 kb
Host smart-fce3eeba-5aa9-47af-a72d-3a897f7d644f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792545201 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.2792545201 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_error/latest

Test location /workspace/coverage/default/3.kmac_key_error.2346809290
Short name T580
Test name
Test status
Simulation time 134915655 ps
CPU time 1.68 seconds
Started Aug 10 06:29:55 PM PDT 24
Finished Aug 10 06:29:57 PM PDT 24
Peak memory 226692 kb
Host smart-7d66854f-cf33-4323-92c5-649827584c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346809290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.2346809290 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_key_error/latest

Test location /workspace/coverage/default/3.kmac_lc_escalation.711947578
Short name T480
Test name
Test status
Simulation time 31125435 ps
CPU time 1.52 seconds
Started Aug 10 06:29:58 PM PDT 24
Finished Aug 10 06:29:59 PM PDT 24
Peak memory 226836 kb
Host smart-659c8e26-9315-4a7c-a5f0-3549bf86e348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711947578 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.711947578 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_lc_escalation/latest

Test location /workspace/coverage/default/3.kmac_long_msg_and_output.1799723996
Short name T93
Test name
Test status
Simulation time 3225193919 ps
CPU time 47.6 seconds
Started Aug 10 06:29:43 PM PDT 24
Finished Aug 10 06:30:31 PM PDT 24
Peak memory 275048 kb
Host smart-6985ccd7-9af0-4665-b00e-d03db6980436
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799723996 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_an
d_output.1799723996 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/3.kmac_mubi.2707045136
Short name T582
Test name
Test status
Simulation time 4720023424 ps
CPU time 111.51 seconds
Started Aug 10 06:29:58 PM PDT 24
Finished Aug 10 06:31:49 PM PDT 24
Peak memory 261164 kb
Host smart-bfd4ecac-b8d5-4de5-917f-093036913af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707045136 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.2707045136 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_mubi/latest

Test location /workspace/coverage/default/3.kmac_sideload.129002360
Short name T369
Test name
Test status
Simulation time 7980293664 ps
CPU time 123.5 seconds
Started Aug 10 06:29:43 PM PDT 24
Finished Aug 10 06:31:46 PM PDT 24
Peak memory 315552 kb
Host smart-c6239d3d-f3a5-41e1-b734-fc9dfda812fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129002360 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.129002360 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_sideload/latest

Test location /workspace/coverage/default/3.kmac_smoke.1570478684
Short name T520
Test name
Test status
Simulation time 3997311800 ps
CPU time 81.41 seconds
Started Aug 10 06:29:43 PM PDT 24
Finished Aug 10 06:31:05 PM PDT 24
Peak memory 227020 kb
Host smart-13e31077-1957-4a29-8113-0806e12fff18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570478684 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.1570478684 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_smoke/latest

Test location /workspace/coverage/default/3.kmac_stress_all.1202263345
Short name T327
Test name
Test status
Simulation time 1446697639 ps
CPU time 56.59 seconds
Started Aug 10 06:30:08 PM PDT 24
Finished Aug 10 06:31:05 PM PDT 24
Peak memory 260048 kb
Host smart-f734f241-4893-4a45-a0f4-bc2f9a31a9f3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1202263345 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.1202263345 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_stress_all/latest

Test location /workspace/coverage/default/3.kmac_stress_all_with_rand_reset.3927505905
Short name T68
Test name
Test status
Simulation time 40621290590 ps
CPU time 916.58 seconds
Started Aug 10 06:30:08 PM PDT 24
Finished Aug 10 06:45:25 PM PDT 24
Peak memory 423196 kb
Host smart-0f4540dc-686e-41e9-8d75-6cdff491e0a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3927505905 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all_with_rand_reset.3927505905 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_kmac.4249374601
Short name T240
Test name
Test status
Simulation time 561956149 ps
CPU time 5.67 seconds
Started Aug 10 06:29:55 PM PDT 24
Finished Aug 10 06:30:01 PM PDT 24
Peak memory 219820 kb
Host smart-c14dbc9b-30b6-4761-b64d-4d9c591ebcfe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249374601 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.kmac_test_vectors_kmac.4249374601 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_kmac_xof.2358304328
Short name T306
Test name
Test status
Simulation time 425223221 ps
CPU time 6.4 seconds
Started Aug 10 06:29:57 PM PDT 24
Finished Aug 10 06:30:03 PM PDT 24
Peak memory 218996 kb
Host smart-516f1ed0-d7dd-47f4-8b17-2e41a69e09da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358304328 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.kmac_test_vectors_kmac_xof.2358304328 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_224.3763950389
Short name T202
Test name
Test status
Simulation time 168669580333 ps
CPU time 3744.64 seconds
Started Aug 10 06:29:45 PM PDT 24
Finished Aug 10 07:32:10 PM PDT 24
Peak memory 3285408 kb
Host smart-d07b0e99-9b37-4926-93c6-6e3633822d96
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3763950389 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.3763950389 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_256.1775287316
Short name T337
Test name
Test status
Simulation time 128167004947 ps
CPU time 3121.55 seconds
Started Aug 10 06:29:43 PM PDT 24
Finished Aug 10 07:21:45 PM PDT 24
Peak memory 3045072 kb
Host smart-ffb194e5-0541-43e3-ba11-f6ca749a4666
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1775287316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.1775287316 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_384.658794621
Short name T1016
Test name
Test status
Simulation time 68617467961 ps
CPU time 1660.93 seconds
Started Aug 10 06:29:44 PM PDT 24
Finished Aug 10 06:57:25 PM PDT 24
Peak memory 937496 kb
Host smart-7887dc64-b07b-4841-847b-f10c00e25997
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=658794621 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.658794621 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_512.308265513
Short name T328
Test name
Test status
Simulation time 103914865209 ps
CPU time 1684.15 seconds
Started Aug 10 06:29:44 PM PDT 24
Finished Aug 10 06:57:49 PM PDT 24
Peak memory 1713160 kb
Host smart-a3b5a5c5-ac28-4b36-b20f-0958408cbb86
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=308265513 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.308265513 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/30.kmac_alert_test.3034155706
Short name T592
Test name
Test status
Simulation time 13654524 ps
CPU time 0.81 seconds
Started Aug 10 06:45:16 PM PDT 24
Finished Aug 10 06:45:17 PM PDT 24
Peak memory 218520 kb
Host smart-b1fddf36-6448-4e24-97b8-00142c1c7340
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034155706 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.3034155706 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_alert_test/latest

Test location /workspace/coverage/default/30.kmac_app.3829530801
Short name T734
Test name
Test status
Simulation time 53898644589 ps
CPU time 257.17 seconds
Started Aug 10 06:44:52 PM PDT 24
Finished Aug 10 06:49:10 PM PDT 24
Peak memory 390652 kb
Host smart-d480453d-e728-47e6-856f-18d30c850f24
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829530801 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.3829530801 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/30.kmac_app/latest

Test location /workspace/coverage/default/30.kmac_burst_write.956339936
Short name T741
Test name
Test status
Simulation time 2728074509 ps
CPU time 19.68 seconds
Started Aug 10 06:44:38 PM PDT 24
Finished Aug 10 06:44:57 PM PDT 24
Peak memory 227048 kb
Host smart-3b11ac6d-7894-4661-9c5a-9f31e71d4253
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956339936 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.956339936
+enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_burst_write/latest

Test location /workspace/coverage/default/30.kmac_entropy_refresh.2700177702
Short name T63
Test name
Test status
Simulation time 4873697208 ps
CPU time 98.14 seconds
Started Aug 10 06:44:58 PM PDT 24
Finished Aug 10 06:46:36 PM PDT 24
Peak memory 280052 kb
Host smart-5a1bc3a5-8da7-4683-b8e2-48a01cff10be
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700177702 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_entropy_refresh.2
700177702 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/30.kmac_error.3296360030
Short name T177
Test name
Test status
Simulation time 8948202307 ps
CPU time 288.78 seconds
Started Aug 10 06:44:57 PM PDT 24
Finished Aug 10 06:49:46 PM PDT 24
Peak memory 316196 kb
Host smart-bc305282-4169-4187-b466-d2903d82d718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296360030 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.3296360030 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_error/latest

Test location /workspace/coverage/default/30.kmac_key_error.1066266109
Short name T574
Test name
Test status
Simulation time 706734213 ps
CPU time 5.37 seconds
Started Aug 10 06:44:59 PM PDT 24
Finished Aug 10 06:45:04 PM PDT 24
Peak memory 226748 kb
Host smart-28ee5064-fa9f-474b-b458-0fd62c67b76e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066266109 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.1066266109 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_key_error/latest

Test location /workspace/coverage/default/30.kmac_lc_escalation.81957620
Short name T681
Test name
Test status
Simulation time 60456314 ps
CPU time 1.24 seconds
Started Aug 10 06:45:06 PM PDT 24
Finished Aug 10 06:45:07 PM PDT 24
Peak memory 226912 kb
Host smart-ad6d1e11-db5a-4cc6-bbdb-416a9947d8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81957620 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.81957620 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_lc_escalation/latest

Test location /workspace/coverage/default/30.kmac_long_msg_and_output.3115812978
Short name T701
Test name
Test status
Simulation time 21844773831 ps
CPU time 318.36 seconds
Started Aug 10 06:44:34 PM PDT 24
Finished Aug 10 06:49:52 PM PDT 24
Peak memory 619760 kb
Host smart-13db0743-2eb1-40f0-acb2-3f3e36f5657b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115812978 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_a
nd_output.3115812978 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/30.kmac_sideload.1577975568
Short name T700
Test name
Test status
Simulation time 4302993801 ps
CPU time 137.73 seconds
Started Aug 10 06:44:32 PM PDT 24
Finished Aug 10 06:46:50 PM PDT 24
Peak memory 325456 kb
Host smart-2e4907ee-94b9-485d-bd28-ade2820af925
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577975568 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.1577975568 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_sideload/latest

Test location /workspace/coverage/default/30.kmac_smoke.3970708340
Short name T226
Test name
Test status
Simulation time 12281156961 ps
CPU time 71.79 seconds
Started Aug 10 06:44:34 PM PDT 24
Finished Aug 10 06:45:46 PM PDT 24
Peak memory 223040 kb
Host smart-8f24bde2-20f3-4d82-bfea-967b5115589f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970708340 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.3970708340 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_smoke/latest

Test location /workspace/coverage/default/30.kmac_stress_all.3542556069
Short name T816
Test name
Test status
Simulation time 370409889200 ps
CPU time 2733.13 seconds
Started Aug 10 06:45:16 PM PDT 24
Finished Aug 10 07:30:49 PM PDT 24
Peak memory 1096636 kb
Host smart-f63e4456-a2ef-486c-9a2d-f4324c66e933
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3542556069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.3542556069 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_stress_all/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_kmac.1370069287
Short name T361
Test name
Test status
Simulation time 216185866 ps
CPU time 5.42 seconds
Started Aug 10 06:44:52 PM PDT 24
Finished Aug 10 06:44:58 PM PDT 24
Peak memory 218872 kb
Host smart-b1e02597-0330-42e4-9f1f-8964561f2d4f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370069287 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.kmac_test_vectors_kmac.1370069287 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_kmac_xof.1256129499
Short name T335
Test name
Test status
Simulation time 217713622 ps
CPU time 6.03 seconds
Started Aug 10 06:44:52 PM PDT 24
Finished Aug 10 06:44:58 PM PDT 24
Peak memory 219820 kb
Host smart-19bddb32-b91b-4599-afd6-d202801032fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256129499 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.kmac_test_vectors_kmac_xof.1256129499 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_224.2669601804
Short name T229
Test name
Test status
Simulation time 83569472201 ps
CPU time 2215.82 seconds
Started Aug 10 06:44:38 PM PDT 24
Finished Aug 10 07:21:34 PM PDT 24
Peak memory 1174192 kb
Host smart-d070c0dc-b8b3-434e-9813-dd11c3d15269
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2669601804 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_224.2669601804 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_256.935194278
Short name T543
Test name
Test status
Simulation time 319945853734 ps
CPU time 3190.48 seconds
Started Aug 10 06:44:37 PM PDT 24
Finished Aug 10 07:37:48 PM PDT 24
Peak memory 3035504 kb
Host smart-242a4b32-d62c-4b7e-83e3-7aaf5abc29e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=935194278 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_256.935194278 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_384.3568661265
Short name T655
Test name
Test status
Simulation time 297707440264 ps
CPU time 2855.86 seconds
Started Aug 10 06:44:38 PM PDT 24
Finished Aug 10 07:32:14 PM PDT 24
Peak memory 2433292 kb
Host smart-56d64e18-8130-4d56-bc29-72828ac79fd6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3568661265 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_384.3568661265 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_512.2266265218
Short name T594
Test name
Test status
Simulation time 133378529368 ps
CPU time 1585.08 seconds
Started Aug 10 06:44:39 PM PDT 24
Finished Aug 10 07:11:05 PM PDT 24
Peak memory 1738460 kb
Host smart-563a58db-e318-42ff-ae25-439b3e31236d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2266265218 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_512.2266265218 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_shake_128.1851558947
Short name T409
Test name
Test status
Simulation time 61371638179 ps
CPU time 6697.22 seconds
Started Aug 10 06:44:46 PM PDT 24
Finished Aug 10 08:36:25 PM PDT 24
Peak memory 2648736 kb
Host smart-129b0772-9ea8-480e-8d1a-bbb069a056f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1851558947 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_128.1851558947 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_shake_256.933214664
Short name T674
Test name
Test status
Simulation time 905195027042 ps
CPU time 5430.93 seconds
Started Aug 10 06:44:45 PM PDT 24
Finished Aug 10 08:15:17 PM PDT 24
Peak memory 2231260 kb
Host smart-7343e98b-5a51-4d10-ae95-db95350e0603
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=933214664 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_256.933214664 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/31.kmac_alert_test.762958544
Short name T767
Test name
Test status
Simulation time 22737371 ps
CPU time 0.8 seconds
Started Aug 10 06:45:44 PM PDT 24
Finished Aug 10 06:45:45 PM PDT 24
Peak memory 218560 kb
Host smart-249e90e5-65b4-42ef-a118-75101de60efc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762958544 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.762958544 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/31.kmac_alert_test/latest

Test location /workspace/coverage/default/31.kmac_app.3706644356
Short name T500
Test name
Test status
Simulation time 5185967597 ps
CPU time 120.08 seconds
Started Aug 10 06:45:42 PM PDT 24
Finished Aug 10 06:47:42 PM PDT 24
Peak memory 301160 kb
Host smart-c287efb4-8557-4395-860e-b4ea5c6ccb5f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706644356 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.3706644356 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/31.kmac_app/latest

Test location /workspace/coverage/default/31.kmac_burst_write.725727900
Short name T430
Test name
Test status
Simulation time 4086853038 ps
CPU time 421.9 seconds
Started Aug 10 06:45:26 PM PDT 24
Finished Aug 10 06:52:28 PM PDT 24
Peak memory 233348 kb
Host smart-b854df45-3390-4422-834b-a09fd1f273cb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725727900 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_write.725727900
+enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_burst_write/latest

Test location /workspace/coverage/default/31.kmac_entropy_refresh.3965761842
Short name T754
Test name
Test status
Simulation time 3839198207 ps
CPU time 82.39 seconds
Started Aug 10 06:45:43 PM PDT 24
Finished Aug 10 06:47:06 PM PDT 24
Peak memory 253576 kb
Host smart-7e618636-c574-427c-ba2c-47220f48c360
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965761842 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.3
965761842 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/31.kmac_error.1514018071
Short name T503
Test name
Test status
Simulation time 35473033076 ps
CPU time 228.59 seconds
Started Aug 10 06:45:43 PM PDT 24
Finished Aug 10 06:49:31 PM PDT 24
Peak memory 399128 kb
Host smart-17d97a4e-aaa8-49f5-8004-c72d29716e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514018071 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.1514018071 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_error/latest

Test location /workspace/coverage/default/31.kmac_key_error.1667780828
Short name T630
Test name
Test status
Simulation time 5886901288 ps
CPU time 11.6 seconds
Started Aug 10 06:45:43 PM PDT 24
Finished Aug 10 06:45:55 PM PDT 24
Peak memory 226844 kb
Host smart-50862d4e-5a71-454a-baf2-de6d8df155ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667780828 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.1667780828 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_key_error/latest

Test location /workspace/coverage/default/31.kmac_lc_escalation.1546574156
Short name T544
Test name
Test status
Simulation time 1947813638 ps
CPU time 12.82 seconds
Started Aug 10 06:45:43 PM PDT 24
Finished Aug 10 06:45:56 PM PDT 24
Peak memory 243500 kb
Host smart-4da57aef-f3bc-445a-bd86-4145833a854c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546574156 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.1546574156 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/31.kmac_lc_escalation/latest

Test location /workspace/coverage/default/31.kmac_long_msg_and_output.708973900
Short name T980
Test name
Test status
Simulation time 61321893141 ps
CPU time 766.67 seconds
Started Aug 10 06:45:16 PM PDT 24
Finished Aug 10 06:58:03 PM PDT 24
Peak memory 999100 kb
Host smart-a4b288de-eed3-438e-85a8-13ed5cc130c6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708973900 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_an
d_output.708973900 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/31.kmac_sideload.1376735269
Short name T536
Test name
Test status
Simulation time 33452146843 ps
CPU time 181.18 seconds
Started Aug 10 06:45:15 PM PDT 24
Finished Aug 10 06:48:16 PM PDT 24
Peak memory 378844 kb
Host smart-6d2ccdd3-e47b-435f-87a1-eaba49bf4007
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376735269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.1376735269 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_sideload/latest

Test location /workspace/coverage/default/31.kmac_stress_all.715702675
Short name T1030
Test name
Test status
Simulation time 8607542864 ps
CPU time 278.52 seconds
Started Aug 10 06:45:44 PM PDT 24
Finished Aug 10 06:50:22 PM PDT 24
Peak memory 303360 kb
Host smart-e5715cf0-82fe-4931-ae28-ff9ec9900e4b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=715702675 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.715702675 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_stress_all/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_kmac.1219593578
Short name T867
Test name
Test status
Simulation time 232224300 ps
CPU time 6.25 seconds
Started Aug 10 06:45:34 PM PDT 24
Finished Aug 10 06:45:41 PM PDT 24
Peak memory 220156 kb
Host smart-5720e623-8eca-40de-87c4-971ed1f018e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219593578 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.kmac_test_vectors_kmac.1219593578 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_kmac_xof.2749247863
Short name T314
Test name
Test status
Simulation time 201097357 ps
CPU time 6.04 seconds
Started Aug 10 06:45:43 PM PDT 24
Finished Aug 10 06:45:49 PM PDT 24
Peak memory 220004 kb
Host smart-783bc783-5e70-4d12-8490-80940b77e4c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749247863 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.kmac_test_vectors_kmac_xof.2749247863 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_224.3616122550
Short name T586
Test name
Test status
Simulation time 266435667962 ps
CPU time 3036.22 seconds
Started Aug 10 06:45:25 PM PDT 24
Finished Aug 10 07:36:02 PM PDT 24
Peak memory 3147932 kb
Host smart-79d159a1-5441-41b5-913b-1519edb48461
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3616122550 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_224.3616122550 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_256.2134551766
Short name T399
Test name
Test status
Simulation time 83155980166 ps
CPU time 3200.99 seconds
Started Aug 10 06:45:24 PM PDT 24
Finished Aug 10 07:38:45 PM PDT 24
Peak memory 3063180 kb
Host smart-df384cef-b112-4636-b110-a7b37bbd94d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2134551766 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_256.2134551766 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_384.1615106820
Short name T907
Test name
Test status
Simulation time 190121503472 ps
CPU time 2400.6 seconds
Started Aug 10 06:45:24 PM PDT 24
Finished Aug 10 07:25:25 PM PDT 24
Peak memory 2393680 kb
Host smart-e8e57697-d80a-40e8-9a9e-ce924eb50365
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1615106820 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_384.1615106820 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_512.4180487780
Short name T997
Test name
Test status
Simulation time 147499115257 ps
CPU time 1387.28 seconds
Started Aug 10 06:45:34 PM PDT 24
Finished Aug 10 07:08:42 PM PDT 24
Peak memory 696628 kb
Host smart-d40511da-cee1-41c0-97a7-3917fcc0cf29
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4180487780 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_512.4180487780 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_shake_256.2746916387
Short name T200
Test name
Test status
Simulation time 225315839287 ps
CPU time 10172.9 seconds
Started Aug 10 06:45:34 PM PDT 24
Finished Aug 10 09:35:09 PM PDT 24
Peak memory 6357276 kb
Host smart-b8e306ca-0971-4bde-bc4d-6ad24adb1f7f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2746916387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_256.2746916387 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/32.kmac_alert_test.4132206454
Short name T717
Test name
Test status
Simulation time 59659265 ps
CPU time 0.78 seconds
Started Aug 10 06:46:28 PM PDT 24
Finished Aug 10 06:46:29 PM PDT 24
Peak memory 218608 kb
Host smart-7194d4bf-17c8-49cc-bdcc-848f53c334b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132206454 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.4132206454 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_alert_test/latest

Test location /workspace/coverage/default/32.kmac_app.1235766889
Short name T870
Test name
Test status
Simulation time 145100003132 ps
CPU time 320.8 seconds
Started Aug 10 06:46:10 PM PDT 24
Finished Aug 10 06:51:30 PM PDT 24
Peak memory 420912 kb
Host smart-67de7f80-ed7d-47d8-85e4-0b05914da1b1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235766889 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.1235766889 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/32.kmac_app/latest

Test location /workspace/coverage/default/32.kmac_burst_write.3494763288
Short name T527
Test name
Test status
Simulation time 54713827946 ps
CPU time 1184.9 seconds
Started Aug 10 06:45:55 PM PDT 24
Finished Aug 10 07:05:40 PM PDT 24
Peak memory 244004 kb
Host smart-f1b62443-216f-4364-9c4d-fe845505ff4e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494763288 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.349476328
8 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_burst_write/latest

Test location /workspace/coverage/default/32.kmac_entropy_refresh.2667815258
Short name T17
Test name
Test status
Simulation time 211937990846 ps
CPU time 433.29 seconds
Started Aug 10 06:46:11 PM PDT 24
Finished Aug 10 06:53:24 PM PDT 24
Peak memory 514108 kb
Host smart-80722e9b-a6ee-43cd-ad12-e14815442980
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667815258 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.2
667815258 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/32.kmac_error.3688412333
Short name T517
Test name
Test status
Simulation time 15807671458 ps
CPU time 337.72 seconds
Started Aug 10 06:46:12 PM PDT 24
Finished Aug 10 06:51:50 PM PDT 24
Peak memory 341852 kb
Host smart-39b42ecb-6a14-4ef3-828c-cc2496f81ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688412333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.3688412333 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_error/latest

Test location /workspace/coverage/default/32.kmac_key_error.2318728174
Short name T442
Test name
Test status
Simulation time 7956937281 ps
CPU time 12.07 seconds
Started Aug 10 06:46:17 PM PDT 24
Finished Aug 10 06:46:29 PM PDT 24
Peak memory 226796 kb
Host smart-7e154b27-6a45-49a0-a150-6430f9a46fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318728174 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.2318728174 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_key_error/latest

Test location /workspace/coverage/default/32.kmac_lc_escalation.1810347858
Short name T702
Test name
Test status
Simulation time 88450413 ps
CPU time 1.42 seconds
Started Aug 10 06:46:18 PM PDT 24
Finished Aug 10 06:46:20 PM PDT 24
Peak memory 226920 kb
Host smart-611c390b-3d24-4957-b99a-464832c97c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810347858 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.1810347858 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/32.kmac_lc_escalation/latest

Test location /workspace/coverage/default/32.kmac_long_msg_and_output.140689940
Short name T475
Test name
Test status
Simulation time 136215466601 ps
CPU time 2789.92 seconds
Started Aug 10 06:45:55 PM PDT 24
Finished Aug 10 07:32:25 PM PDT 24
Peak memory 2588496 kb
Host smart-31b03847-afe6-4a54-9c52-072448cb5baf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140689940 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_long_msg_an
d_output.140689940 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/32.kmac_sideload.4016472369
Short name T975
Test name
Test status
Simulation time 668352435 ps
CPU time 16.95 seconds
Started Aug 10 06:45:55 PM PDT 24
Finished Aug 10 06:46:12 PM PDT 24
Peak memory 238428 kb
Host smart-c9cd3aad-f6be-4d00-ae4e-051294e38404
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016472369 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.4016472369 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_sideload/latest

Test location /workspace/coverage/default/32.kmac_smoke.3438940776
Short name T690
Test name
Test status
Simulation time 13910878869 ps
CPU time 70.52 seconds
Started Aug 10 06:45:43 PM PDT 24
Finished Aug 10 06:46:53 PM PDT 24
Peak memory 228740 kb
Host smart-c1a6ec3d-7bed-43cf-a690-ffb476e80530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438940776 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.3438940776 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_smoke/latest

Test location /workspace/coverage/default/32.kmac_stress_all.3282013640
Short name T830
Test name
Test status
Simulation time 184659581484 ps
CPU time 1470.38 seconds
Started Aug 10 06:46:19 PM PDT 24
Finished Aug 10 07:10:49 PM PDT 24
Peak memory 998244 kb
Host smart-62ae2f47-52b1-4003-b55a-76806e488f2d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3282013640 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.3282013640 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_stress_all/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_kmac.1718930626
Short name T421
Test name
Test status
Simulation time 1186654596 ps
CPU time 6.57 seconds
Started Aug 10 06:46:11 PM PDT 24
Finished Aug 10 06:46:17 PM PDT 24
Peak memory 219832 kb
Host smart-65d0edee-920e-4019-a16a-3b6aeae856c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718930626 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.kmac_test_vectors_kmac.1718930626 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_kmac_xof.2436197046
Short name T677
Test name
Test status
Simulation time 169753634 ps
CPU time 5.17 seconds
Started Aug 10 06:46:09 PM PDT 24
Finished Aug 10 06:46:15 PM PDT 24
Peak memory 219912 kb
Host smart-ef51c0d6-af8d-4ae0-ada6-b577ca7ed86a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436197046 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.kmac_test_vectors_kmac_xof.2436197046 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_224.3350705326
Short name T708
Test name
Test status
Simulation time 69188601502 ps
CPU time 3356.68 seconds
Started Aug 10 06:45:51 PM PDT 24
Finished Aug 10 07:41:48 PM PDT 24
Peak memory 3281876 kb
Host smart-a6a17190-b005-40d7-baf1-61229d9c5112
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3350705326 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_224.3350705326 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_256.2713642602
Short name T691
Test name
Test status
Simulation time 85471797788 ps
CPU time 3315.01 seconds
Started Aug 10 06:46:01 PM PDT 24
Finished Aug 10 07:41:17 PM PDT 24
Peak memory 3117604 kb
Host smart-f5de0706-a923-4d0f-9c46-94d4ddab5749
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2713642602 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_256.2713642602 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_384.1300877296
Short name T502
Test name
Test status
Simulation time 29707800335 ps
CPU time 1770.38 seconds
Started Aug 10 06:46:02 PM PDT 24
Finished Aug 10 07:15:33 PM PDT 24
Peak memory 924700 kb
Host smart-31fa8c27-ce1b-41f6-bbee-e7b2d428da01
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1300877296 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_384.1300877296 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_512.3621298375
Short name T549
Test name
Test status
Simulation time 42037567148 ps
CPU time 1219.96 seconds
Started Aug 10 06:46:02 PM PDT 24
Finished Aug 10 07:06:22 PM PDT 24
Peak memory 683060 kb
Host smart-e97e3e75-268e-4363-9e4d-99f5c74e0701
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3621298375 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_512.3621298375 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_shake_128.4116582180
Short name T607
Test name
Test status
Simulation time 145342406235 ps
CPU time 6576.36 seconds
Started Aug 10 06:46:02 PM PDT 24
Finished Aug 10 08:35:39 PM PDT 24
Peak memory 2666052 kb
Host smart-0414d9b3-bf28-4686-af2f-8e0577ff6ad4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4116582180 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_128.4116582180 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_shake_256.3859445448
Short name T678
Test name
Test status
Simulation time 443080625400 ps
CPU time 10139.1 seconds
Started Aug 10 06:46:00 PM PDT 24
Finished Aug 10 09:35:00 PM PDT 24
Peak memory 6313396 kb
Host smart-42a0667f-c075-4ad0-9984-2cd5d218f109
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3859445448 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_256.3859445448 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/33.kmac_alert_test.3560642078
Short name T390
Test name
Test status
Simulation time 35160324 ps
CPU time 0.8 seconds
Started Aug 10 06:47:16 PM PDT 24
Finished Aug 10 06:47:17 PM PDT 24
Peak memory 218588 kb
Host smart-e53f4dbc-24b6-4440-91c7-c058e7185645
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560642078 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.3560642078 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_alert_test/latest

Test location /workspace/coverage/default/33.kmac_app.790695325
Short name T1001
Test name
Test status
Simulation time 2586319559 ps
CPU time 165.04 seconds
Started Aug 10 06:46:56 PM PDT 24
Finished Aug 10 06:49:41 PM PDT 24
Peak memory 277592 kb
Host smart-157d34b9-f496-4ff6-a8e0-b10563e1ff30
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790695325 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.790695325 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/33.kmac_app/latest

Test location /workspace/coverage/default/33.kmac_burst_write.121234400
Short name T826
Test name
Test status
Simulation time 7171704641 ps
CPU time 205.66 seconds
Started Aug 10 06:46:29 PM PDT 24
Finished Aug 10 06:49:55 PM PDT 24
Peak memory 231780 kb
Host smart-00676ae1-9e21-4a36-874f-e87a13908864
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121234400 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.121234400
+enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_burst_write/latest

Test location /workspace/coverage/default/33.kmac_entropy_refresh.1836929623
Short name T669
Test name
Test status
Simulation time 11003154011 ps
CPU time 150.07 seconds
Started Aug 10 06:47:07 PM PDT 24
Finished Aug 10 06:49:38 PM PDT 24
Peak memory 269780 kb
Host smart-cef8c128-e02e-4228-bbb5-06df8c8947b3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836929623 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.1
836929623 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/33.kmac_error.3208312615
Short name T930
Test name
Test status
Simulation time 2031920334 ps
CPU time 58.28 seconds
Started Aug 10 06:47:08 PM PDT 24
Finished Aug 10 06:48:06 PM PDT 24
Peak memory 284308 kb
Host smart-6029cfcb-551d-45fe-ba90-62eba14c77cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208312615 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.3208312615 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_error/latest

Test location /workspace/coverage/default/33.kmac_key_error.2175013959
Short name T123
Test name
Test status
Simulation time 2909869628 ps
CPU time 5.68 seconds
Started Aug 10 06:47:07 PM PDT 24
Finished Aug 10 06:47:13 PM PDT 24
Peak memory 226860 kb
Host smart-657107c9-0edf-490d-9af5-b9dd14d303a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175013959 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.2175013959 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_key_error/latest

Test location /workspace/coverage/default/33.kmac_long_msg_and_output.3375325077
Short name T127
Test name
Test status
Simulation time 27943121978 ps
CPU time 4004.79 seconds
Started Aug 10 06:46:29 PM PDT 24
Finished Aug 10 07:53:14 PM PDT 24
Peak memory 1915348 kb
Host smart-23721d4f-605e-4aff-9be6-75db0f255b88
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375325077 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_a
nd_output.3375325077 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/33.kmac_sideload.300400639
Short name T242
Test name
Test status
Simulation time 38609653714 ps
CPU time 255.13 seconds
Started Aug 10 06:46:28 PM PDT 24
Finished Aug 10 06:50:44 PM PDT 24
Peak memory 425480 kb
Host smart-6b247514-d9ae-420b-b729-2d7aabc6d66d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300400639 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.300400639 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_sideload/latest

Test location /workspace/coverage/default/33.kmac_smoke.1929778073
Short name T481
Test name
Test status
Simulation time 1812283463 ps
CPU time 43.61 seconds
Started Aug 10 06:46:29 PM PDT 24
Finished Aug 10 06:47:13 PM PDT 24
Peak memory 222520 kb
Host smart-214c5da5-c920-43db-8de1-c3a59138aa26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929778073 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.1929778073 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_smoke/latest

Test location /workspace/coverage/default/33.kmac_stress_all.18228824
Short name T898
Test name
Test status
Simulation time 4416354609 ps
CPU time 471.65 seconds
Started Aug 10 06:47:06 PM PDT 24
Finished Aug 10 06:54:58 PM PDT 24
Peak memory 465860 kb
Host smart-fab9108f-029f-4e62-9042-b8d5bd72e5b0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=18228824 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.18228824 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_stress_all/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_kmac.773457531
Short name T1034
Test name
Test status
Simulation time 1379573685 ps
CPU time 5.71 seconds
Started Aug 10 06:46:55 PM PDT 24
Finished Aug 10 06:47:01 PM PDT 24
Peak memory 219840 kb
Host smart-913c59b7-1044-43a5-a09a-c774386e52e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773457531 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.kmac_test_vectors_kmac.773457531 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_kmac_xof.997928738
Short name T39
Test name
Test status
Simulation time 249181715 ps
CPU time 6.7 seconds
Started Aug 10 06:46:54 PM PDT 24
Finished Aug 10 06:47:01 PM PDT 24
Peak memory 219828 kb
Host smart-ae49ce94-4ba3-43b7-b3e1-bba2ca59aba2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997928738 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.kmac_test_vectors_kmac_xof.997928738 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_224.3143872210
Short name T427
Test name
Test status
Simulation time 170335254557 ps
CPU time 3577.37 seconds
Started Aug 10 06:46:29 PM PDT 24
Finished Aug 10 07:46:07 PM PDT 24
Peak memory 3253316 kb
Host smart-f95a0e50-1476-4a8e-b357-7af127ce98c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3143872210 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_224.3143872210 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_256.189903685
Short name T464
Test name
Test status
Simulation time 81172548635 ps
CPU time 1941.41 seconds
Started Aug 10 06:46:44 PM PDT 24
Finished Aug 10 07:19:06 PM PDT 24
Peak memory 1143116 kb
Host smart-4ecd68f1-cbb7-44f6-aca8-3cb938f9375c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=189903685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_256.189903685 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_384.4240052219
Short name T694
Test name
Test status
Simulation time 32771763909 ps
CPU time 1622.92 seconds
Started Aug 10 06:46:44 PM PDT 24
Finished Aug 10 07:13:47 PM PDT 24
Peak memory 943032 kb
Host smart-66781706-5fe5-4367-9d74-33b40d3530e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4240052219 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_384.4240052219 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_512.1133661765
Short name T444
Test name
Test status
Simulation time 799852137927 ps
CPU time 1728.21 seconds
Started Aug 10 06:46:43 PM PDT 24
Finished Aug 10 07:15:32 PM PDT 24
Peak memory 1696732 kb
Host smart-9b179444-3d1f-43d8-95e8-90618075f737
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1133661765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_512.1133661765 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_shake_128.1705577221
Short name T647
Test name
Test status
Simulation time 127220847828 ps
CPU time 6609.25 seconds
Started Aug 10 06:46:44 PM PDT 24
Finished Aug 10 08:36:54 PM PDT 24
Peak memory 2676492 kb
Host smart-101df77b-842b-4f53-8923-c1b2a9053053
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1705577221 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_128.1705577221 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_shake_256.1602028990
Short name T1002
Test name
Test status
Simulation time 230085883044 ps
CPU time 9141.73 seconds
Started Aug 10 06:46:55 PM PDT 24
Finished Aug 10 09:19:18 PM PDT 24
Peak memory 6356008 kb
Host smart-3616639b-dd62-47a1-a7bb-e13830a1e138
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1602028990 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_256.1602028990 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/34.kmac_alert_test.3498561624
Short name T606
Test name
Test status
Simulation time 14929575 ps
CPU time 0.84 seconds
Started Aug 10 06:47:38 PM PDT 24
Finished Aug 10 06:47:39 PM PDT 24
Peak memory 218580 kb
Host smart-f2a2b3be-9e59-4139-bedb-d9ed3cf1f9cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498561624 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.3498561624 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_alert_test/latest

Test location /workspace/coverage/default/34.kmac_app.2725265203
Short name T251
Test name
Test status
Simulation time 23140432504 ps
CPU time 159.8 seconds
Started Aug 10 06:47:27 PM PDT 24
Finished Aug 10 06:50:07 PM PDT 24
Peak memory 340404 kb
Host smart-0b709400-6c79-435b-9a68-f8f401dff1dc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725265203 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.2725265203 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/34.kmac_app/latest

Test location /workspace/coverage/default/34.kmac_burst_write.874627950
Short name T880
Test name
Test status
Simulation time 29107154098 ps
CPU time 855.61 seconds
Started Aug 10 06:47:15 PM PDT 24
Finished Aug 10 07:01:31 PM PDT 24
Peak memory 250360 kb
Host smart-c710772d-129c-474f-b8eb-7c96af3f578f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874627950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.874627950
+enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_burst_write/latest

Test location /workspace/coverage/default/34.kmac_error.959967248
Short name T46
Test name
Test status
Simulation time 20549476993 ps
CPU time 116.48 seconds
Started Aug 10 06:47:37 PM PDT 24
Finished Aug 10 06:49:33 PM PDT 24
Peak memory 275472 kb
Host smart-e5080c74-5191-4539-868a-485752d1e232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959967248 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.959967248 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_error/latest

Test location /workspace/coverage/default/34.kmac_key_error.1462862338
Short name T524
Test name
Test status
Simulation time 1270247770 ps
CPU time 9.48 seconds
Started Aug 10 06:47:37 PM PDT 24
Finished Aug 10 06:47:47 PM PDT 24
Peak memory 226788 kb
Host smart-1db41e36-e189-4aa9-be81-f502d8e753a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462862338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.1462862338 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_key_error/latest

Test location /workspace/coverage/default/34.kmac_lc_escalation.2649180357
Short name T50
Test name
Test status
Simulation time 69154770 ps
CPU time 1.39 seconds
Started Aug 10 06:47:38 PM PDT 24
Finished Aug 10 06:47:40 PM PDT 24
Peak memory 226956 kb
Host smart-24dd6f22-c0e9-435a-a45b-b8ecdf649c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649180357 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.2649180357 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/34.kmac_lc_escalation/latest

Test location /workspace/coverage/default/34.kmac_long_msg_and_output.1333715540
Short name T566
Test name
Test status
Simulation time 255212564499 ps
CPU time 1435.49 seconds
Started Aug 10 06:47:17 PM PDT 24
Finished Aug 10 07:11:12 PM PDT 24
Peak memory 1535884 kb
Host smart-b68ce98b-c84b-477c-a067-dcc6ac45e8f5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333715540 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_a
nd_output.1333715540 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/34.kmac_sideload.2969397360
Short name T719
Test name
Test status
Simulation time 23385425847 ps
CPU time 601.75 seconds
Started Aug 10 06:47:16 PM PDT 24
Finished Aug 10 06:57:18 PM PDT 24
Peak memory 673032 kb
Host smart-2b43f107-acfb-4803-a9b8-caecb64b4dec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969397360 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.2969397360 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_sideload/latest

Test location /workspace/coverage/default/34.kmac_smoke.177059426
Short name T742
Test name
Test status
Simulation time 7426146918 ps
CPU time 43.23 seconds
Started Aug 10 06:47:17 PM PDT 24
Finished Aug 10 06:48:00 PM PDT 24
Peak memory 227092 kb
Host smart-b1afb169-d6ff-408b-acfa-3d78c1c593af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177059426 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.177059426 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_smoke/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_kmac.3683077247
Short name T711
Test name
Test status
Simulation time 423289112 ps
CPU time 5.9 seconds
Started Aug 10 06:47:17 PM PDT 24
Finished Aug 10 06:47:23 PM PDT 24
Peak memory 218780 kb
Host smart-e4ee0234-cd64-4d23-b6fa-a59ae419cb20
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683077247 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.kmac_test_vectors_kmac.3683077247 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_kmac_xof.565659618
Short name T402
Test name
Test status
Simulation time 474733900 ps
CPU time 6.83 seconds
Started Aug 10 06:47:30 PM PDT 24
Finished Aug 10 06:47:37 PM PDT 24
Peak memory 219800 kb
Host smart-61855010-f569-4e3a-959a-799096b14dda
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565659618 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.kmac_test_vectors_kmac_xof.565659618 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_224.2580619285
Short name T667
Test name
Test status
Simulation time 21650226844 ps
CPU time 2232.67 seconds
Started Aug 10 06:47:16 PM PDT 24
Finished Aug 10 07:24:29 PM PDT 24
Peak memory 1219808 kb
Host smart-6d8e7461-96a7-4e22-b76b-5dbadc0f4a2e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2580619285 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_224.2580619285 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_256.1490041513
Short name T428
Test name
Test status
Simulation time 141294952797 ps
CPU time 2239.26 seconds
Started Aug 10 06:47:17 PM PDT 24
Finished Aug 10 07:24:37 PM PDT 24
Peak memory 1164476 kb
Host smart-28ec88b0-cec6-448e-b4c4-26dc56c61008
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1490041513 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_256.1490041513 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_384.2425948329
Short name T868
Test name
Test status
Simulation time 185118330654 ps
CPU time 2672.23 seconds
Started Aug 10 06:47:15 PM PDT 24
Finished Aug 10 07:31:48 PM PDT 24
Peak memory 2377428 kb
Host smart-cd73a7aa-5e1c-436f-999d-3ce2b60f176c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2425948329 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_384.2425948329 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_512.2648174824
Short name T223
Test name
Test status
Simulation time 34460381337 ps
CPU time 1645.06 seconds
Started Aug 10 06:47:17 PM PDT 24
Finished Aug 10 07:14:42 PM PDT 24
Peak memory 1726868 kb
Host smart-6b7f8364-8958-43c2-ae5e-43a59915394b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2648174824 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_512.2648174824 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_shake_128.494083754
Short name T384
Test name
Test status
Simulation time 239767177785 ps
CPU time 6565.13 seconds
Started Aug 10 06:47:17 PM PDT 24
Finished Aug 10 08:36:42 PM PDT 24
Peak memory 2680116 kb
Host smart-e26d7d7d-6c7f-43b6-ab58-a104638682b8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=494083754 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_128.494083754 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_shake_256.383026922
Short name T598
Test name
Test status
Simulation time 257702618650 ps
CPU time 6085.01 seconds
Started Aug 10 06:47:16 PM PDT 24
Finished Aug 10 08:28:42 PM PDT 24
Peak memory 2261256 kb
Host smart-31d68669-d4c9-4239-93c3-7cca3a9f3262
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=383026922 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_256.383026922 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/35.kmac_alert_test.2020557329
Short name T208
Test name
Test status
Simulation time 55370559 ps
CPU time 0.86 seconds
Started Aug 10 06:48:03 PM PDT 24
Finished Aug 10 06:48:04 PM PDT 24
Peak memory 218424 kb
Host smart-275a4b47-3451-49e8-afa1-2468186c8e4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020557329 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.2020557329 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_alert_test/latest

Test location /workspace/coverage/default/35.kmac_app.4062322761
Short name T839
Test name
Test status
Simulation time 5809320151 ps
CPU time 53.56 seconds
Started Aug 10 06:47:57 PM PDT 24
Finished Aug 10 06:48:51 PM PDT 24
Peak memory 243392 kb
Host smart-3b9a507c-afe5-447b-b762-57f314d8a568
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062322761 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.4062322761 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/35.kmac_app/latest

Test location /workspace/coverage/default/35.kmac_burst_write.2205162320
Short name T757
Test name
Test status
Simulation time 27588720599 ps
CPU time 578.04 seconds
Started Aug 10 06:47:48 PM PDT 24
Finished Aug 10 06:57:26 PM PDT 24
Peak memory 243320 kb
Host smart-1802ae77-cc6b-4753-9114-08eaf6b1e7a1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205162320 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.220516232
0 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_burst_write/latest

Test location /workspace/coverage/default/35.kmac_entropy_refresh.1290090209
Short name T513
Test name
Test status
Simulation time 9783657332 ps
CPU time 239.09 seconds
Started Aug 10 06:47:55 PM PDT 24
Finished Aug 10 06:51:54 PM PDT 24
Peak memory 306368 kb
Host smart-de275cd0-0cf7-4163-9049-e57aab968121
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290090209 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.1
290090209 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/35.kmac_error.681077314
Short name T970
Test name
Test status
Simulation time 2236144976 ps
CPU time 39.7 seconds
Started Aug 10 06:47:55 PM PDT 24
Finished Aug 10 06:48:35 PM PDT 24
Peak memory 251636 kb
Host smart-8ed1ed01-15ce-434f-9604-1cf431e1103f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681077314 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.681077314 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_error/latest

Test location /workspace/coverage/default/35.kmac_key_error.412018132
Short name T1028
Test name
Test status
Simulation time 40932540 ps
CPU time 1.25 seconds
Started Aug 10 06:48:03 PM PDT 24
Finished Aug 10 06:48:05 PM PDT 24
Peak memory 225444 kb
Host smart-85d0a3db-40bd-4977-8db5-df1b8e098fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412018132 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.412018132 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_key_error/latest

Test location /workspace/coverage/default/35.kmac_lc_escalation.895650956
Short name T94
Test name
Test status
Simulation time 1241189710 ps
CPU time 40.67 seconds
Started Aug 10 06:48:04 PM PDT 24
Finished Aug 10 06:48:44 PM PDT 24
Peak memory 251604 kb
Host smart-fa652ab3-4b5d-40eb-9412-e945b0455bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895650956 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.895650956 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/35.kmac_lc_escalation/latest

Test location /workspace/coverage/default/35.kmac_long_msg_and_output.2754078117
Short name T1022
Test name
Test status
Simulation time 11001772197 ps
CPU time 1146.58 seconds
Started Aug 10 06:47:46 PM PDT 24
Finished Aug 10 07:06:53 PM PDT 24
Peak memory 828004 kb
Host smart-6f65740f-e5b5-41dd-a458-adc420b8911c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754078117 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_a
nd_output.2754078117 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/35.kmac_sideload.1094665522
Short name T602
Test name
Test status
Simulation time 13735263764 ps
CPU time 371 seconds
Started Aug 10 06:47:46 PM PDT 24
Finished Aug 10 06:53:57 PM PDT 24
Peak memory 510300 kb
Host smart-4280ee40-7364-404c-9cef-8424c79c8c6b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094665522 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.1094665522 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_sideload/latest

Test location /workspace/coverage/default/35.kmac_smoke.4075605879
Short name T553
Test name
Test status
Simulation time 3322373829 ps
CPU time 33.94 seconds
Started Aug 10 06:47:38 PM PDT 24
Finished Aug 10 06:48:12 PM PDT 24
Peak memory 223824 kb
Host smart-206750e7-2c9c-41d0-92c4-1ade4215ffc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075605879 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.4075605879 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_smoke/latest

Test location /workspace/coverage/default/35.kmac_stress_all.1073631138
Short name T846
Test name
Test status
Simulation time 62837807007 ps
CPU time 2662.18 seconds
Started Aug 10 06:48:04 PM PDT 24
Finished Aug 10 07:32:26 PM PDT 24
Peak memory 1074328 kb
Host smart-881b562b-9a76-4edc-a393-997ebf4a963d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1073631138 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.1073631138 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_stress_all/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_kmac.474137777
Short name T214
Test name
Test status
Simulation time 596993783 ps
CPU time 6.64 seconds
Started Aug 10 06:47:57 PM PDT 24
Finished Aug 10 06:48:03 PM PDT 24
Peak memory 219864 kb
Host smart-d7dbf962-5274-4937-87e1-f9930c717ef8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474137777 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.kmac_test_vectors_kmac.474137777 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_kmac_xof.945411096
Short name T239
Test name
Test status
Simulation time 678950804 ps
CPU time 9 seconds
Started Aug 10 06:47:56 PM PDT 24
Finished Aug 10 06:48:05 PM PDT 24
Peak memory 219824 kb
Host smart-b972d484-c711-4875-902d-1967da40f531
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945411096 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 35.kmac_test_vectors_kmac_xof.945411096 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_224.3618286906
Short name T906
Test name
Test status
Simulation time 100251401565 ps
CPU time 3628.65 seconds
Started Aug 10 06:47:47 PM PDT 24
Finished Aug 10 07:48:16 PM PDT 24
Peak memory 3267104 kb
Host smart-45a308e0-0d56-49a7-916e-550b246116b8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3618286906 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_224.3618286906 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_256.2682660186
Short name T710
Test name
Test status
Simulation time 507887929763 ps
CPU time 3190.43 seconds
Started Aug 10 06:47:46 PM PDT 24
Finished Aug 10 07:40:57 PM PDT 24
Peak memory 3019756 kb
Host smart-c8c907df-e929-47ef-a90e-8a733e4fff46
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2682660186 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_256.2682660186 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_384.1928091048
Short name T641
Test name
Test status
Simulation time 72991325854 ps
CPU time 2763.74 seconds
Started Aug 10 06:47:47 PM PDT 24
Finished Aug 10 07:33:51 PM PDT 24
Peak memory 2386644 kb
Host smart-82e98b9a-788e-4d3e-a290-8ea5ca2682dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1928091048 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_384.1928091048 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_512.400136539
Short name T936
Test name
Test status
Simulation time 33513302936 ps
CPU time 1426.5 seconds
Started Aug 10 06:47:55 PM PDT 24
Finished Aug 10 07:11:42 PM PDT 24
Peak memory 1719080 kb
Host smart-517ae125-724b-4db1-9167-1fd7e47265d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=400136539 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_512.400136539 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_shake_128.2723379383
Short name T426
Test name
Test status
Simulation time 254458650368 ps
CPU time 6356.74 seconds
Started Aug 10 06:47:56 PM PDT 24
Finished Aug 10 08:33:54 PM PDT 24
Peak memory 2687540 kb
Host smart-6f0d41ba-78a5-452f-8732-a93aef95942a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2723379383 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_shake_128.2723379383 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/36.kmac_alert_test.3864954700
Short name T453
Test name
Test status
Simulation time 29241053 ps
CPU time 0.93 seconds
Started Aug 10 06:48:43 PM PDT 24
Finished Aug 10 06:48:44 PM PDT 24
Peak memory 218544 kb
Host smart-c4453746-88d9-4cb8-84d4-dbedaf13333d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864954700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.3864954700 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_alert_test/latest

Test location /workspace/coverage/default/36.kmac_app.2832953219
Short name T590
Test name
Test status
Simulation time 9554655966 ps
CPU time 247.55 seconds
Started Aug 10 06:48:34 PM PDT 24
Finished Aug 10 06:52:42 PM PDT 24
Peak memory 401592 kb
Host smart-9d6b53d6-5b7c-47fa-95f4-0ee21dc2050e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832953219 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.2832953219 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/36.kmac_app/latest

Test location /workspace/coverage/default/36.kmac_burst_write.416128084
Short name T301
Test name
Test status
Simulation time 18018082103 ps
CPU time 166.52 seconds
Started Aug 10 06:48:14 PM PDT 24
Finished Aug 10 06:51:01 PM PDT 24
Peak memory 230444 kb
Host smart-78d0123f-867e-4654-b7ca-b44871d7e9e5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416128084 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.416128084
+enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_burst_write/latest

Test location /workspace/coverage/default/36.kmac_entropy_refresh.1177622327
Short name T131
Test name
Test status
Simulation time 29882892850 ps
CPU time 272.18 seconds
Started Aug 10 06:48:42 PM PDT 24
Finished Aug 10 06:53:15 PM PDT 24
Peak memory 311932 kb
Host smart-02e1f37c-c289-468b-bb82-8106e2456190
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177622327 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.1
177622327 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/36.kmac_error.580646804
Short name T178
Test name
Test status
Simulation time 61835008683 ps
CPU time 374.96 seconds
Started Aug 10 06:48:42 PM PDT 24
Finished Aug 10 06:54:57 PM PDT 24
Peak memory 357748 kb
Host smart-363430e9-3d95-47cf-bb57-23aade2d9d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580646804 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.580646804 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_error/latest

Test location /workspace/coverage/default/36.kmac_key_error.3451619416
Short name T539
Test name
Test status
Simulation time 734597793 ps
CPU time 5.52 seconds
Started Aug 10 06:48:43 PM PDT 24
Finished Aug 10 06:48:48 PM PDT 24
Peak memory 226788 kb
Host smart-69ebc154-83dc-48f0-bd1f-dd4a6c1dccce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451619416 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.3451619416 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_key_error/latest

Test location /workspace/coverage/default/36.kmac_lc_escalation.2306938139
Short name T370
Test name
Test status
Simulation time 1782368658 ps
CPU time 31.09 seconds
Started Aug 10 06:48:42 PM PDT 24
Finished Aug 10 06:49:13 PM PDT 24
Peak memory 254380 kb
Host smart-79c76507-614d-4237-8560-e85caab8b2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306938139 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.2306938139 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/36.kmac_lc_escalation/latest

Test location /workspace/coverage/default/36.kmac_sideload.1936993326
Short name T983
Test name
Test status
Simulation time 14111198144 ps
CPU time 392.94 seconds
Started Aug 10 06:48:14 PM PDT 24
Finished Aug 10 06:54:47 PM PDT 24
Peak memory 532396 kb
Host smart-695e1070-a34d-444b-9b94-fc433160b9b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936993326 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.1936993326 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_sideload/latest

Test location /workspace/coverage/default/36.kmac_smoke.3064644460
Short name T230
Test name
Test status
Simulation time 1934364037 ps
CPU time 45.42 seconds
Started Aug 10 06:48:04 PM PDT 24
Finished Aug 10 06:48:49 PM PDT 24
Peak memory 222928 kb
Host smart-abb26671-e954-44c6-a4d8-237f33386929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064644460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.3064644460 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_smoke/latest

Test location /workspace/coverage/default/36.kmac_stress_all.3295381439
Short name T604
Test name
Test status
Simulation time 283565468434 ps
CPU time 1538.59 seconds
Started Aug 10 06:48:43 PM PDT 24
Finished Aug 10 07:14:21 PM PDT 24
Peak memory 696256 kb
Host smart-942b23c6-d97c-41eb-b299-8bcc2d875690
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3295381439 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all.3295381439 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_stress_all/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_kmac.3484426541
Short name T474
Test name
Test status
Simulation time 287612254 ps
CPU time 6.46 seconds
Started Aug 10 06:48:24 PM PDT 24
Finished Aug 10 06:48:31 PM PDT 24
Peak memory 219008 kb
Host smart-93708e61-e795-47d2-9615-2813648c095e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484426541 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.kmac_test_vectors_kmac.3484426541 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_kmac_xof.978861926
Short name T300
Test name
Test status
Simulation time 182579002 ps
CPU time 6.4 seconds
Started Aug 10 06:48:33 PM PDT 24
Finished Aug 10 06:48:40 PM PDT 24
Peak memory 219028 kb
Host smart-623be4ed-dfdb-45b2-82ea-c266bf8c6b09
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978861926 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.kmac_test_vectors_kmac_xof.978861926 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_224.1844693682
Short name T294
Test name
Test status
Simulation time 20235801206 ps
CPU time 2236.01 seconds
Started Aug 10 06:48:13 PM PDT 24
Finished Aug 10 07:25:29 PM PDT 24
Peak memory 1202352 kb
Host smart-d3b024f2-ce15-418b-9f2e-b0c25710ac8c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1844693682 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_224.1844693682 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_256.4055959876
Short name T533
Test name
Test status
Simulation time 21360008038 ps
CPU time 2088.06 seconds
Started Aug 10 06:48:14 PM PDT 24
Finished Aug 10 07:23:02 PM PDT 24
Peak memory 1149884 kb
Host smart-72c04562-c818-4367-b0da-1b3b40248893
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4055959876 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_256.4055959876 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_384.1229754567
Short name T625
Test name
Test status
Simulation time 641574512919 ps
CPU time 2641.03 seconds
Started Aug 10 06:48:26 PM PDT 24
Finished Aug 10 07:32:28 PM PDT 24
Peak memory 2397328 kb
Host smart-93c994de-ecab-4c6e-9318-9170d6bcb830
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1229754567 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_384.1229754567 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_512.3950357760
Short name T599
Test name
Test status
Simulation time 43539337999 ps
CPU time 1220.49 seconds
Started Aug 10 06:48:25 PM PDT 24
Finished Aug 10 07:08:46 PM PDT 24
Peak memory 700876 kb
Host smart-2d098beb-0a3e-465a-b877-000e93c6e9d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3950357760 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_512.3950357760 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_shake_256.2605065107
Short name T126
Test name
Test status
Simulation time 383247497361 ps
CPU time 9891.42 seconds
Started Aug 10 06:48:25 PM PDT 24
Finished Aug 10 09:33:17 PM PDT 24
Peak memory 6368184 kb
Host smart-acf219ea-cb69-48b4-be5f-0c1a468ebdff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2605065107 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_shake_256.2605065107 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/37.kmac_alert_test.3424891832
Short name T652
Test name
Test status
Simulation time 16877150 ps
CPU time 0.87 seconds
Started Aug 10 06:49:36 PM PDT 24
Finished Aug 10 06:49:37 PM PDT 24
Peak memory 218576 kb
Host smart-63304dc6-08b7-418e-aa2c-247a9b07a936
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424891832 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.3424891832 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_alert_test/latest

Test location /workspace/coverage/default/37.kmac_app.2264563048
Short name T18
Test name
Test status
Simulation time 16100300682 ps
CPU time 339.68 seconds
Started Aug 10 06:49:24 PM PDT 24
Finished Aug 10 06:55:04 PM PDT 24
Peak memory 457460 kb
Host smart-e61d1262-6b30-4f40-b831-fa5f2fc45981
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264563048 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.2264563048 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/37.kmac_app/latest

Test location /workspace/coverage/default/37.kmac_burst_write.10547722
Short name T661
Test name
Test status
Simulation time 101111294267 ps
CPU time 1146.62 seconds
Started Aug 10 06:49:02 PM PDT 24
Finished Aug 10 07:08:09 PM PDT 24
Peak memory 256164 kb
Host smart-b22d3ff0-26a1-4f2f-aace-de1bcc94aef5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10547722 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.10547722 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_burst_write/latest

Test location /workspace/coverage/default/37.kmac_entropy_refresh.298350426
Short name T919
Test name
Test status
Simulation time 87582653419 ps
CPU time 453.83 seconds
Started Aug 10 06:49:23 PM PDT 24
Finished Aug 10 06:56:57 PM PDT 24
Peak memory 556780 kb
Host smart-5f929e22-e57d-4700-957d-7dcced9e6d00
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298350426 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.29
8350426 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/37.kmac_error.1002376994
Short name T541
Test name
Test status
Simulation time 2096074385 ps
CPU time 40.67 seconds
Started Aug 10 06:49:31 PM PDT 24
Finished Aug 10 06:50:11 PM PDT 24
Peak memory 252080 kb
Host smart-bce7e7bc-93ca-4a20-b29a-d0557220c68c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002376994 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.1002376994 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_error/latest

Test location /workspace/coverage/default/37.kmac_key_error.757820684
Short name T743
Test name
Test status
Simulation time 8142782682 ps
CPU time 11.24 seconds
Started Aug 10 06:49:36 PM PDT 24
Finished Aug 10 06:49:47 PM PDT 24
Peak memory 226808 kb
Host smart-de0f8cf0-999f-47f9-bc2f-198b71f859fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757820684 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.757820684 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_key_error/latest

Test location /workspace/coverage/default/37.kmac_lc_escalation.2525483588
Short name T71
Test name
Test status
Simulation time 3468407133 ps
CPU time 17.13 seconds
Started Aug 10 06:49:36 PM PDT 24
Finished Aug 10 06:49:53 PM PDT 24
Peak memory 243572 kb
Host smart-38b11b44-d0c0-408c-959e-cd78a9e28649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525483588 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.2525483588 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/37.kmac_lc_escalation/latest

Test location /workspace/coverage/default/37.kmac_long_msg_and_output.405140453
Short name T627
Test name
Test status
Simulation time 33204407055 ps
CPU time 2070.81 seconds
Started Aug 10 06:48:52 PM PDT 24
Finished Aug 10 07:23:23 PM PDT 24
Peak memory 1194036 kb
Host smart-3f00a253-b75c-4938-b385-1f06afc43d8f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405140453 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_an
d_output.405140453 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/37.kmac_sideload.77504853
Short name T313
Test name
Test status
Simulation time 5811301148 ps
CPU time 44.79 seconds
Started Aug 10 06:49:02 PM PDT 24
Finished Aug 10 06:49:47 PM PDT 24
Peak memory 265304 kb
Host smart-b3354396-054a-4569-ba86-abba7eac2a96
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77504853 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.77504853 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_sideload/latest

Test location /workspace/coverage/default/37.kmac_smoke.2505733098
Short name T777
Test name
Test status
Simulation time 5149306466 ps
CPU time 71.96 seconds
Started Aug 10 06:48:52 PM PDT 24
Finished Aug 10 06:50:04 PM PDT 24
Peak memory 226056 kb
Host smart-d8ac8853-44dc-4bb3-a637-0ac616a7ede0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505733098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.2505733098 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_smoke/latest

Test location /workspace/coverage/default/37.kmac_stress_all.875875278
Short name T422
Test name
Test status
Simulation time 21667661785 ps
CPU time 1771.16 seconds
Started Aug 10 06:49:31 PM PDT 24
Finished Aug 10 07:19:02 PM PDT 24
Peak memory 578692 kb
Host smart-ec9f921c-7443-43fa-acf0-f83ca4541d9d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=875875278 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.875875278 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_stress_all/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_kmac.1878729339
Short name T551
Test name
Test status
Simulation time 1239465607 ps
CPU time 6.36 seconds
Started Aug 10 06:49:16 PM PDT 24
Finished Aug 10 06:49:22 PM PDT 24
Peak memory 219832 kb
Host smart-39ccce41-0061-4abd-b22d-30daa3d25313
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878729339 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.kmac_test_vectors_kmac.1878729339 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_kmac_xof.2831737591
Short name T295
Test name
Test status
Simulation time 105123527 ps
CPU time 5.77 seconds
Started Aug 10 06:49:22 PM PDT 24
Finished Aug 10 06:49:28 PM PDT 24
Peak memory 219828 kb
Host smart-49ac8b26-0400-46c9-834b-d0887a19a92d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831737591 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.kmac_test_vectors_kmac_xof.2831737591 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_224.2467944185
Short name T558
Test name
Test status
Simulation time 290590295959 ps
CPU time 2279.11 seconds
Started Aug 10 06:49:12 PM PDT 24
Finished Aug 10 07:27:12 PM PDT 24
Peak memory 1186548 kb
Host smart-85c820e5-706e-43d9-acd7-3d942f53e3eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2467944185 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_224.2467944185 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_256.1624833283
Short name T262
Test name
Test status
Simulation time 19508576282 ps
CPU time 2098.37 seconds
Started Aug 10 06:49:14 PM PDT 24
Finished Aug 10 07:24:12 PM PDT 24
Peak memory 1128016 kb
Host smart-b2604b2d-e169-4ff0-b52c-414eb548334a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1624833283 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_256.1624833283 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_384.2341369127
Short name T787
Test name
Test status
Simulation time 73106187889 ps
CPU time 2586.68 seconds
Started Aug 10 06:49:13 PM PDT 24
Finished Aug 10 07:32:20 PM PDT 24
Peak memory 2422560 kb
Host smart-514ef642-298b-48f6-8f6c-9bff66712959
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2341369127 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_384.2341369127 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_512.2180228378
Short name T349
Test name
Test status
Simulation time 102892248457 ps
CPU time 1898.7 seconds
Started Aug 10 06:49:13 PM PDT 24
Finished Aug 10 07:20:52 PM PDT 24
Peak memory 1733520 kb
Host smart-0d734ad7-7015-4645-8580-c447fade5386
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2180228378 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_512.2180228378 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_shake_128.3750717632
Short name T739
Test name
Test status
Simulation time 178612681812 ps
CPU time 6583.31 seconds
Started Aug 10 06:49:12 PM PDT 24
Finished Aug 10 08:38:56 PM PDT 24
Peak memory 2750060 kb
Host smart-9f629f7f-fe89-47aa-accf-245440bb23ee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3750717632 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_128.3750717632 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_shake_256.1095228039
Short name T559
Test name
Test status
Simulation time 619584807426 ps
CPU time 9328.06 seconds
Started Aug 10 06:49:13 PM PDT 24
Finished Aug 10 09:24:43 PM PDT 24
Peak memory 6342908 kb
Host smart-c372073d-5d8e-4c4c-9f37-4195080e3d2a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1095228039 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_256.1095228039 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/38.kmac_alert_test.3193385807
Short name T86
Test name
Test status
Simulation time 15102930 ps
CPU time 0.8 seconds
Started Aug 10 06:50:18 PM PDT 24
Finished Aug 10 06:50:19 PM PDT 24
Peak memory 218544 kb
Host smart-75900dcb-5e06-4101-ab45-6469f5fa2caa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193385807 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.3193385807 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_alert_test/latest

Test location /workspace/coverage/default/38.kmac_app.3695470911
Short name T695
Test name
Test status
Simulation time 654726040 ps
CPU time 16.4 seconds
Started Aug 10 06:50:07 PM PDT 24
Finished Aug 10 06:50:23 PM PDT 24
Peak memory 230476 kb
Host smart-2c714aac-8cb1-45cf-9a22-275c6455a5a5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695470911 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.3695470911 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/38.kmac_app/latest

Test location /workspace/coverage/default/38.kmac_burst_write.2207235725
Short name T377
Test name
Test status
Simulation time 33241665167 ps
CPU time 779.84 seconds
Started Aug 10 06:49:49 PM PDT 24
Finished Aug 10 07:02:49 PM PDT 24
Peak memory 243440 kb
Host smart-8a26bf96-6306-4244-ad11-df8385194ff3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207235725 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.220723572
5 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_burst_write/latest

Test location /workspace/coverage/default/38.kmac_error.2206575780
Short name T834
Test name
Test status
Simulation time 1780326730 ps
CPU time 147.52 seconds
Started Aug 10 06:50:09 PM PDT 24
Finished Aug 10 06:52:36 PM PDT 24
Peak memory 276304 kb
Host smart-9a2a78b6-5533-41ea-bc6e-c5a7cb37daf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206575780 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.2206575780 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_error/latest

Test location /workspace/coverage/default/38.kmac_key_error.1804286156
Short name T912
Test name
Test status
Simulation time 5587923071 ps
CPU time 11.2 seconds
Started Aug 10 06:50:17 PM PDT 24
Finished Aug 10 06:50:29 PM PDT 24
Peak memory 226816 kb
Host smart-0387527e-1ea2-423e-a6cf-dd21967f04a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804286156 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.1804286156 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_key_error/latest

Test location /workspace/coverage/default/38.kmac_long_msg_and_output.3356238864
Short name T297
Test name
Test status
Simulation time 59697385694 ps
CPU time 3476.59 seconds
Started Aug 10 06:49:44 PM PDT 24
Finished Aug 10 07:47:41 PM PDT 24
Peak memory 3013652 kb
Host smart-99af33d5-b733-496d-8ca6-1ee634e52dbf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356238864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_a
nd_output.3356238864 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/38.kmac_sideload.2207991874
Short name T279
Test name
Test status
Simulation time 61786517339 ps
CPU time 344.72 seconds
Started Aug 10 06:49:39 PM PDT 24
Finished Aug 10 06:55:24 PM PDT 24
Peak memory 512020 kb
Host smart-16cb593c-b216-4831-a1b0-6c2face89ee4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207991874 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.2207991874 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_sideload/latest

Test location /workspace/coverage/default/38.kmac_smoke.3658592713
Short name T201
Test name
Test status
Simulation time 4455259602 ps
CPU time 44.25 seconds
Started Aug 10 06:49:31 PM PDT 24
Finished Aug 10 06:50:15 PM PDT 24
Peak memory 226920 kb
Host smart-64430459-eeff-4244-a367-334f9d0d7a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658592713 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.3658592713 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_smoke/latest

Test location /workspace/coverage/default/38.kmac_stress_all.3630868901
Short name T64
Test name
Test status
Simulation time 55561796699 ps
CPU time 516.55 seconds
Started Aug 10 06:50:18 PM PDT 24
Finished Aug 10 06:58:54 PM PDT 24
Peak memory 317008 kb
Host smart-487176cc-635e-44ef-8234-358ef2e9be65
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3630868901 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.3630868901 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_stress_all/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_kmac.2342339454
Short name T352
Test name
Test status
Simulation time 972860855 ps
CPU time 7.42 seconds
Started Aug 10 06:50:07 PM PDT 24
Finished Aug 10 06:50:14 PM PDT 24
Peak memory 218972 kb
Host smart-faee3f84-5f06-401d-8085-9ddb0966e364
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342339454 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.kmac_test_vectors_kmac.2342339454 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_kmac_xof.2283235211
Short name T764
Test name
Test status
Simulation time 1207259318 ps
CPU time 5.96 seconds
Started Aug 10 06:50:08 PM PDT 24
Finished Aug 10 06:50:14 PM PDT 24
Peak memory 219808 kb
Host smart-b221d75b-e85c-46de-a5bb-71e4326f7a78
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283235211 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.kmac_test_vectors_kmac_xof.2283235211 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_224.1826546573
Short name T955
Test name
Test status
Simulation time 1363688729861 ps
CPU time 3035.43 seconds
Started Aug 10 06:49:49 PM PDT 24
Finished Aug 10 07:40:25 PM PDT 24
Peak memory 3223364 kb
Host smart-5cc164b8-325b-4d35-b6ca-922abd1f5a29
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1826546573 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_224.1826546573 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_256.671163357
Short name T261
Test name
Test status
Simulation time 19101285013 ps
CPU time 2071.84 seconds
Started Aug 10 06:49:49 PM PDT 24
Finished Aug 10 07:24:21 PM PDT 24
Peak memory 1127564 kb
Host smart-0c9bd293-3a80-430b-af37-90165c2e7bd8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=671163357 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_256.671163357 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_384.3934823722
Short name T890
Test name
Test status
Simulation time 62057944701 ps
CPU time 1659.3 seconds
Started Aug 10 06:50:01 PM PDT 24
Finished Aug 10 07:17:40 PM PDT 24
Peak memory 933112 kb
Host smart-035aad06-f6da-47c5-9554-8e75783db271
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3934823722 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_384.3934823722 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_512.2729101173
Short name T833
Test name
Test status
Simulation time 42021124770 ps
CPU time 1312.29 seconds
Started Aug 10 06:50:00 PM PDT 24
Finished Aug 10 07:11:53 PM PDT 24
Peak memory 693624 kb
Host smart-b920cd20-e6eb-46cb-8440-9c012399db8d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2729101173 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_512.2729101173 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_shake_128.2845945612
Short name T715
Test name
Test status
Simulation time 394647108320 ps
CPU time 5888.24 seconds
Started Aug 10 06:49:57 PM PDT 24
Finished Aug 10 08:28:06 PM PDT 24
Peak memory 2666200 kb
Host smart-6b5aef59-386c-4785-9959-b51e6a1d3813
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2845945612 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_128.2845945612 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_shake_256.1598264063
Short name T439
Test name
Test status
Simulation time 403243902124 ps
CPU time 8560.94 seconds
Started Aug 10 06:50:01 PM PDT 24
Finished Aug 10 09:12:43 PM PDT 24
Peak memory 6351840 kb
Host smart-3c028e05-1dc1-4865-b772-e7a6d93f3439
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1598264063 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_256.1598264063 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/39.kmac_alert_test.2412358926
Short name T637
Test name
Test status
Simulation time 43410719 ps
CPU time 0.82 seconds
Started Aug 10 06:50:56 PM PDT 24
Finished Aug 10 06:50:57 PM PDT 24
Peak memory 218484 kb
Host smart-a949292c-975a-45ab-9739-06a49a18f5b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412358926 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.2412358926 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_alert_test/latest

Test location /workspace/coverage/default/39.kmac_app.4082290890
Short name T452
Test name
Test status
Simulation time 47637744740 ps
CPU time 76.46 seconds
Started Aug 10 06:50:39 PM PDT 24
Finished Aug 10 06:51:56 PM PDT 24
Peak memory 272580 kb
Host smart-46c85db8-6e67-48fe-9fa6-3f9b8378dc6a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082290890 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.4082290890 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/39.kmac_app/latest

Test location /workspace/coverage/default/39.kmac_burst_write.2419250537
Short name T151
Test name
Test status
Simulation time 16544747381 ps
CPU time 733.53 seconds
Started Aug 10 06:50:18 PM PDT 24
Finished Aug 10 07:02:31 PM PDT 24
Peak memory 248852 kb
Host smart-957b1007-fd46-4b47-a321-4bc636664bc6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419250537 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.241925053
7 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_burst_write/latest

Test location /workspace/coverage/default/39.kmac_entropy_refresh.3736952309
Short name T1042
Test name
Test status
Simulation time 43521359683 ps
CPU time 198.84 seconds
Started Aug 10 06:50:48 PM PDT 24
Finished Aug 10 06:54:07 PM PDT 24
Peak memory 355460 kb
Host smart-6eb96a37-2d6f-42c6-aea0-87f63a982a31
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736952309 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.3
736952309 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/39.kmac_error.1536470863
Short name T546
Test name
Test status
Simulation time 8859624919 ps
CPU time 290.09 seconds
Started Aug 10 06:50:47 PM PDT 24
Finished Aug 10 06:55:37 PM PDT 24
Peak memory 444556 kb
Host smart-329fac15-7ccf-47c3-b467-7c660e4743aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536470863 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.1536470863 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_error/latest

Test location /workspace/coverage/default/39.kmac_key_error.2001934034
Short name T914
Test name
Test status
Simulation time 7443099260 ps
CPU time 4.22 seconds
Started Aug 10 06:50:47 PM PDT 24
Finished Aug 10 06:50:51 PM PDT 24
Peak memory 226780 kb
Host smart-9cf4de4d-4c60-44d2-a918-220416560d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001934034 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.2001934034 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_key_error/latest

Test location /workspace/coverage/default/39.kmac_lc_escalation.2212615184
Short name T33
Test name
Test status
Simulation time 131844265 ps
CPU time 1.5 seconds
Started Aug 10 06:50:47 PM PDT 24
Finished Aug 10 06:50:49 PM PDT 24
Peak memory 227012 kb
Host smart-b3622609-3e11-409f-867c-c287d4afe1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212615184 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.2212615184 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/39.kmac_lc_escalation/latest

Test location /workspace/coverage/default/39.kmac_long_msg_and_output.1422440915
Short name T957
Test name
Test status
Simulation time 11855982164 ps
CPU time 1153.32 seconds
Started Aug 10 06:50:16 PM PDT 24
Finished Aug 10 07:09:29 PM PDT 24
Peak memory 816944 kb
Host smart-a78c38d2-5403-4330-9ab8-e9f9a4b49465
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422440915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_a
nd_output.1422440915 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/39.kmac_sideload.2325664464
Short name T250
Test name
Test status
Simulation time 147201773797 ps
CPU time 563.89 seconds
Started Aug 10 06:50:17 PM PDT 24
Finished Aug 10 06:59:41 PM PDT 24
Peak memory 631844 kb
Host smart-f1cfe344-3d0a-4da2-9adb-0173d2f9eb5d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325664464 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.2325664464 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_sideload/latest

Test location /workspace/coverage/default/39.kmac_smoke.1133791482
Short name T628
Test name
Test status
Simulation time 14175460088 ps
CPU time 46.94 seconds
Started Aug 10 06:50:17 PM PDT 24
Finished Aug 10 06:51:04 PM PDT 24
Peak memory 227072 kb
Host smart-3140e100-366a-45ba-8947-a4790c33cbc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133791482 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.1133791482 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_smoke/latest

Test location /workspace/coverage/default/39.kmac_stress_all.2200155155
Short name T436
Test name
Test status
Simulation time 1758454361 ps
CPU time 136.55 seconds
Started Aug 10 06:50:47 PM PDT 24
Finished Aug 10 06:53:04 PM PDT 24
Peak memory 262904 kb
Host smart-cae246f9-f295-47d5-8a03-f9fc21419e45
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2200155155 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.2200155155 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_stress_all/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_kmac.310976750
Short name T160
Test name
Test status
Simulation time 873393288 ps
CPU time 7.33 seconds
Started Aug 10 06:50:39 PM PDT 24
Finished Aug 10 06:50:47 PM PDT 24
Peak memory 219168 kb
Host smart-9a101ae5-82b8-4c9b-8a7e-2ef8990ac6a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310976750 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.kmac_test_vectors_kmac.310976750 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_kmac_xof.1753632747
Short name T221
Test name
Test status
Simulation time 426378295 ps
CPU time 5.98 seconds
Started Aug 10 06:50:38 PM PDT 24
Finished Aug 10 06:50:45 PM PDT 24
Peak memory 218988 kb
Host smart-10a2a266-5301-426b-933b-2b3714307461
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753632747 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.kmac_test_vectors_kmac_xof.1753632747 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_224.3050563846
Short name T713
Test name
Test status
Simulation time 283119697106 ps
CPU time 2279.31 seconds
Started Aug 10 06:50:26 PM PDT 24
Finished Aug 10 07:28:26 PM PDT 24
Peak memory 1165476 kb
Host smart-c9229503-60c7-4bb3-85e9-333642d025e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3050563846 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_224.3050563846 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_256.24552928
Short name T596
Test name
Test status
Simulation time 260415367850 ps
CPU time 3180.83 seconds
Started Aug 10 06:50:29 PM PDT 24
Finished Aug 10 07:43:30 PM PDT 24
Peak memory 3093680 kb
Host smart-0a4fbcd9-96eb-48e9-84b1-2bf1e85cc274
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=24552928 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_256.24552928 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_384.1432343985
Short name T555
Test name
Test status
Simulation time 193595932947 ps
CPU time 2244.31 seconds
Started Aug 10 06:50:25 PM PDT 24
Finished Aug 10 07:27:50 PM PDT 24
Peak memory 2428196 kb
Host smart-6ebb5113-38da-4440-b8ab-1659f2bbf7bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1432343985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_384.1432343985 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_512.196847998
Short name T977
Test name
Test status
Simulation time 90736852177 ps
CPU time 1669.37 seconds
Started Aug 10 06:50:28 PM PDT 24
Finished Aug 10 07:18:18 PM PDT 24
Peak memory 1709752 kb
Host smart-793b7539-6f01-4782-9967-257f05f567df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=196847998 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_512.196847998 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_shake_128.2166775886
Short name T209
Test name
Test status
Simulation time 247545088464 ps
CPU time 6312.14 seconds
Started Aug 10 06:50:27 PM PDT 24
Finished Aug 10 08:35:40 PM PDT 24
Peak memory 2636348 kb
Host smart-d2b5bd1e-e050-49e6-9675-912fd27ba0fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2166775886 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_128.2166775886 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_shake_256.3057134246
Short name T257
Test name
Test status
Simulation time 74211313767 ps
CPU time 5630.86 seconds
Started Aug 10 06:50:25 PM PDT 24
Finished Aug 10 08:24:17 PM PDT 24
Peak memory 2273516 kb
Host smart-6941474a-32b4-45d0-92bd-3785c94e752a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3057134246 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_256.3057134246 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/4.kmac_alert_test.3513232883
Short name T1032
Test name
Test status
Simulation time 57259015 ps
CPU time 0.86 seconds
Started Aug 10 06:30:30 PM PDT 24
Finished Aug 10 06:30:31 PM PDT 24
Peak memory 218544 kb
Host smart-3fe20440-808e-47c5-816e-e22c6d438ee9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513232883 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.3513232883 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_alert_test/latest

Test location /workspace/coverage/default/4.kmac_app.1807130092
Short name T346
Test name
Test status
Simulation time 3219447982 ps
CPU time 100.34 seconds
Started Aug 10 06:30:17 PM PDT 24
Finished Aug 10 06:31:58 PM PDT 24
Peak memory 291680 kb
Host smart-afb10373-643f-4a84-8ec3-6c3595752315
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807130092 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.1807130092 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/4.kmac_app/latest

Test location /workspace/coverage/default/4.kmac_app_with_partial_data.2287522799
Short name T954
Test name
Test status
Simulation time 5553012868 ps
CPU time 89.57 seconds
Started Aug 10 06:30:18 PM PDT 24
Finished Aug 10 06:31:47 PM PDT 24
Peak memory 284704 kb
Host smart-3d3ec5de-c6f7-4e39-be4f-76a72ff911a6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287522799 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_par
tial_data.2287522799 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/4.kmac_burst_write.4250555623
Short name T612
Test name
Test status
Simulation time 5840687811 ps
CPU time 302.48 seconds
Started Aug 10 06:30:17 PM PDT 24
Finished Aug 10 06:35:20 PM PDT 24
Peak memory 235664 kb
Host smart-e021aee2-0286-4dcf-9eea-f8193ef52f32
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250555623 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.4250555623
+enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_burst_write/latest

Test location /workspace/coverage/default/4.kmac_edn_timeout_error.2087154445
Short name T966
Test name
Test status
Simulation time 284638532 ps
CPU time 20.43 seconds
Started Aug 10 06:30:17 PM PDT 24
Finished Aug 10 06:30:38 PM PDT 24
Peak memory 226036 kb
Host smart-36bc5642-6daf-498c-b817-14baf76437bc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2087154445 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.2087154445 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_mode_error.3849784441
Short name T562
Test name
Test status
Simulation time 73041557 ps
CPU time 1.09 seconds
Started Aug 10 06:30:24 PM PDT 24
Finished Aug 10 06:30:26 PM PDT 24
Peak memory 222268 kb
Host smart-0f3b98c8-f58d-43df-85ed-7430bf14aa3f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3849784441 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.3849784441 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_ready_error.2964373406
Short name T431
Test name
Test status
Simulation time 5257077994 ps
CPU time 49.02 seconds
Started Aug 10 06:30:23 PM PDT 24
Finished Aug 10 06:31:12 PM PDT 24
Peak memory 224056 kb
Host smart-e8db520c-e009-4abb-8716-1f21c4b7541a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964373406 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.2964373406 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_refresh.824412420
Short name T510
Test name
Test status
Simulation time 65270346247 ps
CPU time 323.94 seconds
Started Aug 10 06:30:17 PM PDT 24
Finished Aug 10 06:35:41 PM PDT 24
Peak memory 433644 kb
Host smart-952a1ae8-bd90-43a0-a6b8-90b288c5c80c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824412420 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.824
412420 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/4.kmac_error.3522907797
Short name T414
Test name
Test status
Simulation time 19399943980 ps
CPU time 217.03 seconds
Started Aug 10 06:30:18 PM PDT 24
Finished Aug 10 06:33:55 PM PDT 24
Peak memory 306476 kb
Host smart-75a1eacd-2cc5-48b7-a785-3c63f564df35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522907797 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.3522907797 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_error/latest

Test location /workspace/coverage/default/4.kmac_key_error.2155067785
Short name T1011
Test name
Test status
Simulation time 1030995665 ps
CPU time 4.73 seconds
Started Aug 10 06:30:16 PM PDT 24
Finished Aug 10 06:30:21 PM PDT 24
Peak memory 226692 kb
Host smart-f27cc3ba-4315-43b9-a2a1-33cb00a444aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155067785 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.2155067785 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_key_error/latest

Test location /workspace/coverage/default/4.kmac_lc_escalation.2108956400
Short name T447
Test name
Test status
Simulation time 134321580 ps
CPU time 1.49 seconds
Started Aug 10 06:30:22 PM PDT 24
Finished Aug 10 06:30:24 PM PDT 24
Peak memory 226892 kb
Host smart-db60a001-517f-45e4-b551-d6f1b20aa65a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108956400 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.2108956400 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/4.kmac_lc_escalation/latest

Test location /workspace/coverage/default/4.kmac_long_msg_and_output.2128400728
Short name T323
Test name
Test status
Simulation time 5463067875 ps
CPU time 97.89 seconds
Started Aug 10 06:30:08 PM PDT 24
Finished Aug 10 06:31:46 PM PDT 24
Peak memory 348908 kb
Host smart-60ad39db-aa10-4875-a99e-97f2a49ba3d1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128400728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_an
d_output.2128400728 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/4.kmac_mubi.3160390798
Short name T85
Test name
Test status
Simulation time 2938584611 ps
CPU time 36.42 seconds
Started Aug 10 06:30:18 PM PDT 24
Finished Aug 10 06:30:54 PM PDT 24
Peak memory 234156 kb
Host smart-2a058da8-1f69-4e61-aeb4-914b2e1fbfed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160390798 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.3160390798 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_mubi/latest

Test location /workspace/coverage/default/4.kmac_sec_cm.2158919283
Short name T31
Test name
Test status
Simulation time 57863277977 ps
CPU time 63.86 seconds
Started Aug 10 06:30:30 PM PDT 24
Finished Aug 10 06:31:34 PM PDT 24
Peak memory 276832 kb
Host smart-01833ad0-b0fa-4c2f-9478-dca46e732a04
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158919283 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.2158919283 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspace/4.kmac_sec_cm/latest

Test location /workspace/coverage/default/4.kmac_sideload.2406217983
Short name T639
Test name
Test status
Simulation time 13058522475 ps
CPU time 146.48 seconds
Started Aug 10 06:30:18 PM PDT 24
Finished Aug 10 06:32:44 PM PDT 24
Peak memory 339196 kb
Host smart-ace1f29d-40ac-4093-8b2f-d0a6a8b507a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406217983 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.2406217983 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_sideload/latest

Test location /workspace/coverage/default/4.kmac_smoke.1894509465
Short name T660
Test name
Test status
Simulation time 1733660642 ps
CPU time 16.36 seconds
Started Aug 10 06:30:08 PM PDT 24
Finished Aug 10 06:30:24 PM PDT 24
Peak memory 226948 kb
Host smart-a26c9902-2215-4d08-aa70-7f0c14073d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894509465 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.1894509465 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_smoke/latest

Test location /workspace/coverage/default/4.kmac_stress_all.1108542038
Short name T16
Test name
Test status
Simulation time 191969520621 ps
CPU time 1028.45 seconds
Started Aug 10 06:30:23 PM PDT 24
Finished Aug 10 06:47:31 PM PDT 24
Peak memory 378452 kb
Host smart-de2ef706-be2b-4b9e-bd7c-19d31fdf611e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1108542038 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.1108542038 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_stress_all/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_kmac.1015630513
Short name T350
Test name
Test status
Simulation time 184154560 ps
CPU time 5.89 seconds
Started Aug 10 06:30:17 PM PDT 24
Finished Aug 10 06:30:23 PM PDT 24
Peak memory 218916 kb
Host smart-01fe2f34-30e5-4a58-9d1e-da6c4e3d10f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015630513 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.kmac_test_vectors_kmac.1015630513 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_kmac_xof.1860179270
Short name T617
Test name
Test status
Simulation time 212176035 ps
CPU time 5.31 seconds
Started Aug 10 06:30:19 PM PDT 24
Finished Aug 10 06:30:24 PM PDT 24
Peak memory 219776 kb
Host smart-13900284-240e-45df-b4fb-717a6b071c24
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860179270 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.kmac_test_vectors_kmac_xof.1860179270 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_224.1324456755
Short name T550
Test name
Test status
Simulation time 20782854795 ps
CPU time 2175.66 seconds
Started Aug 10 06:30:17 PM PDT 24
Finished Aug 10 07:06:33 PM PDT 24
Peak memory 1202108 kb
Host smart-86e60181-4209-4afd-9cad-51c9f2384d6b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1324456755 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.1324456755 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_256.2819385173
Short name T353
Test name
Test status
Simulation time 100532294904 ps
CPU time 3510.44 seconds
Started Aug 10 06:30:18 PM PDT 24
Finished Aug 10 07:28:49 PM PDT 24
Peak memory 3041528 kb
Host smart-0cc872b1-f9c7-4382-be8a-59748b46955e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2819385173 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.2819385173 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_384.1116123717
Short name T828
Test name
Test status
Simulation time 15496363970 ps
CPU time 1673.64 seconds
Started Aug 10 06:30:18 PM PDT 24
Finished Aug 10 06:58:12 PM PDT 24
Peak memory 925968 kb
Host smart-f22212d4-e991-4e91-ab39-d291d65d748a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1116123717 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.1116123717 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_512.329561429
Short name T153
Test name
Test status
Simulation time 10718628988 ps
CPU time 1161.05 seconds
Started Aug 10 06:30:19 PM PDT 24
Finished Aug 10 06:49:40 PM PDT 24
Peak memory 695440 kb
Host smart-4e19d561-6831-49e3-b2ca-3e3ff292aefa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=329561429 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.329561429 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_shake_256.1665448300
Short name T903
Test name
Test status
Simulation time 1248402202447 ps
CPU time 9268.17 seconds
Started Aug 10 06:30:18 PM PDT 24
Finished Aug 10 09:04:47 PM PDT 24
Peak memory 6383128 kb
Host smart-72854838-ba16-4c13-879b-a174c67448a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1665448300 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.1665448300 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/40.kmac_alert_test.1564191066
Short name T862
Test name
Test status
Simulation time 20845104 ps
CPU time 0.9 seconds
Started Aug 10 06:51:36 PM PDT 24
Finished Aug 10 06:51:37 PM PDT 24
Peak memory 218560 kb
Host smart-28cb4eb3-b946-4eae-a8be-35f934c86047
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564191066 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.1564191066 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_alert_test/latest

Test location /workspace/coverage/default/40.kmac_app.3211927693
Short name T873
Test name
Test status
Simulation time 3804508555 ps
CPU time 101.62 seconds
Started Aug 10 06:51:06 PM PDT 24
Finished Aug 10 06:52:47 PM PDT 24
Peak memory 257100 kb
Host smart-8ad7e091-bd6a-4ba7-a37a-09f0f16cf984
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211927693 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.3211927693 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/40.kmac_app/latest

Test location /workspace/coverage/default/40.kmac_burst_write.4222175769
Short name T882
Test name
Test status
Simulation time 10768714299 ps
CPU time 622.25 seconds
Started Aug 10 06:50:58 PM PDT 24
Finished Aug 10 07:01:20 PM PDT 24
Peak memory 236772 kb
Host smart-d435220e-ba63-47f3-8ebd-cc4c3b5d8038
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222175769 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.422217576
9 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_burst_write/latest

Test location /workspace/coverage/default/40.kmac_entropy_refresh.2068114050
Short name T496
Test name
Test status
Simulation time 33273074146 ps
CPU time 317.08 seconds
Started Aug 10 06:51:20 PM PDT 24
Finished Aug 10 06:56:37 PM PDT 24
Peak memory 422556 kb
Host smart-ae537419-75a0-430d-bd8a-cc6248f85a6d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068114050 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.2
068114050 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/40.kmac_error.1838785705
Short name T507
Test name
Test status
Simulation time 21711738306 ps
CPU time 454.93 seconds
Started Aug 10 06:51:37 PM PDT 24
Finished Aug 10 06:59:12 PM PDT 24
Peak memory 391656 kb
Host smart-dbffe183-c4c5-4ec7-87f3-0ab2e8fa9626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838785705 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.1838785705 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_error/latest

Test location /workspace/coverage/default/40.kmac_key_error.2344607190
Short name T900
Test name
Test status
Simulation time 2928755515 ps
CPU time 5.11 seconds
Started Aug 10 06:51:30 PM PDT 24
Finished Aug 10 06:51:35 PM PDT 24
Peak memory 226800 kb
Host smart-4378c00e-426e-4846-af80-c606e1ad23ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344607190 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.2344607190 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_key_error/latest

Test location /workspace/coverage/default/40.kmac_lc_escalation.2732436042
Short name T74
Test name
Test status
Simulation time 713848853 ps
CPU time 48.68 seconds
Started Aug 10 06:51:29 PM PDT 24
Finished Aug 10 06:52:18 PM PDT 24
Peak memory 247780 kb
Host smart-0ee2aae9-66b3-43ba-9520-2609c380e70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732436042 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.2732436042 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/40.kmac_lc_escalation/latest

Test location /workspace/coverage/default/40.kmac_long_msg_and_output.3918832075
Short name T941
Test name
Test status
Simulation time 259674047680 ps
CPU time 4606.17 seconds
Started Aug 10 06:50:57 PM PDT 24
Finished Aug 10 08:07:44 PM PDT 24
Peak memory 3627944 kb
Host smart-51d5be65-f246-424f-999e-ba2f0d42675f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918832075 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_a
nd_output.3918832075 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/40.kmac_sideload.1858755374
Short name T485
Test name
Test status
Simulation time 7082233214 ps
CPU time 246.18 seconds
Started Aug 10 06:50:56 PM PDT 24
Finished Aug 10 06:55:03 PM PDT 24
Peak memory 411692 kb
Host smart-b94d80de-e1d6-401c-b27c-57fca9cde6fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858755374 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.1858755374 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_sideload/latest

Test location /workspace/coverage/default/40.kmac_smoke.3900694785
Short name T495
Test name
Test status
Simulation time 22238409735 ps
CPU time 50.69 seconds
Started Aug 10 06:51:00 PM PDT 24
Finished Aug 10 06:51:50 PM PDT 24
Peak memory 227012 kb
Host smart-4613d126-ef28-48f8-b369-77fd30ab848d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900694785 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.3900694785 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_smoke/latest

Test location /workspace/coverage/default/40.kmac_stress_all.4239689103
Short name T515
Test name
Test status
Simulation time 105197985238 ps
CPU time 751.39 seconds
Started Aug 10 06:51:36 PM PDT 24
Finished Aug 10 07:04:08 PM PDT 24
Peak memory 484632 kb
Host smart-ba57c0b0-a678-4851-8572-b0dcd5dcea94
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4239689103 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.4239689103 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_stress_all/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_kmac.822590265
Short name T376
Test name
Test status
Simulation time 376346699 ps
CPU time 5.6 seconds
Started Aug 10 06:51:07 PM PDT 24
Finished Aug 10 06:51:13 PM PDT 24
Peak memory 219764 kb
Host smart-1e18eaf3-1f5a-4ca9-99bc-d2ccf75872e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822590265 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.kmac_test_vectors_kmac.822590265 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_kmac_xof.228220559
Short name T795
Test name
Test status
Simulation time 264563675 ps
CPU time 6.61 seconds
Started Aug 10 06:51:07 PM PDT 24
Finished Aug 10 06:51:14 PM PDT 24
Peak memory 219880 kb
Host smart-64c642f0-e5fc-4fb9-b9c4-c0d117de0f68
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228220559 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.kmac_test_vectors_kmac_xof.228220559 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_224.4158714979
Short name T838
Test name
Test status
Simulation time 21966910255 ps
CPU time 2327.47 seconds
Started Aug 10 06:50:59 PM PDT 24
Finished Aug 10 07:29:47 PM PDT 24
Peak memory 1210324 kb
Host smart-f21bf18a-0ea3-4c0a-8ad1-4e6d740c1d60
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4158714979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_224.4158714979 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_256.1054522011
Short name T454
Test name
Test status
Simulation time 91092286734 ps
CPU time 3666.05 seconds
Started Aug 10 06:50:57 PM PDT 24
Finished Aug 10 07:52:04 PM PDT 24
Peak memory 3020524 kb
Host smart-47a3574c-c087-4d76-ac0a-91c87bb24c82
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1054522011 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_256.1054522011 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_384.213146200
Short name T696
Test name
Test status
Simulation time 77016628225 ps
CPU time 1664.67 seconds
Started Aug 10 06:50:59 PM PDT 24
Finished Aug 10 07:18:44 PM PDT 24
Peak memory 952800 kb
Host smart-63a585dd-7be1-479c-8c82-5acc15b06dc9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=213146200 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_384.213146200 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_512.2776288943
Short name T210
Test name
Test status
Simulation time 329175891218 ps
CPU time 1638.54 seconds
Started Aug 10 06:51:07 PM PDT 24
Finished Aug 10 07:18:25 PM PDT 24
Peak memory 1710260 kb
Host smart-d1f674e8-7eb0-495d-aa9e-b4de05dad101
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2776288943 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_512.2776288943 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_shake_256.1909151458
Short name T850
Test name
Test status
Simulation time 59162691524 ps
CPU time 5560.56 seconds
Started Aug 10 06:51:08 PM PDT 24
Finished Aug 10 08:23:50 PM PDT 24
Peak memory 2229104 kb
Host smart-792a915b-3a59-46cd-80f2-0e745aabff6c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1909151458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_256.1909151458 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/41.kmac_alert_test.4110124897
Short name T934
Test name
Test status
Simulation time 21845911 ps
CPU time 0.89 seconds
Started Aug 10 06:52:01 PM PDT 24
Finished Aug 10 06:52:02 PM PDT 24
Peak memory 218528 kb
Host smart-f073fb78-1797-4bae-af8e-3b2ad1d7aead
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110124897 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.4110124897 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_alert_test/latest

Test location /workspace/coverage/default/41.kmac_app.2787470825
Short name T506
Test name
Test status
Simulation time 2922640798 ps
CPU time 67.72 seconds
Started Aug 10 06:51:39 PM PDT 24
Finished Aug 10 06:52:47 PM PDT 24
Peak memory 242988 kb
Host smart-f693c205-48f0-4364-a46c-a46a8de9b9e0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787470825 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.2787470825 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/41.kmac_app/latest

Test location /workspace/coverage/default/41.kmac_burst_write.2106594064
Short name T489
Test name
Test status
Simulation time 289143673 ps
CPU time 28.68 seconds
Started Aug 10 06:51:29 PM PDT 24
Finished Aug 10 06:51:58 PM PDT 24
Peak memory 226984 kb
Host smart-24914252-aecf-4d4a-90dc-8b2add31b3f5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106594064 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.210659406
4 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_burst_write/latest

Test location /workspace/coverage/default/41.kmac_entropy_refresh.1149650214
Short name T829
Test name
Test status
Simulation time 9179077299 ps
CPU time 137.7 seconds
Started Aug 10 06:51:50 PM PDT 24
Finished Aug 10 06:54:08 PM PDT 24
Peak memory 268536 kb
Host smart-14b2dacb-f7b8-4d8b-910a-67b2c7f34819
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149650214 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_entropy_refresh.1
149650214 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/41.kmac_error.3740764474
Short name T508
Test name
Test status
Simulation time 4495622442 ps
CPU time 157.05 seconds
Started Aug 10 06:51:50 PM PDT 24
Finished Aug 10 06:54:28 PM PDT 24
Peak memory 334640 kb
Host smart-c9cb582d-c072-49a9-a2c8-f2e043d9e296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740764474 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.3740764474 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_error/latest

Test location /workspace/coverage/default/41.kmac_key_error.4194583432
Short name T771
Test name
Test status
Simulation time 5608030044 ps
CPU time 9.55 seconds
Started Aug 10 06:51:50 PM PDT 24
Finished Aug 10 06:52:00 PM PDT 24
Peak memory 226752 kb
Host smart-515219e1-b43b-4d19-ad49-c740765f3c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194583432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.4194583432 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_key_error/latest

Test location /workspace/coverage/default/41.kmac_lc_escalation.3775351012
Short name T945
Test name
Test status
Simulation time 614823739 ps
CPU time 31.63 seconds
Started Aug 10 06:51:51 PM PDT 24
Finished Aug 10 06:52:23 PM PDT 24
Peak memory 243448 kb
Host smart-e1302d6d-b318-438a-b905-8bc189dca06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775351012 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.3775351012 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/41.kmac_lc_escalation/latest

Test location /workspace/coverage/default/41.kmac_long_msg_and_output.972434882
Short name T445
Test name
Test status
Simulation time 89019098922 ps
CPU time 912.69 seconds
Started Aug 10 06:51:37 PM PDT 24
Finished Aug 10 07:06:50 PM PDT 24
Peak memory 1207444 kb
Host smart-61437b5f-e65b-48c8-bb58-c7a8d22a66fd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972434882 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_an
d_output.972434882 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/41.kmac_sideload.3753615911
Short name T548
Test name
Test status
Simulation time 219352833 ps
CPU time 6.57 seconds
Started Aug 10 06:51:29 PM PDT 24
Finished Aug 10 06:51:35 PM PDT 24
Peak memory 223892 kb
Host smart-ed6d498f-58d8-463f-b607-efff5b76df35
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753615911 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.3753615911 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_sideload/latest

Test location /workspace/coverage/default/41.kmac_smoke.4127336220
Short name T320
Test name
Test status
Simulation time 11071895047 ps
CPU time 50.49 seconds
Started Aug 10 06:51:29 PM PDT 24
Finished Aug 10 06:52:19 PM PDT 24
Peak memory 224208 kb
Host smart-37e590b9-99ac-44c6-a69d-8ed79c980d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127336220 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.4127336220 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_smoke/latest

Test location /workspace/coverage/default/41.kmac_stress_all.120442113
Short name T951
Test name
Test status
Simulation time 67298850966 ps
CPU time 2794 seconds
Started Aug 10 06:51:49 PM PDT 24
Finished Aug 10 07:38:23 PM PDT 24
Peak memory 1269240 kb
Host smart-c08a2e27-0bbc-4c5b-833d-e66d9e38e5f3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=120442113 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.120442113 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_stress_all/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_kmac.1139739051
Short name T415
Test name
Test status
Simulation time 245094808 ps
CPU time 6.51 seconds
Started Aug 10 06:51:38 PM PDT 24
Finished Aug 10 06:51:45 PM PDT 24
Peak memory 219840 kb
Host smart-ff780c1f-81fd-48ab-98bc-f944a2d4fb0f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139739051 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.kmac_test_vectors_kmac.1139739051 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_kmac_xof.1230501190
Short name T698
Test name
Test status
Simulation time 418869437 ps
CPU time 6.73 seconds
Started Aug 10 06:51:40 PM PDT 24
Finished Aug 10 06:51:47 PM PDT 24
Peak memory 219764 kb
Host smart-7caf4bae-a532-4484-a712-d3a00fb3d177
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230501190 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.kmac_test_vectors_kmac_xof.1230501190 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_224.2397844830
Short name T438
Test name
Test status
Simulation time 409713127610 ps
CPU time 2159.39 seconds
Started Aug 10 06:51:30 PM PDT 24
Finished Aug 10 07:27:30 PM PDT 24
Peak memory 1196552 kb
Host smart-f6db5a09-1dbb-43d6-ac74-ed9ae21016e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2397844830 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_224.2397844830 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_256.3492293056
Short name T584
Test name
Test status
Simulation time 75678094993 ps
CPU time 2097.52 seconds
Started Aug 10 06:51:30 PM PDT 24
Finished Aug 10 07:26:27 PM PDT 24
Peak memory 1129952 kb
Host smart-82432da5-5cd1-4c9b-aee7-d991110fe344
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3492293056 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_256.3492293056 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_384.2943739509
Short name T886
Test name
Test status
Simulation time 220300276248 ps
CPU time 2732.33 seconds
Started Aug 10 06:51:38 PM PDT 24
Finished Aug 10 07:37:10 PM PDT 24
Peak memory 2402108 kb
Host smart-5ec71c64-f572-4d38-ba6d-2c0967571528
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2943739509 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_384.2943739509 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_512.2746900251
Short name T467
Test name
Test status
Simulation time 49243854648 ps
CPU time 1732.17 seconds
Started Aug 10 06:51:40 PM PDT 24
Finished Aug 10 07:20:32 PM PDT 24
Peak memory 1730332 kb
Host smart-cd6aa33d-529a-4254-b78c-8e62bccc5ecd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2746900251 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_512.2746900251 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_shake_256.2502572095
Short name T271
Test name
Test status
Simulation time 946211144585 ps
CPU time 9810.44 seconds
Started Aug 10 06:51:39 PM PDT 24
Finished Aug 10 09:35:11 PM PDT 24
Peak memory 6344776 kb
Host smart-ae5cda82-4458-490a-a769-23ba4e811797
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2502572095 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_256.2502572095 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/42.kmac_alert_test.2421321249
Short name T234
Test name
Test status
Simulation time 30378072 ps
CPU time 0.8 seconds
Started Aug 10 06:52:33 PM PDT 24
Finished Aug 10 06:52:34 PM PDT 24
Peak memory 218568 kb
Host smart-3b789f8b-c795-4920-b717-19e8798b6029
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421321249 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.2421321249 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_alert_test/latest

Test location /workspace/coverage/default/42.kmac_app.1245891633
Short name T988
Test name
Test status
Simulation time 14717401020 ps
CPU time 224.64 seconds
Started Aug 10 06:52:22 PM PDT 24
Finished Aug 10 06:56:07 PM PDT 24
Peak memory 302680 kb
Host smart-5f72546d-97f2-4d08-8a12-31c297de1def
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245891633 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.1245891633 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/42.kmac_app/latest

Test location /workspace/coverage/default/42.kmac_burst_write.2578422466
Short name T424
Test name
Test status
Simulation time 4676684269 ps
CPU time 216.9 seconds
Started Aug 10 06:52:13 PM PDT 24
Finished Aug 10 06:55:50 PM PDT 24
Peak memory 233668 kb
Host smart-46951c21-ee9e-4fb1-8d62-2e3904c8ee9a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578422466 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.257842246
6 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_burst_write/latest

Test location /workspace/coverage/default/42.kmac_entropy_refresh.55158642
Short name T488
Test name
Test status
Simulation time 72388914706 ps
CPU time 331.84 seconds
Started Aug 10 06:52:22 PM PDT 24
Finished Aug 10 06:57:54 PM PDT 24
Peak memory 449732 kb
Host smart-2a700946-c34b-4cdb-9275-140ebfeec7d6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55158642 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.551
58642 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/42.kmac_error.751694906
Short name T545
Test name
Test status
Simulation time 68700106739 ps
CPU time 499.28 seconds
Started Aug 10 06:52:34 PM PDT 24
Finished Aug 10 07:00:53 PM PDT 24
Peak memory 572656 kb
Host smart-26098a2a-35d4-4e0d-8724-9a38fe335f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751694906 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.751694906 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_error/latest

Test location /workspace/coverage/default/42.kmac_key_error.1859014894
Short name T842
Test name
Test status
Simulation time 7914302014 ps
CPU time 11.71 seconds
Started Aug 10 06:52:33 PM PDT 24
Finished Aug 10 06:52:44 PM PDT 24
Peak memory 226904 kb
Host smart-e0a75590-9ea0-41e1-bb23-35e5e829d6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859014894 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.1859014894 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_key_error/latest

Test location /workspace/coverage/default/42.kmac_lc_escalation.2229398290
Short name T11
Test name
Test status
Simulation time 176131262 ps
CPU time 1.36 seconds
Started Aug 10 06:52:33 PM PDT 24
Finished Aug 10 06:52:35 PM PDT 24
Peak memory 226784 kb
Host smart-87f2c156-8e9d-4643-93f3-00224b1345a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229398290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.2229398290 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/42.kmac_lc_escalation/latest

Test location /workspace/coverage/default/42.kmac_long_msg_and_output.47700273
Short name T287
Test name
Test status
Simulation time 15583802164 ps
CPU time 1869.65 seconds
Started Aug 10 06:52:00 PM PDT 24
Finished Aug 10 07:23:10 PM PDT 24
Peak memory 1109072 kb
Host smart-00fe52c4-8c95-4b4d-92ec-871c151fe916
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47700273 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and
_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_and
_output.47700273 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/42.kmac_sideload.2398620904
Short name T1039
Test name
Test status
Simulation time 2987228115 ps
CPU time 239.65 seconds
Started Aug 10 06:52:00 PM PDT 24
Finished Aug 10 06:56:00 PM PDT 24
Peak memory 308132 kb
Host smart-adea6f6a-1a71-4107-a3cb-e684e7887199
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398620904 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.2398620904 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_sideload/latest

Test location /workspace/coverage/default/42.kmac_smoke.1901191442
Short name T749
Test name
Test status
Simulation time 8127282883 ps
CPU time 39.11 seconds
Started Aug 10 06:52:01 PM PDT 24
Finished Aug 10 06:52:40 PM PDT 24
Peak memory 227036 kb
Host smart-c627c5dc-e4f7-4054-b123-c130d61613b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901191442 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.1901191442 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_smoke/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_kmac.160641689
Short name T959
Test name
Test status
Simulation time 117138710 ps
CPU time 5.47 seconds
Started Aug 10 06:52:22 PM PDT 24
Finished Aug 10 06:52:28 PM PDT 24
Peak memory 219844 kb
Host smart-347f92c4-8d19-4f26-b65a-74276e974058
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160641689 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.kmac_test_vectors_kmac.160641689 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_kmac_xof.649729728
Short name T20
Test name
Test status
Simulation time 244858727 ps
CPU time 6.46 seconds
Started Aug 10 06:52:22 PM PDT 24
Finished Aug 10 06:52:29 PM PDT 24
Peak memory 219832 kb
Host smart-2b68e7e8-6286-4008-ba10-75ac7419c761
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649729728 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 42.kmac_test_vectors_kmac_xof.649729728 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_224.3338341340
Short name T392
Test name
Test status
Simulation time 407452908410 ps
CPU time 3328.06 seconds
Started Aug 10 06:52:13 PM PDT 24
Finished Aug 10 07:47:41 PM PDT 24
Peak memory 3173452 kb
Host smart-fd2d3b2b-2e7a-49a6-9aa8-3f3629a26aa0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3338341340 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_224.3338341340 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_256.829116271
Short name T236
Test name
Test status
Simulation time 79281192605 ps
CPU time 2125.08 seconds
Started Aug 10 06:52:13 PM PDT 24
Finished Aug 10 07:27:39 PM PDT 24
Peak memory 1130244 kb
Host smart-ed087e2e-f8a8-44e2-9346-adeb36709ff5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=829116271 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_256.829116271 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_384.1383928012
Short name T722
Test name
Test status
Simulation time 14845656124 ps
CPU time 1610.2 seconds
Started Aug 10 06:52:11 PM PDT 24
Finished Aug 10 07:19:02 PM PDT 24
Peak memory 926984 kb
Host smart-06e29a4a-334f-4c77-a7f6-4a76aa36c4a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1383928012 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_384.1383928012 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_512.2618674479
Short name T249
Test name
Test status
Simulation time 12278018191 ps
CPU time 1192.8 seconds
Started Aug 10 06:52:22 PM PDT 24
Finished Aug 10 07:12:15 PM PDT 24
Peak memory 709660 kb
Host smart-1b5a467c-a8bc-440d-89a1-10d016602a9d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2618674479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_512.2618674479 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_shake_256.4005695149
Short name T755
Test name
Test status
Simulation time 196230394001 ps
CPU time 10023.4 seconds
Started Aug 10 06:52:23 PM PDT 24
Finished Aug 10 09:39:28 PM PDT 24
Peak memory 6348140 kb
Host smart-32ab42e2-7edd-4918-9825-f51610e1070a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4005695149 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_256.4005695149 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/43.kmac_alert_test.1693653220
Short name T560
Test name
Test status
Simulation time 28747383 ps
CPU time 0.83 seconds
Started Aug 10 06:53:11 PM PDT 24
Finished Aug 10 06:53:11 PM PDT 24
Peak memory 218568 kb
Host smart-f6d5f2e0-f9d0-4576-a9fc-fe965fdec3d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693653220 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.1693653220 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_alert_test/latest

Test location /workspace/coverage/default/43.kmac_app.2867857571
Short name T357
Test name
Test status
Simulation time 3431058739 ps
CPU time 108.93 seconds
Started Aug 10 06:53:01 PM PDT 24
Finished Aug 10 06:54:50 PM PDT 24
Peak memory 257592 kb
Host smart-c2deffc7-df9e-4659-ad68-2db828366f44
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867857571 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.2867857571 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/43.kmac_app/latest

Test location /workspace/coverage/default/43.kmac_burst_write.3552191576
Short name T813
Test name
Test status
Simulation time 14913510262 ps
CPU time 248.33 seconds
Started Aug 10 06:52:46 PM PDT 24
Finished Aug 10 06:56:54 PM PDT 24
Peak memory 232592 kb
Host smart-1d628fef-cfa7-4234-8809-50da7a488212
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552191576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.355219157
6 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_burst_write/latest

Test location /workspace/coverage/default/43.kmac_entropy_refresh.939560498
Short name T664
Test name
Test status
Simulation time 3653406857 ps
CPU time 126.06 seconds
Started Aug 10 06:53:00 PM PDT 24
Finished Aug 10 06:55:06 PM PDT 24
Peak memory 272332 kb
Host smart-b173fa68-ad15-4fed-ba5a-7796f5630ccc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939560498 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.93
9560498 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/43.kmac_key_error.3872946823
Short name T1047
Test name
Test status
Simulation time 12417182476 ps
CPU time 9.27 seconds
Started Aug 10 06:53:11 PM PDT 24
Finished Aug 10 06:53:20 PM PDT 24
Peak memory 226856 kb
Host smart-7dcc2dc4-3b56-4033-8d71-68e8376cf574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872946823 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.3872946823 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_key_error/latest

Test location /workspace/coverage/default/43.kmac_lc_escalation.2903841948
Short name T998
Test name
Test status
Simulation time 55897546 ps
CPU time 1.5 seconds
Started Aug 10 06:53:12 PM PDT 24
Finished Aug 10 06:53:14 PM PDT 24
Peak memory 226920 kb
Host smart-996d4141-b552-4de1-886d-00cd371b50ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903841948 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.2903841948 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/43.kmac_lc_escalation/latest

Test location /workspace/coverage/default/43.kmac_long_msg_and_output.2430131175
Short name T435
Test name
Test status
Simulation time 74256523354 ps
CPU time 4039.63 seconds
Started Aug 10 06:52:33 PM PDT 24
Finished Aug 10 07:59:53 PM PDT 24
Peak memory 3410576 kb
Host smart-21619310-8bbf-4997-9cd0-f1c9884fe861
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430131175 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_a
nd_output.2430131175 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/43.kmac_sideload.3138085556
Short name T610
Test name
Test status
Simulation time 4419856274 ps
CPU time 176.96 seconds
Started Aug 10 06:52:45 PM PDT 24
Finished Aug 10 06:55:42 PM PDT 24
Peak memory 342528 kb
Host smart-32604d18-ec64-4f71-bab4-296f64f9c5f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138085556 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.3138085556 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_sideload/latest

Test location /workspace/coverage/default/43.kmac_smoke.329937437
Short name T89
Test name
Test status
Simulation time 7948097145 ps
CPU time 39.01 seconds
Started Aug 10 06:52:33 PM PDT 24
Finished Aug 10 06:53:12 PM PDT 24
Peak memory 227036 kb
Host smart-c17dcbbf-ffae-4c5f-bb3b-9b45fb83ec32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329937437 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.329937437 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_smoke/latest

Test location /workspace/coverage/default/43.kmac_stress_all.869204052
Short name T712
Test name
Test status
Simulation time 33812605550 ps
CPU time 1389.48 seconds
Started Aug 10 06:53:10 PM PDT 24
Finished Aug 10 07:16:19 PM PDT 24
Peak memory 1158392 kb
Host smart-9044c962-85f9-43e1-95b6-ef71dc0ab033
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=869204052 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.869204052 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_stress_all/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_kmac.980345378
Short name T245
Test name
Test status
Simulation time 505647428 ps
CPU time 5.46 seconds
Started Aug 10 06:53:01 PM PDT 24
Finished Aug 10 06:53:06 PM PDT 24
Peak memory 218956 kb
Host smart-340488de-8b18-448b-850d-a6e903af39a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980345378 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.kmac_test_vectors_kmac.980345378 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_kmac_xof.3236990410
Short name T1033
Test name
Test status
Simulation time 592405383 ps
CPU time 6.09 seconds
Started Aug 10 06:53:01 PM PDT 24
Finished Aug 10 06:53:07 PM PDT 24
Peak memory 219804 kb
Host smart-91650c54-6ee4-4659-a280-bca468bd0a0b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236990410 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.kmac_test_vectors_kmac_xof.3236990410 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_224.3717720216
Short name T217
Test name
Test status
Simulation time 390696069364 ps
CPU time 3881.19 seconds
Started Aug 10 06:52:43 PM PDT 24
Finished Aug 10 07:57:25 PM PDT 24
Peak memory 3232716 kb
Host smart-6bdff6a8-e7f0-4c90-9de7-76f248fc0809
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3717720216 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_224.3717720216 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_256.626108216
Short name T1046
Test name
Test status
Simulation time 92924401409 ps
CPU time 3261.64 seconds
Started Aug 10 06:52:41 PM PDT 24
Finished Aug 10 07:47:04 PM PDT 24
Peak memory 3002936 kb
Host smart-2a0f1615-c755-42dd-868e-121b2e0ed241
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=626108216 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_256.626108216 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_384.3055819419
Short name T703
Test name
Test status
Simulation time 60371135078 ps
CPU time 2270.41 seconds
Started Aug 10 06:52:45 PM PDT 24
Finished Aug 10 07:30:36 PM PDT 24
Peak memory 2320024 kb
Host smart-3e3b0a87-f1b0-4ee2-bc42-943d3bfec6fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3055819419 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_384.3055819419 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_512.2761505665
Short name T718
Test name
Test status
Simulation time 44383723837 ps
CPU time 1729.94 seconds
Started Aug 10 06:52:42 PM PDT 24
Finished Aug 10 07:21:33 PM PDT 24
Peak memory 1749724 kb
Host smart-7a7d9912-4a28-4af7-9706-38b52ba84a3d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2761505665 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_512.2761505665 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_shake_128.398821725
Short name T808
Test name
Test status
Simulation time 369671319453 ps
CPU time 9378.69 seconds
Started Aug 10 06:52:51 PM PDT 24
Finished Aug 10 09:29:11 PM PDT 24
Peak memory 7834516 kb
Host smart-caa73eb6-3be5-4d60-af36-d89dc5c46fb5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=398821725 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_128.398821725 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_shake_256.2711438174
Short name T419
Test name
Test status
Simulation time 183979387956 ps
CPU time 9199.91 seconds
Started Aug 10 06:52:51 PM PDT 24
Finished Aug 10 09:26:13 PM PDT 24
Peak memory 6356732 kb
Host smart-dfe00584-0282-4a2b-8b33-a5ac72463956
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2711438174 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_256.2711438174 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/44.kmac_alert_test.2349250142
Short name T479
Test name
Test status
Simulation time 58161413 ps
CPU time 0.8 seconds
Started Aug 10 06:53:46 PM PDT 24
Finished Aug 10 06:53:47 PM PDT 24
Peak memory 218552 kb
Host smart-6421303c-dbd4-4a5d-be5b-c232883304bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349250142 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.2349250142 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_alert_test/latest

Test location /workspace/coverage/default/44.kmac_app.896150006
Short name T1000
Test name
Test status
Simulation time 2825100787 ps
CPU time 72.7 seconds
Started Aug 10 06:53:27 PM PDT 24
Finished Aug 10 06:54:40 PM PDT 24
Peak memory 264524 kb
Host smart-0548e201-578d-4124-a59a-eadf050df77a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896150006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.896150006 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/44.kmac_app/latest

Test location /workspace/coverage/default/44.kmac_burst_write.2746955825
Short name T1041
Test name
Test status
Simulation time 7590043646 ps
CPU time 207.38 seconds
Started Aug 10 06:53:20 PM PDT 24
Finished Aug 10 06:56:48 PM PDT 24
Peak memory 239660 kb
Host smart-3bf7a5b6-65a8-4df3-b140-5aa90bdf410e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746955825 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.274695582
5 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_burst_write/latest

Test location /workspace/coverage/default/44.kmac_entropy_refresh.934601795
Short name T819
Test name
Test status
Simulation time 17266181668 ps
CPU time 71.16 seconds
Started Aug 10 06:53:38 PM PDT 24
Finished Aug 10 06:54:50 PM PDT 24
Peak memory 271144 kb
Host smart-0ddf3b93-50ea-4c86-96c1-a86c149d1ca4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934601795 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.93
4601795 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/44.kmac_error.35951089
Short name T910
Test name
Test status
Simulation time 2831861441 ps
CPU time 59.89 seconds
Started Aug 10 06:53:38 PM PDT 24
Finished Aug 10 06:54:38 PM PDT 24
Peak memory 251628 kb
Host smart-1cd8d258-7ce6-4550-a5e4-fa0cc155469c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35951089 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_error.35951089 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_error/latest

Test location /workspace/coverage/default/44.kmac_lc_escalation.4058021993
Short name T920
Test name
Test status
Simulation time 40553315 ps
CPU time 1.27 seconds
Started Aug 10 06:53:46 PM PDT 24
Finished Aug 10 06:53:47 PM PDT 24
Peak memory 226936 kb
Host smart-c1f2581e-9af5-454b-95c5-c758287fc7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058021993 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.4058021993 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/44.kmac_lc_escalation/latest

Test location /workspace/coverage/default/44.kmac_long_msg_and_output.1772941292
Short name T459
Test name
Test status
Simulation time 92190633240 ps
CPU time 3518.43 seconds
Started Aug 10 06:53:11 PM PDT 24
Finished Aug 10 07:51:50 PM PDT 24
Peak memory 2994224 kb
Host smart-cf639964-6196-41a9-a148-1ca1de3d0e90
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772941292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_a
nd_output.1772941292 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/44.kmac_sideload.3023894108
Short name T317
Test name
Test status
Simulation time 6161146626 ps
CPU time 475.44 seconds
Started Aug 10 06:53:18 PM PDT 24
Finished Aug 10 07:01:13 PM PDT 24
Peak memory 392524 kb
Host smart-fb1b250d-22a8-48de-95ba-51ec006e3773
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023894108 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.3023894108 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_sideload/latest

Test location /workspace/coverage/default/44.kmac_smoke.3748390177
Short name T940
Test name
Test status
Simulation time 4854075257 ps
CPU time 38.64 seconds
Started Aug 10 06:53:09 PM PDT 24
Finished Aug 10 06:53:48 PM PDT 24
Peak memory 226892 kb
Host smart-3df4762c-b7db-4a37-b68b-9fb69689c991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748390177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.3748390177 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_smoke/latest

Test location /workspace/coverage/default/44.kmac_stress_all.1225568590
Short name T14
Test name
Test status
Simulation time 21216561768 ps
CPU time 1570.88 seconds
Started Aug 10 06:53:46 PM PDT 24
Finished Aug 10 07:19:57 PM PDT 24
Peak memory 715360 kb
Host smart-6aa5701f-16d4-43c2-871a-bde0c67fb3da
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1225568590 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all.1225568590 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_stress_all/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_kmac.4105820814
Short name T684
Test name
Test status
Simulation time 417945727 ps
CPU time 6.72 seconds
Started Aug 10 06:53:27 PM PDT 24
Finished Aug 10 06:53:34 PM PDT 24
Peak memory 218896 kb
Host smart-6a56428e-3c2f-4a08-8e3a-40aecc06984d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105820814 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.kmac_test_vectors_kmac.4105820814 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_kmac_xof.3109550286
Short name T272
Test name
Test status
Simulation time 230611307 ps
CPU time 5.89 seconds
Started Aug 10 06:53:28 PM PDT 24
Finished Aug 10 06:53:34 PM PDT 24
Peak memory 218852 kb
Host smart-9c30b892-af5f-41c4-b5e2-be577c06254b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109550286 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.kmac_test_vectors_kmac_xof.3109550286 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_224.375075189
Short name T793
Test name
Test status
Simulation time 124664760996 ps
CPU time 2087.85 seconds
Started Aug 10 06:53:20 PM PDT 24
Finished Aug 10 07:28:08 PM PDT 24
Peak memory 1165124 kb
Host smart-51300441-d7f7-4cb1-9d2d-bf8dbfad5e4c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=375075189 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_224.375075189 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_256.3039698263
Short name T531
Test name
Test status
Simulation time 80644014532 ps
CPU time 2166.19 seconds
Started Aug 10 06:53:19 PM PDT 24
Finished Aug 10 07:29:25 PM PDT 24
Peak memory 1151312 kb
Host smart-08041494-b646-48f7-80db-cca6dd9bb6e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3039698263 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_256.3039698263 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_384.3950268169
Short name T259
Test name
Test status
Simulation time 50784314662 ps
CPU time 1682.68 seconds
Started Aug 10 06:53:17 PM PDT 24
Finished Aug 10 07:21:20 PM PDT 24
Peak memory 918736 kb
Host smart-d28d1b3c-c00d-4a12-ba2a-f1bb17b3f7aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3950268169 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_384.3950268169 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_512.5780070
Short name T95
Test name
Test status
Simulation time 33532829975 ps
CPU time 1623 seconds
Started Aug 10 06:53:20 PM PDT 24
Finished Aug 10 07:20:23 PM PDT 24
Peak memory 1740404 kb
Host smart-e32f4816-8065-4cd0-99b1-973459a1235e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=5780070 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_512.5780070 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_shake_128.631009322
Short name T902
Test name
Test status
Simulation time 60334195069 ps
CPU time 6332.58 seconds
Started Aug 10 06:53:19 PM PDT 24
Finished Aug 10 08:38:52 PM PDT 24
Peak memory 2655760 kb
Host smart-64249da7-0d56-4373-bd89-8f069b271c31
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=631009322 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_shake_128.631009322 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_shake_256.2288868604
Short name T372
Test name
Test status
Simulation time 779635357525 ps
CPU time 10012.4 seconds
Started Aug 10 06:53:18 PM PDT 24
Finished Aug 10 09:40:11 PM PDT 24
Peak memory 6328960 kb
Host smart-aaca31f5-42cd-49b6-af17-5fad8a804666
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2288868604 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_shake_256.2288868604 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/45.kmac_alert_test.1070313761
Short name T635
Test name
Test status
Simulation time 31875514 ps
CPU time 0.87 seconds
Started Aug 10 06:54:30 PM PDT 24
Finished Aug 10 06:54:31 PM PDT 24
Peak memory 218548 kb
Host smart-22008c54-bbd4-4f8d-8c73-a8edc0b8682c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070313761 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.1070313761 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_alert_test/latest

Test location /workspace/coverage/default/45.kmac_app.438765790
Short name T8
Test name
Test status
Simulation time 96702883377 ps
CPU time 269.67 seconds
Started Aug 10 06:54:21 PM PDT 24
Finished Aug 10 06:58:51 PM PDT 24
Peak memory 414796 kb
Host smart-66c303eb-bd23-4f2a-b899-d1a6e68b6f09
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438765790 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.438765790 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/45.kmac_app/latest

Test location /workspace/coverage/default/45.kmac_burst_write.3044139039
Short name T705
Test name
Test status
Simulation time 5199116441 ps
CPU time 206.71 seconds
Started Aug 10 06:53:55 PM PDT 24
Finished Aug 10 06:57:22 PM PDT 24
Peak memory 240416 kb
Host smart-04322102-b9f3-4828-9484-ec4ba105a8ea
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044139039 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.304413903
9 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_burst_write/latest

Test location /workspace/coverage/default/45.kmac_entropy_refresh.1380758443
Short name T968
Test name
Test status
Simulation time 19823243963 ps
CPU time 220.56 seconds
Started Aug 10 06:54:22 PM PDT 24
Finished Aug 10 06:58:02 PM PDT 24
Peak memory 307256 kb
Host smart-f2dd9316-7667-4cb9-b47b-eb2bfaea641b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380758443 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_entropy_refresh.1
380758443 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/45.kmac_error.1211306716
Short name T740
Test name
Test status
Simulation time 29412946368 ps
CPU time 234.26 seconds
Started Aug 10 06:54:29 PM PDT 24
Finished Aug 10 06:58:23 PM PDT 24
Peak memory 412792 kb
Host smart-ab9fcc71-11f0-48e2-92f3-65b46f78b668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211306716 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.1211306716 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_error/latest

Test location /workspace/coverage/default/45.kmac_key_error.2330665889
Short name T675
Test name
Test status
Simulation time 966756691 ps
CPU time 1.9 seconds
Started Aug 10 06:54:29 PM PDT 24
Finished Aug 10 06:54:31 PM PDT 24
Peak memory 226624 kb
Host smart-1375c870-2500-4587-9b4a-ec0108af4bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330665889 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.2330665889 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_key_error/latest

Test location /workspace/coverage/default/45.kmac_lc_escalation.659513387
Short name T75
Test name
Test status
Simulation time 62168751 ps
CPU time 1.44 seconds
Started Aug 10 06:54:30 PM PDT 24
Finished Aug 10 06:54:31 PM PDT 24
Peak memory 227076 kb
Host smart-efc97b73-3ff9-4ae4-b384-a698a7357295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659513387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.659513387 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/45.kmac_lc_escalation/latest

Test location /workspace/coverage/default/45.kmac_long_msg_and_output.2865007788
Short name T434
Test name
Test status
Simulation time 316045538996 ps
CPU time 2808.51 seconds
Started Aug 10 06:53:53 PM PDT 24
Finished Aug 10 07:40:42 PM PDT 24
Peak memory 2631456 kb
Host smart-6debb3dd-5926-44c5-9da8-9e1ae7cb6390
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865007788 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_a
nd_output.2865007788 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/45.kmac_sideload.3247751915
Short name T593
Test name
Test status
Simulation time 4594422373 ps
CPU time 377.49 seconds
Started Aug 10 06:53:55 PM PDT 24
Finished Aug 10 07:00:12 PM PDT 24
Peak memory 348868 kb
Host smart-8d83528e-ba37-4190-a41b-ff69060c9436
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247751915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.3247751915 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_sideload/latest

Test location /workspace/coverage/default/45.kmac_smoke.445684125
Short name T687
Test name
Test status
Simulation time 17438416833 ps
CPU time 84.31 seconds
Started Aug 10 06:53:48 PM PDT 24
Finished Aug 10 06:55:12 PM PDT 24
Peak memory 228324 kb
Host smart-a7c4733a-40f9-4547-a22b-6e6465c0339c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445684125 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.445684125 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_smoke/latest

Test location /workspace/coverage/default/45.kmac_stress_all.1552992723
Short name T962
Test name
Test status
Simulation time 13497565732 ps
CPU time 476.26 seconds
Started Aug 10 06:54:30 PM PDT 24
Finished Aug 10 07:02:27 PM PDT 24
Peak memory 341796 kb
Host smart-43da7fcf-7969-4207-a92a-e374ab81b3ab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1552992723 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.1552992723 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_stress_all/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_kmac.1236863401
Short name T378
Test name
Test status
Simulation time 322251058 ps
CPU time 6.26 seconds
Started Aug 10 06:54:12 PM PDT 24
Finished Aug 10 06:54:19 PM PDT 24
Peak memory 219804 kb
Host smart-ef70e5ba-337c-4967-8b29-7e04db12bb6f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236863401 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.kmac_test_vectors_kmac.1236863401 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_kmac_xof.53560012
Short name T437
Test name
Test status
Simulation time 1514783006 ps
CPU time 5.06 seconds
Started Aug 10 06:54:13 PM PDT 24
Finished Aug 10 06:54:18 PM PDT 24
Peak memory 218896 kb
Host smart-6bc8b036-aec5-4ad7-a3da-35f3afa04681
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53560012 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 45.kmac_test_vectors_kmac_xof.53560012 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_224.942218889
Short name T41
Test name
Test status
Simulation time 149202630528 ps
CPU time 2336.29 seconds
Started Aug 10 06:53:55 PM PDT 24
Finished Aug 10 07:32:51 PM PDT 24
Peak memory 1236108 kb
Host smart-19efdfbd-b05a-4bd5-8af2-7ca641233889
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=942218889 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_224.942218889 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_256.2623814614
Short name T231
Test name
Test status
Simulation time 124497073407 ps
CPU time 3042.94 seconds
Started Aug 10 06:53:54 PM PDT 24
Finished Aug 10 07:44:38 PM PDT 24
Peak memory 3007508 kb
Host smart-277780e8-74a9-4edb-98ae-1ee6f6e44476
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2623814614 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_256.2623814614 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_384.745844282
Short name T576
Test name
Test status
Simulation time 47615205269 ps
CPU time 2183.14 seconds
Started Aug 10 06:54:03 PM PDT 24
Finished Aug 10 07:30:26 PM PDT 24
Peak memory 2400448 kb
Host smart-dc4f98e7-e1d0-4c83-803e-4849edb769f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=745844282 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_384.745844282 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_512.171400586
Short name T979
Test name
Test status
Simulation time 36386883102 ps
CPU time 1582.84 seconds
Started Aug 10 06:54:03 PM PDT 24
Finished Aug 10 07:20:26 PM PDT 24
Peak memory 1702904 kb
Host smart-a66d600c-2f49-4a58-9faf-a189f41cb79e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=171400586 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_512.171400586 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_shake_128.3430375275
Short name T285
Test name
Test status
Simulation time 989596580617 ps
CPU time 5912.08 seconds
Started Aug 10 06:54:04 PM PDT 24
Finished Aug 10 08:32:36 PM PDT 24
Peak memory 2664092 kb
Host smart-d20ea220-73b6-40a7-94c1-698685d4f2a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3430375275 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_shake_128.3430375275 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/46.kmac_alert_test.1895020316
Short name T401
Test name
Test status
Simulation time 49068239 ps
CPU time 0.86 seconds
Started Aug 10 06:55:12 PM PDT 24
Finished Aug 10 06:55:13 PM PDT 24
Peak memory 218424 kb
Host smart-3f23af82-1698-432c-986d-9e8871095575
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895020316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.1895020316 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_alert_test/latest

Test location /workspace/coverage/default/46.kmac_app.4215701210
Short name T956
Test name
Test status
Simulation time 12349135881 ps
CPU time 217.24 seconds
Started Aug 10 06:54:57 PM PDT 24
Finished Aug 10 06:58:35 PM PDT 24
Peak memory 300168 kb
Host smart-ef5cec3a-945b-4486-a7a3-a2a7f6aa1789
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215701210 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.4215701210 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/46.kmac_app/latest

Test location /workspace/coverage/default/46.kmac_burst_write.3983991987
Short name T614
Test name
Test status
Simulation time 12979254753 ps
CPU time 1161.55 seconds
Started Aug 10 06:54:37 PM PDT 24
Finished Aug 10 07:13:59 PM PDT 24
Peak memory 246096 kb
Host smart-a87f037a-9cd4-480f-bf37-073f4d3da293
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983991987 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.398399198
7 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_burst_write/latest

Test location /workspace/coverage/default/46.kmac_entropy_refresh.3403895835
Short name T939
Test name
Test status
Simulation time 17523765532 ps
CPU time 336.68 seconds
Started Aug 10 06:54:58 PM PDT 24
Finished Aug 10 07:00:34 PM PDT 24
Peak memory 336432 kb
Host smart-eda5dd98-3e84-4ecb-b8d1-2bde9e8014a6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403895835 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_entropy_refresh.3
403895835 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/46.kmac_error.1493613828
Short name T616
Test name
Test status
Simulation time 1413447805 ps
CPU time 113.26 seconds
Started Aug 10 06:55:06 PM PDT 24
Finished Aug 10 06:56:59 PM PDT 24
Peak memory 274680 kb
Host smart-800b6e30-0515-4345-a8b0-78bcbf2b3ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493613828 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.1493613828 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_error/latest

Test location /workspace/coverage/default/46.kmac_key_error.875484529
Short name T1055
Test name
Test status
Simulation time 2130680977 ps
CPU time 4.79 seconds
Started Aug 10 06:55:06 PM PDT 24
Finished Aug 10 06:55:11 PM PDT 24
Peak memory 226680 kb
Host smart-4b921713-8e44-401b-a2ee-8f2a38c5d989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875484529 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.875484529 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_key_error/latest

Test location /workspace/coverage/default/46.kmac_lc_escalation.2463760325
Short name T629
Test name
Test status
Simulation time 194745375 ps
CPU time 1.43 seconds
Started Aug 10 06:55:06 PM PDT 24
Finished Aug 10 06:55:08 PM PDT 24
Peak memory 227064 kb
Host smart-b36924c4-ebec-4c4d-b2ce-cacc814adeeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463760325 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.2463760325 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/46.kmac_lc_escalation/latest

Test location /workspace/coverage/default/46.kmac_long_msg_and_output.1653105039
Short name T385
Test name
Test status
Simulation time 70232667085 ps
CPU time 4453.29 seconds
Started Aug 10 06:54:29 PM PDT 24
Finished Aug 10 08:08:43 PM PDT 24
Peak memory 3431388 kb
Host smart-5e29231a-dd03-4940-a9c2-aab589bae2a3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653105039 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_a
nd_output.1653105039 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/46.kmac_sideload.2655736820
Short name T1009
Test name
Test status
Simulation time 8035808403 ps
CPU time 305.77 seconds
Started Aug 10 06:54:37 PM PDT 24
Finished Aug 10 06:59:42 PM PDT 24
Peak memory 450428 kb
Host smart-6a4b6b53-835a-45ad-8f9c-9062d43cffa3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655736820 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.2655736820 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_sideload/latest

Test location /workspace/coverage/default/46.kmac_smoke.1423072236
Short name T564
Test name
Test status
Simulation time 634450242 ps
CPU time 11.52 seconds
Started Aug 10 06:54:29 PM PDT 24
Finished Aug 10 06:54:41 PM PDT 24
Peak memory 222492 kb
Host smart-55d37367-e3d5-43c7-85c1-b6a5ba46abdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423072236 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.1423072236 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_smoke/latest

Test location /workspace/coverage/default/46.kmac_stress_all.1789166155
Short name T498
Test name
Test status
Simulation time 210526293 ps
CPU time 10.31 seconds
Started Aug 10 06:55:04 PM PDT 24
Finished Aug 10 06:55:14 PM PDT 24
Peak memory 240184 kb
Host smart-a09c9396-a00d-4bb5-9301-a8330addf023
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1789166155 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.1789166155 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_stress_all/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_kmac.2431916717
Short name T322
Test name
Test status
Simulation time 104228645 ps
CPU time 5.79 seconds
Started Aug 10 06:54:56 PM PDT 24
Finished Aug 10 06:55:01 PM PDT 24
Peak memory 218924 kb
Host smart-6596414d-f019-4a8d-bdef-91c7a584761b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431916717 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.kmac_test_vectors_kmac.2431916717 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_kmac_xof.2963677793
Short name T535
Test name
Test status
Simulation time 1039587981 ps
CPU time 5.88 seconds
Started Aug 10 06:54:57 PM PDT 24
Finished Aug 10 06:55:03 PM PDT 24
Peak memory 219800 kb
Host smart-801ce483-9ca3-41d5-855b-fced604a9658
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963677793 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.kmac_test_vectors_kmac_xof.2963677793 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_224.2888245373
Short name T1024
Test name
Test status
Simulation time 401838995607 ps
CPU time 3640.87 seconds
Started Aug 10 06:54:37 PM PDT 24
Finished Aug 10 07:55:19 PM PDT 24
Peak memory 3207032 kb
Host smart-a82f811d-3c6c-47bc-a6de-1ef695a1e025
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2888245373 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_224.2888245373 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_256.1588185389
Short name T528
Test name
Test status
Simulation time 243108562908 ps
CPU time 3215.63 seconds
Started Aug 10 06:54:39 PM PDT 24
Finished Aug 10 07:48:15 PM PDT 24
Peak memory 3000684 kb
Host smart-46c464d2-547c-4586-a548-006b17d108b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1588185389 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_256.1588185389 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_384.1769639070
Short name T656
Test name
Test status
Simulation time 785094268536 ps
CPU time 2662.05 seconds
Started Aug 10 06:54:48 PM PDT 24
Finished Aug 10 07:39:10 PM PDT 24
Peak memory 2394488 kb
Host smart-4e9b6133-9b35-4584-bd18-e8b71e091ec4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1769639070 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_384.1769639070 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_512.201930191
Short name T932
Test name
Test status
Simulation time 49725892230 ps
CPU time 1801.43 seconds
Started Aug 10 06:54:49 PM PDT 24
Finished Aug 10 07:24:50 PM PDT 24
Peak memory 1753788 kb
Host smart-c089ff0e-4309-4524-8441-ae7cf40c5349
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=201930191 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_512.201930191 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_shake_128.2822261942
Short name T799
Test name
Test status
Simulation time 287977324956 ps
CPU time 6101.73 seconds
Started Aug 10 06:54:50 PM PDT 24
Finished Aug 10 08:36:32 PM PDT 24
Peak memory 2636792 kb
Host smart-8d27ecb4-4219-428b-aa92-b4c36725f51e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2822261942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_128.2822261942 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_shake_256.2778316886
Short name T993
Test name
Test status
Simulation time 311955036455 ps
CPU time 5373.7 seconds
Started Aug 10 06:54:57 PM PDT 24
Finished Aug 10 08:24:31 PM PDT 24
Peak memory 2230168 kb
Host smart-f5577fc4-e0fc-49eb-bb8a-eeea462a9eae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2778316886 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_256.2778316886 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/47.kmac_alert_test.3775877872
Short name T273
Test name
Test status
Simulation time 53933589 ps
CPU time 0.84 seconds
Started Aug 10 06:55:46 PM PDT 24
Finished Aug 10 06:55:47 PM PDT 24
Peak memory 218560 kb
Host smart-a95b72f9-9d5e-4cf0-a8fc-f05bc963b571
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775877872 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.3775877872 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_alert_test/latest

Test location /workspace/coverage/default/47.kmac_app.3239403750
Short name T132
Test name
Test status
Simulation time 41636785136 ps
CPU time 246.5 seconds
Started Aug 10 06:55:34 PM PDT 24
Finished Aug 10 06:59:40 PM PDT 24
Peak memory 406900 kb
Host smart-108de0b2-1da5-4473-aef5-7e5cc9a5f748
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239403750 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.3239403750 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/47.kmac_app/latest

Test location /workspace/coverage/default/47.kmac_burst_write.891124556
Short name T165
Test name
Test status
Simulation time 9210452899 ps
CPU time 122.34 seconds
Started Aug 10 06:55:23 PM PDT 24
Finished Aug 10 06:57:25 PM PDT 24
Peak memory 228900 kb
Host smart-2121ff04-c982-4772-8f63-e971d76c599c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891124556 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.891124556
+enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_burst_write/latest

Test location /workspace/coverage/default/47.kmac_entropy_refresh.2084467088
Short name T1026
Test name
Test status
Simulation time 5752749859 ps
CPU time 150.79 seconds
Started Aug 10 06:55:33 PM PDT 24
Finished Aug 10 06:58:04 PM PDT 24
Peak memory 330452 kb
Host smart-0252da3c-8d4f-4902-be8c-e8ffe804b640
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084467088 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.2
084467088 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/47.kmac_error.3507129175
Short name T179
Test name
Test status
Simulation time 9237665517 ps
CPU time 298.15 seconds
Started Aug 10 06:55:35 PM PDT 24
Finished Aug 10 07:00:33 PM PDT 24
Peak memory 341420 kb
Host smart-af37b00c-78fc-4f89-af20-d853170a57c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507129175 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.3507129175 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_error/latest

Test location /workspace/coverage/default/47.kmac_key_error.1948117157
Short name T4
Test name
Test status
Simulation time 396209915 ps
CPU time 1.46 seconds
Started Aug 10 06:55:45 PM PDT 24
Finished Aug 10 06:55:47 PM PDT 24
Peak memory 226680 kb
Host smart-cabc7d4a-c484-4993-8992-277c60abfd31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948117157 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.1948117157 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_key_error/latest

Test location /workspace/coverage/default/47.kmac_lc_escalation.1664284424
Short name T119
Test name
Test status
Simulation time 152308133 ps
CPU time 1.53 seconds
Started Aug 10 06:55:46 PM PDT 24
Finished Aug 10 06:55:48 PM PDT 24
Peak memory 226876 kb
Host smart-093d0aa7-1232-4f8a-8c22-05465b4b5b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664284424 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.1664284424 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/47.kmac_lc_escalation/latest

Test location /workspace/coverage/default/47.kmac_long_msg_and_output.1234875587
Short name T232
Test name
Test status
Simulation time 78647758653 ps
CPU time 5297.42 seconds
Started Aug 10 06:55:15 PM PDT 24
Finished Aug 10 08:23:33 PM PDT 24
Peak memory 3821420 kb
Host smart-ad698ad4-d648-475d-92ce-0cde2e5bacf3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234875587 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_a
nd_output.1234875587 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/47.kmac_sideload.4228814109
Short name T670
Test name
Test status
Simulation time 5985349109 ps
CPU time 423.55 seconds
Started Aug 10 06:55:23 PM PDT 24
Finished Aug 10 07:02:27 PM PDT 24
Peak memory 382568 kb
Host smart-cadd3e93-6c5b-4070-85b9-29da0a4004f3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228814109 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.4228814109 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_sideload/latest

Test location /workspace/coverage/default/47.kmac_smoke.4248742094
Short name T844
Test name
Test status
Simulation time 5158459967 ps
CPU time 59.16 seconds
Started Aug 10 06:55:15 PM PDT 24
Finished Aug 10 06:56:14 PM PDT 24
Peak memory 224756 kb
Host smart-b9c6a069-7715-479d-985c-2f82482d9fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248742094 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.4248742094 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_smoke/latest

Test location /workspace/coverage/default/47.kmac_stress_all.2627855257
Short name T499
Test name
Test status
Simulation time 69358540549 ps
CPU time 493.68 seconds
Started Aug 10 06:55:46 PM PDT 24
Finished Aug 10 07:04:00 PM PDT 24
Peak memory 691988 kb
Host smart-d92f24bb-f8e8-4874-938e-d10feb962507
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2627855257 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.2627855257 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_stress_all/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_kmac.3096368262
Short name T587
Test name
Test status
Simulation time 436482568 ps
CPU time 5.89 seconds
Started Aug 10 06:55:35 PM PDT 24
Finished Aug 10 06:55:41 PM PDT 24
Peak memory 218940 kb
Host smart-5a126c22-4ac3-4d9b-8b1c-e156a733d4da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096368262 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.kmac_test_vectors_kmac.3096368262 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_kmac_xof.3476841565
Short name T895
Test name
Test status
Simulation time 266204370 ps
CPU time 6.61 seconds
Started Aug 10 06:55:35 PM PDT 24
Finished Aug 10 06:55:42 PM PDT 24
Peak memory 219780 kb
Host smart-9ba384df-3d62-45dc-9de1-0012b76294a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476841565 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.kmac_test_vectors_kmac_xof.3476841565 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_224.1038383665
Short name T267
Test name
Test status
Simulation time 20725917674 ps
CPU time 2133.02 seconds
Started Aug 10 06:55:23 PM PDT 24
Finished Aug 10 07:30:56 PM PDT 24
Peak memory 1179272 kb
Host smart-9a83b48e-468e-460b-b8ab-a5bf5c5861b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1038383665 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_224.1038383665 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_256.2243072024
Short name T406
Test name
Test status
Simulation time 148947883547 ps
CPU time 3392.64 seconds
Started Aug 10 06:55:23 PM PDT 24
Finished Aug 10 07:51:57 PM PDT 24
Peak memory 3121092 kb
Host smart-c1006d2b-d1da-49ef-ada7-811b152ab7a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2243072024 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_256.2243072024 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_384.2268139144
Short name T389
Test name
Test status
Simulation time 73099779847 ps
CPU time 2648.86 seconds
Started Aug 10 06:55:21 PM PDT 24
Finished Aug 10 07:39:30 PM PDT 24
Peak memory 2389224 kb
Host smart-0798d0c0-e687-4f2f-ad17-b6be2ed10019
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2268139144 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_384.2268139144 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_512.1355194836
Short name T288
Test name
Test status
Simulation time 81594157856 ps
CPU time 1404.9 seconds
Started Aug 10 06:55:24 PM PDT 24
Finished Aug 10 07:18:49 PM PDT 24
Peak memory 1686196 kb
Host smart-af7ed250-b654-41d1-9ec4-8e924832586c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1355194836 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_512.1355194836 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_shake_256.2784487474
Short name T163
Test name
Test status
Simulation time 307899363346 ps
CPU time 5223.77 seconds
Started Aug 10 06:55:33 PM PDT 24
Finished Aug 10 08:22:38 PM PDT 24
Peak memory 2201196 kb
Host smart-315728ba-080d-4558-81f6-dce722a6f4d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2784487474 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_shake_256.2784487474 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/48.kmac_alert_test.737424119
Short name T619
Test name
Test status
Simulation time 42584645 ps
CPU time 0.8 seconds
Started Aug 10 06:56:24 PM PDT 24
Finished Aug 10 06:56:25 PM PDT 24
Peak memory 218552 kb
Host smart-ca1759dd-67e9-4864-85b6-a3488c6782c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737424119 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.737424119 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/48.kmac_alert_test/latest

Test location /workspace/coverage/default/48.kmac_app.2541698758
Short name T609
Test name
Test status
Simulation time 17988860860 ps
CPU time 103.63 seconds
Started Aug 10 06:56:20 PM PDT 24
Finished Aug 10 06:58:04 PM PDT 24
Peak memory 303368 kb
Host smart-b0c4abd2-9fc8-4986-a17b-1ca97acbbeed
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541698758 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.2541698758 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/48.kmac_app/latest

Test location /workspace/coverage/default/48.kmac_burst_write.1277995934
Short name T92
Test name
Test status
Simulation time 10899531459 ps
CPU time 551.93 seconds
Started Aug 10 06:55:46 PM PDT 24
Finished Aug 10 07:04:58 PM PDT 24
Peak memory 241396 kb
Host smart-f0e49061-170a-47dd-a7d2-73ebc41f3fba
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277995934 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.127799593
4 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_burst_write/latest

Test location /workspace/coverage/default/48.kmac_entropy_refresh.1493164119
Short name T247
Test name
Test status
Simulation time 27009446365 ps
CPU time 381.05 seconds
Started Aug 10 06:56:20 PM PDT 24
Finished Aug 10 07:02:41 PM PDT 24
Peak memory 512168 kb
Host smart-a144fc40-5c60-431c-9a54-4f5d4871b803
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493164119 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.1
493164119 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/48.kmac_error.792533809
Short name T874
Test name
Test status
Simulation time 12905962747 ps
CPU time 362.7 seconds
Started Aug 10 06:56:15 PM PDT 24
Finished Aug 10 07:02:18 PM PDT 24
Peak memory 513612 kb
Host smart-e9f46c2b-6259-49e3-a8ac-ddb69c6302bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792533809 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.792533809 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_error/latest

Test location /workspace/coverage/default/48.kmac_key_error.3325486402
Short name T575
Test name
Test status
Simulation time 1295652311 ps
CPU time 3.39 seconds
Started Aug 10 06:56:16 PM PDT 24
Finished Aug 10 06:56:20 PM PDT 24
Peak memory 226736 kb
Host smart-6f5a387e-aab3-4235-a6b3-785b1c82c03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325486402 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.3325486402 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_key_error/latest

Test location /workspace/coverage/default/48.kmac_lc_escalation.509409317
Short name T78
Test name
Test status
Simulation time 67743741 ps
CPU time 1.33 seconds
Started Aug 10 06:56:22 PM PDT 24
Finished Aug 10 06:56:23 PM PDT 24
Peak memory 226936 kb
Host smart-340bb210-fcd3-43c7-a089-80f3bebcb079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509409317 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.509409317 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/48.kmac_lc_escalation/latest

Test location /workspace/coverage/default/48.kmac_long_msg_and_output.644739822
Short name T680
Test name
Test status
Simulation time 66275270128 ps
CPU time 1514.5 seconds
Started Aug 10 06:55:46 PM PDT 24
Finished Aug 10 07:21:01 PM PDT 24
Peak memory 1752572 kb
Host smart-7bebcfa4-78ef-465f-a15f-5ce5177ad773
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644739822 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_an
d_output.644739822 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/48.kmac_sideload.4040821777
Short name T726
Test name
Test status
Simulation time 8122862629 ps
CPU time 469.94 seconds
Started Aug 10 06:55:46 PM PDT 24
Finished Aug 10 07:03:36 PM PDT 24
Peak memory 376744 kb
Host smart-b8d6c6fe-9ca9-428b-bbcf-d686c05614de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040821777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.4040821777 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_sideload/latest

Test location /workspace/coverage/default/48.kmac_smoke.3867368883
Short name T70
Test name
Test status
Simulation time 1389421234 ps
CPU time 23.3 seconds
Started Aug 10 06:55:46 PM PDT 24
Finished Aug 10 06:56:09 PM PDT 24
Peak memory 227008 kb
Host smart-9deb7543-00f9-40fe-9eca-67f4420bd491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867368883 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.3867368883 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_smoke/latest

Test location /workspace/coverage/default/48.kmac_stress_all.883328643
Short name T61
Test name
Test status
Simulation time 85095546449 ps
CPU time 1358.68 seconds
Started Aug 10 06:56:15 PM PDT 24
Finished Aug 10 07:18:54 PM PDT 24
Peak memory 830992 kb
Host smart-3583e7b6-00b9-45b6-889b-dd7d606c02af
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=883328643 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.883328643 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_stress_all/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_kmac.898406408
Short name T568
Test name
Test status
Simulation time 130208302 ps
CPU time 6.78 seconds
Started Aug 10 06:56:06 PM PDT 24
Finished Aug 10 06:56:13 PM PDT 24
Peak memory 219700 kb
Host smart-3a945a85-4c0c-4904-ae37-f7ab13de7acb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898406408 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.kmac_test_vectors_kmac.898406408 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_kmac_xof.3635135670
Short name T451
Test name
Test status
Simulation time 902519264 ps
CPU time 6.29 seconds
Started Aug 10 06:56:06 PM PDT 24
Finished Aug 10 06:56:12 PM PDT 24
Peak memory 219848 kb
Host smart-befe2863-61d8-4a13-a96e-722b7547f49c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635135670 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.kmac_test_vectors_kmac_xof.3635135670 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_224.2938815114
Short name T522
Test name
Test status
Simulation time 93873768054 ps
CPU time 3231.25 seconds
Started Aug 10 06:55:58 PM PDT 24
Finished Aug 10 07:49:50 PM PDT 24
Peak memory 3230380 kb
Host smart-662d82cc-d276-4cac-a3e5-e90260032a1c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2938815114 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_224.2938815114 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_256.84098280
Short name T733
Test name
Test status
Simulation time 182793786844 ps
CPU time 2158.84 seconds
Started Aug 10 06:55:59 PM PDT 24
Finished Aug 10 07:31:58 PM PDT 24
Peak memory 1153232 kb
Host smart-a619e602-a936-4c61-9254-dda6b14bec88
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=84098280 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_256.84098280 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_384.3786834875
Short name T307
Test name
Test status
Simulation time 72724475641 ps
CPU time 2666.72 seconds
Started Aug 10 06:55:57 PM PDT 24
Finished Aug 10 07:40:24 PM PDT 24
Peak memory 2421108 kb
Host smart-2003383a-050e-485f-828b-05d6b1e1250b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3786834875 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_384.3786834875 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_512.3191209634
Short name T523
Test name
Test status
Simulation time 10633095292 ps
CPU time 1187.2 seconds
Started Aug 10 06:55:59 PM PDT 24
Finished Aug 10 07:15:47 PM PDT 24
Peak memory 706468 kb
Host smart-8e5b4303-d733-427c-8a19-41f33e5c8d10
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3191209634 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_512.3191209634 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_shake_128.904545589
Short name T728
Test name
Test status
Simulation time 122198180892 ps
CPU time 6784.81 seconds
Started Aug 10 06:55:58 PM PDT 24
Finished Aug 10 08:49:04 PM PDT 24
Peak memory 2684448 kb
Host smart-3b9d1627-85b4-4a92-a45a-97018d69c772
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=904545589 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_128.904545589 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_shake_256.2991485440
Short name T626
Test name
Test status
Simulation time 226181261944 ps
CPU time 10027.7 seconds
Started Aug 10 06:56:07 PM PDT 24
Finished Aug 10 09:43:16 PM PDT 24
Peak memory 6365824 kb
Host smart-d729e1d9-fcb7-441e-b39e-26a724bd7849
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2991485440 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_256.2991485440 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/49.kmac_alert_test.750380153
Short name T779
Test name
Test status
Simulation time 27206269 ps
CPU time 0.83 seconds
Started Aug 10 06:57:09 PM PDT 24
Finished Aug 10 06:57:10 PM PDT 24
Peak memory 218560 kb
Host smart-f89140fb-4870-41a3-8ee9-99dae6d5fcbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750380153 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.750380153 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/49.kmac_alert_test/latest

Test location /workspace/coverage/default/49.kmac_app.1854597355
Short name T798
Test name
Test status
Simulation time 192849485 ps
CPU time 9.5 seconds
Started Aug 10 06:56:57 PM PDT 24
Finished Aug 10 06:57:06 PM PDT 24
Peak memory 227404 kb
Host smart-f1e6d09a-d531-4f98-9e53-676a37091fe1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854597355 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.1854597355 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/49.kmac_app/latest

Test location /workspace/coverage/default/49.kmac_burst_write.48864808
Short name T380
Test name
Test status
Simulation time 16166502677 ps
CPU time 900.6 seconds
Started Aug 10 06:56:25 PM PDT 24
Finished Aug 10 07:11:25 PM PDT 24
Peak memory 251404 kb
Host smart-7e51b9a5-8f71-49b7-86b2-133bdbf733fd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48864808 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.48864808 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_burst_write/latest

Test location /workspace/coverage/default/49.kmac_entropy_refresh.2893081103
Short name T1040
Test name
Test status
Simulation time 67572937786 ps
CPU time 397.92 seconds
Started Aug 10 06:56:58 PM PDT 24
Finished Aug 10 07:03:36 PM PDT 24
Peak memory 457684 kb
Host smart-b2190827-f736-41a7-8dfe-8a139b538bbc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893081103 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.2
893081103 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/49.kmac_error.654656411
Short name T806
Test name
Test status
Simulation time 2562210220 ps
CPU time 22.71 seconds
Started Aug 10 06:56:58 PM PDT 24
Finished Aug 10 06:57:21 PM PDT 24
Peak memory 243408 kb
Host smart-816c05ab-0ce6-4d62-b86d-97952ad181dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654656411 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.654656411 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_error/latest

Test location /workspace/coverage/default/49.kmac_key_error.3623964606
Short name T928
Test name
Test status
Simulation time 3086942152 ps
CPU time 5.9 seconds
Started Aug 10 06:56:57 PM PDT 24
Finished Aug 10 06:57:03 PM PDT 24
Peak memory 226772 kb
Host smart-d010505a-95ca-4421-b8f9-cfba411bb830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623964606 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.3623964606 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_key_error/latest

Test location /workspace/coverage/default/49.kmac_lc_escalation.3977621225
Short name T28
Test name
Test status
Simulation time 96973837 ps
CPU time 1.2 seconds
Started Aug 10 06:57:09 PM PDT 24
Finished Aug 10 06:57:10 PM PDT 24
Peak memory 226872 kb
Host smart-c7876c53-e61b-421b-a129-d45c451d8203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977621225 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.3977621225 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/49.kmac_lc_escalation/latest

Test location /workspace/coverage/default/49.kmac_long_msg_and_output.2101376271
Short name T814
Test name
Test status
Simulation time 748167275944 ps
CPU time 1905.89 seconds
Started Aug 10 06:56:25 PM PDT 24
Finished Aug 10 07:28:11 PM PDT 24
Peak memory 1781744 kb
Host smart-bea9af8f-1d7d-4881-94c1-d2e7dae4226a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101376271 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_a
nd_output.2101376271 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/49.kmac_sideload.2235993827
Short name T825
Test name
Test status
Simulation time 10816062849 ps
CPU time 353.66 seconds
Started Aug 10 06:56:25 PM PDT 24
Finished Aug 10 07:02:18 PM PDT 24
Peak memory 483844 kb
Host smart-4f19b1fb-4b76-4e1d-87e3-a285781dcac1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235993827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.2235993827 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_sideload/latest

Test location /workspace/coverage/default/49.kmac_smoke.4165514598
Short name T863
Test name
Test status
Simulation time 3774126294 ps
CPU time 30.61 seconds
Started Aug 10 06:56:24 PM PDT 24
Finished Aug 10 06:56:55 PM PDT 24
Peak memory 227060 kb
Host smart-b698c6df-d3ab-41f3-aa25-ab8af02642af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165514598 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.4165514598 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_smoke/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_kmac.2161265513
Short name T621
Test name
Test status
Simulation time 285923315 ps
CPU time 6.66 seconds
Started Aug 10 06:56:44 PM PDT 24
Finished Aug 10 06:56:51 PM PDT 24
Peak memory 218940 kb
Host smart-fc387283-6d93-4174-ab30-dc20224117ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161265513 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.kmac_test_vectors_kmac.2161265513 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_kmac_xof.1522075920
Short name T745
Test name
Test status
Simulation time 938530574 ps
CPU time 6.81 seconds
Started Aug 10 06:56:57 PM PDT 24
Finished Aug 10 06:57:04 PM PDT 24
Peak memory 218824 kb
Host smart-f2e1bbb5-5031-4b3c-a76d-b1809016e4b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522075920 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.kmac_test_vectors_kmac_xof.1522075920 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_224.3354820612
Short name T316
Test name
Test status
Simulation time 203912299737 ps
CPU time 2174.17 seconds
Started Aug 10 06:56:25 PM PDT 24
Finished Aug 10 07:32:40 PM PDT 24
Peak memory 1196852 kb
Host smart-941845f0-bc02-4ed2-9177-7fca4160a5b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3354820612 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_224.3354820612 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_256.1093247548
Short name T747
Test name
Test status
Simulation time 82314256096 ps
CPU time 2073.9 seconds
Started Aug 10 06:56:35 PM PDT 24
Finished Aug 10 07:31:10 PM PDT 24
Peak memory 1171744 kb
Host smart-7ffe4a13-2cae-46f7-b4d4-b274029d9806
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1093247548 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_256.1093247548 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_384.942391026
Short name T640
Test name
Test status
Simulation time 30536338448 ps
CPU time 1566.92 seconds
Started Aug 10 06:56:36 PM PDT 24
Finished Aug 10 07:22:43 PM PDT 24
Peak memory 913052 kb
Host smart-b885e5f2-a231-41d0-9076-2a9a89bf1cca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=942391026 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_384.942391026 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_512.4037578482
Short name T858
Test name
Test status
Simulation time 170981237607 ps
CPU time 1913.15 seconds
Started Aug 10 06:56:44 PM PDT 24
Finished Aug 10 07:28:38 PM PDT 24
Peak memory 1733884 kb
Host smart-cc281089-f813-4c4a-88d5-88f4d76d868e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4037578482 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_512.4037578482 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_shake_256.2336521908
Short name T884
Test name
Test status
Simulation time 218347832297 ps
CPU time 5547.96 seconds
Started Aug 10 06:56:44 PM PDT 24
Finished Aug 10 08:29:13 PM PDT 24
Peak memory 2221780 kb
Host smart-2dac65b9-3482-4d6b-9f69-511f4d32f678
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2336521908 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_256.2336521908 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/5.kmac_alert_test.1799388054
Short name T118
Test name
Test status
Simulation time 46811067 ps
CPU time 0.85 seconds
Started Aug 10 06:30:57 PM PDT 24
Finished Aug 10 06:30:58 PM PDT 24
Peak memory 218588 kb
Host smart-8e290956-d8ec-4243-8ba1-0a00afc9c036
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799388054 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.1799388054 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_alert_test/latest

Test location /workspace/coverage/default/5.kmac_app.3728432816
Short name T686
Test name
Test status
Simulation time 2609562165 ps
CPU time 47.39 seconds
Started Aug 10 06:30:40 PM PDT 24
Finished Aug 10 06:31:28 PM PDT 24
Peak memory 239420 kb
Host smart-77c63e9f-b426-4c8f-848e-5ac81060d5ba
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728432816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.3728432816 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/5.kmac_app/latest

Test location /workspace/coverage/default/5.kmac_app_with_partial_data.3620285743
Short name T985
Test name
Test status
Simulation time 10783079834 ps
CPU time 54.58 seconds
Started Aug 10 06:30:40 PM PDT 24
Finished Aug 10 06:31:34 PM PDT 24
Peak memory 259788 kb
Host smart-036dcef6-fe8e-40cc-ac2a-86aebb3fe35c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620285743 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_par
tial_data.3620285743 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/5.kmac_burst_write.3911600921
Short name T605
Test name
Test status
Simulation time 14739071376 ps
CPU time 1630.73 seconds
Started Aug 10 06:30:40 PM PDT 24
Finished Aug 10 06:57:51 PM PDT 24
Peak memory 248788 kb
Host smart-4bd8876f-9f78-45fc-b468-581a0ea4e280
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911600921 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.3911600921
+enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_burst_write/latest

Test location /workspace/coverage/default/5.kmac_edn_timeout_error.16646334
Short name T947
Test name
Test status
Simulation time 15213451 ps
CPU time 0.82 seconds
Started Aug 10 06:30:42 PM PDT 24
Finished Aug 10 06:30:43 PM PDT 24
Peak memory 218480 kb
Host smart-54acebb5-37d0-4b1d-87c5-df8833b0a586
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=16646334 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.16646334 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/5.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_mode_error.1274141828
Short name T35
Test name
Test status
Simulation time 106073151 ps
CPU time 1.1 seconds
Started Aug 10 06:30:48 PM PDT 24
Finished Aug 10 06:30:49 PM PDT 24
Peak memory 222236 kb
Host smart-d49a12a9-30cd-4e49-9dd7-79ba9dcc4bc6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1274141828 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.1274141828 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_ready_error.3650156408
Short name T9
Test name
Test status
Simulation time 3583133043 ps
CPU time 29.27 seconds
Started Aug 10 06:30:48 PM PDT 24
Finished Aug 10 06:31:17 PM PDT 24
Peak memory 226940 kb
Host smart-49be541a-26a7-48b0-a54d-b9fdf7e25616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650156408 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.3650156408 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_refresh.447496356
Short name T58
Test name
Test status
Simulation time 12707819560 ps
CPU time 268.81 seconds
Started Aug 10 06:30:42 PM PDT 24
Finished Aug 10 06:35:11 PM PDT 24
Peak memory 309668 kb
Host smart-00861d7d-c8ed-424e-9c79-9837ad04ff7d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447496356 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.447
496356 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/5.kmac_error.1504769755
Short name T937
Test name
Test status
Simulation time 3991371474 ps
CPU time 209.51 seconds
Started Aug 10 06:30:39 PM PDT 24
Finished Aug 10 06:34:09 PM PDT 24
Peak memory 308904 kb
Host smart-81c4551d-dd3b-41f6-84ae-a41c216bdf59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504769755 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.1504769755 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_error/latest

Test location /workspace/coverage/default/5.kmac_key_error.2870924151
Short name T852
Test name
Test status
Simulation time 541349453 ps
CPU time 4.47 seconds
Started Aug 10 06:30:41 PM PDT 24
Finished Aug 10 06:30:46 PM PDT 24
Peak memory 226660 kb
Host smart-efe4d532-8e51-43d1-8edb-d09a7274a4c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870924151 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.2870924151 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_key_error/latest

Test location /workspace/coverage/default/5.kmac_lc_escalation.3978426105
Short name T264
Test name
Test status
Simulation time 32768417 ps
CPU time 1.42 seconds
Started Aug 10 06:30:49 PM PDT 24
Finished Aug 10 06:30:50 PM PDT 24
Peak memory 226836 kb
Host smart-42971b12-9b3c-4e77-b32b-d3b077fbf8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978426105 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.3978426105 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/5.kmac_lc_escalation/latest

Test location /workspace/coverage/default/5.kmac_long_msg_and_output.2341216086
Short name T1008
Test name
Test status
Simulation time 529738711282 ps
CPU time 3844.07 seconds
Started Aug 10 06:30:30 PM PDT 24
Finished Aug 10 07:34:35 PM PDT 24
Peak memory 2948468 kb
Host smart-186d9d2e-69d2-48f2-bd28-53f0dcb04611
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341216086 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_an
d_output.2341216086 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/5.kmac_mubi.938432293
Short name T382
Test name
Test status
Simulation time 4891802779 ps
CPU time 126.04 seconds
Started Aug 10 06:30:41 PM PDT 24
Finished Aug 10 06:32:48 PM PDT 24
Peak memory 319176 kb
Host smart-64e01944-1554-41b3-a0a1-2a30cea1f317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938432293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.938432293 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_mubi/latest

Test location /workspace/coverage/default/5.kmac_sideload.486693203
Short name T462
Test name
Test status
Simulation time 4075869113 ps
CPU time 162.48 seconds
Started Aug 10 06:30:40 PM PDT 24
Finished Aug 10 06:33:22 PM PDT 24
Peak memory 281208 kb
Host smart-04da1bfc-7dfa-4b62-ad75-5509f46fad71
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486693203 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.486693203 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_sideload/latest

Test location /workspace/coverage/default/5.kmac_smoke.3408573277
Short name T805
Test name
Test status
Simulation time 3309332298 ps
CPU time 59.02 seconds
Started Aug 10 06:30:30 PM PDT 24
Finished Aug 10 06:31:29 PM PDT 24
Peak memory 222936 kb
Host smart-13f8c956-20f0-444b-948b-e5b993fc2609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408573277 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.3408573277 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_smoke/latest

Test location /workspace/coverage/default/5.kmac_stress_all.714978789
Short name T601
Test name
Test status
Simulation time 40452701808 ps
CPU time 1651.02 seconds
Started Aug 10 06:30:58 PM PDT 24
Finished Aug 10 06:58:29 PM PDT 24
Peak memory 649028 kb
Host smart-b050c9ba-5eba-4016-bbfe-19dad2a0614d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=714978789 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.714978789 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_stress_all/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_kmac.793534416
Short name T642
Test name
Test status
Simulation time 480299967 ps
CPU time 7.03 seconds
Started Aug 10 06:30:40 PM PDT 24
Finished Aug 10 06:30:47 PM PDT 24
Peak memory 219776 kb
Host smart-6620f6b0-4129-4cfc-8e3d-d54ff194874f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793534416 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.kmac_test_vectors_kmac.793534416 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_kmac_xof.2328578372
Short name T673
Test name
Test status
Simulation time 813172730 ps
CPU time 6.07 seconds
Started Aug 10 06:30:41 PM PDT 24
Finished Aug 10 06:30:47 PM PDT 24
Peak memory 218936 kb
Host smart-a0360de5-1b11-4815-b479-25a3c6245ac0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328578372 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.kmac_test_vectors_kmac_xof.2328578372 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_224.4214189517
Short name T238
Test name
Test status
Simulation time 83828578922 ps
CPU time 2286.47 seconds
Started Aug 10 06:30:40 PM PDT 24
Finished Aug 10 07:08:47 PM PDT 24
Peak memory 1183260 kb
Host smart-f4c92074-6afe-4744-aa1c-ebd502c908b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4214189517 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_224.4214189517 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_256.642563291
Short name T986
Test name
Test status
Simulation time 384636218319 ps
CPU time 2181.03 seconds
Started Aug 10 06:30:40 PM PDT 24
Finished Aug 10 07:07:01 PM PDT 24
Peak memory 1145792 kb
Host smart-f37ebb8e-9bd3-4189-b9f5-a0a48078f74d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=642563291 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_256.642563291 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_384.227864322
Short name T851
Test name
Test status
Simulation time 219134426505 ps
CPU time 2077.99 seconds
Started Aug 10 06:30:40 PM PDT 24
Finished Aug 10 07:05:19 PM PDT 24
Peak memory 2416352 kb
Host smart-f4b1aa62-6935-4d40-bc83-70f9fb98ae25
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=227864322 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_384.227864322 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_512.2923859199
Short name T763
Test name
Test status
Simulation time 48393470489 ps
CPU time 1341.99 seconds
Started Aug 10 06:30:42 PM PDT 24
Finished Aug 10 06:53:04 PM PDT 24
Peak memory 696128 kb
Host smart-0aaea76f-7673-49e2-bdc8-fb71b17c8a42
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2923859199 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_512.2923859199 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_shake_256.4160176062
Short name T309
Test name
Test status
Simulation time 208241409299 ps
CPU time 5472.2 seconds
Started Aug 10 06:30:41 PM PDT 24
Finished Aug 10 08:01:54 PM PDT 24
Peak memory 2211744 kb
Host smart-bda176ac-4c90-4798-a86e-48104372598a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4160176062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_shake_256.4160176062 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/6.kmac_alert_test.3020600760
Short name T304
Test name
Test status
Simulation time 15792761 ps
CPU time 0.87 seconds
Started Aug 10 06:31:24 PM PDT 24
Finished Aug 10 06:31:25 PM PDT 24
Peak memory 218528 kb
Host smart-f5b78d78-564a-4d86-b819-ce99ad004d98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020600760 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.3020600760 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_alert_test/latest

Test location /workspace/coverage/default/6.kmac_app.3220374919
Short name T800
Test name
Test status
Simulation time 17008915949 ps
CPU time 263.23 seconds
Started Aug 10 06:31:06 PM PDT 24
Finished Aug 10 06:35:29 PM PDT 24
Peak memory 305324 kb
Host smart-bae718f3-c517-4042-b2a5-048efe441b47
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220374919 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.3220374919 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/6.kmac_app/latest

Test location /workspace/coverage/default/6.kmac_app_with_partial_data.3387318716
Short name T948
Test name
Test status
Simulation time 50458801687 ps
CPU time 161.44 seconds
Started Aug 10 06:31:06 PM PDT 24
Finished Aug 10 06:33:48 PM PDT 24
Peak memory 334252 kb
Host smart-46fcfc76-9d0b-4976-bd4b-043296a92a01
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387318716 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_par
tial_data.3387318716 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/6.kmac_burst_write.3741466898
Short name T781
Test name
Test status
Simulation time 9198753187 ps
CPU time 503.05 seconds
Started Aug 10 06:31:06 PM PDT 24
Finished Aug 10 06:39:29 PM PDT 24
Peak memory 243416 kb
Host smart-4cb4d281-1999-4020-b0a0-73e5455b6ec7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741466898 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.3741466898
+enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_burst_write/latest

Test location /workspace/coverage/default/6.kmac_edn_timeout_error.1496417940
Short name T657
Test name
Test status
Simulation time 19713782 ps
CPU time 1.01 seconds
Started Aug 10 06:31:15 PM PDT 24
Finished Aug 10 06:31:16 PM PDT 24
Peak memory 218616 kb
Host smart-df4ebdf7-c351-484b-9c89-a60de0908843
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1496417940 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.1496417940 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_mode_error.1823823110
Short name T837
Test name
Test status
Simulation time 29762040 ps
CPU time 1.08 seconds
Started Aug 10 06:31:15 PM PDT 24
Finished Aug 10 06:31:16 PM PDT 24
Peak memory 218460 kb
Host smart-5b8ecb24-3179-47be-ac0a-bc647fbb5f77
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1823823110 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.1823823110 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_ready_error.2857691982
Short name T615
Test name
Test status
Simulation time 13732216964 ps
CPU time 39.07 seconds
Started Aug 10 06:31:16 PM PDT 24
Finished Aug 10 06:31:55 PM PDT 24
Peak memory 222652 kb
Host smart-3017829a-ccdc-40a3-8b9e-917f90e4db95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857691982 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.2857691982 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_refresh.1256121400
Short name T775
Test name
Test status
Simulation time 25108034157 ps
CPU time 280.12 seconds
Started Aug 10 06:31:06 PM PDT 24
Finished Aug 10 06:35:46 PM PDT 24
Peak memory 321104 kb
Host smart-cc87481d-6f78-4cd7-8661-d0ca28af86e0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256121400 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.12
56121400 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/6.kmac_error.448298688
Short name T413
Test name
Test status
Simulation time 8210988166 ps
CPU time 331.98 seconds
Started Aug 10 06:31:15 PM PDT 24
Finished Aug 10 06:36:47 PM PDT 24
Peak memory 343136 kb
Host smart-7927f30a-7b1b-4ea2-a384-6018bde0c7df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448298688 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.448298688 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_error/latest

Test location /workspace/coverage/default/6.kmac_key_error.202768410
Short name T122
Test name
Test status
Simulation time 497334013 ps
CPU time 1.5 seconds
Started Aug 10 06:31:15 PM PDT 24
Finished Aug 10 06:31:17 PM PDT 24
Peak memory 226420 kb
Host smart-8ea1c9f9-b4bd-422d-bab0-36fa95048775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202768410 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.202768410 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_key_error/latest

Test location /workspace/coverage/default/6.kmac_long_msg_and_output.1239450896
Short name T773
Test name
Test status
Simulation time 15895466528 ps
CPU time 679.03 seconds
Started Aug 10 06:31:07 PM PDT 24
Finished Aug 10 06:42:26 PM PDT 24
Peak memory 958532 kb
Host smart-11016191-4e96-4941-976e-5b9d4611c60a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239450896 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_an
d_output.1239450896 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/6.kmac_mubi.1933551614
Short name T338
Test name
Test status
Simulation time 18765518261 ps
CPU time 313.23 seconds
Started Aug 10 06:31:16 PM PDT 24
Finished Aug 10 06:36:29 PM PDT 24
Peak memory 317848 kb
Host smart-340ff54f-064b-443b-94e7-e86a0527796b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933551614 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.1933551614 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_mubi/latest

Test location /workspace/coverage/default/6.kmac_sideload.1407572049
Short name T676
Test name
Test status
Simulation time 8132913778 ps
CPU time 162.48 seconds
Started Aug 10 06:31:07 PM PDT 24
Finished Aug 10 06:33:49 PM PDT 24
Peak memory 347100 kb
Host smart-7c4d359c-7576-47cc-a6a0-39f028bd8d0f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407572049 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.1407572049 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_sideload/latest

Test location /workspace/coverage/default/6.kmac_smoke.1456438603
Short name T973
Test name
Test status
Simulation time 436814870 ps
CPU time 3.71 seconds
Started Aug 10 06:30:59 PM PDT 24
Finished Aug 10 06:31:02 PM PDT 24
Peak memory 223332 kb
Host smart-7568e655-d02f-421b-906c-f85d9d0b95b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456438603 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.1456438603 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_smoke/latest

Test location /workspace/coverage/default/6.kmac_stress_all.817810096
Short name T909
Test name
Test status
Simulation time 22468750853 ps
CPU time 427.85 seconds
Started Aug 10 06:31:25 PM PDT 24
Finished Aug 10 06:38:33 PM PDT 24
Peak memory 267984 kb
Host smart-f016a6e9-f4f7-453a-afdc-4e460429cda4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=817810096 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.817810096 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_stress_all/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_kmac.3662819380
Short name T318
Test name
Test status
Simulation time 286631881 ps
CPU time 6.73 seconds
Started Aug 10 06:31:08 PM PDT 24
Finished Aug 10 06:31:15 PM PDT 24
Peak memory 219060 kb
Host smart-bd530f8a-04f0-4ea0-9bc4-c0daa632d8a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662819380 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.kmac_test_vectors_kmac.3662819380 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_kmac_xof.531857801
Short name T216
Test name
Test status
Simulation time 1051895252 ps
CPU time 6.42 seconds
Started Aug 10 06:31:07 PM PDT 24
Finished Aug 10 06:31:13 PM PDT 24
Peak memory 218892 kb
Host smart-b735bbdd-3eb8-44f8-b400-f3882df44339
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531857801 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.kmac_test_vectors_kmac_xof.531857801 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_224.3651242440
Short name T923
Test name
Test status
Simulation time 298185341153 ps
CPU time 3431.52 seconds
Started Aug 10 06:31:06 PM PDT 24
Finished Aug 10 07:28:18 PM PDT 24
Peak memory 3184200 kb
Host smart-1b57e517-6ec9-49fd-839b-125e1de76665
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3651242440 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_224.3651242440 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_256.1947406791
Short name T494
Test name
Test status
Simulation time 39710326512 ps
CPU time 1943.73 seconds
Started Aug 10 06:31:06 PM PDT 24
Finished Aug 10 07:03:30 PM PDT 24
Peak memory 1153120 kb
Host smart-df2b19b0-b2a5-4094-b80b-995f12771e32
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1947406791 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_256.1947406791 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_384.3706451516
Short name T276
Test name
Test status
Simulation time 146098308510 ps
CPU time 2591.13 seconds
Started Aug 10 06:31:08 PM PDT 24
Finished Aug 10 07:14:19 PM PDT 24
Peak memory 2378260 kb
Host smart-44a2f9db-4187-43bd-b45e-d181d65f4e3b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3706451516 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_384.3706451516 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_512.2043222307
Short name T55
Test name
Test status
Simulation time 41312803906 ps
CPU time 1175.01 seconds
Started Aug 10 06:31:06 PM PDT 24
Finished Aug 10 06:50:41 PM PDT 24
Peak memory 697492 kb
Host smart-1b3cbedb-13b3-4e13-87e1-841a0bed8b97
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2043222307 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_512.2043222307 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_shake_256.3733298318
Short name T671
Test name
Test status
Simulation time 89293431329 ps
CPU time 5059.12 seconds
Started Aug 10 06:31:08 PM PDT 24
Finished Aug 10 07:55:28 PM PDT 24
Peak memory 2200840 kb
Host smart-53e74324-c0f5-4638-81e1-b350cc613a9c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3733298318 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_256.3733298318 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/7.kmac_alert_test.1648376192
Short name T845
Test name
Test status
Simulation time 16081700 ps
CPU time 0.84 seconds
Started Aug 10 06:31:47 PM PDT 24
Finished Aug 10 06:31:48 PM PDT 24
Peak memory 218600 kb
Host smart-9be3ed14-39b0-45db-9ed7-bef37220962d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648376192 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.1648376192 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_alert_test/latest

Test location /workspace/coverage/default/7.kmac_app.375173719
Short name T583
Test name
Test status
Simulation time 2544072772 ps
CPU time 123.13 seconds
Started Aug 10 06:31:33 PM PDT 24
Finished Aug 10 06:33:36 PM PDT 24
Peak memory 270840 kb
Host smart-9d7c4d7a-97b9-4a8a-bac8-6a851d324324
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375173719 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.375173719 +enable_masking=1
+sw_key_masked=0
Directory /workspace/7.kmac_app/latest

Test location /workspace/coverage/default/7.kmac_app_with_partial_data.2770975329
Short name T976
Test name
Test status
Simulation time 60283138927 ps
CPU time 415.95 seconds
Started Aug 10 06:31:33 PM PDT 24
Finished Aug 10 06:38:29 PM PDT 24
Peak memory 515888 kb
Host smart-cbe46ae2-9fac-445d-b6ae-bfa8409450a0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770975329 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_par
tial_data.2770975329 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/7.kmac_burst_write.322694088
Short name T589
Test name
Test status
Simulation time 33977071804 ps
CPU time 1590.67 seconds
Started Aug 10 06:31:25 PM PDT 24
Finished Aug 10 06:57:56 PM PDT 24
Peak memory 266776 kb
Host smart-855c75cb-8308-42f7-81ac-b6390f9fe2e3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322694088 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.322694088 +
enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_burst_write/latest

Test location /workspace/coverage/default/7.kmac_edn_timeout_error.1780304990
Short name T820
Test name
Test status
Simulation time 50612336 ps
CPU time 0.89 seconds
Started Aug 10 06:31:46 PM PDT 24
Finished Aug 10 06:31:47 PM PDT 24
Peak memory 218456 kb
Host smart-80c4f083-7e64-4010-bc01-dbd8022092d7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1780304990 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.1780304990 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_mode_error.4120515572
Short name T815
Test name
Test status
Simulation time 4953990086 ps
CPU time 37.57 seconds
Started Aug 10 06:31:46 PM PDT 24
Finished Aug 10 06:32:23 PM PDT 24
Peak memory 234884 kb
Host smart-33e080da-6149-4f41-bf93-1beb821e476d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4120515572 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.4120515572 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_ready_error.2324986365
Short name T187
Test name
Test status
Simulation time 1807082775 ps
CPU time 7.5 seconds
Started Aug 10 06:31:47 PM PDT 24
Finished Aug 10 06:31:54 PM PDT 24
Peak memory 221904 kb
Host smart-69e45e52-297e-4d74-83c3-2b36cb6c7b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324986365 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.2324986365 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_refresh.3373452668
Short name T893
Test name
Test status
Simulation time 23486770466 ps
CPU time 118.58 seconds
Started Aug 10 06:31:35 PM PDT 24
Finished Aug 10 06:33:34 PM PDT 24
Peak memory 290856 kb
Host smart-2159f9d0-6f0b-4cfa-b3bc-70f9fe4e1270
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373452668 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.33
73452668 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/7.kmac_error.1617655308
Short name T484
Test name
Test status
Simulation time 6349743316 ps
CPU time 388.64 seconds
Started Aug 10 06:31:33 PM PDT 24
Finished Aug 10 06:38:02 PM PDT 24
Peak memory 375636 kb
Host smart-405d36c3-ff6c-4c44-8ca6-57b6321abb1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617655308 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.1617655308 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_error/latest

Test location /workspace/coverage/default/7.kmac_key_error.3643536431
Short name T367
Test name
Test status
Simulation time 478168991 ps
CPU time 4.14 seconds
Started Aug 10 06:31:32 PM PDT 24
Finished Aug 10 06:31:37 PM PDT 24
Peak memory 226756 kb
Host smart-91d3a3c5-9d5d-4601-a9c8-51e5f197d237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643536431 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.3643536431 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_key_error/latest

Test location /workspace/coverage/default/7.kmac_lc_escalation.3851561737
Short name T478
Test name
Test status
Simulation time 92313638 ps
CPU time 1.31 seconds
Started Aug 10 06:31:46 PM PDT 24
Finished Aug 10 06:31:48 PM PDT 24
Peak memory 226916 kb
Host smart-0785db00-e5d6-4e23-b7f2-4e03e3b43b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851561737 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.3851561737 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/7.kmac_lc_escalation/latest

Test location /workspace/coverage/default/7.kmac_long_msg_and_output.2142155497
Short name T204
Test name
Test status
Simulation time 8079346231 ps
CPU time 144.76 seconds
Started Aug 10 06:31:25 PM PDT 24
Finished Aug 10 06:33:49 PM PDT 24
Peak memory 399804 kb
Host smart-8fa3cbfe-a213-447b-80b6-4fb3b6d1b779
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142155497 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_an
d_output.2142155497 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/7.kmac_mubi.2586333250
Short name T81
Test name
Test status
Simulation time 6913803884 ps
CPU time 230.41 seconds
Started Aug 10 06:31:33 PM PDT 24
Finished Aug 10 06:35:23 PM PDT 24
Peak memory 397724 kb
Host smart-8afd5215-0020-4634-a106-add7363d2bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586333250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.2586333250 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_mubi/latest

Test location /workspace/coverage/default/7.kmac_sideload.1124313280
Short name T246
Test name
Test status
Simulation time 1417659513 ps
CPU time 132.07 seconds
Started Aug 10 06:31:24 PM PDT 24
Finished Aug 10 06:33:36 PM PDT 24
Peak memory 265308 kb
Host smart-4e310e30-d5cd-4749-ae8a-187082e080fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124313280 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.1124313280 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_sideload/latest

Test location /workspace/coverage/default/7.kmac_smoke.3633699821
Short name T79
Test name
Test status
Simulation time 1520941008 ps
CPU time 12.61 seconds
Started Aug 10 06:31:24 PM PDT 24
Finished Aug 10 06:31:37 PM PDT 24
Peak memory 227008 kb
Host smart-c349216b-0058-4e32-a3a0-003c77f16e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633699821 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.3633699821 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_smoke/latest

Test location /workspace/coverage/default/7.kmac_stress_all.3986573632
Short name T872
Test name
Test status
Simulation time 224026321 ps
CPU time 4.89 seconds
Started Aug 10 06:31:47 PM PDT 24
Finished Aug 10 06:31:52 PM PDT 24
Peak memory 220856 kb
Host smart-2b119d5b-db0a-4c6e-806d-b2791dd59a9e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3986573632 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.3986573632 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_stress_all/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_kmac.2458735121
Short name T969
Test name
Test status
Simulation time 259847148 ps
CPU time 6.17 seconds
Started Aug 10 06:31:33 PM PDT 24
Finished Aug 10 06:31:39 PM PDT 24
Peak memory 220172 kb
Host smart-64916e7d-6ebf-43f1-98fa-2ce232b569d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458735121 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.kmac_test_vectors_kmac.2458735121 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_kmac_xof.2423056684
Short name T668
Test name
Test status
Simulation time 293406455 ps
CPU time 6.64 seconds
Started Aug 10 06:31:33 PM PDT 24
Finished Aug 10 06:31:40 PM PDT 24
Peak memory 218980 kb
Host smart-7ba6ba72-3d95-4069-a860-afb816404676
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423056684 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.kmac_test_vectors_kmac_xof.2423056684 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_224.2139821462
Short name T953
Test name
Test status
Simulation time 961566752925 ps
CPU time 3940.44 seconds
Started Aug 10 06:31:24 PM PDT 24
Finished Aug 10 07:37:05 PM PDT 24
Peak memory 3206236 kb
Host smart-404de628-0105-4909-bad0-f63711c55741
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2139821462 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_224.2139821462 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_256.3631976224
Short name T340
Test name
Test status
Simulation time 19410185967 ps
CPU time 2170.02 seconds
Started Aug 10 06:31:25 PM PDT 24
Finished Aug 10 07:07:35 PM PDT 24
Peak memory 1139224 kb
Host smart-2f1faa55-4efb-44d9-8f37-3a88135783d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3631976224 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_256.3631976224 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_384.760633429
Short name T283
Test name
Test status
Simulation time 15522466206 ps
CPU time 1688.91 seconds
Started Aug 10 06:31:25 PM PDT 24
Finished Aug 10 06:59:35 PM PDT 24
Peak memory 909012 kb
Host smart-022d760d-6741-44f5-a92b-36b482e14317
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=760633429 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_384.760633429 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_512.716416622
Short name T518
Test name
Test status
Simulation time 49902006879 ps
CPU time 1287.44 seconds
Started Aug 10 06:31:25 PM PDT 24
Finished Aug 10 06:52:52 PM PDT 24
Peak memory 713712 kb
Host smart-9cda74f3-6108-4eaf-a3db-073b809e747a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=716416622 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_512.716416622 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/8.kmac_alert_test.3567697192
Short name T324
Test name
Test status
Simulation time 17431658 ps
CPU time 0.83 seconds
Started Aug 10 06:32:12 PM PDT 24
Finished Aug 10 06:32:13 PM PDT 24
Peak memory 218528 kb
Host smart-2eef024a-152c-4c42-9f05-6f8b0e07f00d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567697192 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.3567697192 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_alert_test/latest

Test location /workspace/coverage/default/8.kmac_app.2294640399
Short name T840
Test name
Test status
Simulation time 37769971594 ps
CPU time 250.15 seconds
Started Aug 10 06:31:56 PM PDT 24
Finished Aug 10 06:36:06 PM PDT 24
Peak memory 394152 kb
Host smart-742f809e-1c1f-4778-aefc-5c56024358ba
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294640399 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.2294640399 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/8.kmac_app/latest

Test location /workspace/coverage/default/8.kmac_app_with_partial_data.3766227638
Short name T284
Test name
Test status
Simulation time 25576743835 ps
CPU time 282.17 seconds
Started Aug 10 06:31:56 PM PDT 24
Finished Aug 10 06:36:38 PM PDT 24
Peak memory 307324 kb
Host smart-4cb75eea-ca6e-40f1-937e-445412e18744
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766227638 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_par
tial_data.3766227638 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/8.kmac_burst_write.4127611535
Short name T752
Test name
Test status
Simulation time 40790249721 ps
CPU time 1712.63 seconds
Started Aug 10 06:31:57 PM PDT 24
Finished Aug 10 07:00:29 PM PDT 24
Peak memory 269988 kb
Host smart-0f09a586-2d94-4a86-a5b4-30bd7cfb4826
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127611535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.4127611535
+enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_burst_write/latest

Test location /workspace/coverage/default/8.kmac_edn_timeout_error.4133574599
Short name T821
Test name
Test status
Simulation time 1107057259 ps
CPU time 25.88 seconds
Started Aug 10 06:32:07 PM PDT 24
Finished Aug 10 06:32:33 PM PDT 24
Peak memory 241112 kb
Host smart-b4cd52b1-09ec-4130-9fe4-e7ada95ca2ba
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4133574599 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.4133574599 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_mode_error.810059605
Short name T581
Test name
Test status
Simulation time 48748878 ps
CPU time 0.99 seconds
Started Aug 10 06:32:07 PM PDT 24
Finished Aug 10 06:32:08 PM PDT 24
Peak memory 222044 kb
Host smart-555653f5-8e3e-4a47-a28b-f352fe74f980
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=810059605 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.810059605 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_ready_error.959713506
Short name T866
Test name
Test status
Simulation time 2863723436 ps
CPU time 22.13 seconds
Started Aug 10 06:32:03 PM PDT 24
Finished Aug 10 06:32:25 PM PDT 24
Peak memory 227140 kb
Host smart-334e9780-e424-4c7e-ae7d-d070261073a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959713506 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.959713506 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_refresh.1874682567
Short name T114
Test name
Test status
Simulation time 85116733508 ps
CPU time 425.23 seconds
Started Aug 10 06:31:58 PM PDT 24
Finished Aug 10 06:39:03 PM PDT 24
Peak memory 543444 kb
Host smart-d165b8d6-dbd2-42f4-a29f-ea6c9d831339
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874682567 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.18
74682567 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/8.kmac_error.542924606
Short name T483
Test name
Test status
Simulation time 14825205297 ps
CPU time 324.13 seconds
Started Aug 10 06:32:04 PM PDT 24
Finished Aug 10 06:37:29 PM PDT 24
Peak memory 330332 kb
Host smart-1d890126-0197-4df4-a32f-3184900027b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542924606 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.542924606 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_error/latest

Test location /workspace/coverage/default/8.kmac_key_error.1328243113
Short name T121
Test name
Test status
Simulation time 5561494387 ps
CPU time 12.7 seconds
Started Aug 10 06:32:04 PM PDT 24
Finished Aug 10 06:32:17 PM PDT 24
Peak memory 226800 kb
Host smart-bf78b97d-9576-487e-881e-1c8f578a8d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328243113 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.1328243113 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_key_error/latest

Test location /workspace/coverage/default/8.kmac_lc_escalation.3260261327
Short name T27
Test name
Test status
Simulation time 44717469 ps
CPU time 1.35 seconds
Started Aug 10 06:32:04 PM PDT 24
Finished Aug 10 06:32:05 PM PDT 24
Peak memory 226944 kb
Host smart-36890927-abb0-4307-a2d0-8fa41abbf12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260261327 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.3260261327 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/8.kmac_lc_escalation/latest

Test location /workspace/coverage/default/8.kmac_long_msg_and_output.1205256010
Short name T363
Test name
Test status
Simulation time 40597241946 ps
CPU time 1072 seconds
Started Aug 10 06:31:57 PM PDT 24
Finished Aug 10 06:49:50 PM PDT 24
Peak memory 765108 kb
Host smart-fdeae9e8-ec22-48e2-9b44-6edd3fd28ba8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205256010 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_an
d_output.1205256010 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/8.kmac_mubi.623487817
Short name T751
Test name
Test status
Simulation time 5223140415 ps
CPU time 172.36 seconds
Started Aug 10 06:31:56 PM PDT 24
Finished Aug 10 06:34:48 PM PDT 24
Peak memory 356212 kb
Host smart-f05cb024-417b-485c-845e-6f334e645496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623487817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.623487817 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_mubi/latest

Test location /workspace/coverage/default/8.kmac_sideload.3014322383
Short name T1050
Test name
Test status
Simulation time 11596284324 ps
CPU time 335.28 seconds
Started Aug 10 06:31:57 PM PDT 24
Finished Aug 10 06:37:32 PM PDT 24
Peak memory 493968 kb
Host smart-c23a57ed-8ee4-45e3-b99b-6d945536d25c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014322383 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.3014322383 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_sideload/latest

Test location /workspace/coverage/default/8.kmac_smoke.3645227694
Short name T878
Test name
Test status
Simulation time 1997818703 ps
CPU time 13.24 seconds
Started Aug 10 06:31:56 PM PDT 24
Finished Aug 10 06:32:09 PM PDT 24
Peak memory 226892 kb
Host smart-ebe382af-624a-45f8-a813-6bcdfcb3558d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645227694 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.3645227694 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_smoke/latest

Test location /workspace/coverage/default/8.kmac_stress_all.4282495834
Short name T466
Test name
Test status
Simulation time 11222224857 ps
CPU time 239.9 seconds
Started Aug 10 06:32:07 PM PDT 24
Finished Aug 10 06:36:07 PM PDT 24
Peak memory 272268 kb
Host smart-44dc2e76-33f3-4d01-975d-90602a3808ba
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4282495834 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.4282495834 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_stress_all/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_kmac.3577242311
Short name T270
Test name
Test status
Simulation time 112636220 ps
CPU time 5.73 seconds
Started Aug 10 06:31:56 PM PDT 24
Finished Aug 10 06:32:02 PM PDT 24
Peak memory 218880 kb
Host smart-d3e43d8d-9542-4186-b219-7ea888eb6115
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577242311 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.kmac_test_vectors_kmac.3577242311 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_kmac_xof.1306407921
Short name T44
Test name
Test status
Simulation time 136958696 ps
CPU time 5.92 seconds
Started Aug 10 06:31:58 PM PDT 24
Finished Aug 10 06:32:04 PM PDT 24
Peak memory 217912 kb
Host smart-26d3f59a-ad9c-4f5f-93eb-0ca61f724473
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306407921 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.kmac_test_vectors_kmac_xof.1306407921 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_224.2502463618
Short name T738
Test name
Test status
Simulation time 1605957859439 ps
CPU time 4122.74 seconds
Started Aug 10 06:31:55 PM PDT 24
Finished Aug 10 07:40:39 PM PDT 24
Peak memory 3207944 kb
Host smart-617b4ba1-ebea-4696-bfc1-b591f9b59ce2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2502463618 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_224.2502463618 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_256.3185656286
Short name T461
Test name
Test status
Simulation time 202782835353 ps
CPU time 3342.69 seconds
Started Aug 10 06:31:57 PM PDT 24
Finished Aug 10 07:27:40 PM PDT 24
Peak memory 3064792 kb
Host smart-c000e870-783d-40be-9c01-6cac9a48e22c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3185656286 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_256.3185656286 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_384.428279813
Short name T731
Test name
Test status
Simulation time 69135412775 ps
CPU time 2372.34 seconds
Started Aug 10 06:31:57 PM PDT 24
Finished Aug 10 07:11:30 PM PDT 24
Peak memory 2325636 kb
Host smart-42cbaeda-1d32-4297-9110-3375a9b22934
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=428279813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_384.428279813 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_512.727635207
Short name T645
Test name
Test status
Simulation time 10421521670 ps
CPU time 1175.51 seconds
Started Aug 10 06:31:55 PM PDT 24
Finished Aug 10 06:51:31 PM PDT 24
Peak memory 714144 kb
Host smart-3ced8a01-130b-4ebb-96ad-0c728c941d9f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=727635207 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_512.727635207 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_shake_256.282619551
Short name T219
Test name
Test status
Simulation time 61461711240 ps
CPU time 5254.93 seconds
Started Aug 10 06:31:56 PM PDT 24
Finished Aug 10 07:59:31 PM PDT 24
Peak memory 2240652 kb
Host smart-30979bff-3dcd-4274-ac63-56a2fc26120c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=282619551 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_256.282619551 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/9.kmac_alert_test.402246944
Short name T504
Test name
Test status
Simulation time 80736600 ps
CPU time 0.84 seconds
Started Aug 10 06:32:34 PM PDT 24
Finished Aug 10 06:32:35 PM PDT 24
Peak memory 218592 kb
Host smart-2d722a3f-45c8-4023-b926-368758d56ac3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402246944 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.402246944 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/9.kmac_alert_test/latest

Test location /workspace/coverage/default/9.kmac_app.4103406565
Short name T585
Test name
Test status
Simulation time 8468647338 ps
CPU time 150.67 seconds
Started Aug 10 06:32:18 PM PDT 24
Finished Aug 10 06:34:49 PM PDT 24
Peak memory 266468 kb
Host smart-71a63b61-dc9f-4781-aa34-f1410f22abfe
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103406565 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.4103406565 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/9.kmac_app/latest

Test location /workspace/coverage/default/9.kmac_app_with_partial_data.2503432109
Short name T1004
Test name
Test status
Simulation time 41105287467 ps
CPU time 170.19 seconds
Started Aug 10 06:32:26 PM PDT 24
Finished Aug 10 06:35:16 PM PDT 24
Peak memory 349624 kb
Host smart-4955a9d5-59e7-41d8-a343-695a1c9657e4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503432109 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_par
tial_data.2503432109 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/9.kmac_burst_write.350726668
Short name T563
Test name
Test status
Simulation time 18815466027 ps
CPU time 1003.36 seconds
Started Aug 10 06:32:11 PM PDT 24
Finished Aug 10 06:48:55 PM PDT 24
Peak memory 253296 kb
Host smart-f8784438-eeba-47bf-9f1e-c08f63e4fefe
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350726668 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.350726668 +
enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_burst_write/latest

Test location /workspace/coverage/default/9.kmac_edn_timeout_error.1488742586
Short name T56
Test name
Test status
Simulation time 36209608 ps
CPU time 0.94 seconds
Started Aug 10 06:32:28 PM PDT 24
Finished Aug 10 06:32:29 PM PDT 24
Peak memory 218492 kb
Host smart-16883eb1-499b-4331-803a-dda7c8eacead
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1488742586 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.1488742586 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_mode_error.3496946947
Short name T460
Test name
Test status
Simulation time 124327693 ps
CPU time 1.19 seconds
Started Aug 10 06:32:27 PM PDT 24
Finished Aug 10 06:32:28 PM PDT 24
Peak memory 222332 kb
Host smart-721799ef-c9b5-433b-9858-5a9ebd66c8a7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3496946947 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.3496946947 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_ready_error.1891153225
Short name T10
Test name
Test status
Simulation time 1835729495 ps
CPU time 19.9 seconds
Started Aug 10 06:32:28 PM PDT 24
Finished Aug 10 06:32:48 PM PDT 24
Peak memory 219832 kb
Host smart-e8ded9a5-d8b6-4e7b-abfe-35306d3f98ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891153225 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.1891153225 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_refresh.2246787612
Short name T1038
Test name
Test status
Simulation time 7087327719 ps
CPU time 262.82 seconds
Started Aug 10 06:32:29 PM PDT 24
Finished Aug 10 06:36:52 PM PDT 24
Peak memory 308260 kb
Host smart-ef2ae664-56ff-453c-8d8e-9eb747ecd96b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246787612 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.22
46787612 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/9.kmac_error.846061182
Short name T321
Test name
Test status
Simulation time 9020981731 ps
CPU time 317.06 seconds
Started Aug 10 06:32:27 PM PDT 24
Finished Aug 10 06:37:44 PM PDT 24
Peak memory 467388 kb
Host smart-d59f9598-5e5f-440f-b2e9-72496b152ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846061182 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.846061182 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_error/latest

Test location /workspace/coverage/default/9.kmac_key_error.2811901571
Short name T292
Test name
Test status
Simulation time 1857811427 ps
CPU time 12.6 seconds
Started Aug 10 06:32:29 PM PDT 24
Finished Aug 10 06:32:41 PM PDT 24
Peak memory 226752 kb
Host smart-09f4f411-944c-4cdf-9bf6-1aeabbe5bc5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811901571 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.2811901571 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_key_error/latest

Test location /workspace/coverage/default/9.kmac_lc_escalation.1130891134
Short name T1
Test name
Test status
Simulation time 27515860 ps
CPU time 1.34 seconds
Started Aug 10 06:32:28 PM PDT 24
Finished Aug 10 06:32:29 PM PDT 24
Peak memory 226920 kb
Host smart-04b8525c-3773-4a61-a929-bb762a690ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130891134 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.1130891134 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/9.kmac_lc_escalation/latest

Test location /workspace/coverage/default/9.kmac_long_msg_and_output.1509611917
Short name T161
Test name
Test status
Simulation time 1496351563 ps
CPU time 68.72 seconds
Started Aug 10 06:32:12 PM PDT 24
Finished Aug 10 06:33:20 PM PDT 24
Peak memory 259660 kb
Host smart-2ff3ce38-3fc4-4400-bd35-4b1dc656f0dd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509611917 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_an
d_output.1509611917 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/9.kmac_mubi.789617920
Short name T1014
Test name
Test status
Simulation time 746174016 ps
CPU time 17.49 seconds
Started Aug 10 06:32:27 PM PDT 24
Finished Aug 10 06:32:45 PM PDT 24
Peak memory 243268 kb
Host smart-e2666a3d-a107-43ef-b7cb-7621e0b8dd56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789617920 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.789617920 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_mubi/latest

Test location /workspace/coverage/default/9.kmac_sideload.2604680629
Short name T765
Test name
Test status
Simulation time 2598067610 ps
CPU time 17.64 seconds
Started Aug 10 06:32:10 PM PDT 24
Finished Aug 10 06:32:28 PM PDT 24
Peak memory 239752 kb
Host smart-caffcf99-aa5c-46c2-abb9-4dced6acff81
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604680629 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.2604680629 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_sideload/latest

Test location /workspace/coverage/default/9.kmac_smoke.4072630616
Short name T244
Test name
Test status
Simulation time 760214338 ps
CPU time 30.22 seconds
Started Aug 10 06:32:12 PM PDT 24
Finished Aug 10 06:32:42 PM PDT 24
Peak memory 222972 kb
Host smart-cde5a941-6f3e-49b9-8294-31437f6ae33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072630616 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.4072630616 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_smoke/latest

Test location /workspace/coverage/default/9.kmac_stress_all.870229132
Short name T1020
Test name
Test status
Simulation time 24807459792 ps
CPU time 1107.24 seconds
Started Aug 10 06:32:27 PM PDT 24
Finished Aug 10 06:50:55 PM PDT 24
Peak memory 405048 kb
Host smart-94c28f9c-7532-4292-9ea8-6a34b47cfba9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=870229132 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.870229132 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_stress_all/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_kmac.3846918108
Short name T723
Test name
Test status
Simulation time 307776196 ps
CPU time 6.46 seconds
Started Aug 10 06:32:21 PM PDT 24
Finished Aug 10 06:32:28 PM PDT 24
Peak memory 219852 kb
Host smart-1cbf9881-d2de-4e23-9894-7094eb433762
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846918108 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.kmac_test_vectors_kmac.3846918108 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_kmac_xof.3039382997
Short name T811
Test name
Test status
Simulation time 394317536 ps
CPU time 5.69 seconds
Started Aug 10 06:32:19 PM PDT 24
Finished Aug 10 06:32:25 PM PDT 24
Peak memory 218968 kb
Host smart-c53eca89-e777-4ad8-89c8-975543083acf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039382997 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.kmac_test_vectors_kmac_xof.3039382997 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_224.1127685805
Short name T732
Test name
Test status
Simulation time 67324853353 ps
CPU time 3429.25 seconds
Started Aug 10 06:32:12 PM PDT 24
Finished Aug 10 07:29:22 PM PDT 24
Peak memory 3317088 kb
Host smart-a8c9975b-34c1-47a1-ba63-d442034de552
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1127685805 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_224.1127685805 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_256.1997584243
Short name T724
Test name
Test status
Simulation time 75543232429 ps
CPU time 1968.1 seconds
Started Aug 10 06:32:11 PM PDT 24
Finished Aug 10 07:04:59 PM PDT 24
Peak memory 1102416 kb
Host smart-8915ccbd-9ca7-4869-a61a-42b03c9b4885
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1997584243 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_256.1997584243 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_384.3315724627
Short name T804
Test name
Test status
Simulation time 49425046014 ps
CPU time 2178.18 seconds
Started Aug 10 06:32:19 PM PDT 24
Finished Aug 10 07:08:38 PM PDT 24
Peak memory 2382872 kb
Host smart-5c268165-03b8-4a0b-8061-bd84acc92ca4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3315724627 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_384.3315724627 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_512.1024688389
Short name T348
Test name
Test status
Simulation time 42657655120 ps
CPU time 1454.93 seconds
Started Aug 10 06:32:19 PM PDT 24
Finished Aug 10 06:56:34 PM PDT 24
Peak memory 1680816 kb
Host smart-a88d80a1-ddff-464b-9394-5b3b1dc877ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1024688389 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_512.1024688389 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_shake_128.1346601435
Short name T470
Test name
Test status
Simulation time 185706422459 ps
CPU time 10734 seconds
Started Aug 10 06:32:19 PM PDT 24
Finished Aug 10 09:31:15 PM PDT 24
Peak memory 7799536 kb
Host smart-2bd43001-fb6d-4bd9-9503-23aef26c461e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1346601435 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_128.1346601435 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_shake_256.630691741
Short name T689
Test name
Test status
Simulation time 193427682532 ps
CPU time 5405.66 seconds
Started Aug 10 06:32:19 PM PDT 24
Finished Aug 10 08:02:25 PM PDT 24
Peak memory 2248260 kb
Host smart-3c53ff0a-797d-454f-84d3-b5420f5257f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=630691741 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_256.630691741 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_shake_256/latest
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