Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	77340366	1			T1	205361		T3	12799		T18	277
all_values[1]	77340366	1			T1	205361		T3	12799		T18	277
all_values[2]	77340366	1			T1	205361		T3	12799		T18	277

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

600650

1

T1

3

T3

172

T18

6

auto[1]

231420448

1

T1

616080

T3

38225

T18

825

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

230906874

1

T1

614427

T3

38010

T18

792

auto[1]

1114224

1

T1

1656

T3

387

T18

39

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	221628	1			T37	31		T38	431		T39	4
all_values[0]	auto[0]	auto[1]	1997	1			T37	2		T38	2		T39	2
all_values[0]	auto[1]	auto[0]	76747330	1			T1	204809		T3	12670		T18	264
all_values[0]	auto[1]	auto[1]	369411	1			T1	552		T3	129		T18	13
all_values[1]	auto[0]	auto[0]	163437	1			T1	2		T7	401		T35	6
all_values[1]	auto[0]	auto[1]	1499	1			T1	1		T7	4		T35	1
all_values[1]	auto[1]	auto[0]	76805521	1			T1	204807		T3	12670		T18	264
all_values[1]	auto[1]	auto[1]	369909	1			T1	551		T3	129		T18	13
all_values[2]	auto[0]	auto[0]	210568	1			T3	171		T18	5		T7	215
all_values[2]	auto[0]	auto[1]	1521	1			T3	1		T18	1		T7	3
all_values[2]	auto[1]	auto[0]	76758390	1			T1	204809		T3	12499		T18	259
all_values[2]	auto[1]	auto[1]	369887	1			T1	552		T3	128		T18	12