Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
264028 |
1 |
|
|
T1 |
2 |
|
T3 |
2 |
|
T18 |
2 |
auto[1] |
245534 |
1 |
|
|
T1 |
746 |
|
T3 |
260 |
|
T18 |
16 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
127509 |
1 |
|
|
T1 |
191 |
|
T3 |
50 |
|
T18 |
5 |
lower_val |
126257 |
1 |
|
|
T1 |
192 |
|
T3 |
77 |
|
T18 |
4 |
zero_val |
1680 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T18 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
193810 |
1 |
|
|
T1 |
210 |
|
T3 |
68 |
|
T18 |
2 |
lower_val |
192720 |
1 |
|
|
T1 |
174 |
|
T3 |
58 |
|
T18 |
4 |
zero_val |
123032 |
1 |
|
|
T1 |
364 |
|
T3 |
136 |
|
T18 |
12 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
33140 |
1 |
|
|
T35 |
3 |
|
T37 |
25 |
|
T40 |
4 |
higher_val |
higher_val |
auto[1] |
15347 |
1 |
|
|
T1 |
54 |
|
T3 |
10 |
|
T7 |
10 |
higher_val |
lower_val |
auto[0] |
33021 |
1 |
|
|
T35 |
4 |
|
T37 |
31 |
|
T40 |
3 |
higher_val |
lower_val |
auto[1] |
15343 |
1 |
|
|
T1 |
41 |
|
T3 |
9 |
|
T18 |
2 |
higher_val |
zero_val |
auto[0] |
68 |
1 |
|
|
T18 |
1 |
|
T22 |
1 |
|
T195 |
1 |
higher_val |
zero_val |
auto[1] |
30590 |
1 |
|
|
T1 |
96 |
|
T3 |
31 |
|
T18 |
2 |
lower_val |
higher_val |
auto[0] |
32729 |
1 |
|
|
T35 |
1 |
|
T37 |
24 |
|
T75 |
26 |
lower_val |
higher_val |
auto[1] |
15331 |
1 |
|
|
T1 |
57 |
|
T3 |
18 |
|
T18 |
2 |
lower_val |
lower_val |
auto[0] |
32428 |
1 |
|
|
T35 |
3 |
|
T37 |
26 |
|
T40 |
2 |
lower_val |
lower_val |
auto[1] |
15259 |
1 |
|
|
T1 |
46 |
|
T3 |
17 |
|
T7 |
6 |
lower_val |
zero_val |
auto[0] |
82 |
1 |
|
|
T38 |
1 |
|
T15 |
1 |
|
T21 |
1 |
lower_val |
zero_val |
auto[1] |
30428 |
1 |
|
|
T1 |
89 |
|
T3 |
42 |
|
T18 |
2 |
zero_val |
higher_val |
auto[0] |
515 |
1 |
|
|
T40 |
1 |
|
T71 |
3 |
|
T72 |
3 |
zero_val |
higher_val |
auto[1] |
138 |
1 |
|
|
T36 |
1 |
|
T15 |
2 |
|
T21 |
1 |
zero_val |
lower_val |
auto[0] |
527 |
1 |
|
|
T3 |
1 |
|
T35 |
1 |
|
T37 |
1 |
zero_val |
lower_val |
auto[1] |
105 |
1 |
|
|
T36 |
1 |
|
T195 |
2 |
|
T127 |
1 |
zero_val |
zero_val |
auto[0] |
228 |
1 |
|
|
T1 |
1 |
|
T18 |
1 |
|
T7 |
1 |
zero_val |
zero_val |
auto[1] |
167 |
1 |
|
|
T36 |
2 |
|
T195 |
2 |
|
T127 |
1 |