Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	7210	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	7604	1			T1	19		T36	38		T37	13
len_5001_7500	12825	1			T1	18		T36	36		T37	59
len_2501_5000	7916	1			T1	18		T36	36		T37	14
len_1025_2500	4682	1			T1	11		T36	22		T37	7
len_769_1024	6045	1			T1	2		T3	18		T7	16
len_513_768	6543	1			T1	2		T3	26		T7	24
len_257_512	12935	1			T1	2		T3	22		T7	15
len_0_256	181618	1			T1	274		T3	20		T18	9
len_keccak_block_sizes[72]	594	1			T1	2		T3	1		T36	3
len_keccak_block_sizes[104]	506	1			T1	2		T36	3		T71	3
len_keccak_block_sizes[136]	398	1			T1	2		T36	3		T71	3
len_keccak_block_sizes[144]	312	1			T36	3		T71	3		T72	3
len_keccak_block_sizes[168]	204	1			T3	1		T36	3		T71	3
len_1	629	1			T1	2		T3	1		T36	3
len_0	1057	1			T1	2		T36	3		T37	3