Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	77340366	1			T1	205361		T3	12799		T18	277
all_pins[1]	77340366	1			T1	205361		T3	12799		T18	277
all_pins[2]	77340366	1			T1	205361		T3	12799		T18	277

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	231341044	1			T1	615531		T3	38268		T18	818
values[0x1]	680054	1			T1	552		T3	129		T18	13
transitions[0x0=>0x1]	677804	1			T1	552		T3	129		T18	13
transitions[0x1=>0x0]	677833	1			T1	552		T3	129		T18	13

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	76970955	1			T1	204809		T3	12670		T18	264
all_pins[0]	values[0x1]	369411	1			T1	552		T3	129		T18	13
all_pins[0]	transitions[0x0=>0x1]	369402	1			T1	552		T3	129		T18	13
all_pins[0]	transitions[0x1=>0x0]	5421	1			T7	36		T37	3		T22	3
all_pins[1]	values[0x0]	77334936	1			T1	205361		T3	12799		T18	277
all_pins[1]	values[0x1]	5430	1			T7	36		T37	3		T22	3
all_pins[1]	transitions[0x0=>0x1]	5100	1			T7	36		T37	3		T22	3
all_pins[1]	transitions[0x1=>0x0]	304883	1			T7	282		T20	343		T41	555
all_pins[2]	values[0x0]	77035153	1			T1	205361		T3	12799		T18	277
all_pins[2]	values[0x1]	305213	1			T7	282		T20	343		T41	555
all_pins[2]	transitions[0x0=>0x1]	303302	1			T7	282		T20	342		T41	555
all_pins[2]	transitions[0x1=>0x0]	367529	1			T1	552		T3	129		T18	13