Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	657	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5408	1			T3	13		T7	10		T37	13
len_601_800	12318	1			T3	23		T7	23		T37	35
len_401_600	8168	1			T3	27		T7	5		T37	29
len_201_400	14977	1			T3	15		T7	11		T36	251
len_65_200	46819	1			T3	3		T7	2		T36	680
len_min_for_xof_require_squeeze	658	1			T3	1		T36	10		T71	10
len_keccak_block_sizes[72]	416	1			T36	5		T75	1		T71	5
len_keccak_block_sizes[104]	419	1			T36	5		T75	1		T71	5
len_keccak_block_sizes[136]	428	1			T36	5		T75	1		T71	5
len_keccak_block_sizes[144]	254	1			T36	5		T71	5		T72	5
len_keccak_block_sizes[168]	256	1			T36	5		T75	1		T71	5
len_datapath_width	13452	1			T3	1		T18	3		T35	3
len_2_63	151253	1			T1	374		T3	47		T18	6
len_1	44	1			T75	1		T196	1		T197	1