Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9440364 |
1 |
|
|
T1 |
2992 |
|
T3 |
15098 |
|
T18 |
96 |
auto[1] |
9440319 |
1 |
|
|
T1 |
2992 |
|
T3 |
15098 |
|
T18 |
96 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
18710123 |
1 |
|
|
T1 |
5984 |
|
T3 |
30074 |
|
T18 |
192 |
triple_byte_access |
56498 |
1 |
|
|
T3 |
40 |
|
T7 |
46 |
|
T36 |
620 |
halfword_access |
57456 |
1 |
|
|
T3 |
36 |
|
T7 |
34 |
|
T36 |
632 |
byte_access |
56606 |
1 |
|
|
T3 |
46 |
|
T7 |
20 |
|
T36 |
620 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
9355084 |
1 |
|
|
T1 |
2992 |
|
T3 |
15037 |
|
T18 |
96 |
auto[0] |
triple_byte_access |
28249 |
1 |
|
|
T3 |
20 |
|
T7 |
23 |
|
T36 |
310 |
auto[0] |
halfword_access |
28728 |
1 |
|
|
T3 |
18 |
|
T7 |
17 |
|
T36 |
316 |
auto[0] |
byte_access |
28303 |
1 |
|
|
T3 |
23 |
|
T7 |
10 |
|
T36 |
310 |
auto[1] |
word_access |
9355039 |
1 |
|
|
T1 |
2992 |
|
T3 |
15037 |
|
T18 |
96 |
auto[1] |
triple_byte_access |
28249 |
1 |
|
|
T3 |
20 |
|
T7 |
23 |
|
T36 |
310 |
auto[1] |
halfword_access |
28728 |
1 |
|
|
T3 |
18 |
|
T7 |
17 |
|
T36 |
316 |
auto[1] |
byte_access |
28303 |
1 |
|
|
T3 |
23 |
|
T7 |
10 |
|
T36 |
310 |