Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	15521362	1			T1	5		T2	25970		T3	5104
all_values[1]	15521362	1			T1	5		T2	25970		T3	5104
all_values[2]	15521362	1			T1	5		T2	25970		T3	5104

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

562394

1

T2

30

T3

730

T8

881

auto[1]

46001692

1

T1

15

T2

77880

T3

14582

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46340037

1

T1

15

T2

77133

T3

15150

auto[1]

224049

1

T2

777

T3

162

T8

153

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	187453	1			T3	65		T33	345		T34	174
all_values[0]	auto[0]	auto[1]	1247	1			T3	2		T33	2		T34	2
all_values[0]	auto[1]	auto[0]	15259226	1			T1	5		T2	25711		T3	4985
all_values[0]	auto[1]	auto[1]	73436	1			T2	259		T3	52		T8	51
all_values[1]	auto[0]	auto[0]	211991	1			T2	29		T3	235		T33	345
all_values[1]	auto[0]	auto[1]	1051	1			T2	1		T3	3		T33	2
all_values[1]	auto[1]	auto[0]	15234688	1			T1	5		T2	25682		T3	4815
all_values[1]	auto[1]	auto[1]	73632	1			T2	258		T3	51		T8	51
all_values[2]	auto[0]	auto[0]	159672	1			T3	420		T8	872		T33	345
all_values[2]	auto[0]	auto[1]	980	1			T3	5		T8	9		T33	2
all_values[2]	auto[1]	auto[0]	15287007	1			T1	5		T2	25711		T3	4630
all_values[2]	auto[1]	auto[1]	73703	1			T2	259		T3	49		T8	42