Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56974 |
1 |
|
|
T1 |
2 |
|
T2 |
378 |
|
T3 |
76 |
auto[1] |
56212 |
1 |
|
|
T8 |
68 |
|
T33 |
78 |
|
T34 |
134 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
28235 |
1 |
|
|
T1 |
1 |
|
T2 |
95 |
|
T3 |
27 |
lower_val |
27774 |
1 |
|
|
T2 |
96 |
|
T3 |
14 |
|
T7 |
1 |
zero_val |
894 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
42800 |
1 |
|
|
T2 |
192 |
|
T3 |
30 |
|
T8 |
22 |
lower_val |
41968 |
1 |
|
|
T1 |
2 |
|
T2 |
186 |
|
T3 |
46 |
zero_val |
28418 |
1 |
|
|
T7 |
2 |
|
T8 |
24 |
|
T33 |
42 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
7057 |
1 |
|
|
T2 |
46 |
|
T3 |
15 |
|
T18 |
5 |
higher_val |
higher_val |
auto[1] |
3579 |
1 |
|
|
T8 |
7 |
|
T33 |
5 |
|
T34 |
7 |
higher_val |
lower_val |
auto[0] |
7088 |
1 |
|
|
T1 |
1 |
|
T2 |
49 |
|
T3 |
12 |
higher_val |
lower_val |
auto[1] |
3440 |
1 |
|
|
T8 |
7 |
|
T33 |
3 |
|
T34 |
3 |
higher_val |
zero_val |
auto[0] |
64 |
1 |
|
|
T13 |
1 |
|
T14 |
1 |
|
T19 |
1 |
higher_val |
zero_val |
auto[1] |
7007 |
1 |
|
|
T8 |
6 |
|
T33 |
17 |
|
T34 |
13 |
lower_val |
higher_val |
auto[0] |
6958 |
1 |
|
|
T2 |
54 |
|
T3 |
1 |
|
T33 |
1 |
lower_val |
higher_val |
auto[1] |
3487 |
1 |
|
|
T8 |
2 |
|
T33 |
9 |
|
T34 |
19 |
lower_val |
lower_val |
auto[0] |
6856 |
1 |
|
|
T2 |
42 |
|
T3 |
13 |
|
T18 |
3 |
lower_val |
lower_val |
auto[1] |
3397 |
1 |
|
|
T8 |
2 |
|
T33 |
5 |
|
T34 |
7 |
lower_val |
zero_val |
auto[0] |
53 |
1 |
|
|
T7 |
1 |
|
T34 |
1 |
|
T30 |
1 |
lower_val |
zero_val |
auto[1] |
7023 |
1 |
|
|
T8 |
2 |
|
T33 |
9 |
|
T34 |
13 |
zero_val |
higher_val |
auto[0] |
262 |
1 |
|
|
T33 |
1 |
|
T11 |
1 |
|
T18 |
1 |
zero_val |
higher_val |
auto[1] |
76 |
1 |
|
|
T199 |
1 |
|
T189 |
3 |
|
T69 |
2 |
zero_val |
lower_val |
auto[0] |
272 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
zero_val |
lower_val |
auto[1] |
60 |
1 |
|
|
T13 |
2 |
|
T14 |
1 |
|
T40 |
2 |
zero_val |
zero_val |
auto[0] |
163 |
1 |
|
|
T7 |
1 |
|
T34 |
1 |
|
T30 |
1 |
zero_val |
zero_val |
auto[1] |
61 |
1 |
|
|
T13 |
1 |
|
T14 |
2 |
|
T42 |
2 |