Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	15521362	1			T1	5		T2	25970		T3	5104
all_pins[1]	15521362	1			T1	5		T2	25970		T3	5104
all_pins[2]	15521362	1			T1	5		T2	25970		T3	5104

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	46182828	1			T1	15		T2	76898		T3	15151
values[0x1]	381258	1			T2	1012		T3	161		T8	381
transitions[0x0=>0x1]	379213	1			T2	1012		T3	161		T8	381
transitions[0x1=>0x0]	379231	1			T2	1012		T3	161		T8	381

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	15447926	1			T1	5		T2	25711		T3	5052
all_pins[0]	values[0x1]	73436	1			T2	259		T3	52		T8	51
all_pins[0]	transitions[0x0=>0x1]	73426	1			T2	259		T3	52		T8	51
all_pins[0]	transitions[0x1=>0x0]	5860	1			T2	82		T37	41		T36	9
all_pins[1]	values[0x0]	15515492	1			T1	5		T2	25888		T3	5104
all_pins[1]	values[0x1]	5870	1			T2	82		T37	41		T36	9
all_pins[1]	transitions[0x0=>0x1]	5647	1			T2	82		T37	41		T36	9
all_pins[1]	transitions[0x1=>0x0]	301729	1			T2	671		T3	109		T8	330
all_pins[2]	values[0x0]	15219410	1			T1	5		T2	25299		T3	4995
all_pins[2]	values[0x1]	301952	1			T2	671		T3	109		T8	330
all_pins[2]	transitions[0x0=>0x1]	300140	1			T2	671		T3	109		T8	330
all_pins[2]	transitions[0x1=>0x0]	71642	1			T2	259		T3	52		T8	51