Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6360049 |
1 |
|
|
T2 |
28051 |
|
T3 |
5730 |
|
T8 |
5395 |
auto[1] |
6360049 |
1 |
|
|
T2 |
28051 |
|
T3 |
5730 |
|
T8 |
5395 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
12653110 |
1 |
|
|
T2 |
55846 |
|
T3 |
11410 |
|
T8 |
10732 |
triple_byte_access |
22376 |
1 |
|
|
T2 |
80 |
|
T3 |
12 |
|
T8 |
20 |
halfword_access |
22462 |
1 |
|
|
T2 |
78 |
|
T3 |
14 |
|
T8 |
16 |
byte_access |
22150 |
1 |
|
|
T2 |
98 |
|
T3 |
24 |
|
T8 |
22 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
6326555 |
1 |
|
|
T2 |
27923 |
|
T3 |
5705 |
|
T8 |
5366 |
auto[0] |
triple_byte_access |
11188 |
1 |
|
|
T2 |
40 |
|
T3 |
6 |
|
T8 |
10 |
auto[0] |
halfword_access |
11231 |
1 |
|
|
T2 |
39 |
|
T3 |
7 |
|
T8 |
8 |
auto[0] |
byte_access |
11075 |
1 |
|
|
T2 |
49 |
|
T3 |
12 |
|
T8 |
11 |
auto[1] |
word_access |
6326555 |
1 |
|
|
T2 |
27923 |
|
T3 |
5705 |
|
T8 |
5366 |
auto[1] |
triple_byte_access |
11188 |
1 |
|
|
T2 |
40 |
|
T3 |
6 |
|
T8 |
10 |
auto[1] |
halfword_access |
11231 |
1 |
|
|
T2 |
39 |
|
T3 |
7 |
|
T8 |
8 |
auto[1] |
byte_access |
11075 |
1 |
|
|
T2 |
49 |
|
T3 |
12 |
|
T8 |
11 |