Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	13619942	1			T2	2		T3	7396		T16	207838
all_values[1]	13619942	1			T2	2		T3	7396		T16	207838
all_values[2]	13619942	1			T2	2		T3	7396		T16	207838

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

482489

1

T2

6

T16

204

T7

251

auto[1]

40377337

1

T3

22188

T16

623310

T7

4930

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

40645905

1

T2

6

T3

21972

T16

623082

auto[1]

213921

1

T3

216

T16

432

T7

66

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	157697	1			T2	2		T7	249		T30	53
all_values[0]	auto[0]	auto[1]	1244	1			T7	2		T30	6		T32	2
all_values[0]	auto[1]	auto[0]	13390938	1			T3	7324		T16	207694		T7	1456
all_values[0]	auto[1]	auto[1]	70063	1			T3	72		T16	144		T7	20
all_values[1]	auto[0]	auto[0]	173705	1			T2	2		T16	202		T20	96
all_values[1]	auto[0]	auto[1]	1083	1			T16	2		T20	1		T8	1
all_values[1]	auto[1]	auto[0]	13374930	1			T3	7324		T16	207492		T7	1705
all_values[1]	auto[1]	auto[1]	70224	1			T3	72		T16	142		T7	22
all_values[2]	auto[0]	auto[0]	147729	1			T2	2		T30	23		T20	470
all_values[2]	auto[0]	auto[1]	1031	1			T30	2		T20	5		T31	1
all_values[2]	auto[1]	auto[0]	13400906	1			T3	7324		T16	207694		T7	1705
all_values[2]	auto[1]	auto[1]	70276	1			T3	72		T16	144		T7	22