Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
58940 |
1 |
|
|
T2 |
2 |
|
T3 |
116 |
|
T16 |
200 |
auto[1] |
48548 |
1 |
|
|
T7 |
46 |
|
T30 |
136 |
|
T31 |
672 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
26520 |
1 |
|
|
T3 |
38 |
|
T16 |
43 |
|
T7 |
9 |
lower_val |
26494 |
1 |
|
|
T3 |
24 |
|
T16 |
50 |
|
T7 |
14 |
zero_val |
881 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
40968 |
1 |
|
|
T2 |
2 |
|
T3 |
56 |
|
T16 |
110 |
lower_val |
41964 |
1 |
|
|
T3 |
60 |
|
T16 |
90 |
|
T7 |
8 |
zero_val |
24556 |
1 |
|
|
T7 |
32 |
|
T30 |
64 |
|
T31 |
340 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
7184 |
1 |
|
|
T3 |
18 |
|
T16 |
21 |
|
T20 |
33 |
higher_val |
higher_val |
auto[1] |
2967 |
1 |
|
|
T7 |
1 |
|
T30 |
6 |
|
T31 |
49 |
higher_val |
lower_val |
auto[0] |
7274 |
1 |
|
|
T3 |
20 |
|
T16 |
22 |
|
T20 |
49 |
higher_val |
lower_val |
auto[1] |
3086 |
1 |
|
|
T7 |
2 |
|
T30 |
11 |
|
T31 |
47 |
higher_val |
zero_val |
auto[0] |
57 |
1 |
|
|
T21 |
1 |
|
T18 |
1 |
|
T49 |
1 |
higher_val |
zero_val |
auto[1] |
5952 |
1 |
|
|
T7 |
6 |
|
T30 |
15 |
|
T31 |
90 |
lower_val |
higher_val |
auto[0] |
7143 |
1 |
|
|
T3 |
10 |
|
T16 |
25 |
|
T20 |
38 |
lower_val |
higher_val |
auto[1] |
2997 |
1 |
|
|
T7 |
3 |
|
T30 |
6 |
|
T31 |
37 |
lower_val |
lower_val |
auto[0] |
7359 |
1 |
|
|
T3 |
14 |
|
T16 |
25 |
|
T20 |
46 |
lower_val |
lower_val |
auto[1] |
3003 |
1 |
|
|
T7 |
2 |
|
T30 |
9 |
|
T31 |
34 |
lower_val |
zero_val |
auto[0] |
40 |
1 |
|
|
T7 |
1 |
|
T32 |
1 |
|
T34 |
1 |
lower_val |
zero_val |
auto[1] |
5952 |
1 |
|
|
T7 |
8 |
|
T30 |
20 |
|
T31 |
77 |
zero_val |
higher_val |
auto[0] |
268 |
1 |
|
|
T2 |
1 |
|
T16 |
1 |
|
T20 |
2 |
zero_val |
higher_val |
auto[1] |
54 |
1 |
|
|
T15 |
1 |
|
T49 |
1 |
|
T61 |
1 |
zero_val |
lower_val |
auto[0] |
291 |
1 |
|
|
T3 |
1 |
|
T30 |
1 |
|
T20 |
1 |
zero_val |
lower_val |
auto[1] |
66 |
1 |
|
|
T14 |
2 |
|
T93 |
1 |
|
T15 |
1 |
zero_val |
zero_val |
auto[0] |
153 |
1 |
|
|
T7 |
1 |
|
T32 |
1 |
|
T12 |
1 |
zero_val |
zero_val |
auto[1] |
49 |
1 |
|
|
T189 |
1 |
|
T73 |
3 |
|
T74 |
1 |