Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	13619942	1			T2	2		T3	7396		T16	207838
all_pins[1]	13619942	1			T2	2		T3	7396		T16	207838
all_pins[2]	13619942	1			T2	2		T3	7396		T16	207838

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	40521560	1			T2	6		T3	14768		T16	623370
values[0x1]	338266	1			T3	7420		T16	144		T7	20
transitions[0x0=>0x1]	336452	1			T3	7372		T16	144		T7	20
transitions[0x1=>0x0]	336477	1			T3	7373		T16	144		T7	20

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	13549879	1			T2	2		T3	7324		T16	207694
all_pins[0]	values[0x1]	70063	1			T3	72		T16	144		T7	20
all_pins[0]	transitions[0x0=>0x1]	70052	1			T3	72		T16	144		T7	20
all_pins[0]	transitions[0x1=>0x0]	5280	1			T19	28		T54	23		T22	21
all_pins[1]	values[0x0]	13614651	1			T2	2		T3	7396		T16	207838
all_pins[1]	values[0x1]	5291	1			T19	28		T54	23		T22	21
all_pins[1]	transitions[0x0=>0x1]	5059	1			T19	28		T54	23		T22	21
all_pins[1]	transitions[0x1=>0x0]	262680	1			T3	7348		T8	1374		T21	735
all_pins[2]	values[0x0]	13357030	1			T2	2		T3	48		T16	207838
all_pins[2]	values[0x1]	262912	1			T3	7348		T8	1374		T21	735
all_pins[2]	transitions[0x0=>0x1]	261341	1			T3	7300		T8	1374		T21	735
all_pins[2]	transitions[0x1=>0x0]	68517	1			T3	25		T16	144		T7	20