Summary for Variable in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for in_app_keymgr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56220 |
1 |
|
|
T2 |
1 |
|
T3 |
61 |
|
T16 |
97 |
auto[1] |
2998 |
1 |
|
|
T3 |
6 |
|
T7 |
4 |
|
T8 |
5 |
Summary for Variable kmac_mode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_mode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
25872 |
1 |
|
|
T3 |
30 |
|
T16 |
97 |
|
T7 |
19 |
auto[1] |
33346 |
1 |
|
|
T2 |
1 |
|
T3 |
37 |
|
T7 |
14 |
Summary for Variable sideload
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for sideload
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
45936 |
1 |
|
|
T2 |
1 |
|
T3 |
56 |
|
T16 |
97 |
auto[1] |
13282 |
1 |
|
|
T3 |
11 |
|
T7 |
7 |
|
T20 |
163 |
Summary for Cross sideload_cross
Samples crossed: sideload kmac_mode in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins for sideload_cross
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
sw_kmac_valid_sideload |
13282 |
1 |
|
|
T3 |
11 |
|
T7 |
7 |
|
T20 |
163 |
sw_kmac_invalid_sideload |
45936 |
1 |
|
|
T2 |
1 |
|
T3 |
56 |
|
T16 |
97 |
app_valid_sideload |
13282 |
1 |
|
|
T3 |
11 |
|
T7 |
7 |
|
T20 |
163 |
app_invalid_sideload |
45936 |
1 |
|
|
T2 |
1 |
|
T3 |
56 |
|
T16 |
97 |