Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5971423 |
1 |
|
|
T3 |
7832 |
|
T16 |
800 |
|
T7 |
2443 |
auto[1] |
5971341 |
1 |
|
|
T3 |
7832 |
|
T16 |
800 |
|
T7 |
2443 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
11880318 |
1 |
|
|
T3 |
15594 |
|
T16 |
1600 |
|
T7 |
4874 |
triple_byte_access |
20940 |
1 |
|
|
T3 |
28 |
|
T7 |
2 |
|
T30 |
28 |
halfword_access |
20658 |
1 |
|
|
T3 |
20 |
|
T7 |
6 |
|
T30 |
46 |
byte_access |
20848 |
1 |
|
|
T3 |
22 |
|
T7 |
4 |
|
T30 |
26 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
5940200 |
1 |
|
|
T3 |
7797 |
|
T16 |
800 |
|
T7 |
2437 |
auto[0] |
triple_byte_access |
10470 |
1 |
|
|
T3 |
14 |
|
T7 |
1 |
|
T30 |
14 |
auto[0] |
halfword_access |
10329 |
1 |
|
|
T3 |
10 |
|
T7 |
3 |
|
T30 |
23 |
auto[0] |
byte_access |
10424 |
1 |
|
|
T3 |
11 |
|
T7 |
2 |
|
T30 |
13 |
auto[1] |
word_access |
5940118 |
1 |
|
|
T3 |
7797 |
|
T16 |
800 |
|
T7 |
2437 |
auto[1] |
triple_byte_access |
10470 |
1 |
|
|
T3 |
14 |
|
T7 |
1 |
|
T30 |
14 |
auto[1] |
halfword_access |
10329 |
1 |
|
|
T3 |
10 |
|
T7 |
3 |
|
T30 |
23 |
auto[1] |
byte_access |
10424 |
1 |
|
|
T3 |
11 |
|
T7 |
2 |
|
T30 |
13 |