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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.34 97.91 92.62 99.89 77.46 95.59 99.05 97.88


Total test records in report: 876
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T758 /workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.3609509811 Aug 13 05:22:11 PM PDT 24 Aug 13 05:22:12 PM PDT 24 109438920 ps
T759 /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.1410646653 Aug 13 05:22:08 PM PDT 24 Aug 13 05:22:18 PM PDT 24 10364219270 ps
T760 /workspace/coverage/cover_reg_top/21.kmac_intr_test.71590056 Aug 13 05:22:44 PM PDT 24 Aug 13 05:22:45 PM PDT 24 15015637 ps
T761 /workspace/coverage/cover_reg_top/3.kmac_intr_test.499095380 Aug 13 05:22:03 PM PDT 24 Aug 13 05:22:04 PM PDT 24 16214283 ps
T762 /workspace/coverage/cover_reg_top/11.kmac_csr_rw.4021872068 Aug 13 05:21:58 PM PDT 24 Aug 13 05:21:59 PM PDT 24 378664944 ps
T763 /workspace/coverage/cover_reg_top/33.kmac_intr_test.1268857599 Aug 13 05:22:29 PM PDT 24 Aug 13 05:22:30 PM PDT 24 20923459 ps
T764 /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.2479587398 Aug 13 05:22:17 PM PDT 24 Aug 13 05:22:19 PM PDT 24 21956698 ps
T765 /workspace/coverage/cover_reg_top/1.kmac_mem_walk.2739012227 Aug 13 05:22:02 PM PDT 24 Aug 13 05:22:02 PM PDT 24 13329969 ps
T766 /workspace/coverage/cover_reg_top/43.kmac_intr_test.746360392 Aug 13 05:22:24 PM PDT 24 Aug 13 05:22:25 PM PDT 24 41040551 ps
T767 /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.3237864280 Aug 13 05:22:09 PM PDT 24 Aug 13 05:22:11 PM PDT 24 184364956 ps
T768 /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.3645454753 Aug 13 05:22:11 PM PDT 24 Aug 13 05:22:12 PM PDT 24 22950299 ps
T769 /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.1377862803 Aug 13 05:22:15 PM PDT 24 Aug 13 05:22:18 PM PDT 24 198234227 ps
T770 /workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.2611381329 Aug 13 05:22:12 PM PDT 24 Aug 13 05:22:16 PM PDT 24 74117461 ps
T771 /workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.4223305799 Aug 13 05:22:03 PM PDT 24 Aug 13 05:22:04 PM PDT 24 25621694 ps
T772 /workspace/coverage/cover_reg_top/0.kmac_mem_walk.1694198358 Aug 13 05:22:05 PM PDT 24 Aug 13 05:22:06 PM PDT 24 32242462 ps
T773 /workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.1328389143 Aug 13 05:22:16 PM PDT 24 Aug 13 05:22:17 PM PDT 24 53074914 ps
T181 /workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.2528389719 Aug 13 05:22:24 PM PDT 24 Aug 13 05:22:27 PM PDT 24 127416726 ps
T774 /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.662798885 Aug 13 05:22:19 PM PDT 24 Aug 13 05:22:20 PM PDT 24 59264974 ps
T775 /workspace/coverage/cover_reg_top/5.kmac_csr_rw.2687243285 Aug 13 05:21:59 PM PDT 24 Aug 13 05:22:00 PM PDT 24 53462731 ps
T776 /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.1052654290 Aug 13 05:22:29 PM PDT 24 Aug 13 05:22:31 PM PDT 24 75978001 ps
T777 /workspace/coverage/cover_reg_top/16.kmac_intr_test.1750127942 Aug 13 05:22:32 PM PDT 24 Aug 13 05:22:33 PM PDT 24 16055089 ps
T778 /workspace/coverage/cover_reg_top/6.kmac_tl_errors.3299113915 Aug 13 05:22:03 PM PDT 24 Aug 13 05:22:06 PM PDT 24 295154022 ps
T779 /workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.799505671 Aug 13 05:22:23 PM PDT 24 Aug 13 05:22:25 PM PDT 24 29423856 ps
T780 /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.3875083998 Aug 13 05:22:30 PM PDT 24 Aug 13 05:22:31 PM PDT 24 401419039 ps
T781 /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.1365643312 Aug 13 05:22:36 PM PDT 24 Aug 13 05:22:37 PM PDT 24 26950315 ps
T182 /workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.1255921657 Aug 13 05:22:14 PM PDT 24 Aug 13 05:22:16 PM PDT 24 189208692 ps
T782 /workspace/coverage/cover_reg_top/6.kmac_csr_rw.3824168957 Aug 13 05:22:05 PM PDT 24 Aug 13 05:22:06 PM PDT 24 98695607 ps
T783 /workspace/coverage/cover_reg_top/11.kmac_tl_errors.3054304301 Aug 13 05:22:33 PM PDT 24 Aug 13 05:22:35 PM PDT 24 62166701 ps
T784 /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.335267885 Aug 13 05:22:16 PM PDT 24 Aug 13 05:22:18 PM PDT 24 275172437 ps
T785 /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.3667960639 Aug 13 05:22:10 PM PDT 24 Aug 13 05:22:13 PM PDT 24 87422569 ps
T786 /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.3238900578 Aug 13 05:22:04 PM PDT 24 Aug 13 05:22:05 PM PDT 24 252657827 ps
T787 /workspace/coverage/cover_reg_top/48.kmac_intr_test.2159901331 Aug 13 05:22:18 PM PDT 24 Aug 13 05:22:19 PM PDT 24 16610652 ps
T788 /workspace/coverage/cover_reg_top/32.kmac_intr_test.3067312233 Aug 13 05:22:16 PM PDT 24 Aug 13 05:22:17 PM PDT 24 36902272 ps
T789 /workspace/coverage/cover_reg_top/13.kmac_intr_test.3146952378 Aug 13 05:22:10 PM PDT 24 Aug 13 05:22:11 PM PDT 24 15603509 ps
T790 /workspace/coverage/cover_reg_top/10.kmac_csr_rw.2030779833 Aug 13 05:22:02 PM PDT 24 Aug 13 05:22:03 PM PDT 24 103418961 ps
T791 /workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.3479186683 Aug 13 05:22:08 PM PDT 24 Aug 13 05:22:13 PM PDT 24 385252759 ps
T792 /workspace/coverage/cover_reg_top/15.kmac_intr_test.1406426317 Aug 13 05:22:27 PM PDT 24 Aug 13 05:22:27 PM PDT 24 54274571 ps
T793 /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.3585040145 Aug 13 05:22:02 PM PDT 24 Aug 13 05:22:04 PM PDT 24 52160829 ps
T794 /workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.722761432 Aug 13 05:21:59 PM PDT 24 Aug 13 05:22:01 PM PDT 24 56070654 ps
T795 /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.2225347509 Aug 13 05:22:04 PM PDT 24 Aug 13 05:22:05 PM PDT 24 67876104 ps
T796 /workspace/coverage/cover_reg_top/27.kmac_intr_test.2405569820 Aug 13 05:22:42 PM PDT 24 Aug 13 05:22:43 PM PDT 24 19915009 ps
T797 /workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.517975819 Aug 13 05:22:19 PM PDT 24 Aug 13 05:22:27 PM PDT 24 140194226 ps
T798 /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.3677371090 Aug 13 05:22:06 PM PDT 24 Aug 13 05:22:09 PM PDT 24 402459664 ps
T799 /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.3384039619 Aug 13 05:22:07 PM PDT 24 Aug 13 05:22:10 PM PDT 24 87770354 ps
T800 /workspace/coverage/cover_reg_top/19.kmac_tl_errors.3148142601 Aug 13 05:22:09 PM PDT 24 Aug 13 05:22:13 PM PDT 24 671085527 ps
T801 /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.2815494640 Aug 13 05:22:00 PM PDT 24 Aug 13 05:22:03 PM PDT 24 95502800 ps
T185 /workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.3779072426 Aug 13 05:22:22 PM PDT 24 Aug 13 05:22:26 PM PDT 24 356801009 ps
T802 /workspace/coverage/cover_reg_top/1.kmac_tl_errors.311960251 Aug 13 05:21:52 PM PDT 24 Aug 13 05:21:56 PM PDT 24 454079144 ps
T803 /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.113737747 Aug 13 05:22:42 PM PDT 24 Aug 13 05:22:44 PM PDT 24 230976095 ps
T804 /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.2824960915 Aug 13 05:21:56 PM PDT 24 Aug 13 05:21:57 PM PDT 24 66385735 ps
T805 /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.143848891 Aug 13 05:22:43 PM PDT 24 Aug 13 05:22:45 PM PDT 24 103357718 ps
T806 /workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.2667238740 Aug 13 05:22:07 PM PDT 24 Aug 13 05:22:10 PM PDT 24 399273699 ps
T807 /workspace/coverage/cover_reg_top/25.kmac_intr_test.1492742844 Aug 13 05:22:22 PM PDT 24 Aug 13 05:22:23 PM PDT 24 16130692 ps
T808 /workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.920954368 Aug 13 05:22:44 PM PDT 24 Aug 13 05:22:46 PM PDT 24 99521871 ps
T809 /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.4269911344 Aug 13 05:22:07 PM PDT 24 Aug 13 05:22:08 PM PDT 24 123621718 ps
T810 /workspace/coverage/cover_reg_top/28.kmac_intr_test.1774740655 Aug 13 05:22:26 PM PDT 24 Aug 13 05:22:27 PM PDT 24 36617617 ps
T811 /workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.620130310 Aug 13 05:22:21 PM PDT 24 Aug 13 05:22:23 PM PDT 24 300344388 ps
T812 /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.2534253541 Aug 13 05:22:01 PM PDT 24 Aug 13 05:22:04 PM PDT 24 160033759 ps
T813 /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.848062726 Aug 13 05:21:58 PM PDT 24 Aug 13 05:22:00 PM PDT 24 230372389 ps
T814 /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.3808587990 Aug 13 05:22:13 PM PDT 24 Aug 13 05:22:19 PM PDT 24 539761382 ps
T815 /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.2948195440 Aug 13 05:22:27 PM PDT 24 Aug 13 05:22:30 PM PDT 24 171051518 ps
T816 /workspace/coverage/cover_reg_top/10.kmac_tl_errors.2692251029 Aug 13 05:22:07 PM PDT 24 Aug 13 05:22:11 PM PDT 24 144095779 ps
T817 /workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.3062787304 Aug 13 05:22:03 PM PDT 24 Aug 13 05:22:06 PM PDT 24 537458211 ps
T818 /workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.87691755 Aug 13 05:22:08 PM PDT 24 Aug 13 05:22:10 PM PDT 24 141222795 ps
T819 /workspace/coverage/cover_reg_top/1.kmac_intr_test.4048709498 Aug 13 05:21:57 PM PDT 24 Aug 13 05:21:58 PM PDT 24 13081420 ps
T820 /workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.3112699926 Aug 13 05:22:07 PM PDT 24 Aug 13 05:22:10 PM PDT 24 151761620 ps
T821 /workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.1796487672 Aug 13 05:22:14 PM PDT 24 Aug 13 05:22:17 PM PDT 24 330394060 ps
T178 /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.1343813033 Aug 13 05:22:25 PM PDT 24 Aug 13 05:22:30 PM PDT 24 200397102 ps
T822 /workspace/coverage/cover_reg_top/13.kmac_csr_rw.1857578201 Aug 13 05:22:09 PM PDT 24 Aug 13 05:22:10 PM PDT 24 57287424 ps
T143 /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.149625623 Aug 13 05:22:01 PM PDT 24 Aug 13 05:22:02 PM PDT 24 18840248 ps
T823 /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.3233649805 Aug 13 05:21:55 PM PDT 24 Aug 13 05:21:56 PM PDT 24 15966575 ps
T824 /workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.220345322 Aug 13 05:22:08 PM PDT 24 Aug 13 05:22:10 PM PDT 24 58391846 ps
T825 /workspace/coverage/cover_reg_top/37.kmac_intr_test.2378595395 Aug 13 05:22:17 PM PDT 24 Aug 13 05:22:18 PM PDT 24 13946164 ps
T144 /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.3787812670 Aug 13 05:22:01 PM PDT 24 Aug 13 05:22:02 PM PDT 24 42091978 ps
T826 /workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.1697875961 Aug 13 05:22:25 PM PDT 24 Aug 13 05:22:27 PM PDT 24 58388050 ps
T827 /workspace/coverage/cover_reg_top/9.kmac_tl_errors.1679842281 Aug 13 05:22:07 PM PDT 24 Aug 13 05:22:10 PM PDT 24 305904440 ps
T828 /workspace/coverage/cover_reg_top/16.kmac_csr_rw.3379900865 Aug 13 05:22:10 PM PDT 24 Aug 13 05:22:11 PM PDT 24 33159717 ps
T829 /workspace/coverage/cover_reg_top/16.kmac_tl_errors.1344078015 Aug 13 05:22:25 PM PDT 24 Aug 13 05:22:28 PM PDT 24 51519491 ps
T830 /workspace/coverage/cover_reg_top/2.kmac_intr_test.106557236 Aug 13 05:21:58 PM PDT 24 Aug 13 05:21:59 PM PDT 24 14068096 ps
T831 /workspace/coverage/cover_reg_top/12.kmac_intr_test.2933556151 Aug 13 05:22:08 PM PDT 24 Aug 13 05:22:09 PM PDT 24 80094405 ps
T832 /workspace/coverage/cover_reg_top/3.kmac_tl_errors.2237568607 Aug 13 05:22:07 PM PDT 24 Aug 13 05:22:10 PM PDT 24 298703182 ps
T833 /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.4009357530 Aug 13 05:22:15 PM PDT 24 Aug 13 05:22:17 PM PDT 24 83956216 ps
T834 /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.3412826281 Aug 13 05:21:58 PM PDT 24 Aug 13 05:21:59 PM PDT 24 55472902 ps
T835 /workspace/coverage/cover_reg_top/9.kmac_csr_rw.707229378 Aug 13 05:22:07 PM PDT 24 Aug 13 05:22:08 PM PDT 24 38181946 ps
T836 /workspace/coverage/cover_reg_top/34.kmac_intr_test.2716138431 Aug 13 05:22:35 PM PDT 24 Aug 13 05:22:36 PM PDT 24 63807792 ps
T837 /workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.1594039953 Aug 13 05:22:12 PM PDT 24 Aug 13 05:22:16 PM PDT 24 242912532 ps
T838 /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.3730611291 Aug 13 05:22:22 PM PDT 24 Aug 13 05:22:23 PM PDT 24 114487025 ps
T839 /workspace/coverage/cover_reg_top/14.kmac_tl_errors.1989587910 Aug 13 05:22:07 PM PDT 24 Aug 13 05:22:10 PM PDT 24 94794148 ps
T840 /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.2281617172 Aug 13 05:22:06 PM PDT 24 Aug 13 05:22:07 PM PDT 24 42174454 ps
T841 /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.2416054948 Aug 13 05:22:23 PM PDT 24 Aug 13 05:22:26 PM PDT 24 117183023 ps
T145 /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.2716455881 Aug 13 05:21:56 PM PDT 24 Aug 13 05:21:57 PM PDT 24 50901194 ps
T842 /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.1162343271 Aug 13 05:22:04 PM PDT 24 Aug 13 05:22:15 PM PDT 24 3317087173 ps
T843 /workspace/coverage/cover_reg_top/4.kmac_tl_errors.2868227573 Aug 13 05:22:06 PM PDT 24 Aug 13 05:22:09 PM PDT 24 245771658 ps
T844 /workspace/coverage/cover_reg_top/31.kmac_intr_test.934508895 Aug 13 05:22:12 PM PDT 24 Aug 13 05:22:13 PM PDT 24 106138535 ps
T845 /workspace/coverage/cover_reg_top/17.kmac_intr_test.2590614295 Aug 13 05:22:33 PM PDT 24 Aug 13 05:22:34 PM PDT 24 19871459 ps
T846 /workspace/coverage/cover_reg_top/36.kmac_intr_test.1927404533 Aug 13 05:22:46 PM PDT 24 Aug 13 05:22:47 PM PDT 24 42347865 ps
T847 /workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.2430172057 Aug 13 05:22:06 PM PDT 24 Aug 13 05:22:08 PM PDT 24 25177894 ps
T848 /workspace/coverage/cover_reg_top/12.kmac_tl_errors.3514308527 Aug 13 05:22:28 PM PDT 24 Aug 13 05:22:30 PM PDT 24 62765562 ps
T849 /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.3237364670 Aug 13 05:22:15 PM PDT 24 Aug 13 05:22:18 PM PDT 24 391065125 ps
T850 /workspace/coverage/cover_reg_top/40.kmac_intr_test.4192441326 Aug 13 05:22:17 PM PDT 24 Aug 13 05:22:18 PM PDT 24 40135018 ps
T851 /workspace/coverage/cover_reg_top/0.kmac_csr_rw.2814678778 Aug 13 05:22:00 PM PDT 24 Aug 13 05:22:01 PM PDT 24 48168767 ps
T852 /workspace/coverage/cover_reg_top/15.kmac_tl_errors.3511817947 Aug 13 05:22:14 PM PDT 24 Aug 13 05:22:15 PM PDT 24 95265674 ps
T853 /workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.1055107880 Aug 13 05:22:34 PM PDT 24 Aug 13 05:22:36 PM PDT 24 39059020 ps
T854 /workspace/coverage/cover_reg_top/44.kmac_intr_test.3117970214 Aug 13 05:22:32 PM PDT 24 Aug 13 05:22:33 PM PDT 24 26337400 ps
T855 /workspace/coverage/cover_reg_top/18.kmac_intr_test.1093336259 Aug 13 05:22:11 PM PDT 24 Aug 13 05:22:12 PM PDT 24 33988800 ps
T856 /workspace/coverage/cover_reg_top/3.kmac_mem_walk.1540148957 Aug 13 05:22:06 PM PDT 24 Aug 13 05:22:07 PM PDT 24 12912368 ps
T857 /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.1026274668 Aug 13 05:22:31 PM PDT 24 Aug 13 05:22:33 PM PDT 24 106150991 ps
T858 /workspace/coverage/cover_reg_top/23.kmac_intr_test.2326014561 Aug 13 05:22:16 PM PDT 24 Aug 13 05:22:17 PM PDT 24 84073847 ps
T859 /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.3725395813 Aug 13 05:22:12 PM PDT 24 Aug 13 05:22:21 PM PDT 24 1013287610 ps
T860 /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.1369624202 Aug 13 05:22:09 PM PDT 24 Aug 13 05:22:10 PM PDT 24 27243072 ps
T861 /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.4278292930 Aug 13 05:21:59 PM PDT 24 Aug 13 05:22:02 PM PDT 24 174234647 ps
T862 /workspace/coverage/cover_reg_top/8.kmac_intr_test.587543855 Aug 13 05:22:04 PM PDT 24 Aug 13 05:22:05 PM PDT 24 52112328 ps
T863 /workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.4129964325 Aug 13 05:21:59 PM PDT 24 Aug 13 05:22:09 PM PDT 24 2026652121 ps
T864 /workspace/coverage/cover_reg_top/39.kmac_intr_test.2875779069 Aug 13 05:22:29 PM PDT 24 Aug 13 05:22:30 PM PDT 24 14244959 ps
T865 /workspace/coverage/cover_reg_top/11.kmac_intr_test.4235267817 Aug 13 05:22:08 PM PDT 24 Aug 13 05:22:08 PM PDT 24 101340437 ps
T866 /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.1068146385 Aug 13 05:22:07 PM PDT 24 Aug 13 05:22:09 PM PDT 24 102343306 ps
T867 /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.3570398289 Aug 13 05:22:06 PM PDT 24 Aug 13 05:22:07 PM PDT 24 65752709 ps
T868 /workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.3707672131 Aug 13 05:22:14 PM PDT 24 Aug 13 05:22:33 PM PDT 24 3842840543 ps
T869 /workspace/coverage/cover_reg_top/17.kmac_csr_rw.2857271050 Aug 13 05:22:31 PM PDT 24 Aug 13 05:22:32 PM PDT 24 21529204 ps
T870 /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.3691098836 Aug 13 05:22:13 PM PDT 24 Aug 13 05:22:16 PM PDT 24 158461303 ps
T871 /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.3424869352 Aug 13 05:22:16 PM PDT 24 Aug 13 05:22:17 PM PDT 24 160560345 ps
T872 /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.3122666489 Aug 13 05:22:07 PM PDT 24 Aug 13 05:22:08 PM PDT 24 81658129 ps
T873 /workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.324163159 Aug 13 05:22:12 PM PDT 24 Aug 13 05:22:16 PM PDT 24 370784495 ps
T874 /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.3668487955 Aug 13 05:22:45 PM PDT 24 Aug 13 05:22:47 PM PDT 24 34629071 ps
T875 /workspace/coverage/cover_reg_top/2.kmac_tl_errors.1603802848 Aug 13 05:21:56 PM PDT 24 Aug 13 05:21:58 PM PDT 24 78399452 ps
T876 /workspace/coverage/cover_reg_top/19.kmac_csr_rw.3551699556 Aug 13 05:22:31 PM PDT 24 Aug 13 05:22:32 PM PDT 24 22475284 ps

Test location /workspace/coverage/default/14.kmac_entropy_refresh.286319640
Short name T7
Test name
Test status
Simulation time 1835073713 ps
CPU time 41.11 seconds
Started Aug 13 04:40:27 PM PDT 24
Finished Aug 13 04:41:09 PM PDT 24
Peak memory 246752 kb
Host smart-24bd523c-68a4-4a80-bdaf-d0ce6a930912
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286319640 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.28
6319640 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_entropy_refresh/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.3188700400
Short name T125
Test name
Test status
Simulation time 4467132859 ps
CPU time 4.88 seconds
Started Aug 13 05:22:02 PM PDT 24
Finished Aug 13 05:22:07 PM PDT 24
Peak memory 216132 kb
Host smart-ca18fb4c-e19d-44c1-bf8c-6ea6ab607c15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188700400 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.31887
00400 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/45.kmac_lc_escalation.2447413434
Short name T34
Test name
Test status
Simulation time 863258349 ps
CPU time 43.3 seconds
Started Aug 13 04:41:40 PM PDT 24
Finished Aug 13 04:42:23 PM PDT 24
Peak memory 251360 kb
Host smart-a90ebe34-7b5b-4dbb-ae42-e8403e195b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447413434 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.2447413434 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/45.kmac_lc_escalation/latest

Test location /workspace/coverage/default/27.kmac_error.3292864531
Short name T8
Test name
Test status
Simulation time 14003424931 ps
CPU time 529.45 seconds
Started Aug 13 04:40:51 PM PDT 24
Finished Aug 13 04:49:40 PM PDT 24
Peak memory 590596 kb
Host smart-50cb870d-2ee5-4f84-bfd1-a24ccbdebc53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292864531 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.3292864531 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_error/latest

Test location /workspace/coverage/default/6.kmac_stress_all_with_rand_reset.2577513120
Short name T15
Test name
Test status
Simulation time 3615671473 ps
CPU time 57.9 seconds
Started Aug 13 04:40:02 PM PDT 24
Finished Aug 13 04:41:00 PM PDT 24
Peak memory 243584 kb
Host smart-48099439-eb2c-4f66-b893-25228ddf7514
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2577513120 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all_with_rand_reset.2577513120 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.kmac_sec_cm.1594857986
Short name T27
Test name
Test status
Simulation time 9351542657 ps
CPU time 40.53 seconds
Started Aug 13 04:39:56 PM PDT 24
Finished Aug 13 04:40:37 PM PDT 24
Peak memory 256664 kb
Host smart-2e84dcc9-4497-480b-94bb-a7b4fe31a9c5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594857986 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.1594857986 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspace/2.kmac_sec_cm/latest

Test location /workspace/coverage/default/19.kmac_key_error.470512475
Short name T36
Test name
Test status
Simulation time 358665923 ps
CPU time 2.79 seconds
Started Aug 13 04:40:32 PM PDT 24
Finished Aug 13 04:40:36 PM PDT 24
Peak memory 226512 kb
Host smart-d2fd8251-593e-4242-8040-9b68125c6be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470512475 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.470512475 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_key_error/latest

Test location /workspace/coverage/default/21.kmac_lc_escalation.3004822392
Short name T13
Test name
Test status
Simulation time 171588261 ps
CPU time 1.65 seconds
Started Aug 13 04:40:32 PM PDT 24
Finished Aug 13 04:40:34 PM PDT 24
Peak memory 226624 kb
Host smart-e1d9d731-616a-4fd7-b40b-08502ca12ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004822392 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.3004822392 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/21.kmac_lc_escalation/latest

Test location /workspace/coverage/default/39.kmac_lc_escalation.1755447404
Short name T43
Test name
Test status
Simulation time 83579026 ps
CPU time 1.3 seconds
Started Aug 13 04:41:26 PM PDT 24
Finished Aug 13 04:41:28 PM PDT 24
Peak memory 226628 kb
Host smart-14a3e2f7-aacd-4481-82b7-7b459c4b4d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755447404 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.1755447404 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/39.kmac_lc_escalation/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.1715557769
Short name T88
Test name
Test status
Simulation time 215037346 ps
CPU time 2.67 seconds
Started Aug 13 05:22:14 PM PDT 24
Finished Aug 13 05:22:21 PM PDT 24
Peak memory 219880 kb
Host smart-432051b2-4263-40bb-a117-884250b604f8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715557769 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kma
c_shadow_reg_errors_with_csr_rw.1715557769 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.kmac_entropy_ready_error.352156116
Short name T9
Test name
Test status
Simulation time 20754391902 ps
CPU time 56.36 seconds
Started Aug 13 04:39:41 PM PDT 24
Finished Aug 13 04:40:38 PM PDT 24
Peak memory 226784 kb
Host smart-600d0328-d5bc-43b0-89a6-7c0d48793368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352156116 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.352156116 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/1.kmac_edn_timeout_error.1236377418
Short name T58
Test name
Test status
Simulation time 48131763 ps
CPU time 1.05 seconds
Started Aug 13 04:39:56 PM PDT 24
Finished Aug 13 04:39:57 PM PDT 24
Peak memory 218244 kb
Host smart-bfc8ea35-f139-437c-8764-113e34bbe160
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1236377418 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.1236377418 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_edn_timeout_error/latest

Test location /workspace/coverage/cover_reg_top/24.kmac_intr_test.613885643
Short name T167
Test name
Test status
Simulation time 25263885 ps
CPU time 0.81 seconds
Started Aug 13 05:22:33 PM PDT 24
Finished Aug 13 05:22:34 PM PDT 24
Peak memory 215476 kb
Host smart-7a52f32e-af40-40aa-8e4f-25977e1d7fec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613885643 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.613885643 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/24.kmac_intr_test/latest

Test location /workspace/coverage/default/10.kmac_entropy_mode_error.3212713454
Short name T365
Test name
Test status
Simulation time 19869302 ps
CPU time 1.02 seconds
Started Aug 13 04:40:13 PM PDT 24
Finished Aug 13 04:40:14 PM PDT 24
Peak memory 218160 kb
Host smart-930ffeae-f1c3-4bea-85e5-e61764b222c5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3212713454 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.3212713454 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/36.kmac_stress_all.1669574644
Short name T74
Test name
Test status
Simulation time 54994819555 ps
CPU time 871.81 seconds
Started Aug 13 04:41:14 PM PDT 24
Finished Aug 13 04:55:46 PM PDT 24
Peak memory 518856 kb
Host smart-b941e90c-9920-4906-a78c-2efb5492b4da
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1669574644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all.1669574644 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_stress_all/latest

Test location /workspace/coverage/default/0.kmac_lc_escalation.2774594009
Short name T45
Test name
Test status
Simulation time 39959327 ps
CPU time 1.26 seconds
Started Aug 13 04:39:43 PM PDT 24
Finished Aug 13 04:39:44 PM PDT 24
Peak memory 226576 kb
Host smart-7b4e5c80-3dc1-4c39-93d4-57f1eb40ffec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774594009 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.2774594009 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/0.kmac_lc_escalation/latest

Test location /workspace/coverage/default/14.kmac_lc_escalation.1868480127
Short name T389
Test name
Test status
Simulation time 82810613 ps
CPU time 1.41 seconds
Started Aug 13 04:40:27 PM PDT 24
Finished Aug 13 04:40:29 PM PDT 24
Peak memory 226588 kb
Host smart-011b53b6-144a-4554-b118-2ae6e3befb03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868480127 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.1868480127 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/14.kmac_lc_escalation/latest

Test location /workspace/coverage/default/26.kmac_lc_escalation.3290190609
Short name T71
Test name
Test status
Simulation time 136550240 ps
CPU time 1.35 seconds
Started Aug 13 04:40:48 PM PDT 24
Finished Aug 13 04:40:49 PM PDT 24
Peak memory 226776 kb
Host smart-c3291b97-0ae3-4df4-8c89-59bb200b68f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290190609 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.3290190609 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/26.kmac_lc_escalation/latest

Test location /workspace/coverage/default/49.kmac_burst_write.1001717221
Short name T37
Test name
Test status
Simulation time 17924528947 ps
CPU time 803.81 seconds
Started Aug 13 04:41:55 PM PDT 24
Finished Aug 13 04:55:19 PM PDT 24
Peak memory 249744 kb
Host smart-c4fd352e-53ce-456c-8c2d-dfcd8a66a830
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001717221 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.100171722
1 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_burst_write/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.3787812670
Short name T144
Test name
Test status
Simulation time 42091978 ps
CPU time 1.51 seconds
Started Aug 13 05:22:01 PM PDT 24
Finished Aug 13 05:22:02 PM PDT 24
Peak memory 216008 kb
Host smart-10bc2e93-391c-452a-88dd-52a4629e2bc7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787812670 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partia
l_access.3787812670 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_mem_partial_access/latest

Test location /workspace/coverage/default/1.kmac_lc_escalation.1482284423
Short name T24
Test name
Test status
Simulation time 60841169 ps
CPU time 1.21 seconds
Started Aug 13 04:39:56 PM PDT 24
Finished Aug 13 04:39:57 PM PDT 24
Peak memory 226496 kb
Host smart-b10a4cd4-5bc3-41f7-8d37-65f7a31bcba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482284423 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.1482284423 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/1.kmac_lc_escalation/latest

Test location /workspace/coverage/default/15.kmac_alert_test.4213841982
Short name T199
Test name
Test status
Simulation time 14917034 ps
CPU time 0.8 seconds
Started Aug 13 04:40:34 PM PDT 24
Finished Aug 13 04:40:34 PM PDT 24
Peak memory 218236 kb
Host smart-b7503ddb-6e06-4a63-80b6-ee4d0f0cd484
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213841982 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.4213841982 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.2479587398
Short name T764
Test name
Test status
Simulation time 21956698 ps
CPU time 1.09 seconds
Started Aug 13 05:22:17 PM PDT 24
Finished Aug 13 05:22:19 PM PDT 24
Peak memory 216188 kb
Host smart-812413ee-a6ac-46d2-a1ed-18234235a38f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479587398 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg
_errors.2479587398 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_intr_test.769461519
Short name T169
Test name
Test status
Simulation time 21529281 ps
CPU time 0.82 seconds
Started Aug 13 05:22:08 PM PDT 24
Finished Aug 13 05:22:09 PM PDT 24
Peak memory 215804 kb
Host smart-13c4871d-c918-4a94-8cec-af7bd99fa7c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769461519 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.769461519 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/10.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.3779072426
Short name T185
Test name
Test status
Simulation time 356801009 ps
CPU time 3.72 seconds
Started Aug 13 05:22:22 PM PDT 24
Finished Aug 13 05:22:26 PM PDT 24
Peak memory 216084 kb
Host smart-be922fa0-2cb1-4f98-918f-4381cbd396c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779072426 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.37790
72426 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/19.kmac_sideload.3606758697
Short name T33
Test name
Test status
Simulation time 15682223728 ps
CPU time 458.3 seconds
Started Aug 13 04:40:36 PM PDT 24
Finished Aug 13 04:48:14 PM PDT 24
Peak memory 559016 kb
Host smart-050f20c6-e26b-464f-93d5-8ab91b1acf06
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606758697 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.3606758697 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_sideload/latest

Test location /workspace/coverage/default/3.kmac_entropy_refresh.3445901954
Short name T62
Test name
Test status
Simulation time 18389697333 ps
CPU time 369.79 seconds
Started Aug 13 04:39:58 PM PDT 24
Finished Aug 13 04:46:08 PM PDT 24
Peak memory 462992 kb
Host smart-5697cfae-9acf-46c7-bf9d-370c5d118431
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445901954 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.34
45901954 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/6.kmac_error.3251258225
Short name T307
Test name
Test status
Simulation time 15926549201 ps
CPU time 448.67 seconds
Started Aug 13 04:40:13 PM PDT 24
Finished Aug 13 04:47:42 PM PDT 24
Peak memory 572240 kb
Host smart-044faa58-ec57-4ada-9bcb-234ed2e4943a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251258225 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.3251258225 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_error/latest

Test location /workspace/coverage/default/0.kmac_sec_cm.2612721338
Short name T79
Test name
Test status
Simulation time 4785243405 ps
CPU time 48.38 seconds
Started Aug 13 04:39:51 PM PDT 24
Finished Aug 13 04:40:40 PM PDT 24
Peak memory 257776 kb
Host smart-b0ed8825-7426-466b-ae1d-4affb9ba66f0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612721338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.2612721338 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspace/0.kmac_sec_cm/latest

Test location /workspace/coverage/default/46.kmac_key_error.3323829227
Short name T96
Test name
Test status
Simulation time 4476820760 ps
CPU time 10.97 seconds
Started Aug 13 04:41:41 PM PDT 24
Finished Aug 13 04:41:52 PM PDT 24
Peak memory 226788 kb
Host smart-707c02fa-245a-48b4-8c85-de8fcc9662ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323829227 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.3323829227 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_key_error/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.1343813033
Short name T178
Test name
Test status
Simulation time 200397102 ps
CPU time 4.9 seconds
Started Aug 13 05:22:25 PM PDT 24
Finished Aug 13 05:22:30 PM PDT 24
Peak memory 216008 kb
Host smart-b595c11a-6607-4fa6-8be1-523de529ffbf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343813033 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.1343
813033 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.149030671
Short name T90
Test name
Test status
Simulation time 37174549 ps
CPU time 0.93 seconds
Started Aug 13 05:22:23 PM PDT 24
Finished Aug 13 05:22:24 PM PDT 24
Peak memory 216144 kb
Host smart-5efd6802-de6b-45f5-b313-80601ff9a99d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149030671 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_
errors.149030671 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/default/0.kmac_entropy_refresh.2348701071
Short name T171
Test name
Test status
Simulation time 59128991727 ps
CPU time 354.63 seconds
Started Aug 13 04:39:44 PM PDT 24
Finished Aug 13 04:45:39 PM PDT 24
Peak memory 461064 kb
Host smart-2487e074-f633-4bd2-84dc-0ec260c58aa4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348701071 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.23
48701071 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/47.kmac_stress_all.298231000
Short name T18
Test name
Test status
Simulation time 29463810293 ps
CPU time 739.38 seconds
Started Aug 13 04:41:47 PM PDT 24
Finished Aug 13 04:54:07 PM PDT 24
Peak memory 615884 kb
Host smart-1d524d31-2536-4deb-8e70-df017d0f4180
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=298231000 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.298231000 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.477221571
Short name T179
Test name
Test status
Simulation time 863289990 ps
CPU time 3.89 seconds
Started Aug 13 05:21:51 PM PDT 24
Finished Aug 13 05:21:55 PM PDT 24
Peak memory 216152 kb
Host smart-8947abaa-2e6b-4507-b645-8da32bcec923
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477221571 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.477221
571 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/19.kmac_stress_all.513686311
Short name T599
Test name
Test status
Simulation time 51655385228 ps
CPU time 713.87 seconds
Started Aug 13 04:40:33 PM PDT 24
Finished Aug 13 04:52:27 PM PDT 24
Peak memory 420672 kb
Host smart-288cc7fd-7f18-417c-a557-fd8cb41ba99b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=513686311 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.513686311 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.2611381329
Short name T770
Test name
Test status
Simulation time 74117461 ps
CPU time 4.16 seconds
Started Aug 13 05:22:12 PM PDT 24
Finished Aug 13 05:22:16 PM PDT 24
Peak memory 216008 kb
Host smart-44574b67-0586-43ff-b9cc-a4a4a6e5e4c0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611381329 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.2611381
329 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.921572428
Short name T187
Test name
Test status
Simulation time 302007626 ps
CPU time 14.78 seconds
Started Aug 13 05:21:58 PM PDT 24
Finished Aug 13 05:22:13 PM PDT 24
Peak memory 216072 kb
Host smart-0aa0a497-df9d-4b31-8b5f-0601aa6a20f1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921572428 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.92157242
8 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.3570398289
Short name T867
Test name
Test status
Simulation time 65752709 ps
CPU time 1 seconds
Started Aug 13 05:22:06 PM PDT 24
Finished Aug 13 05:22:07 PM PDT 24
Peak memory 215908 kb
Host smart-37254161-74f0-4c71-8ac4-e483c091b15d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570398289 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.3570398
289 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.848062726
Short name T813
Test name
Test status
Simulation time 230372389 ps
CPU time 2.28 seconds
Started Aug 13 05:21:58 PM PDT 24
Finished Aug 13 05:22:00 PM PDT 24
Peak memory 221544 kb
Host smart-83a9c3e5-ee64-4b0a-b9b2-2a346b170b26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848062726 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.kmac_csr_mem_rw_with_rand_reset.848062726 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_rw.2814678778
Short name T851
Test name
Test status
Simulation time 48168767 ps
CPU time 0.94 seconds
Started Aug 13 05:22:00 PM PDT 24
Finished Aug 13 05:22:01 PM PDT 24
Peak memory 215784 kb
Host smart-690f4d37-0651-4f72-876f-7d44d002005e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814678778 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.2814678778 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_intr_test.3218226165
Short name T157
Test name
Test status
Simulation time 36022335 ps
CPU time 0.78 seconds
Started Aug 13 05:21:59 PM PDT 24
Finished Aug 13 05:21:59 PM PDT 24
Peak memory 215856 kb
Host smart-c8b8326a-50bf-4435-a6af-440f3ec52933
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218226165 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.3218226165 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_mem_walk.1694198358
Short name T772
Test name
Test status
Simulation time 32242462 ps
CPU time 0.74 seconds
Started Aug 13 05:22:05 PM PDT 24
Finished Aug 13 05:22:06 PM PDT 24
Peak memory 215884 kb
Host smart-c1056db0-28a2-43b1-8f6e-2bd23df2ca96
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694198358 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.1694198358
+enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.579130867
Short name T732
Test name
Test status
Simulation time 116972599 ps
CPU time 2.65 seconds
Started Aug 13 05:21:52 PM PDT 24
Finished Aug 13 05:21:55 PM PDT 24
Peak memory 216116 kb
Host smart-e858540f-3e93-45ed-8aa5-19bcae257d56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579130867 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr_
outstanding.579130867 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.3412826281
Short name T834
Test name
Test status
Simulation time 55472902 ps
CPU time 1.34 seconds
Started Aug 13 05:21:58 PM PDT 24
Finished Aug 13 05:21:59 PM PDT 24
Peak memory 216392 kb
Host smart-b0566b2a-ad1f-4006-a7dc-6c153c91966d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412826281 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_
errors.3412826281 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.3677371090
Short name T798
Test name
Test status
Simulation time 402459664 ps
CPU time 2.9 seconds
Started Aug 13 05:22:06 PM PDT 24
Finished Aug 13 05:22:09 PM PDT 24
Peak memory 219044 kb
Host smart-388b1ad4-c1ed-47cd-8aac-cb74313b3a88
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677371090 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac
_shadow_reg_errors_with_csr_rw.3677371090 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_tl_errors.2376438331
Short name T726
Test name
Test status
Simulation time 676095113 ps
CPU time 4.2 seconds
Started Aug 13 05:22:03 PM PDT 24
Finished Aug 13 05:22:07 PM PDT 24
Peak memory 216216 kb
Host smart-8bda5544-c52e-4dac-98e9-89adf3f8b799
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376438331 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.2376438331 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.1410646653
Short name T759
Test name
Test status
Simulation time 10364219270 ps
CPU time 10.45 seconds
Started Aug 13 05:22:08 PM PDT 24
Finished Aug 13 05:22:18 PM PDT 24
Peak memory 216184 kb
Host smart-ef7db921-03cb-4622-b496-df07284494a3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410646653 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.1410646
653 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.3725395813
Short name T859
Test name
Test status
Simulation time 1013287610 ps
CPU time 9.69 seconds
Started Aug 13 05:22:12 PM PDT 24
Finished Aug 13 05:22:21 PM PDT 24
Peak memory 216040 kb
Host smart-018a78b2-728f-48d1-b20d-327cfaf58509
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725395813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.3725395
813 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.2824960915
Short name T804
Test name
Test status
Simulation time 66385735 ps
CPU time 1.21 seconds
Started Aug 13 05:21:56 PM PDT 24
Finished Aug 13 05:21:57 PM PDT 24
Peak memory 216064 kb
Host smart-c8237279-182f-4441-bc40-aebce372e657
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824960915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.2824960
915 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.620130310
Short name T811
Test name
Test status
Simulation time 300344388 ps
CPU time 1.63 seconds
Started Aug 13 05:22:21 PM PDT 24
Finished Aug 13 05:22:23 PM PDT 24
Peak memory 221116 kb
Host smart-66126a5a-0e07-426a-b69f-09fea00dbaca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620130310 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.kmac_csr_mem_rw_with_rand_reset.620130310 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_rw.1164659417
Short name T740
Test name
Test status
Simulation time 17813590 ps
CPU time 0.97 seconds
Started Aug 13 05:21:53 PM PDT 24
Finished Aug 13 05:21:55 PM PDT 24
Peak memory 215788 kb
Host smart-6b06c410-bae4-432d-8e5a-35b41452af3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164659417 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.1164659417 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_intr_test.4048709498
Short name T819
Test name
Test status
Simulation time 13081420 ps
CPU time 0.8 seconds
Started Aug 13 05:21:57 PM PDT 24
Finished Aug 13 05:21:58 PM PDT 24
Peak memory 215756 kb
Host smart-913846c4-a003-4adc-a98f-b9e4a8e0a54b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048709498 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.4048709498 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.149625623
Short name T143
Test name
Test status
Simulation time 18840248 ps
CPU time 1.14 seconds
Started Aug 13 05:22:01 PM PDT 24
Finished Aug 13 05:22:02 PM PDT 24
Peak memory 216056 kb
Host smart-1e41074b-d787-4267-a9fa-2ad0a8dc1446
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149625623 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partial
_access.149625623 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_mem_walk.2739012227
Short name T765
Test name
Test status
Simulation time 13329969 ps
CPU time 0.75 seconds
Started Aug 13 05:22:02 PM PDT 24
Finished Aug 13 05:22:02 PM PDT 24
Peak memory 215764 kb
Host smart-f82cb44d-cb5b-45c7-be48-00a0d1455efd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739012227 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.2739012227
+enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.87691755
Short name T818
Test name
Test status
Simulation time 141222795 ps
CPU time 1.51 seconds
Started Aug 13 05:22:08 PM PDT 24
Finished Aug 13 05:22:10 PM PDT 24
Peak memory 216016 kb
Host smart-6b1449c0-d1ac-47e9-9c56-e5fc42f1facc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87691755 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr_o
utstanding.87691755 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.3233649805
Short name T823
Test name
Test status
Simulation time 15966575 ps
CPU time 0.81 seconds
Started Aug 13 05:21:55 PM PDT 24
Finished Aug 13 05:21:56 PM PDT 24
Peak memory 215868 kb
Host smart-4bab74e9-e391-4470-98d7-4d1e5cedc4e1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233649805 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_
errors.3233649805 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.3384039619
Short name T799
Test name
Test status
Simulation time 87770354 ps
CPU time 2.27 seconds
Started Aug 13 05:22:07 PM PDT 24
Finished Aug 13 05:22:10 PM PDT 24
Peak memory 216104 kb
Host smart-3b0b815f-9b5a-4d53-959b-ae9a9c79196b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384039619 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac
_shadow_reg_errors_with_csr_rw.3384039619 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_tl_errors.311960251
Short name T802
Test name
Test status
Simulation time 454079144 ps
CPU time 3.46 seconds
Started Aug 13 05:21:52 PM PDT 24
Finished Aug 13 05:21:56 PM PDT 24
Peak memory 216092 kb
Host smart-27e990bc-bc81-4781-8133-9f0aff47b8f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311960251 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.311960251 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/1.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.978351065
Short name T180
Test name
Test status
Simulation time 472925431 ps
CPU time 3.97 seconds
Started Aug 13 05:21:56 PM PDT 24
Finished Aug 13 05:22:00 PM PDT 24
Peak memory 216132 kb
Host smart-c96cd4e0-ad0b-4a53-b263-c328a925bed4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978351065 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.978351
065 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.3112699926
Short name T820
Test name
Test status
Simulation time 151761620 ps
CPU time 2.51 seconds
Started Aug 13 05:22:07 PM PDT 24
Finished Aug 13 05:22:10 PM PDT 24
Peak memory 221240 kb
Host smart-02c28880-c237-4d9a-be6c-308b36243334
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112699926 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.kmac_csr_mem_rw_with_rand_reset.3112699926 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_csr_rw.2030779833
Short name T790
Test name
Test status
Simulation time 103418961 ps
CPU time 1.09 seconds
Started Aug 13 05:22:02 PM PDT 24
Finished Aug 13 05:22:03 PM PDT 24
Peak memory 216088 kb
Host smart-e56d2c55-f8c9-45d7-82d8-06b5fb9b0eda
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030779833 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.2030779833 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.3237864280
Short name T767
Test name
Test status
Simulation time 184364956 ps
CPU time 1.48 seconds
Started Aug 13 05:22:09 PM PDT 24
Finished Aug 13 05:22:11 PM PDT 24
Peak memory 216020 kb
Host smart-96e37b6e-7fee-4e0f-9fc1-3673372710bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237864280 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_cs
r_outstanding.3237864280 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.3645454753
Short name T768
Test name
Test status
Simulation time 22950299 ps
CPU time 0.98 seconds
Started Aug 13 05:22:11 PM PDT 24
Finished Aug 13 05:22:12 PM PDT 24
Peak memory 215924 kb
Host smart-d5f087c6-7041-4e8e-bb24-2bcf10be6b9d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645454753 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg
_errors.3645454753 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.3585040145
Short name T793
Test name
Test status
Simulation time 52160829 ps
CPU time 1.79 seconds
Started Aug 13 05:22:02 PM PDT 24
Finished Aug 13 05:22:04 PM PDT 24
Peak memory 216148 kb
Host smart-e13153dd-54fc-4c8a-b926-25b487c76544
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585040145 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kma
c_shadow_reg_errors_with_csr_rw.3585040145 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_tl_errors.2692251029
Short name T816
Test name
Test status
Simulation time 144095779 ps
CPU time 3.8 seconds
Started Aug 13 05:22:07 PM PDT 24
Finished Aug 13 05:22:11 PM PDT 24
Peak memory 216248 kb
Host smart-8dd333fc-0815-411c-9b00-dca01e34fa71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692251029 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.2692251029 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.2534253541
Short name T812
Test name
Test status
Simulation time 160033759 ps
CPU time 2.8 seconds
Started Aug 13 05:22:01 PM PDT 24
Finished Aug 13 05:22:04 PM PDT 24
Peak memory 215984 kb
Host smart-e555e643-c6da-4a8c-a4ed-5243a8194d3d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534253541 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.2534
253541 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.4009357530
Short name T833
Test name
Test status
Simulation time 83956216 ps
CPU time 2.3 seconds
Started Aug 13 05:22:15 PM PDT 24
Finished Aug 13 05:22:17 PM PDT 24
Peak memory 221920 kb
Host smart-28e5538c-4229-4329-b73e-38872796be6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009357530 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.kmac_csr_mem_rw_with_rand_reset.4009357530 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_csr_rw.4021872068
Short name T762
Test name
Test status
Simulation time 378664944 ps
CPU time 1.23 seconds
Started Aug 13 05:21:58 PM PDT 24
Finished Aug 13 05:21:59 PM PDT 24
Peak memory 216152 kb
Host smart-a06bf361-ae88-4f36-bc03-3dd97975cb21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021872068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.4021872068 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_intr_test.4235267817
Short name T865
Test name
Test status
Simulation time 101340437 ps
CPU time 0.81 seconds
Started Aug 13 05:22:08 PM PDT 24
Finished Aug 13 05:22:08 PM PDT 24
Peak memory 215868 kb
Host smart-cf4377c5-1674-4f61-8b86-ad357060bbc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235267817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.4235267817 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.1328389143
Short name T773
Test name
Test status
Simulation time 53074914 ps
CPU time 1.52 seconds
Started Aug 13 05:22:16 PM PDT 24
Finished Aug 13 05:22:17 PM PDT 24
Peak memory 216148 kb
Host smart-f363ba13-0c70-40e1-964c-54e6c926e894
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328389143 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_cs
r_outstanding.1328389143 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.3237364670
Short name T849
Test name
Test status
Simulation time 391065125 ps
CPU time 2.9 seconds
Started Aug 13 05:22:15 PM PDT 24
Finished Aug 13 05:22:18 PM PDT 24
Peak memory 219096 kb
Host smart-120e697b-f90f-40cc-9ffb-5dfeb76bce3d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237364670 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kma
c_shadow_reg_errors_with_csr_rw.3237364670 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_tl_errors.3054304301
Short name T783
Test name
Test status
Simulation time 62166701 ps
CPU time 2.14 seconds
Started Aug 13 05:22:33 PM PDT 24
Finished Aug 13 05:22:35 PM PDT 24
Peak memory 216112 kb
Host smart-5fd2903f-44bf-4f34-89e4-10b8e5c8c5bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054304301 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.3054304301 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.2822525133
Short name T154
Test name
Test status
Simulation time 76201149 ps
CPU time 1.6 seconds
Started Aug 13 05:22:11 PM PDT 24
Finished Aug 13 05:22:13 PM PDT 24
Peak memory 219000 kb
Host smart-0294540f-8d4f-47c0-b077-e5c76b6a4cd5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822525133 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.kmac_csr_mem_rw_with_rand_reset.2822525133 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_csr_rw.3330233948
Short name T156
Test name
Test status
Simulation time 71522570 ps
CPU time 0.91 seconds
Started Aug 13 05:22:11 PM PDT 24
Finished Aug 13 05:22:12 PM PDT 24
Peak memory 215916 kb
Host smart-8a4031e5-4e75-48dd-9206-84b050dba9d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330233948 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.3330233948 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_intr_test.2933556151
Short name T831
Test name
Test status
Simulation time 80094405 ps
CPU time 0.81 seconds
Started Aug 13 05:22:08 PM PDT 24
Finished Aug 13 05:22:09 PM PDT 24
Peak memory 215868 kb
Host smart-f27ecb93-9940-40ee-b8ed-7a21ee073a3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933556151 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.2933556151 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.4278292930
Short name T861
Test name
Test status
Simulation time 174234647 ps
CPU time 2.58 seconds
Started Aug 13 05:21:59 PM PDT 24
Finished Aug 13 05:22:02 PM PDT 24
Peak memory 216076 kb
Host smart-2aeae9b2-459f-488b-81ac-4f1cc4cac8c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278292930 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_cs
r_outstanding.4278292930 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.4269911344
Short name T809
Test name
Test status
Simulation time 123621718 ps
CPU time 1.04 seconds
Started Aug 13 05:22:07 PM PDT 24
Finished Aug 13 05:22:08 PM PDT 24
Peak memory 216392 kb
Host smart-a315d580-db7d-42a8-a686-82e2257f7178
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269911344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg
_errors.4269911344 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.143848891
Short name T805
Test name
Test status
Simulation time 103357718 ps
CPU time 2.49 seconds
Started Aug 13 05:22:43 PM PDT 24
Finished Aug 13 05:22:45 PM PDT 24
Peak memory 216144 kb
Host smart-2dc56d13-2fbc-426f-82d4-37b5d89255ad
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143848891 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac
_shadow_reg_errors_with_csr_rw.143848891 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_tl_errors.3514308527
Short name T848
Test name
Test status
Simulation time 62765562 ps
CPU time 1.9 seconds
Started Aug 13 05:22:28 PM PDT 24
Finished Aug 13 05:22:30 PM PDT 24
Peak memory 216120 kb
Host smart-7537a077-60c4-436f-abca-f6b525bfa01d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514308527 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.3514308527 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.1255921657
Short name T182
Test name
Test status
Simulation time 189208692 ps
CPU time 2.47 seconds
Started Aug 13 05:22:14 PM PDT 24
Finished Aug 13 05:22:16 PM PDT 24
Peak memory 216104 kb
Host smart-0ab832e3-d0d9-4e8b-8e1d-25b218be34c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255921657 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.1255
921657 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.2242922242
Short name T737
Test name
Test status
Simulation time 38811504 ps
CPU time 2.62 seconds
Started Aug 13 05:22:00 PM PDT 24
Finished Aug 13 05:22:03 PM PDT 24
Peak memory 221280 kb
Host smart-169103fa-6752-418f-92d3-ddf61b66dc96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242922242 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.kmac_csr_mem_rw_with_rand_reset.2242922242 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_csr_rw.1857578201
Short name T822
Test name
Test status
Simulation time 57287424 ps
CPU time 1 seconds
Started Aug 13 05:22:09 PM PDT 24
Finished Aug 13 05:22:10 PM PDT 24
Peak memory 215796 kb
Host smart-2a02b430-a285-402f-b672-5212aeeb44eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857578201 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.1857578201 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_intr_test.3146952378
Short name T789
Test name
Test status
Simulation time 15603509 ps
CPU time 0.79 seconds
Started Aug 13 05:22:10 PM PDT 24
Finished Aug 13 05:22:11 PM PDT 24
Peak memory 215836 kb
Host smart-7cb6ffe5-8076-47b8-94a5-ed4edfdb1b3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146952378 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.3146952378 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.662798885
Short name T774
Test name
Test status
Simulation time 59264974 ps
CPU time 1.65 seconds
Started Aug 13 05:22:19 PM PDT 24
Finished Aug 13 05:22:20 PM PDT 24
Peak memory 216084 kb
Host smart-be63bd19-ca0c-4d21-b6d7-e9ceabe92bee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662798885 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_csr
_outstanding.662798885 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.1369624202
Short name T860
Test name
Test status
Simulation time 27243072 ps
CPU time 1.25 seconds
Started Aug 13 05:22:09 PM PDT 24
Finished Aug 13 05:22:10 PM PDT 24
Peak memory 216412 kb
Host smart-a04fb19e-873c-43de-b4c1-a40fc2618433
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369624202 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg
_errors.1369624202 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.1052654290
Short name T776
Test name
Test status
Simulation time 75978001 ps
CPU time 2.37 seconds
Started Aug 13 05:22:29 PM PDT 24
Finished Aug 13 05:22:31 PM PDT 24
Peak memory 219132 kb
Host smart-2c8332fb-9177-42cc-ae38-f114fbe4e162
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052654290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kma
c_shadow_reg_errors_with_csr_rw.1052654290 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_tl_errors.2753574779
Short name T734
Test name
Test status
Simulation time 133620332 ps
CPU time 2.41 seconds
Started Aug 13 05:22:54 PM PDT 24
Finished Aug 13 05:22:57 PM PDT 24
Peak memory 216068 kb
Host smart-af45a8ba-bfaa-4ed6-9b23-2bd440987c4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753574779 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.2753574779 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.1697875961
Short name T826
Test name
Test status
Simulation time 58388050 ps
CPU time 2.42 seconds
Started Aug 13 05:22:25 PM PDT 24
Finished Aug 13 05:22:27 PM PDT 24
Peak memory 216152 kb
Host smart-c1080798-6ff2-41ad-9adf-a204769de3e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697875961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.1697
875961 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.598022116
Short name T749
Test name
Test status
Simulation time 44713161 ps
CPU time 1.61 seconds
Started Aug 13 05:22:02 PM PDT 24
Finished Aug 13 05:22:04 PM PDT 24
Peak memory 220816 kb
Host smart-786c62e4-8b08-4c6e-9f96-3f44dc17701b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598022116 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.kmac_csr_mem_rw_with_rand_reset.598022116 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_csr_rw.327961129
Short name T151
Test name
Test status
Simulation time 20089283 ps
CPU time 1 seconds
Started Aug 13 05:22:17 PM PDT 24
Finished Aug 13 05:22:18 PM PDT 24
Peak memory 215844 kb
Host smart-5cfb6e24-b903-46fc-a208-183d5a2bc649
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327961129 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.327961129 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/14.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_intr_test.713306021
Short name T746
Test name
Test status
Simulation time 24173852 ps
CPU time 0.77 seconds
Started Aug 13 05:22:25 PM PDT 24
Finished Aug 13 05:22:25 PM PDT 24
Peak memory 215840 kb
Host smart-c6a99cba-03f7-4d03-8f6b-6d1e36e0ebc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713306021 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.713306021 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/14.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.1526000091
Short name T158
Test name
Test status
Simulation time 66640217 ps
CPU time 1.64 seconds
Started Aug 13 05:22:07 PM PDT 24
Finished Aug 13 05:22:09 PM PDT 24
Peak memory 216088 kb
Host smart-b58cb757-eaf9-4671-b81c-dd3a2f22baf1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526000091 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_cs
r_outstanding.1526000091 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.1026274668
Short name T857
Test name
Test status
Simulation time 106150991 ps
CPU time 1.67 seconds
Started Aug 13 05:22:31 PM PDT 24
Finished Aug 13 05:22:33 PM PDT 24
Peak memory 218700 kb
Host smart-4c2e0501-6be9-4b4c-b58a-264be55067e4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026274668 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kma
c_shadow_reg_errors_with_csr_rw.1026274668 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_tl_errors.1989587910
Short name T839
Test name
Test status
Simulation time 94794148 ps
CPU time 2.66 seconds
Started Aug 13 05:22:07 PM PDT 24
Finished Aug 13 05:22:10 PM PDT 24
Peak memory 216200 kb
Host smart-a2f40881-ce82-4e47-baa1-2b4769cbfbcd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989587910 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.1989587910 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.4005763727
Short name T177
Test name
Test status
Simulation time 250212248 ps
CPU time 2.61 seconds
Started Aug 13 05:22:23 PM PDT 24
Finished Aug 13 05:22:25 PM PDT 24
Peak memory 216064 kb
Host smart-615674df-3a29-429e-aab7-b6e72dfd6b65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005763727 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.4005
763727 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.1068146385
Short name T866
Test name
Test status
Simulation time 102343306 ps
CPU time 1.78 seconds
Started Aug 13 05:22:07 PM PDT 24
Finished Aug 13 05:22:09 PM PDT 24
Peak memory 220048 kb
Host smart-dd67b2e9-4edf-4c96-81d0-949e692a862a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068146385 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.kmac_csr_mem_rw_with_rand_reset.1068146385 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_csr_rw.29759002
Short name T188
Test name
Test status
Simulation time 22087921 ps
CPU time 0.93 seconds
Started Aug 13 05:22:23 PM PDT 24
Finished Aug 13 05:22:24 PM PDT 24
Peak memory 215828 kb
Host smart-2ffcdb87-4aa8-4c6d-a2b0-2de38aa84d19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29759002 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.29759002 +enable_mas
king=1 +sw_key_masked=0
Directory /workspace/15.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_intr_test.1406426317
Short name T792
Test name
Test status
Simulation time 54274571 ps
CPU time 0.79 seconds
Started Aug 13 05:22:27 PM PDT 24
Finished Aug 13 05:22:27 PM PDT 24
Peak memory 215792 kb
Host smart-df71cc94-5782-4745-aabc-dcd5beed6d06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406426317 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.1406426317 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.2814387423
Short name T725
Test name
Test status
Simulation time 89083239 ps
CPU time 1.5 seconds
Started Aug 13 05:22:44 PM PDT 24
Finished Aug 13 05:22:46 PM PDT 24
Peak memory 216024 kb
Host smart-939d91de-bd2d-4042-a0e8-f553926ec353
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814387423 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_cs
r_outstanding.2814387423 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.4272827142
Short name T80
Test name
Test status
Simulation time 187273499 ps
CPU time 1.31 seconds
Started Aug 13 05:22:02 PM PDT 24
Finished Aug 13 05:22:03 PM PDT 24
Peak memory 217284 kb
Host smart-7c430fd3-570c-43a3-91cc-581a8ef12cb5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272827142 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg
_errors.4272827142 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.2704384892
Short name T92
Test name
Test status
Simulation time 115331912 ps
CPU time 2.42 seconds
Started Aug 13 05:22:28 PM PDT 24
Finished Aug 13 05:22:30 PM PDT 24
Peak memory 219788 kb
Host smart-95347cd4-ecaf-4eab-b016-9cd2fa206f12
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704384892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kma
c_shadow_reg_errors_with_csr_rw.2704384892 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_tl_errors.3511817947
Short name T852
Test name
Test status
Simulation time 95265674 ps
CPU time 1.65 seconds
Started Aug 13 05:22:14 PM PDT 24
Finished Aug 13 05:22:15 PM PDT 24
Peak memory 216108 kb
Host smart-61edacb1-a321-46ef-bfe8-81815d4dbfed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511817947 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.3511817947 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.2667238740
Short name T806
Test name
Test status
Simulation time 399273699 ps
CPU time 2.91 seconds
Started Aug 13 05:22:07 PM PDT 24
Finished Aug 13 05:22:10 PM PDT 24
Peak memory 215840 kb
Host smart-f1432d10-f1bb-4637-a7e4-140695d494d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667238740 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.2667
238740 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.825850931
Short name T743
Test name
Test status
Simulation time 91772874 ps
CPU time 1.69 seconds
Started Aug 13 05:22:18 PM PDT 24
Finished Aug 13 05:22:20 PM PDT 24
Peak memory 217736 kb
Host smart-363c7a49-c706-4c36-a1d4-40e93eca9b9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825850931 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.kmac_csr_mem_rw_with_rand_reset.825850931 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_csr_rw.3379900865
Short name T828
Test name
Test status
Simulation time 33159717 ps
CPU time 0.92 seconds
Started Aug 13 05:22:10 PM PDT 24
Finished Aug 13 05:22:11 PM PDT 24
Peak memory 215916 kb
Host smart-b05b606a-88a7-411c-a58a-cdb6bb7d8e9a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379900865 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.3379900865 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_intr_test.1750127942
Short name T777
Test name
Test status
Simulation time 16055089 ps
CPU time 0.75 seconds
Started Aug 13 05:22:32 PM PDT 24
Finished Aug 13 05:22:33 PM PDT 24
Peak memory 215756 kb
Host smart-fe4562e6-9468-4f68-acfb-5d823c4269f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750127942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.1750127942 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.335267885
Short name T784
Test name
Test status
Simulation time 275172437 ps
CPU time 1.6 seconds
Started Aug 13 05:22:16 PM PDT 24
Finished Aug 13 05:22:18 PM PDT 24
Peak memory 216060 kb
Host smart-f278971e-83b5-47d1-b193-4d87d930bd87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335267885 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_csr
_outstanding.335267885 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.3864575652
Short name T87
Test name
Test status
Simulation time 415524270 ps
CPU time 1.19 seconds
Started Aug 13 05:22:34 PM PDT 24
Finished Aug 13 05:22:35 PM PDT 24
Peak memory 216692 kb
Host smart-4d9245c6-fca1-41f5-8521-62de5aab2790
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864575652 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg
_errors.3864575652 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.3668487955
Short name T874
Test name
Test status
Simulation time 34629071 ps
CPU time 1.53 seconds
Started Aug 13 05:22:45 PM PDT 24
Finished Aug 13 05:22:47 PM PDT 24
Peak memory 216148 kb
Host smart-365365b3-3326-4971-8739-31b7cd95e014
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668487955 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kma
c_shadow_reg_errors_with_csr_rw.3668487955 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_tl_errors.1344078015
Short name T829
Test name
Test status
Simulation time 51519491 ps
CPU time 3.05 seconds
Started Aug 13 05:22:25 PM PDT 24
Finished Aug 13 05:22:28 PM PDT 24
Peak memory 216208 kb
Host smart-b1b663e6-4a9e-4499-9d77-a0f1848608fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344078015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.1344078015 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.3762543482
Short name T127
Test name
Test status
Simulation time 394947836 ps
CPU time 3.83 seconds
Started Aug 13 05:22:13 PM PDT 24
Finished Aug 13 05:22:17 PM PDT 24
Peak memory 216168 kb
Host smart-e59bd69a-ab1a-4815-bb62-f8c15d37ae6a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762543482 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.3762
543482 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.1337437110
Short name T155
Test name
Test status
Simulation time 1495750096 ps
CPU time 2.58 seconds
Started Aug 13 05:22:26 PM PDT 24
Finished Aug 13 05:22:29 PM PDT 24
Peak memory 221412 kb
Host smart-28a287d6-8be6-4f1f-9e75-00f038e3bcfe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337437110 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.kmac_csr_mem_rw_with_rand_reset.1337437110 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_csr_rw.2857271050
Short name T869
Test name
Test status
Simulation time 21529204 ps
CPU time 0.99 seconds
Started Aug 13 05:22:31 PM PDT 24
Finished Aug 13 05:22:32 PM PDT 24
Peak memory 215704 kb
Host smart-39654446-52ec-44db-80c7-5a28c090156a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857271050 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.2857271050 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_intr_test.2590614295
Short name T845
Test name
Test status
Simulation time 19871459 ps
CPU time 0.81 seconds
Started Aug 13 05:22:33 PM PDT 24
Finished Aug 13 05:22:34 PM PDT 24
Peak memory 215520 kb
Host smart-ff7e181c-559e-4b54-ba16-7c55ca5267e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590614295 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.2590614295 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.2738512806
Short name T149
Test name
Test status
Simulation time 58401348 ps
CPU time 1.64 seconds
Started Aug 13 05:22:12 PM PDT 24
Finished Aug 13 05:22:14 PM PDT 24
Peak memory 216152 kb
Host smart-c49a256b-dc7c-419d-b9d7-9925dcf4b690
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738512806 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_cs
r_outstanding.2738512806 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.3691584237
Short name T86
Test name
Test status
Simulation time 17727494 ps
CPU time 1.07 seconds
Started Aug 13 05:22:29 PM PDT 24
Finished Aug 13 05:22:30 PM PDT 24
Peak memory 216112 kb
Host smart-82257cf1-6b7a-4e2b-a2f5-da0e438f4bab
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691584237 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg
_errors.3691584237 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_tl_errors.3807353799
Short name T134
Test name
Test status
Simulation time 131536992 ps
CPU time 3.47 seconds
Started Aug 13 05:22:48 PM PDT 24
Finished Aug 13 05:22:52 PM PDT 24
Peak memory 216188 kb
Host smart-313b259b-a030-4cfe-bdd2-821e280d690f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807353799 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.3807353799 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.3151038010
Short name T126
Test name
Test status
Simulation time 234930307 ps
CPU time 2.88 seconds
Started Aug 13 05:22:10 PM PDT 24
Finished Aug 13 05:22:13 PM PDT 24
Peak memory 216048 kb
Host smart-083ec610-6872-4e9c-99c3-3792bcf134a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151038010 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.3151
038010 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.3424869352
Short name T871
Test name
Test status
Simulation time 160560345 ps
CPU time 1.63 seconds
Started Aug 13 05:22:16 PM PDT 24
Finished Aug 13 05:22:17 PM PDT 24
Peak memory 220016 kb
Host smart-1a87ef77-fa16-44c6-80c0-b091cbe7395b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424869352 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.kmac_csr_mem_rw_with_rand_reset.3424869352 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_csr_rw.2605686407
Short name T738
Test name
Test status
Simulation time 20525411 ps
CPU time 0.93 seconds
Started Aug 13 05:22:15 PM PDT 24
Finished Aug 13 05:22:16 PM PDT 24
Peak memory 215940 kb
Host smart-c14a0329-805f-475b-8c91-6aff64721e64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605686407 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.2605686407 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_intr_test.1093336259
Short name T855
Test name
Test status
Simulation time 33988800 ps
CPU time 0.8 seconds
Started Aug 13 05:22:11 PM PDT 24
Finished Aug 13 05:22:12 PM PDT 24
Peak memory 215864 kb
Host smart-98970ebf-95e3-4b4e-b049-bf75b8aae96b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093336259 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.1093336259 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.591028794
Short name T150
Test name
Test status
Simulation time 360206048 ps
CPU time 1.56 seconds
Started Aug 13 05:22:40 PM PDT 24
Finished Aug 13 05:22:42 PM PDT 24
Peak memory 216020 kb
Host smart-0406e64d-498e-44de-a0f8-ffcac59edc23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591028794 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_csr
_outstanding.591028794 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.1365643312
Short name T781
Test name
Test status
Simulation time 26950315 ps
CPU time 0.97 seconds
Started Aug 13 05:22:36 PM PDT 24
Finished Aug 13 05:22:37 PM PDT 24
Peak memory 216196 kb
Host smart-9f8ae2bc-ada0-49ce-9f89-56555bfc96aa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365643312 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg
_errors.1365643312 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.2416054948
Short name T841
Test name
Test status
Simulation time 117183023 ps
CPU time 2.79 seconds
Started Aug 13 05:22:23 PM PDT 24
Finished Aug 13 05:22:26 PM PDT 24
Peak memory 218748 kb
Host smart-3a6089ca-1887-4d39-ad9d-6e153725188d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416054948 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kma
c_shadow_reg_errors_with_csr_rw.2416054948 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_tl_errors.11509825
Short name T733
Test name
Test status
Simulation time 265375944 ps
CPU time 2.12 seconds
Started Aug 13 05:22:22 PM PDT 24
Finished Aug 13 05:22:24 PM PDT 24
Peak memory 216072 kb
Host smart-8461f8be-b735-4c4a-b21d-141cc50448ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11509825 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.11509825 +enable_mas
king=1 +sw_key_masked=0
Directory /workspace/18.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.324163159
Short name T873
Test name
Test status
Simulation time 370784495 ps
CPU time 4.12 seconds
Started Aug 13 05:22:12 PM PDT 24
Finished Aug 13 05:22:16 PM PDT 24
Peak memory 216144 kb
Host smart-21a72c1d-84a9-499d-bf18-66eb2d71ed9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324163159 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.32416
3159 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.920954368
Short name T808
Test name
Test status
Simulation time 99521871 ps
CPU time 2.19 seconds
Started Aug 13 05:22:44 PM PDT 24
Finished Aug 13 05:22:46 PM PDT 24
Peak memory 218084 kb
Host smart-8c80a276-29d7-442b-9d4e-65666565ba76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920954368 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.kmac_csr_mem_rw_with_rand_reset.920954368 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_csr_rw.3551699556
Short name T876
Test name
Test status
Simulation time 22475284 ps
CPU time 1.01 seconds
Started Aug 13 05:22:31 PM PDT 24
Finished Aug 13 05:22:32 PM PDT 24
Peak memory 215932 kb
Host smart-73e4366f-fa6d-4f29-bb61-ec2e5635b691
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551699556 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.3551699556 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_intr_test.1293396734
Short name T168
Test name
Test status
Simulation time 13766102 ps
CPU time 0.83 seconds
Started Aug 13 05:22:21 PM PDT 24
Finished Aug 13 05:22:22 PM PDT 24
Peak memory 215844 kb
Host smart-49915752-5a87-465a-ac56-5bb0527cb8bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293396734 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.1293396734 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.799505671
Short name T779
Test name
Test status
Simulation time 29423856 ps
CPU time 1.58 seconds
Started Aug 13 05:22:23 PM PDT 24
Finished Aug 13 05:22:25 PM PDT 24
Peak memory 216004 kb
Host smart-88e309d9-ee5b-47ac-bc5e-9e1193fb7a09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799505671 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_csr
_outstanding.799505671 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.3730611291
Short name T838
Test name
Test status
Simulation time 114487025 ps
CPU time 0.98 seconds
Started Aug 13 05:22:22 PM PDT 24
Finished Aug 13 05:22:23 PM PDT 24
Peak memory 215900 kb
Host smart-f1205f6c-5be2-492f-ab71-a0525758832b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730611291 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg
_errors.3730611291 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.113737747
Short name T803
Test name
Test status
Simulation time 230976095 ps
CPU time 1.93 seconds
Started Aug 13 05:22:42 PM PDT 24
Finished Aug 13 05:22:44 PM PDT 24
Peak memory 219960 kb
Host smart-7cf41ae9-5e3d-44cc-b1d5-9f7dd9b3a042
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113737747 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac
_shadow_reg_errors_with_csr_rw.113737747 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_tl_errors.3148142601
Short name T800
Test name
Test status
Simulation time 671085527 ps
CPU time 3.87 seconds
Started Aug 13 05:22:09 PM PDT 24
Finished Aug 13 05:22:13 PM PDT 24
Peak memory 216020 kb
Host smart-a9bb8b90-fb9d-4c2c-b165-a518287ffaad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148142601 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.3148142601 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.2528389719
Short name T181
Test name
Test status
Simulation time 127416726 ps
CPU time 2.74 seconds
Started Aug 13 05:22:24 PM PDT 24
Finished Aug 13 05:22:27 PM PDT 24
Peak memory 215992 kb
Host smart-91f17e0c-3346-4f81-8207-6cb24b3bff35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528389719 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.2528
389719 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.3808587990
Short name T814
Test name
Test status
Simulation time 539761382 ps
CPU time 5.44 seconds
Started Aug 13 05:22:13 PM PDT 24
Finished Aug 13 05:22:19 PM PDT 24
Peak memory 216028 kb
Host smart-6bafc8b2-6e5f-4526-b7ed-662ca3610f24
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808587990 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.3808587
990 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.4129964325
Short name T863
Test name
Test status
Simulation time 2026652121 ps
CPU time 9.73 seconds
Started Aug 13 05:21:59 PM PDT 24
Finished Aug 13 05:22:09 PM PDT 24
Peak memory 216060 kb
Host smart-3d422e11-8996-4f28-92d2-2940eafdc9c0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129964325 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.4129964
325 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.220345322
Short name T824
Test name
Test status
Simulation time 58391846 ps
CPU time 1.21 seconds
Started Aug 13 05:22:08 PM PDT 24
Finished Aug 13 05:22:10 PM PDT 24
Peak memory 216172 kb
Host smart-e42a5f05-28d4-45fa-b79a-9679aae8d07d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220345322 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.22034532
2 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.3062787304
Short name T817
Test name
Test status
Simulation time 537458211 ps
CPU time 2.64 seconds
Started Aug 13 05:22:03 PM PDT 24
Finished Aug 13 05:22:06 PM PDT 24
Peak memory 221840 kb
Host smart-dfffe48b-db5d-4cea-b546-bbc5cf4e0318
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062787304 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.kmac_csr_mem_rw_with_rand_reset.3062787304 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_rw.1862880411
Short name T736
Test name
Test status
Simulation time 22824993 ps
CPU time 1 seconds
Started Aug 13 05:22:06 PM PDT 24
Finished Aug 13 05:22:07 PM PDT 24
Peak memory 215868 kb
Host smart-a06de43a-db75-4974-8c2b-f35cbd53f5b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862880411 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.1862880411 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_intr_test.106557236
Short name T830
Test name
Test status
Simulation time 14068096 ps
CPU time 0.78 seconds
Started Aug 13 05:21:58 PM PDT 24
Finished Aug 13 05:21:59 PM PDT 24
Peak memory 215744 kb
Host smart-dc03659e-9b87-4a00-b7f2-c227e3937e3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106557236 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.106557236 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/2.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.1055107880
Short name T853
Test name
Test status
Simulation time 39059020 ps
CPU time 1.46 seconds
Started Aug 13 05:22:34 PM PDT 24
Finished Aug 13 05:22:36 PM PDT 24
Peak memory 216004 kb
Host smart-2ea51aea-30b8-4a26-846b-89491f223c26
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055107880 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partia
l_access.1055107880 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_mem_walk.295874225
Short name T742
Test name
Test status
Simulation time 19466949 ps
CPU time 0.75 seconds
Started Aug 13 05:22:15 PM PDT 24
Finished Aug 13 05:22:15 PM PDT 24
Peak memory 215828 kb
Host smart-04a57ee5-b9e4-45aa-babd-e94137788d4e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295874225 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.295874225 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.958157000
Short name T730
Test name
Test status
Simulation time 84512832 ps
CPU time 2.43 seconds
Started Aug 13 05:22:04 PM PDT 24
Finished Aug 13 05:22:07 PM PDT 24
Peak memory 216032 kb
Host smart-cbb00d30-3315-4c3f-bed8-9ed645730d74
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958157000 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr_
outstanding.958157000 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.2689387054
Short name T81
Test name
Test status
Simulation time 21299214 ps
CPU time 1.07 seconds
Started Aug 13 05:22:02 PM PDT 24
Finished Aug 13 05:22:03 PM PDT 24
Peak memory 216232 kb
Host smart-89c29083-24a4-446a-b772-88d5e7e1c7f0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689387054 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_
errors.2689387054 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.2513449629
Short name T84
Test name
Test status
Simulation time 282492140 ps
CPU time 1.6 seconds
Started Aug 13 05:22:10 PM PDT 24
Finished Aug 13 05:22:12 PM PDT 24
Peak memory 216060 kb
Host smart-37169d9c-fdcd-4007-9e1e-cc0d548a2b38
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513449629 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac
_shadow_reg_errors_with_csr_rw.2513449629 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_tl_errors.1603802848
Short name T875
Test name
Test status
Simulation time 78399452 ps
CPU time 2.19 seconds
Started Aug 13 05:21:56 PM PDT 24
Finished Aug 13 05:21:58 PM PDT 24
Peak memory 216184 kb
Host smart-d080b7f6-7066-4b7d-b054-aaf52c6031ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603802848 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.1603802848 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.4109065029
Short name T184
Test name
Test status
Simulation time 346764676 ps
CPU time 4.02 seconds
Started Aug 13 05:21:58 PM PDT 24
Finished Aug 13 05:22:02 PM PDT 24
Peak memory 216048 kb
Host smart-8eeb2d18-ea55-417f-ac86-362b79846d94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109065029 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.41090
65029 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.kmac_intr_test.2872092539
Short name T161
Test name
Test status
Simulation time 31717315 ps
CPU time 0.79 seconds
Started Aug 13 05:22:43 PM PDT 24
Finished Aug 13 05:22:44 PM PDT 24
Peak memory 215812 kb
Host smart-8a086dbe-fcaa-4082-ae79-73a1632add28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872092539 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.2872092539 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.kmac_intr_test.71590056
Short name T760
Test name
Test status
Simulation time 15015637 ps
CPU time 0.81 seconds
Started Aug 13 05:22:44 PM PDT 24
Finished Aug 13 05:22:45 PM PDT 24
Peak memory 215784 kb
Host smart-da079745-b68b-4ce9-8aa4-ea31cb1ec2fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71590056 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.71590056 +enable_mas
king=1 +sw_key_masked=0
Directory /workspace/21.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.kmac_intr_test.1376148742
Short name T162
Test name
Test status
Simulation time 14985105 ps
CPU time 0.82 seconds
Started Aug 13 05:22:24 PM PDT 24
Finished Aug 13 05:22:25 PM PDT 24
Peak memory 215768 kb
Host smart-151dba94-8dff-475b-8690-a59d6e076713
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376148742 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.1376148742 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.kmac_intr_test.2326014561
Short name T858
Test name
Test status
Simulation time 84073847 ps
CPU time 0.8 seconds
Started Aug 13 05:22:16 PM PDT 24
Finished Aug 13 05:22:17 PM PDT 24
Peak memory 215748 kb
Host smart-835baa55-27ae-48c9-bb76-12c9e160be10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326014561 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.2326014561 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.kmac_intr_test.1492742844
Short name T807
Test name
Test status
Simulation time 16130692 ps
CPU time 0.79 seconds
Started Aug 13 05:22:22 PM PDT 24
Finished Aug 13 05:22:23 PM PDT 24
Peak memory 215804 kb
Host smart-744fb62d-87d6-4973-b14a-5394ec192770
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492742844 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.1492742844 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.kmac_intr_test.208443237
Short name T750
Test name
Test status
Simulation time 14833360 ps
CPU time 0.83 seconds
Started Aug 13 05:22:33 PM PDT 24
Finished Aug 13 05:22:34 PM PDT 24
Peak memory 215828 kb
Host smart-e090c89c-65c0-456d-b209-4a93e2dfa7e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208443237 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.208443237 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/26.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.kmac_intr_test.2405569820
Short name T796
Test name
Test status
Simulation time 19915009 ps
CPU time 0.86 seconds
Started Aug 13 05:22:42 PM PDT 24
Finished Aug 13 05:22:43 PM PDT 24
Peak memory 215460 kb
Host smart-42ddc824-4032-44cb-813a-5c4647766ecf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405569820 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.2405569820 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.kmac_intr_test.1774740655
Short name T810
Test name
Test status
Simulation time 36617617 ps
CPU time 0.75 seconds
Started Aug 13 05:22:26 PM PDT 24
Finished Aug 13 05:22:27 PM PDT 24
Peak memory 215844 kb
Host smart-48a3c849-0ba0-4af0-b62a-1435bb331663
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774740655 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.1774740655 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.kmac_intr_test.2268594370
Short name T753
Test name
Test status
Simulation time 16395767 ps
CPU time 0.78 seconds
Started Aug 13 05:22:17 PM PDT 24
Finished Aug 13 05:22:18 PM PDT 24
Peak memory 215844 kb
Host smart-99fbc635-2b95-4c34-a029-a64eceb96f20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268594370 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.2268594370 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.517975819
Short name T797
Test name
Test status
Simulation time 140194226 ps
CPU time 7.79 seconds
Started Aug 13 05:22:19 PM PDT 24
Finished Aug 13 05:22:27 PM PDT 24
Peak memory 216096 kb
Host smart-ff0dbdde-c9ad-44de-92b4-c32e2fa40893
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517975819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.51797581
9 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.1162343271
Short name T842
Test name
Test status
Simulation time 3317087173 ps
CPU time 10.87 seconds
Started Aug 13 05:22:04 PM PDT 24
Finished Aug 13 05:22:15 PM PDT 24
Peak memory 216112 kb
Host smart-8a1e1106-be9c-4a66-ab76-565101bafacd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162343271 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.1162343
271 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.3609509811
Short name T758
Test name
Test status
Simulation time 109438920 ps
CPU time 1.14 seconds
Started Aug 13 05:22:11 PM PDT 24
Finished Aug 13 05:22:12 PM PDT 24
Peak memory 216036 kb
Host smart-88a6bd01-3fb3-4fbe-8920-77aba9fbbe32
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609509811 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.3609509
811 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.811990975
Short name T744
Test name
Test status
Simulation time 97712655 ps
CPU time 2.1 seconds
Started Aug 13 05:22:03 PM PDT 24
Finished Aug 13 05:22:05 PM PDT 24
Peak memory 222520 kb
Host smart-285b1223-8e33-4d7e-bc05-ab3defe5e63b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811990975 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.kmac_csr_mem_rw_with_rand_reset.811990975 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_rw.2263217253
Short name T186
Test name
Test status
Simulation time 28944574 ps
CPU time 1.12 seconds
Started Aug 13 05:22:08 PM PDT 24
Finished Aug 13 05:22:09 PM PDT 24
Peak memory 215988 kb
Host smart-75c5fae1-569e-4867-a2af-d5f2db87a6b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263217253 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.2263217253 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_intr_test.499095380
Short name T761
Test name
Test status
Simulation time 16214283 ps
CPU time 0.8 seconds
Started Aug 13 05:22:03 PM PDT 24
Finished Aug 13 05:22:04 PM PDT 24
Peak memory 215836 kb
Host smart-734084ca-18ce-41a4-8646-c1f3cd963d3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499095380 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.499095380 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/3.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.2716455881
Short name T145
Test name
Test status
Simulation time 50901194 ps
CPU time 1.23 seconds
Started Aug 13 05:21:56 PM PDT 24
Finished Aug 13 05:21:57 PM PDT 24
Peak memory 216004 kb
Host smart-41bf2aa1-313a-4ee6-8da9-43cec194bde0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716455881 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partia
l_access.2716455881 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_mem_walk.1540148957
Short name T856
Test name
Test status
Simulation time 12912368 ps
CPU time 0.75 seconds
Started Aug 13 05:22:06 PM PDT 24
Finished Aug 13 05:22:07 PM PDT 24
Peak memory 215864 kb
Host smart-cf2b1e36-d04d-44d6-b722-e8742f125794
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540148957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.1540148957
+enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.3912922657
Short name T745
Test name
Test status
Simulation time 71739234 ps
CPU time 2.13 seconds
Started Aug 13 05:21:59 PM PDT 24
Finished Aug 13 05:22:02 PM PDT 24
Peak memory 216128 kb
Host smart-5cc64659-6aae-438e-a9be-98ab8bc55c11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912922657 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr
_outstanding.3912922657 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.3238900578
Short name T786
Test name
Test status
Simulation time 252657827 ps
CPU time 1.46 seconds
Started Aug 13 05:22:04 PM PDT 24
Finished Aug 13 05:22:05 PM PDT 24
Peak memory 217408 kb
Host smart-48a1a4c8-4b3d-4275-96dd-ebfd171175bc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238900578 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_
errors.3238900578 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.2948195440
Short name T815
Test name
Test status
Simulation time 171051518 ps
CPU time 2.99 seconds
Started Aug 13 05:22:27 PM PDT 24
Finished Aug 13 05:22:30 PM PDT 24
Peak memory 218904 kb
Host smart-0c2944b1-20a4-45d2-bb79-0a8a49ee3bf5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948195440 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac
_shadow_reg_errors_with_csr_rw.2948195440 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_tl_errors.2237568607
Short name T832
Test name
Test status
Simulation time 298703182 ps
CPU time 2.56 seconds
Started Aug 13 05:22:07 PM PDT 24
Finished Aug 13 05:22:10 PM PDT 24
Peak memory 216176 kb
Host smart-cd8cf510-434d-4807-9dcb-f7e7a428464d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237568607 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.2237568607 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.kmac_intr_test.292867478
Short name T163
Test name
Test status
Simulation time 27363513 ps
CPU time 0.82 seconds
Started Aug 13 05:22:13 PM PDT 24
Finished Aug 13 05:22:14 PM PDT 24
Peak memory 215588 kb
Host smart-b0430359-9351-4005-8db2-2090c776b49d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292867478 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.292867478 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/30.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.kmac_intr_test.934508895
Short name T844
Test name
Test status
Simulation time 106138535 ps
CPU time 0.8 seconds
Started Aug 13 05:22:12 PM PDT 24
Finished Aug 13 05:22:13 PM PDT 24
Peak memory 215684 kb
Host smart-f0df3ae6-cdca-4ce9-8496-d6ef8a2bf86c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934508895 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.934508895 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/31.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.kmac_intr_test.3067312233
Short name T788
Test name
Test status
Simulation time 36902272 ps
CPU time 0.78 seconds
Started Aug 13 05:22:16 PM PDT 24
Finished Aug 13 05:22:17 PM PDT 24
Peak memory 215864 kb
Host smart-7993433b-3d0c-4aa7-aac1-7c8ea1e5b401
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067312233 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.3067312233 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.kmac_intr_test.1268857599
Short name T763
Test name
Test status
Simulation time 20923459 ps
CPU time 0.76 seconds
Started Aug 13 05:22:29 PM PDT 24
Finished Aug 13 05:22:30 PM PDT 24
Peak memory 215832 kb
Host smart-979f5ac1-223d-43b3-86a8-1ec3780c9f96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268857599 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.1268857599 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.kmac_intr_test.2716138431
Short name T836
Test name
Test status
Simulation time 63807792 ps
CPU time 0.8 seconds
Started Aug 13 05:22:35 PM PDT 24
Finished Aug 13 05:22:36 PM PDT 24
Peak memory 215760 kb
Host smart-e1a0ee3a-1484-425b-83a1-56704cdc6a83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716138431 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.2716138431 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.kmac_intr_test.3285466303
Short name T130
Test name
Test status
Simulation time 15907419 ps
CPU time 0.83 seconds
Started Aug 13 05:22:15 PM PDT 24
Finished Aug 13 05:22:16 PM PDT 24
Peak memory 215788 kb
Host smart-25d077dd-cd32-414e-9924-e4b20b4cee5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285466303 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.3285466303 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.kmac_intr_test.1927404533
Short name T846
Test name
Test status
Simulation time 42347865 ps
CPU time 0.79 seconds
Started Aug 13 05:22:46 PM PDT 24
Finished Aug 13 05:22:47 PM PDT 24
Peak memory 215752 kb
Host smart-e25954fe-7bea-412b-93fa-67713556b105
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927404533 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.1927404533 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.kmac_intr_test.2378595395
Short name T825
Test name
Test status
Simulation time 13946164 ps
CPU time 0.79 seconds
Started Aug 13 05:22:17 PM PDT 24
Finished Aug 13 05:22:18 PM PDT 24
Peak memory 215804 kb
Host smart-c4d1084a-48eb-4a87-a0d8-63fbfdf24dc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378595395 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.2378595395 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.kmac_intr_test.387302027
Short name T129
Test name
Test status
Simulation time 11999052 ps
CPU time 0.79 seconds
Started Aug 13 05:22:42 PM PDT 24
Finished Aug 13 05:22:43 PM PDT 24
Peak memory 215604 kb
Host smart-4583b5df-71af-4888-a40b-51287204fe26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387302027 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.387302027 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/38.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.kmac_intr_test.2875779069
Short name T864
Test name
Test status
Simulation time 14244959 ps
CPU time 0.77 seconds
Started Aug 13 05:22:29 PM PDT 24
Finished Aug 13 05:22:30 PM PDT 24
Peak memory 215764 kb
Host smart-e3ecdf2b-5794-481b-9a9a-63129d5d8f25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875779069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.2875779069 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.3258176322
Short name T739
Test name
Test status
Simulation time 664991234 ps
CPU time 9.62 seconds
Started Aug 13 05:22:01 PM PDT 24
Finished Aug 13 05:22:11 PM PDT 24
Peak memory 216048 kb
Host smart-522319c3-adf8-4037-a5dd-e98e407c4c27
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258176322 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.3258176
322 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.3707672131
Short name T868
Test name
Test status
Simulation time 3842840543 ps
CPU time 18.44 seconds
Started Aug 13 05:22:14 PM PDT 24
Finished Aug 13 05:22:33 PM PDT 24
Peak memory 216204 kb
Host smart-9c8a8048-df51-4502-a2c2-3de40218281d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707672131 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.3707672
131 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.3877101649
Short name T752
Test name
Test status
Simulation time 53657399 ps
CPU time 0.94 seconds
Started Aug 13 05:21:58 PM PDT 24
Finished Aug 13 05:22:00 PM PDT 24
Peak memory 215824 kb
Host smart-f8998d66-4636-48a2-a86e-2d3c1e7f2bb7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877101649 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.3877101
649 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.3672885504
Short name T135
Test name
Test status
Simulation time 52444591 ps
CPU time 1.64 seconds
Started Aug 13 05:21:57 PM PDT 24
Finished Aug 13 05:21:58 PM PDT 24
Peak memory 219476 kb
Host smart-b94a52ef-cb59-4f87-8737-67ac615bd882
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672885504 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.kmac_csr_mem_rw_with_rand_reset.3672885504 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_rw.896131648
Short name T153
Test name
Test status
Simulation time 27747140 ps
CPU time 0.97 seconds
Started Aug 13 05:22:15 PM PDT 24
Finished Aug 13 05:22:16 PM PDT 24
Peak memory 215824 kb
Host smart-0896eeaf-7470-4ac9-97d7-bc61d2c309e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896131648 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.896131648 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_intr_test.666661733
Short name T166
Test name
Test status
Simulation time 51888132 ps
CPU time 0.8 seconds
Started Aug 13 05:22:19 PM PDT 24
Finished Aug 13 05:22:20 PM PDT 24
Peak memory 215704 kb
Host smart-51678849-c4ca-4dd5-901f-dfccf4997c83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666661733 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.666661733 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/4.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.3532875388
Short name T142
Test name
Test status
Simulation time 76936465 ps
CPU time 1.31 seconds
Started Aug 13 05:22:09 PM PDT 24
Finished Aug 13 05:22:10 PM PDT 24
Peak memory 215996 kb
Host smart-fb49b097-c505-41ed-b50f-f4d053a14780
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532875388 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partia
l_access.3532875388 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_mem_walk.3465877116
Short name T722
Test name
Test status
Simulation time 39146464 ps
CPU time 0.72 seconds
Started Aug 13 05:22:08 PM PDT 24
Finished Aug 13 05:22:09 PM PDT 24
Peak memory 215804 kb
Host smart-44c3ad1e-2611-4b32-a701-9a407de28c42
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465877116 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.3465877116
+enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.1164293469
Short name T152
Test name
Test status
Simulation time 210116552 ps
CPU time 2.76 seconds
Started Aug 13 05:22:08 PM PDT 24
Finished Aug 13 05:22:11 PM PDT 24
Peak memory 216096 kb
Host smart-6503ab02-bb1e-4633-a20b-7ccad06418af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164293469 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr
_outstanding.1164293469 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.3122666489
Short name T872
Test name
Test status
Simulation time 81658129 ps
CPU time 1.33 seconds
Started Aug 13 05:22:07 PM PDT 24
Finished Aug 13 05:22:08 PM PDT 24
Peak memory 216372 kb
Host smart-bd7d66dd-2504-4e19-93d9-8caa95b2c0b3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122666489 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_
errors.3122666489 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.1377862803
Short name T769
Test name
Test status
Simulation time 198234227 ps
CPU time 2.89 seconds
Started Aug 13 05:22:15 PM PDT 24
Finished Aug 13 05:22:18 PM PDT 24
Peak memory 219024 kb
Host smart-85f3a7d2-af81-40a3-b89f-47e64e29a77d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377862803 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac
_shadow_reg_errors_with_csr_rw.1377862803 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_tl_errors.2868227573
Short name T843
Test name
Test status
Simulation time 245771658 ps
CPU time 3.38 seconds
Started Aug 13 05:22:06 PM PDT 24
Finished Aug 13 05:22:09 PM PDT 24
Peak memory 216140 kb
Host smart-0069b5fb-3c0c-4c71-bc7c-d0965953817c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868227573 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.2868227573 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.717080737
Short name T176
Test name
Test status
Simulation time 503545721 ps
CPU time 5.04 seconds
Started Aug 13 05:22:06 PM PDT 24
Finished Aug 13 05:22:11 PM PDT 24
Peak memory 216060 kb
Host smart-aa48d494-fcfe-4fbd-a95a-76909bc70ca1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717080737 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.717080
737 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.kmac_intr_test.4192441326
Short name T850
Test name
Test status
Simulation time 40135018 ps
CPU time 0.79 seconds
Started Aug 13 05:22:17 PM PDT 24
Finished Aug 13 05:22:18 PM PDT 24
Peak memory 215844 kb
Host smart-92560ee6-241a-4455-9639-4dfbca616171
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192441326 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.4192441326 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.kmac_intr_test.488900966
Short name T751
Test name
Test status
Simulation time 13811375 ps
CPU time 0.78 seconds
Started Aug 13 05:22:15 PM PDT 24
Finished Aug 13 05:22:16 PM PDT 24
Peak memory 215752 kb
Host smart-ed2d9868-57b2-4516-9a82-9b4cdee147d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488900966 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.488900966 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/41.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.kmac_intr_test.3027660216
Short name T728
Test name
Test status
Simulation time 39698317 ps
CPU time 0.75 seconds
Started Aug 13 05:22:22 PM PDT 24
Finished Aug 13 05:22:23 PM PDT 24
Peak memory 215684 kb
Host smart-5b5733f2-1083-42fc-a749-9d0f0de1c958
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027660216 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.3027660216 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.kmac_intr_test.746360392
Short name T766
Test name
Test status
Simulation time 41040551 ps
CPU time 0.79 seconds
Started Aug 13 05:22:24 PM PDT 24
Finished Aug 13 05:22:25 PM PDT 24
Peak memory 215736 kb
Host smart-2754bf64-b74b-4074-ba0b-66370e35f920
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746360392 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.746360392 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/43.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.kmac_intr_test.3117970214
Short name T854
Test name
Test status
Simulation time 26337400 ps
CPU time 0.78 seconds
Started Aug 13 05:22:32 PM PDT 24
Finished Aug 13 05:22:33 PM PDT 24
Peak memory 215768 kb
Host smart-ba3b80b5-fe07-4dc2-bde4-c0ed751d234e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117970214 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.3117970214 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.kmac_intr_test.2065950189
Short name T757
Test name
Test status
Simulation time 19153050 ps
CPU time 0.78 seconds
Started Aug 13 05:22:29 PM PDT 24
Finished Aug 13 05:22:30 PM PDT 24
Peak memory 215720 kb
Host smart-bfd91d00-8a2f-4713-aa3f-594c8342a548
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065950189 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.2065950189 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.kmac_intr_test.1098841659
Short name T164
Test name
Test status
Simulation time 55703095 ps
CPU time 0.79 seconds
Started Aug 13 05:22:47 PM PDT 24
Finished Aug 13 05:22:48 PM PDT 24
Peak memory 215832 kb
Host smart-66da4d72-5837-4537-a94d-c6d4e6f159e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098841659 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.1098841659 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.kmac_intr_test.3203602420
Short name T731
Test name
Test status
Simulation time 39333598 ps
CPU time 0.78 seconds
Started Aug 13 05:22:42 PM PDT 24
Finished Aug 13 05:22:43 PM PDT 24
Peak memory 215784 kb
Host smart-827a56f4-8216-4c9f-b435-c58848311567
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203602420 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.3203602420 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.kmac_intr_test.2159901331
Short name T787
Test name
Test status
Simulation time 16610652 ps
CPU time 0.78 seconds
Started Aug 13 05:22:18 PM PDT 24
Finished Aug 13 05:22:19 PM PDT 24
Peak memory 215732 kb
Host smart-e799229e-b897-45dc-91c5-8575a67768fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159901331 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.2159901331 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.kmac_intr_test.1960380922
Short name T170
Test name
Test status
Simulation time 51797940 ps
CPU time 0.77 seconds
Started Aug 13 05:22:30 PM PDT 24
Finished Aug 13 05:22:31 PM PDT 24
Peak memory 215812 kb
Host smart-87475de4-2c67-4879-bbd2-5f963ae1d130
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960380922 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.1960380922 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.3567249688
Short name T755
Test name
Test status
Simulation time 168340048 ps
CPU time 1.66 seconds
Started Aug 13 05:22:02 PM PDT 24
Finished Aug 13 05:22:03 PM PDT 24
Peak memory 217064 kb
Host smart-87641451-9549-46fe-8122-39133f24a8b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567249688 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.kmac_csr_mem_rw_with_rand_reset.3567249688 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_csr_rw.2687243285
Short name T775
Test name
Test status
Simulation time 53462731 ps
CPU time 0.99 seconds
Started Aug 13 05:21:59 PM PDT 24
Finished Aug 13 05:22:00 PM PDT 24
Peak memory 215864 kb
Host smart-0f18607a-2895-4948-9b64-91c8ea3b64fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687243285 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.2687243285 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_intr_test.3355697628
Short name T165
Test name
Test status
Simulation time 33106471 ps
CPU time 0.82 seconds
Started Aug 13 05:22:08 PM PDT 24
Finished Aug 13 05:22:09 PM PDT 24
Peak memory 215840 kb
Host smart-26590424-9126-4ea3-bc37-e4ac759f0507
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355697628 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.3355697628 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.722761432
Short name T794
Test name
Test status
Simulation time 56070654 ps
CPU time 1.57 seconds
Started Aug 13 05:21:59 PM PDT 24
Finished Aug 13 05:22:01 PM PDT 24
Peak memory 216324 kb
Host smart-1b9e7d8f-fab7-4adc-8c90-841ee7c195bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722761432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr_
outstanding.722761432 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.3875083998
Short name T780
Test name
Test status
Simulation time 401419039 ps
CPU time 1.46 seconds
Started Aug 13 05:22:30 PM PDT 24
Finished Aug 13 05:22:31 PM PDT 24
Peak memory 217404 kb
Host smart-2033cebf-8d4a-46b1-ba4c-57c2c99178be
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875083998 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_
errors.3875083998 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.467845196
Short name T89
Test name
Test status
Simulation time 243321306 ps
CPU time 2.33 seconds
Started Aug 13 05:22:09 PM PDT 24
Finished Aug 13 05:22:11 PM PDT 24
Peak memory 219836 kb
Host smart-8bff9a06-97ab-412c-afd2-06ffcd3a9d8b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467845196 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_
shadow_reg_errors_with_csr_rw.467845196 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_tl_errors.3435952212
Short name T729
Test name
Test status
Simulation time 818363419 ps
CPU time 2.2 seconds
Started Aug 13 05:22:05 PM PDT 24
Finished Aug 13 05:22:07 PM PDT 24
Peak memory 216184 kb
Host smart-22beda72-b40a-4e6b-8d81-b29cf87d2bec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435952212 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.3435952212 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.3479186683
Short name T791
Test name
Test status
Simulation time 385252759 ps
CPU time 4.84 seconds
Started Aug 13 05:22:08 PM PDT 24
Finished Aug 13 05:22:13 PM PDT 24
Peak memory 216104 kb
Host smart-eafa2cc4-8662-42dd-abcc-96e3bdbd03d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479186683 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.34791
86683 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.1010497283
Short name T741
Test name
Test status
Simulation time 38631887 ps
CPU time 2.57 seconds
Started Aug 13 05:22:07 PM PDT 24
Finished Aug 13 05:22:10 PM PDT 24
Peak memory 221668 kb
Host smart-7bf497a9-59c0-42ca-a5cf-b20b2033a095
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010497283 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.kmac_csr_mem_rw_with_rand_reset.1010497283 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_csr_rw.3824168957
Short name T782
Test name
Test status
Simulation time 98695607 ps
CPU time 1.12 seconds
Started Aug 13 05:22:05 PM PDT 24
Finished Aug 13 05:22:06 PM PDT 24
Peak memory 216152 kb
Host smart-c31c7e42-1378-4488-8f22-78549430cdf9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824168957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.3824168957 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_intr_test.3217303338
Short name T128
Test name
Test status
Simulation time 15264060 ps
CPU time 0.83 seconds
Started Aug 13 05:22:06 PM PDT 24
Finished Aug 13 05:22:07 PM PDT 24
Peak memory 215760 kb
Host smart-411dedc9-003d-4516-ae2e-9fa19b253afe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217303338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.3217303338 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.3064400694
Short name T747
Test name
Test status
Simulation time 190157957 ps
CPU time 1.56 seconds
Started Aug 13 05:22:19 PM PDT 24
Finished Aug 13 05:22:21 PM PDT 24
Peak memory 216120 kb
Host smart-fab80cfe-1b1e-4111-83c8-be85f9eee0e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064400694 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr
_outstanding.3064400694 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.2225347509
Short name T795
Test name
Test status
Simulation time 67876104 ps
CPU time 1.28 seconds
Started Aug 13 05:22:04 PM PDT 24
Finished Aug 13 05:22:05 PM PDT 24
Peak memory 216768 kb
Host smart-776ef067-6acc-4e1c-a4bf-6f4db50a6692
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225347509 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_
errors.2225347509 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.3637314657
Short name T82
Test name
Test status
Simulation time 152591636 ps
CPU time 1.55 seconds
Started Aug 13 05:22:12 PM PDT 24
Finished Aug 13 05:22:14 PM PDT 24
Peak memory 219732 kb
Host smart-38978a97-3489-4a6e-9fb1-e5cbc1f3ce9f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637314657 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac
_shadow_reg_errors_with_csr_rw.3637314657 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_tl_errors.3299113915
Short name T778
Test name
Test status
Simulation time 295154022 ps
CPU time 2.17 seconds
Started Aug 13 05:22:03 PM PDT 24
Finished Aug 13 05:22:06 PM PDT 24
Peak memory 216132 kb
Host smart-87a50450-1deb-470c-9d6e-a25a2725994c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299113915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.3299113915 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.1796487672
Short name T821
Test name
Test status
Simulation time 330394060 ps
CPU time 2.8 seconds
Started Aug 13 05:22:14 PM PDT 24
Finished Aug 13 05:22:17 PM PDT 24
Peak memory 216092 kb
Host smart-61f19a7b-86a4-473b-8000-dc10754434ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796487672 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.17964
87672 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.2430172057
Short name T847
Test name
Test status
Simulation time 25177894 ps
CPU time 1.56 seconds
Started Aug 13 05:22:06 PM PDT 24
Finished Aug 13 05:22:08 PM PDT 24
Peak memory 219192 kb
Host smart-46455b33-0e1b-4d68-8b1f-69901be48c3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430172057 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.kmac_csr_mem_rw_with_rand_reset.2430172057 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_csr_rw.181527264
Short name T748
Test name
Test status
Simulation time 18171023 ps
CPU time 1.13 seconds
Started Aug 13 05:22:01 PM PDT 24
Finished Aug 13 05:22:03 PM PDT 24
Peak memory 216024 kb
Host smart-1330cefc-e8eb-42c4-9686-b6e6a46d4150
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181527264 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.181527264 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/7.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_intr_test.594576678
Short name T756
Test name
Test status
Simulation time 19869264 ps
CPU time 0.83 seconds
Started Aug 13 05:22:05 PM PDT 24
Finished Aug 13 05:22:06 PM PDT 24
Peak memory 215788 kb
Host smart-d8e8b587-c838-42cb-849c-ec4dde7a7fe8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594576678 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.594576678 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/7.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.1026100461
Short name T727
Test name
Test status
Simulation time 42055101 ps
CPU time 2.3 seconds
Started Aug 13 05:22:03 PM PDT 24
Finished Aug 13 05:22:06 PM PDT 24
Peak memory 216024 kb
Host smart-54ebec83-32c9-4cee-9bcb-15050aed6276
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026100461 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr
_outstanding.1026100461 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.469334853
Short name T91
Test name
Test status
Simulation time 251404790 ps
CPU time 1.12 seconds
Started Aug 13 05:21:55 PM PDT 24
Finished Aug 13 05:21:56 PM PDT 24
Peak memory 216272 kb
Host smart-33d5b903-b7b9-421c-add8-8987debbc95e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469334853 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_e
rrors.469334853 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.1015776446
Short name T83
Test name
Test status
Simulation time 161122609 ps
CPU time 1.59 seconds
Started Aug 13 05:22:05 PM PDT 24
Finished Aug 13 05:22:07 PM PDT 24
Peak memory 216076 kb
Host smart-a3a52f66-eba7-4946-8946-d5acc16709ad
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015776446 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac
_shadow_reg_errors_with_csr_rw.1015776446 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_tl_errors.2885413730
Short name T136
Test name
Test status
Simulation time 330855923 ps
CPU time 2.33 seconds
Started Aug 13 05:22:04 PM PDT 24
Finished Aug 13 05:22:07 PM PDT 24
Peak memory 216140 kb
Host smart-44eab392-4716-415b-b0b1-1674779ae27c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885413730 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.2885413730 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.1594039953
Short name T837
Test name
Test status
Simulation time 242912532 ps
CPU time 4.57 seconds
Started Aug 13 05:22:12 PM PDT 24
Finished Aug 13 05:22:16 PM PDT 24
Peak memory 216104 kb
Host smart-2c9664fb-f451-4c53-b90d-cf3282ba29a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594039953 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.15940
39953 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.4081740006
Short name T735
Test name
Test status
Simulation time 39421251 ps
CPU time 1.43 seconds
Started Aug 13 05:22:13 PM PDT 24
Finished Aug 13 05:22:15 PM PDT 24
Peak memory 218784 kb
Host smart-250f520d-4077-48a3-b425-29ecad665dcf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081740006 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.kmac_csr_mem_rw_with_rand_reset.4081740006 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_csr_rw.1092778058
Short name T723
Test name
Test status
Simulation time 20091003 ps
CPU time 0.95 seconds
Started Aug 13 05:22:19 PM PDT 24
Finished Aug 13 05:22:20 PM PDT 24
Peak memory 215756 kb
Host smart-f35c1568-0352-4f63-a183-04045d8f1634
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092778058 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.1092778058 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_intr_test.587543855
Short name T862
Test name
Test status
Simulation time 52112328 ps
CPU time 0.77 seconds
Started Aug 13 05:22:04 PM PDT 24
Finished Aug 13 05:22:05 PM PDT 24
Peak memory 215832 kb
Host smart-ef5a5cea-3112-4dbe-b776-f20eb1675af0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587543855 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.587543855 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/8.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.4223305799
Short name T771
Test name
Test status
Simulation time 25621694 ps
CPU time 1.5 seconds
Started Aug 13 05:22:03 PM PDT 24
Finished Aug 13 05:22:04 PM PDT 24
Peak memory 216168 kb
Host smart-ac065667-efc3-4de0-b8ac-40f5539e306a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223305799 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr
_outstanding.4223305799 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.3293419319
Short name T85
Test name
Test status
Simulation time 21266093 ps
CPU time 0.99 seconds
Started Aug 13 05:22:08 PM PDT 24
Finished Aug 13 05:22:09 PM PDT 24
Peak memory 216160 kb
Host smart-42b9bb7a-be44-4a63-a421-6347f1f7a9fe
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293419319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_
errors.3293419319 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.3691098836
Short name T870
Test name
Test status
Simulation time 158461303 ps
CPU time 2.56 seconds
Started Aug 13 05:22:13 PM PDT 24
Finished Aug 13 05:22:16 PM PDT 24
Peak memory 219764 kb
Host smart-4d51eacf-8abe-4bfc-ba3c-4a1e7b377844
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691098836 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac
_shadow_reg_errors_with_csr_rw.3691098836 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_tl_errors.3745978999
Short name T133
Test name
Test status
Simulation time 52376736 ps
CPU time 3.39 seconds
Started Aug 13 05:22:03 PM PDT 24
Finished Aug 13 05:22:07 PM PDT 24
Peak memory 216128 kb
Host smart-0f9df7fc-75b6-4d30-86ad-31c6d652b46e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745978999 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.3745978999 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.3667960639
Short name T785
Test name
Test status
Simulation time 87422569 ps
CPU time 2.46 seconds
Started Aug 13 05:22:10 PM PDT 24
Finished Aug 13 05:22:13 PM PDT 24
Peak memory 220900 kb
Host smart-161d95c4-8981-412e-927d-dc83a475a7a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667960639 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.kmac_csr_mem_rw_with_rand_reset.3667960639 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_csr_rw.707229378
Short name T835
Test name
Test status
Simulation time 38181946 ps
CPU time 0.98 seconds
Started Aug 13 05:22:07 PM PDT 24
Finished Aug 13 05:22:08 PM PDT 24
Peak memory 215904 kb
Host smart-39401d25-ff57-4b90-a84d-1e73d4fc3ae3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707229378 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.707229378 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/9.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_intr_test.2367363948
Short name T754
Test name
Test status
Simulation time 12543729 ps
CPU time 0.78 seconds
Started Aug 13 05:22:13 PM PDT 24
Finished Aug 13 05:22:14 PM PDT 24
Peak memory 215832 kb
Host smart-b897fd9b-c26a-4742-88de-4de3b350b941
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367363948 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.2367363948 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.4169743583
Short name T724
Test name
Test status
Simulation time 97169546 ps
CPU time 2.5 seconds
Started Aug 13 05:22:28 PM PDT 24
Finished Aug 13 05:22:31 PM PDT 24
Peak memory 216020 kb
Host smart-912779b7-7b38-4fc0-a27c-f4a1acbe2232
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169743583 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr
_outstanding.4169743583 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.2281617172
Short name T840
Test name
Test status
Simulation time 42174454 ps
CPU time 0.91 seconds
Started Aug 13 05:22:06 PM PDT 24
Finished Aug 13 05:22:07 PM PDT 24
Peak memory 216212 kb
Host smart-1ed32c40-3838-476b-b7b8-7397c7e47c6d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281617172 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_
errors.2281617172 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.2815494640
Short name T801
Test name
Test status
Simulation time 95502800 ps
CPU time 2.83 seconds
Started Aug 13 05:22:00 PM PDT 24
Finished Aug 13 05:22:03 PM PDT 24
Peak memory 219736 kb
Host smart-47dfd8e5-dd87-4ae5-a140-a4961c2770c1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815494640 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac
_shadow_reg_errors_with_csr_rw.2815494640 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_tl_errors.1679842281
Short name T827
Test name
Test status
Simulation time 305904440 ps
CPU time 2.34 seconds
Started Aug 13 05:22:07 PM PDT 24
Finished Aug 13 05:22:10 PM PDT 24
Peak memory 216172 kb
Host smart-b6830dba-33f2-43c9-923c-189e36870dcd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679842281 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.1679842281 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.1709847349
Short name T183
Test name
Test status
Simulation time 744098522 ps
CPU time 4.84 seconds
Started Aug 13 05:22:05 PM PDT 24
Finished Aug 13 05:22:10 PM PDT 24
Peak memory 215952 kb
Host smart-94a9fcd4-7c93-49d5-93c2-65ff3a83da21
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709847349 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.17098
47349 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.kmac_alert_test.969614053
Short name T491
Test name
Test status
Simulation time 35546037 ps
CPU time 0.83 seconds
Started Aug 13 04:39:51 PM PDT 24
Finished Aug 13 04:39:52 PM PDT 24
Peak memory 218248 kb
Host smart-1303627d-a2f6-46bc-be4a-d403eeb3439e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969614053 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.969614053 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/0.kmac_alert_test/latest

Test location /workspace/coverage/default/0.kmac_app.2405222636
Short name T373
Test name
Test status
Simulation time 6245385689 ps
CPU time 82.35 seconds
Started Aug 13 04:39:38 PM PDT 24
Finished Aug 13 04:41:01 PM PDT 24
Peak memory 247804 kb
Host smart-44c6071f-9632-44f1-b539-ed196092769e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405222636 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.2405222636 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/0.kmac_app/latest

Test location /workspace/coverage/default/0.kmac_app_with_partial_data.2951866974
Short name T417
Test name
Test status
Simulation time 40123359540 ps
CPU time 252.46 seconds
Started Aug 13 04:39:41 PM PDT 24
Finished Aug 13 04:43:53 PM PDT 24
Peak memory 413964 kb
Host smart-64495f06-abaa-4494-8491-081b95d99c71
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951866974 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_par
tial_data.2951866974 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/0.kmac_burst_write.3603580674
Short name T318
Test name
Test status
Simulation time 85141889286 ps
CPU time 1097.8 seconds
Started Aug 13 04:39:44 PM PDT 24
Finished Aug 13 04:58:02 PM PDT 24
Peak memory 254808 kb
Host smart-52c41b75-6296-477f-9607-8bd8b37e035e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603580674 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.3603580674
+enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_burst_write/latest

Test location /workspace/coverage/default/0.kmac_edn_timeout_error.1401246967
Short name T517
Test name
Test status
Simulation time 11192817 ps
CPU time 0.82 seconds
Started Aug 13 04:39:46 PM PDT 24
Finished Aug 13 04:39:47 PM PDT 24
Peak memory 218072 kb
Host smart-ccf84023-1e10-4d05-9ce5-06916580169d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1401246967 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.1401246967 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_mode_error.2738274095
Short name T620
Test name
Test status
Simulation time 26706337 ps
CPU time 0.89 seconds
Started Aug 13 04:39:54 PM PDT 24
Finished Aug 13 04:39:55 PM PDT 24
Peak memory 220372 kb
Host smart-f791a34d-eaf8-4eb6-90d3-768ada152923
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2738274095 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.2738274095 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/0.kmac_error.2814320355
Short name T459
Test name
Test status
Simulation time 41811916827 ps
CPU time 381.88 seconds
Started Aug 13 04:39:46 PM PDT 24
Finished Aug 13 04:46:08 PM PDT 24
Peak memory 508056 kb
Host smart-6215899f-4b98-4208-ae62-f0461f72e42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814320355 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.2814320355 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_error/latest

Test location /workspace/coverage/default/0.kmac_key_error.1230073401
Short name T478
Test name
Test status
Simulation time 3132710390 ps
CPU time 7.05 seconds
Started Aug 13 04:39:44 PM PDT 24
Finished Aug 13 04:39:51 PM PDT 24
Peak memory 218452 kb
Host smart-815f8d30-18d0-420e-a926-07859134f962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230073401 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.1230073401 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_key_error/latest

Test location /workspace/coverage/default/0.kmac_long_msg_and_output.2489978401
Short name T212
Test name
Test status
Simulation time 336951039740 ps
CPU time 1381.99 seconds
Started Aug 13 04:39:45 PM PDT 24
Finished Aug 13 05:02:47 PM PDT 24
Peak memory 1492584 kb
Host smart-b8c9e2dc-4b33-4188-b8f8-3d72d4d3133e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489978401 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_an
d_output.2489978401 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/0.kmac_mubi.3954636292
Short name T436
Test name
Test status
Simulation time 24981823112 ps
CPU time 168.19 seconds
Started Aug 13 04:39:40 PM PDT 24
Finished Aug 13 04:42:29 PM PDT 24
Peak memory 343244 kb
Host smart-870edea6-d1a6-4d0c-8d08-0cfe789b8ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954636292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.3954636292 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_mubi/latest

Test location /workspace/coverage/default/0.kmac_sideload.1183770344
Short name T483
Test name
Test status
Simulation time 79751793270 ps
CPU time 595.1 seconds
Started Aug 13 04:39:41 PM PDT 24
Finished Aug 13 04:49:37 PM PDT 24
Peak memory 611556 kb
Host smart-f9da906b-8086-4896-a80c-1d0e9ccedd39
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183770344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.1183770344 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_sideload/latest

Test location /workspace/coverage/default/0.kmac_smoke.2579446366
Short name T193
Test name
Test status
Simulation time 1884604197 ps
CPU time 39.31 seconds
Started Aug 13 04:39:42 PM PDT 24
Finished Aug 13 04:40:22 PM PDT 24
Peak memory 226624 kb
Host smart-39676522-467c-42bc-a6c2-75677b96142f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579446366 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.2579446366 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_smoke/latest

Test location /workspace/coverage/default/0.kmac_stress_all.1033617973
Short name T366
Test name
Test status
Simulation time 14266527000 ps
CPU time 530.08 seconds
Started Aug 13 04:39:45 PM PDT 24
Finished Aug 13 04:48:35 PM PDT 24
Peak memory 354808 kb
Host smart-b53b47d4-98ec-402d-b3b0-d1ef5c560d48
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1033617973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.1033617973 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_stress_all/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_kmac.1504000691
Short name T107
Test name
Test status
Simulation time 51208643 ps
CPU time 2.43 seconds
Started Aug 13 04:39:40 PM PDT 24
Finished Aug 13 04:39:42 PM PDT 24
Peak memory 219408 kb
Host smart-bad23e3c-6b55-4518-b624-0391d66f6ceb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504000691 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.kmac_test_vectors_kmac.1504000691 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_kmac_xof.2960811882
Short name T553
Test name
Test status
Simulation time 224368030 ps
CPU time 2.7 seconds
Started Aug 13 04:39:39 PM PDT 24
Finished Aug 13 04:39:42 PM PDT 24
Peak memory 226608 kb
Host smart-a9dc8442-12b9-4482-b370-6760a5c60a51
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960811882 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.kmac_test_vectors_kmac_xof.2960811882 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_224.3605365787
Short name T200
Test name
Test status
Simulation time 90050903867 ps
CPU time 3566.75 seconds
Started Aug 13 04:39:40 PM PDT 24
Finished Aug 13 05:39:08 PM PDT 24
Peak memory 3053516 kb
Host smart-19f989b9-956c-4b9b-a8fe-92b79703626b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3605365787 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.3605365787 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_256.2204026764
Short name T388
Test name
Test status
Simulation time 4799788842 ps
CPU time 43.17 seconds
Started Aug 13 04:39:46 PM PDT 24
Finished Aug 13 04:40:29 PM PDT 24
Peak memory 249752 kb
Host smart-533ddfb6-c86d-478f-bdfc-1f8a05fc86c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2204026764 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.2204026764 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_384.1930448822
Short name T299
Test name
Test status
Simulation time 13236015522 ps
CPU time 1533.8 seconds
Started Aug 13 04:39:40 PM PDT 24
Finished Aug 13 05:05:14 PM PDT 24
Peak memory 893640 kb
Host smart-a3f15924-b388-4516-88a0-f42fb53f4e32
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1930448822 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.1930448822 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_512.1269964414
Short name T609
Test name
Test status
Simulation time 46721105982 ps
CPU time 1579.63 seconds
Started Aug 13 04:39:44 PM PDT 24
Finished Aug 13 05:06:04 PM PDT 24
Peak memory 1690080 kb
Host smart-634d1026-9f6c-438f-8a31-5b5fff93eef4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1269964414 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.1269964414 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_shake_128.1615275223
Short name T346
Test name
Test status
Simulation time 21173672611 ps
CPU time 173.91 seconds
Started Aug 13 04:39:41 PM PDT 24
Finished Aug 13 04:42:35 PM PDT 24
Peak memory 281696 kb
Host smart-7488025d-a215-47ce-8351-aed6ddb298cf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1615275223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.1615275223 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_shake_256.1122236098
Short name T272
Test name
Test status
Simulation time 21434051373 ps
CPU time 116.28 seconds
Started Aug 13 04:39:42 PM PDT 24
Finished Aug 13 04:41:38 PM PDT 24
Peak memory 259264 kb
Host smart-de38db67-0fab-431a-8e0d-add10ccaeb11
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1122236098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.1122236098 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/1.kmac_alert_test.187949938
Short name T280
Test name
Test status
Simulation time 33535244 ps
CPU time 0.88 seconds
Started Aug 13 04:39:54 PM PDT 24
Finished Aug 13 04:39:55 PM PDT 24
Peak memory 218164 kb
Host smart-200cf5f8-3c96-4f35-8bb3-1a653b02a192
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187949938 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.187949938 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/1.kmac_alert_test/latest

Test location /workspace/coverage/default/1.kmac_app.2354068742
Short name T540
Test name
Test status
Simulation time 6074511398 ps
CPU time 184.03 seconds
Started Aug 13 04:39:44 PM PDT 24
Finished Aug 13 04:42:48 PM PDT 24
Peak memory 359408 kb
Host smart-568b3e3f-5d4b-4dc1-89b9-827332aeae86
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354068742 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.2354068742 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/1.kmac_app/latest

Test location /workspace/coverage/default/1.kmac_app_with_partial_data.3376030123
Short name T547
Test name
Test status
Simulation time 5310938731 ps
CPU time 37.69 seconds
Started Aug 13 04:39:53 PM PDT 24
Finished Aug 13 04:40:31 PM PDT 24
Peak memory 249024 kb
Host smart-0b56c0b8-a372-400c-ba40-2fd5544f7763
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376030123 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_par
tial_data.3376030123 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/1.kmac_burst_write.3331942598
Short name T250
Test name
Test status
Simulation time 29604508512 ps
CPU time 500.42 seconds
Started Aug 13 04:39:48 PM PDT 24
Finished Aug 13 04:48:09 PM PDT 24
Peak memory 234556 kb
Host smart-84ad5f6c-bfdd-42ea-92ab-8fc290f7d1e1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331942598 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.3331942598
+enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_burst_write/latest

Test location /workspace/coverage/default/1.kmac_entropy_mode_error.3016917188
Short name T705
Test name
Test status
Simulation time 81226257 ps
CPU time 0.99 seconds
Started Aug 13 04:40:08 PM PDT 24
Finished Aug 13 04:40:09 PM PDT 24
Peak memory 221344 kb
Host smart-f1b15330-7d4b-429b-94ef-8ad106d97717
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3016917188 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.3016917188 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_ready_error.3740053138
Short name T539
Test name
Test status
Simulation time 583075801 ps
CPU time 8.7 seconds
Started Aug 13 04:39:54 PM PDT 24
Finished Aug 13 04:40:03 PM PDT 24
Peak memory 219180 kb
Host smart-321fb679-89f3-46c5-a8d8-254e9a51ff44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740053138 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.3740053138 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_refresh.2286284383
Short name T548
Test name
Test status
Simulation time 5069392404 ps
CPU time 107.2 seconds
Started Aug 13 04:39:52 PM PDT 24
Finished Aug 13 04:41:39 PM PDT 24
Peak memory 300464 kb
Host smart-19f9c18d-dd6e-48e8-95d8-af2eeadf7ae6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286284383 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.22
86284383 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/1.kmac_error.2049221964
Short name T466
Test name
Test status
Simulation time 17158816709 ps
CPU time 397.42 seconds
Started Aug 13 04:39:57 PM PDT 24
Finished Aug 13 04:46:35 PM PDT 24
Peak memory 519248 kb
Host smart-8a532af2-3ced-4274-ae3a-c478c8eb95b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049221964 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.2049221964 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_error/latest

Test location /workspace/coverage/default/1.kmac_key_error.3141220727
Short name T486
Test name
Test status
Simulation time 668617653 ps
CPU time 3 seconds
Started Aug 13 04:39:56 PM PDT 24
Finished Aug 13 04:40:00 PM PDT 24
Peak memory 226356 kb
Host smart-9db03e33-6943-4c4a-bb20-3b77111748dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141220727 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.3141220727 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_key_error/latest

Test location /workspace/coverage/default/1.kmac_long_msg_and_output.2951011730
Short name T623
Test name
Test status
Simulation time 60191005613 ps
CPU time 1079.69 seconds
Started Aug 13 04:39:46 PM PDT 24
Finished Aug 13 04:57:46 PM PDT 24
Peak memory 1231656 kb
Host smart-cc3030a7-ee1c-4f73-b665-37eec81e6ceb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951011730 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_an
d_output.2951011730 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/1.kmac_mubi.2018046240
Short name T431
Test name
Test status
Simulation time 1668728670 ps
CPU time 55.23 seconds
Started Aug 13 04:40:04 PM PDT 24
Finished Aug 13 04:40:59 PM PDT 24
Peak memory 242552 kb
Host smart-a1fae81c-0d02-4652-9909-f68ef6ae868d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018046240 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.2018046240 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_mubi/latest

Test location /workspace/coverage/default/1.kmac_sec_cm.438367263
Short name T115
Test name
Test status
Simulation time 13327604752 ps
CPU time 99.63 seconds
Started Aug 13 04:40:04 PM PDT 24
Finished Aug 13 04:41:44 PM PDT 24
Peak memory 291896 kb
Host smart-f49e6c8f-6bf0-4d8d-9966-fa59284d20e7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438367263 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.438367263 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/1.kmac_sec_cm/latest

Test location /workspace/coverage/default/1.kmac_sideload.6498701
Short name T277
Test name
Test status
Simulation time 7506685387 ps
CPU time 60.05 seconds
Started Aug 13 04:39:40 PM PDT 24
Finished Aug 13 04:40:40 PM PDT 24
Peak memory 271196 kb
Host smart-4fb2b915-3ddc-4a6f-b1ac-2c988b40835e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6498701 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.6498701 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/1.kmac_sideload/latest

Test location /workspace/coverage/default/1.kmac_smoke.3094259662
Short name T616
Test name
Test status
Simulation time 4963261639 ps
CPU time 53.57 seconds
Started Aug 13 04:39:46 PM PDT 24
Finished Aug 13 04:40:40 PM PDT 24
Peak memory 226780 kb
Host smart-4da7b824-453c-43fb-8d59-e541c0e1aacd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094259662 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.3094259662 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_smoke/latest

Test location /workspace/coverage/default/1.kmac_stress_all.2162951670
Short name T230
Test name
Test status
Simulation time 30330950625 ps
CPU time 521.36 seconds
Started Aug 13 04:40:02 PM PDT 24
Finished Aug 13 04:48:48 PM PDT 24
Peak memory 285048 kb
Host smart-8494276c-51cc-481f-8b6e-1d6ee197c144
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2162951670 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.2162951670 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_stress_all/latest

Test location /workspace/coverage/default/1.kmac_stress_all_with_rand_reset.3961529624
Short name T49
Test name
Test status
Simulation time 6210655123 ps
CPU time 130.75 seconds
Started Aug 13 04:39:58 PM PDT 24
Finished Aug 13 04:42:09 PM PDT 24
Peak memory 287468 kb
Host smart-f4efc138-86b0-4849-9f9f-49293af59bd9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3961529624 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all_with_rand_reset.3961529624 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_kmac.4014010817
Short name T141
Test name
Test status
Simulation time 780244427 ps
CPU time 3.08 seconds
Started Aug 13 04:39:43 PM PDT 24
Finished Aug 13 04:39:46 PM PDT 24
Peak memory 219468 kb
Host smart-38e63792-1abe-4c8f-8bfb-c2cb75f7917c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014010817 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.kmac_test_vectors_kmac.4014010817 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_kmac_xof.4131559520
Short name T711
Test name
Test status
Simulation time 147866392 ps
CPU time 2.41 seconds
Started Aug 13 04:39:44 PM PDT 24
Finished Aug 13 04:39:47 PM PDT 24
Peak memory 218588 kb
Host smart-49b3b8b5-cb4f-4051-95c3-625b45262ec5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131559520 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.kmac_test_vectors_kmac_xof.4131559520 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_224.4253731877
Short name T404
Test name
Test status
Simulation time 2347098877 ps
CPU time 39.66 seconds
Started Aug 13 04:39:47 PM PDT 24
Finished Aug 13 04:40:27 PM PDT 24
Peak memory 226336 kb
Host smart-77b8a07d-3aec-4b87-af64-08b499651c83
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4253731877 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.4253731877 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_256.3580661707
Short name T16
Test name
Test status
Simulation time 587346797982 ps
CPU time 3627.74 seconds
Started Aug 13 04:39:40 PM PDT 24
Finished Aug 13 05:40:09 PM PDT 24
Peak memory 3031024 kb
Host smart-fd740ebd-6439-435a-b833-c363d33d002a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3580661707 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.3580661707 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_384.702571860
Short name T629
Test name
Test status
Simulation time 2289288675 ps
CPU time 23.49 seconds
Started Aug 13 04:39:48 PM PDT 24
Finished Aug 13 04:40:11 PM PDT 24
Peak memory 219356 kb
Host smart-35319eb5-f350-41ab-819a-981abfe4874b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=702571860 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.702571860 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_512.3913432918
Short name T221
Test name
Test status
Simulation time 257815756723 ps
CPU time 1781.02 seconds
Started Aug 13 04:39:58 PM PDT 24
Finished Aug 13 05:09:39 PM PDT 24
Peak memory 1692348 kb
Host smart-e7924711-6df3-4b33-8f8a-1aa75f99c56a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3913432918 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.3913432918 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_shake_128.2882443499
Short name T31
Test name
Test status
Simulation time 14047792287 ps
CPU time 163.65 seconds
Started Aug 13 04:39:50 PM PDT 24
Finished Aug 13 04:42:34 PM PDT 24
Peak memory 283344 kb
Host smart-fe722213-cdc1-49c1-a340-5c83cdc0164f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2882443499 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_128.2882443499 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_shake_256.1530122498
Short name T662
Test name
Test status
Simulation time 242722206316 ps
CPU time 2847.29 seconds
Started Aug 13 04:39:53 PM PDT 24
Finished Aug 13 05:27:21 PM PDT 24
Peak memory 2996588 kb
Host smart-51c7f5d0-4d19-4667-95f8-332abea97753
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1530122498 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.1530122498 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/10.kmac_alert_test.51163545
Short name T336
Test name
Test status
Simulation time 50623019 ps
CPU time 0.84 seconds
Started Aug 13 04:40:14 PM PDT 24
Finished Aug 13 04:40:15 PM PDT 24
Peak memory 218152 kb
Host smart-664b3397-b8a7-4281-847d-204b013081aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51163545 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.51163545 +enable_mas
king=1 +sw_key_masked=0
Directory /workspace/10.kmac_alert_test/latest

Test location /workspace/coverage/default/10.kmac_app.3958982023
Short name T387
Test name
Test status
Simulation time 15090192239 ps
CPU time 230.89 seconds
Started Aug 13 04:40:11 PM PDT 24
Finished Aug 13 04:44:02 PM PDT 24
Peak memory 387356 kb
Host smart-de55c6ce-6f93-46c7-b383-b79431a1e7cc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958982023 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.3958982023 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/10.kmac_app/latest

Test location /workspace/coverage/default/10.kmac_burst_write.1245507856
Short name T396
Test name
Test status
Simulation time 11904179406 ps
CPU time 1249.73 seconds
Started Aug 13 04:40:11 PM PDT 24
Finished Aug 13 05:01:01 PM PDT 24
Peak memory 245696 kb
Host smart-6d26fba5-96e2-4561-b432-89ff80ae3c61
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245507856 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.124550785
6 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_burst_write/latest

Test location /workspace/coverage/default/10.kmac_edn_timeout_error.2177378441
Short name T500
Test name
Test status
Simulation time 291311373 ps
CPU time 1.13 seconds
Started Aug 13 04:40:29 PM PDT 24
Finished Aug 13 04:40:30 PM PDT 24
Peak memory 218340 kb
Host smart-ee5207b2-5b98-402e-8847-64d11575158d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2177378441 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.2177378441 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/10.kmac_entropy_refresh.3547651262
Short name T237
Test name
Test status
Simulation time 180342641 ps
CPU time 1.93 seconds
Started Aug 13 04:40:12 PM PDT 24
Finished Aug 13 04:40:14 PM PDT 24
Peak memory 218608 kb
Host smart-b5d6a7b7-1b5f-4fba-bbe9-94666eb90047
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547651262 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.3
547651262 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/10.kmac_error.3923088977
Short name T328
Test name
Test status
Simulation time 56195828339 ps
CPU time 496.92 seconds
Started Aug 13 04:40:19 PM PDT 24
Finished Aug 13 04:48:36 PM PDT 24
Peak memory 587176 kb
Host smart-09570d1d-567c-48b6-af02-8a35f9cf603f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923088977 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.3923088977 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_error/latest

Test location /workspace/coverage/default/10.kmac_key_error.782954402
Short name T549
Test name
Test status
Simulation time 4182411501 ps
CPU time 6.32 seconds
Started Aug 13 04:40:14 PM PDT 24
Finished Aug 13 04:40:20 PM PDT 24
Peak memory 226484 kb
Host smart-b383f9b7-01cf-42eb-8624-b4a8ab69f2c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782954402 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.782954402 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_key_error/latest

Test location /workspace/coverage/default/10.kmac_lc_escalation.2081680085
Short name T26
Test name
Test status
Simulation time 112955423 ps
CPU time 1.25 seconds
Started Aug 13 04:40:22 PM PDT 24
Finished Aug 13 04:40:23 PM PDT 24
Peak memory 226548 kb
Host smart-ba579313-7585-4150-aa85-e8273b0957ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081680085 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.2081680085 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/10.kmac_lc_escalation/latest

Test location /workspace/coverage/default/10.kmac_sideload.1997282315
Short name T679
Test name
Test status
Simulation time 213761190100 ps
CPU time 509.24 seconds
Started Aug 13 04:40:30 PM PDT 24
Finished Aug 13 04:49:00 PM PDT 24
Peak memory 574732 kb
Host smart-7d73b1f7-ca52-45d2-a440-afb53007b7d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997282315 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.1997282315 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_sideload/latest

Test location /workspace/coverage/default/10.kmac_smoke.56264708
Short name T343
Test name
Test status
Simulation time 4021442388 ps
CPU time 78.3 seconds
Started Aug 13 04:40:11 PM PDT 24
Finished Aug 13 04:41:29 PM PDT 24
Peak memory 226704 kb
Host smart-b4e2c6c9-1d1f-4b80-9d74-365c93b06db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56264708 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.56264708 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_smoke/latest

Test location /workspace/coverage/default/10.kmac_stress_all.2900969407
Short name T695
Test name
Test status
Simulation time 10122405098 ps
CPU time 255.52 seconds
Started Aug 13 04:40:26 PM PDT 24
Finished Aug 13 04:44:42 PM PDT 24
Peak memory 291596 kb
Host smart-9d62251c-3dab-4035-8f27-511d323a5731
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2900969407 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.2900969407 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_stress_all/latest

Test location /workspace/coverage/default/11.kmac_alert_test.1158243761
Short name T524
Test name
Test status
Simulation time 15804175 ps
CPU time 0.83 seconds
Started Aug 13 04:40:22 PM PDT 24
Finished Aug 13 04:40:23 PM PDT 24
Peak memory 218188 kb
Host smart-867d9b68-b464-4298-9641-cc99fecf5664
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158243761 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.1158243761 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_alert_test/latest

Test location /workspace/coverage/default/11.kmac_app.1476655172
Short name T490
Test name
Test status
Simulation time 74180383302 ps
CPU time 160.82 seconds
Started Aug 13 04:40:10 PM PDT 24
Finished Aug 13 04:42:51 PM PDT 24
Peak memory 322456 kb
Host smart-67b4a954-b3f8-4007-9f35-f932d7bb4911
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476655172 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.1476655172 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/11.kmac_app/latest

Test location /workspace/coverage/default/11.kmac_burst_write.2403667571
Short name T498
Test name
Test status
Simulation time 123669982767 ps
CPU time 1583.88 seconds
Started Aug 13 04:40:30 PM PDT 24
Finished Aug 13 05:06:55 PM PDT 24
Peak memory 264740 kb
Host smart-ccdfc5ef-d5fe-4805-91c8-5606ed7ccea3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403667571 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.240366757
1 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_burst_write/latest

Test location /workspace/coverage/default/11.kmac_edn_timeout_error.3094460852
Short name T310
Test name
Test status
Simulation time 22841037 ps
CPU time 0.98 seconds
Started Aug 13 04:40:20 PM PDT 24
Finished Aug 13 04:40:21 PM PDT 24
Peak memory 218116 kb
Host smart-a6ae0848-e5bd-432c-8a59-1baec9e64936
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3094460852 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.3094460852 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/11.kmac_entropy_mode_error.1686847290
Short name T68
Test name
Test status
Simulation time 43597857 ps
CPU time 1.09 seconds
Started Aug 13 04:40:29 PM PDT 24
Finished Aug 13 04:40:30 PM PDT 24
Peak memory 218316 kb
Host smart-ad68afa1-141a-488e-a63a-959a9da98c44
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1686847290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.1686847290 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/11.kmac_entropy_refresh.1737879498
Short name T560
Test name
Test status
Simulation time 40239150275 ps
CPU time 343.05 seconds
Started Aug 13 04:40:10 PM PDT 24
Finished Aug 13 04:45:53 PM PDT 24
Peak memory 316868 kb
Host smart-0ceb5e4c-591b-4e1c-8dfb-64befb714325
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737879498 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.1
737879498 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/11.kmac_error.3899672086
Short name T22
Test name
Test status
Simulation time 7088206478 ps
CPU time 138.21 seconds
Started Aug 13 04:40:20 PM PDT 24
Finished Aug 13 04:42:39 PM PDT 24
Peak memory 275876 kb
Host smart-6f135a53-1b7d-4323-be41-155961fe6d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899672086 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.3899672086 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_error/latest

Test location /workspace/coverage/default/11.kmac_key_error.2153917687
Short name T106
Test name
Test status
Simulation time 3471510737 ps
CPU time 7.36 seconds
Started Aug 13 04:40:30 PM PDT 24
Finished Aug 13 04:40:38 PM PDT 24
Peak memory 226472 kb
Host smart-1d509aab-8f74-4143-bc3b-5c16e00f265f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153917687 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.2153917687 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_key_error/latest

Test location /workspace/coverage/default/11.kmac_lc_escalation.1083958816
Short name T400
Test name
Test status
Simulation time 943476389 ps
CPU time 12.05 seconds
Started Aug 13 04:40:27 PM PDT 24
Finished Aug 13 04:40:39 PM PDT 24
Peak memory 234964 kb
Host smart-01ff3389-82ba-4e87-b662-4a3b86392d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083958816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.1083958816 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/11.kmac_lc_escalation/latest

Test location /workspace/coverage/default/11.kmac_long_msg_and_output.3917280054
Short name T637
Test name
Test status
Simulation time 106001130680 ps
CPU time 1134.53 seconds
Started Aug 13 04:40:28 PM PDT 24
Finished Aug 13 04:59:28 PM PDT 24
Peak memory 1280472 kb
Host smart-ff1489ff-0ba9-46e8-8790-c0df56aadc84
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917280054 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_a
nd_output.3917280054 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/11.kmac_sideload.2537605518
Short name T367
Test name
Test status
Simulation time 14321077026 ps
CPU time 544.71 seconds
Started Aug 13 04:40:25 PM PDT 24
Finished Aug 13 04:49:30 PM PDT 24
Peak memory 593632 kb
Host smart-0705d934-eefd-4c5a-9562-b1534b808856
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537605518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.2537605518 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_sideload/latest

Test location /workspace/coverage/default/11.kmac_smoke.1704951657
Short name T390
Test name
Test status
Simulation time 14013440987 ps
CPU time 68.52 seconds
Started Aug 13 04:40:32 PM PDT 24
Finished Aug 13 04:41:41 PM PDT 24
Peak memory 226804 kb
Host smart-b55860a3-9197-4188-8496-d5db35159756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704951657 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.1704951657 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_smoke/latest

Test location /workspace/coverage/default/11.kmac_stress_all.1203724329
Short name T369
Test name
Test status
Simulation time 30503451461 ps
CPU time 140.61 seconds
Started Aug 13 04:40:17 PM PDT 24
Finished Aug 13 04:42:38 PM PDT 24
Peak memory 350220 kb
Host smart-3b3ce7ef-66f7-42dc-9e27-00af38f6bdd6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1203724329 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.1203724329 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_stress_all/latest

Test location /workspace/coverage/default/12.kmac_alert_test.1688868919
Short name T577
Test name
Test status
Simulation time 18155575 ps
CPU time 0.82 seconds
Started Aug 13 04:40:33 PM PDT 24
Finished Aug 13 04:40:34 PM PDT 24
Peak memory 218196 kb
Host smart-52a8e0e0-3d16-43f7-86b1-1874f6278d9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688868919 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.1688868919 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_alert_test/latest

Test location /workspace/coverage/default/12.kmac_app.3539827747
Short name T536
Test name
Test status
Simulation time 11169494784 ps
CPU time 348.28 seconds
Started Aug 13 04:40:19 PM PDT 24
Finished Aug 13 04:46:07 PM PDT 24
Peak memory 488796 kb
Host smart-483c9ea8-66d1-4c71-8bc0-37c3ca1bf01b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539827747 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.3539827747 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/12.kmac_app/latest

Test location /workspace/coverage/default/12.kmac_burst_write.556521013
Short name T148
Test name
Test status
Simulation time 30019855093 ps
CPU time 1652.98 seconds
Started Aug 13 04:40:18 PM PDT 24
Finished Aug 13 05:07:51 PM PDT 24
Peak memory 268036 kb
Host smart-3421c63a-419f-4027-b115-6144def7897b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556521013 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.556521013
+enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_burst_write/latest

Test location /workspace/coverage/default/12.kmac_edn_timeout_error.600495393
Short name T677
Test name
Test status
Simulation time 306337878 ps
CPU time 1.18 seconds
Started Aug 13 04:40:27 PM PDT 24
Finished Aug 13 04:40:29 PM PDT 24
Peak memory 218300 kb
Host smart-9a9c4683-3be0-4490-accb-25439ae6d4f6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=600495393 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.600495393 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/12.kmac_entropy_mode_error.4103070424
Short name T482
Test name
Test status
Simulation time 12425112 ps
CPU time 0.82 seconds
Started Aug 13 04:40:26 PM PDT 24
Finished Aug 13 04:40:27 PM PDT 24
Peak memory 220160 kb
Host smart-87b43241-8aa5-4697-941d-5b308a555d9c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4103070424 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.4103070424 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/12.kmac_entropy_refresh.1083063723
Short name T238
Test name
Test status
Simulation time 24357322688 ps
CPU time 319.56 seconds
Started Aug 13 04:40:24 PM PDT 24
Finished Aug 13 04:45:43 PM PDT 24
Peak memory 450476 kb
Host smart-d518b2b6-cfb2-432d-970e-f6b644738532
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083063723 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.1
083063723 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/12.kmac_error.542726223
Short name T584
Test name
Test status
Simulation time 1451572196 ps
CPU time 56.89 seconds
Started Aug 13 04:40:34 PM PDT 24
Finished Aug 13 04:41:31 PM PDT 24
Peak memory 251272 kb
Host smart-073a7923-0d3e-41f8-b554-fc6806df3d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542726223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.542726223 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_error/latest

Test location /workspace/coverage/default/12.kmac_key_error.3870080866
Short name T140
Test name
Test status
Simulation time 1752490657 ps
CPU time 8.28 seconds
Started Aug 13 04:40:27 PM PDT 24
Finished Aug 13 04:40:36 PM PDT 24
Peak memory 226564 kb
Host smart-21f25840-c467-4935-9d5d-cead15bc9a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870080866 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.3870080866 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_key_error/latest

Test location /workspace/coverage/default/12.kmac_lc_escalation.3526698487
Short name T473
Test name
Test status
Simulation time 414716577 ps
CPU time 11.13 seconds
Started Aug 13 04:40:17 PM PDT 24
Finished Aug 13 04:40:29 PM PDT 24
Peak memory 236556 kb
Host smart-6c618a45-a059-4222-8e2d-4a97c9ce187a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526698487 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.3526698487 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/12.kmac_lc_escalation/latest

Test location /workspace/coverage/default/12.kmac_long_msg_and_output.3288966401
Short name T239
Test name
Test status
Simulation time 78329378886 ps
CPU time 3932.2 seconds
Started Aug 13 04:40:17 PM PDT 24
Finished Aug 13 05:45:50 PM PDT 24
Peak memory 3094648 kb
Host smart-30875a94-ff09-48a5-ba1a-054be9429e52
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288966401 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_a
nd_output.3288966401 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/12.kmac_sideload.701497818
Short name T505
Test name
Test status
Simulation time 9029740479 ps
CPU time 161.51 seconds
Started Aug 13 04:40:27 PM PDT 24
Finished Aug 13 04:43:09 PM PDT 24
Peak memory 277928 kb
Host smart-af3e8d91-e8e0-409d-8c5f-afe06151cb3f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701497818 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.701497818 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_sideload/latest

Test location /workspace/coverage/default/12.kmac_smoke.3243999260
Short name T630
Test name
Test status
Simulation time 1331236907 ps
CPU time 24.87 seconds
Started Aug 13 04:40:32 PM PDT 24
Finished Aug 13 04:40:58 PM PDT 24
Peak memory 226680 kb
Host smart-5dcb030c-4d4d-48ae-82b4-3648d18edba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243999260 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.3243999260 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_smoke/latest

Test location /workspace/coverage/default/12.kmac_stress_all.3203434459
Short name T312
Test name
Test status
Simulation time 16762148402 ps
CPU time 872.53 seconds
Started Aug 13 04:40:33 PM PDT 24
Finished Aug 13 04:55:06 PM PDT 24
Peak memory 350848 kb
Host smart-e3d3b376-4d14-4ccd-862d-baf0d23dbd4f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3203434459 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.3203434459 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_stress_all/latest

Test location /workspace/coverage/default/13.kmac_alert_test.1170641993
Short name T688
Test name
Test status
Simulation time 42951966 ps
CPU time 0.8 seconds
Started Aug 13 04:40:19 PM PDT 24
Finished Aug 13 04:40:20 PM PDT 24
Peak memory 218288 kb
Host smart-db1836a3-d7bf-4515-92ef-b6185350155f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170641993 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.1170641993 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_alert_test/latest

Test location /workspace/coverage/default/13.kmac_app.3334790551
Short name T120
Test name
Test status
Simulation time 93556138593 ps
CPU time 427.58 seconds
Started Aug 13 04:40:31 PM PDT 24
Finished Aug 13 04:47:39 PM PDT 24
Peak memory 505904 kb
Host smart-a9b07c98-a54d-43a7-ad66-6dfcd997bd4e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334790551 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.3334790551 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/13.kmac_app/latest

Test location /workspace/coverage/default/13.kmac_burst_write.324891302
Short name T504
Test name
Test status
Simulation time 17460627782 ps
CPU time 217.55 seconds
Started Aug 13 04:40:27 PM PDT 24
Finished Aug 13 04:44:05 PM PDT 24
Peak memory 230324 kb
Host smart-4044caa6-8d2e-4578-99ce-8ef02b94f8a3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324891302 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.324891302
+enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_burst_write/latest

Test location /workspace/coverage/default/13.kmac_edn_timeout_error.2448897629
Short name T321
Test name
Test status
Simulation time 1164154250 ps
CPU time 31.76 seconds
Started Aug 13 04:40:27 PM PDT 24
Finished Aug 13 04:40:59 PM PDT 24
Peak memory 227208 kb
Host smart-dd7ea102-4fd2-4276-84fb-910be2b56cd3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2448897629 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.2448897629 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/13.kmac_entropy_mode_error.943428011
Short name T66
Test name
Test status
Simulation time 40136072 ps
CPU time 1.23 seconds
Started Aug 13 04:40:31 PM PDT 24
Finished Aug 13 04:40:33 PM PDT 24
Peak memory 221288 kb
Host smart-b8301f80-19d4-4f02-bcaa-7ddbc36a26a2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=943428011 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.943428011 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/13.kmac_entropy_refresh.4150374575
Short name T532
Test name
Test status
Simulation time 7096946232 ps
CPU time 175.43 seconds
Started Aug 13 04:40:31 PM PDT 24
Finished Aug 13 04:43:27 PM PDT 24
Peak memory 345100 kb
Host smart-5eeaeef0-fcf1-4f49-9871-35d19f7813c6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150374575 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.4
150374575 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/13.kmac_error.1900702820
Short name T254
Test name
Test status
Simulation time 45370891191 ps
CPU time 303.24 seconds
Started Aug 13 04:40:31 PM PDT 24
Finished Aug 13 04:45:35 PM PDT 24
Peak memory 330964 kb
Host smart-13a526c4-cff4-4888-b53a-aeac9f0abee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900702820 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.1900702820 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_error/latest

Test location /workspace/coverage/default/13.kmac_key_error.207194707
Short name T604
Test name
Test status
Simulation time 942119023 ps
CPU time 5.31 seconds
Started Aug 13 04:40:28 PM PDT 24
Finished Aug 13 04:40:33 PM PDT 24
Peak memory 226564 kb
Host smart-9495273c-308c-435c-9a5d-417d474056d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207194707 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.207194707 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_key_error/latest

Test location /workspace/coverage/default/13.kmac_lc_escalation.3904034047
Short name T429
Test name
Test status
Simulation time 34907684 ps
CPU time 1.42 seconds
Started Aug 13 04:40:17 PM PDT 24
Finished Aug 13 04:40:19 PM PDT 24
Peak memory 226492 kb
Host smart-81ef0526-f190-49e2-aeec-2217f1d50ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904034047 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.3904034047 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/13.kmac_lc_escalation/latest

Test location /workspace/coverage/default/13.kmac_long_msg_and_output.48709505
Short name T472
Test name
Test status
Simulation time 65017966782 ps
CPU time 1873.09 seconds
Started Aug 13 04:40:30 PM PDT 24
Finished Aug 13 05:11:44 PM PDT 24
Peak memory 1143532 kb
Host smart-32aa9146-0c3a-4605-878c-18e1fe0a87e8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48709505 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and
_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_and
_output.48709505 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/13.kmac_sideload.3447824717
Short name T510
Test name
Test status
Simulation time 3861771407 ps
CPU time 125.47 seconds
Started Aug 13 04:40:23 PM PDT 24
Finished Aug 13 04:42:29 PM PDT 24
Peak memory 324992 kb
Host smart-a68376ce-0a0f-486f-972e-fd1521944982
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447824717 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.3447824717 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_sideload/latest

Test location /workspace/coverage/default/13.kmac_smoke.366448511
Short name T124
Test name
Test status
Simulation time 45063851006 ps
CPU time 73.51 seconds
Started Aug 13 04:40:36 PM PDT 24
Finished Aug 13 04:41:50 PM PDT 24
Peak memory 226692 kb
Host smart-e1b8c51d-ac6a-4880-9998-b7eaef0e771b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366448511 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.366448511 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_smoke/latest

Test location /workspace/coverage/default/13.kmac_stress_all.3498857497
Short name T349
Test name
Test status
Simulation time 465964888833 ps
CPU time 1577.94 seconds
Started Aug 13 04:40:28 PM PDT 24
Finished Aug 13 05:06:47 PM PDT 24
Peak memory 1170404 kb
Host smart-7fa32bdf-c377-4ee9-92af-677fdd6df913
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3498857497 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.3498857497 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_stress_all/latest

Test location /workspace/coverage/default/14.kmac_alert_test.2146991443
Short name T405
Test name
Test status
Simulation time 57180085 ps
CPU time 0.85 seconds
Started Aug 13 04:40:22 PM PDT 24
Finished Aug 13 04:40:23 PM PDT 24
Peak memory 218188 kb
Host smart-f667e8f7-d47e-40ca-98a9-0406be011373
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146991443 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.2146991443 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_alert_test/latest

Test location /workspace/coverage/default/14.kmac_app.2571268658
Short name T503
Test name
Test status
Simulation time 5467806873 ps
CPU time 141.5 seconds
Started Aug 13 04:40:27 PM PDT 24
Finished Aug 13 04:42:49 PM PDT 24
Peak memory 325096 kb
Host smart-b63e2d09-8e15-4169-87fc-ffbee6e88278
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571268658 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.2571268658 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/14.kmac_app/latest

Test location /workspace/coverage/default/14.kmac_burst_write.1823212190
Short name T402
Test name
Test status
Simulation time 28235340862 ps
CPU time 327.76 seconds
Started Aug 13 04:40:29 PM PDT 24
Finished Aug 13 04:45:57 PM PDT 24
Peak memory 243004 kb
Host smart-8986e8d4-0ff1-4cf8-8895-38663168f893
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823212190 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.182321219
0 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_burst_write/latest

Test location /workspace/coverage/default/14.kmac_edn_timeout_error.4103682442
Short name T445
Test name
Test status
Simulation time 673445761 ps
CPU time 17.29 seconds
Started Aug 13 04:40:22 PM PDT 24
Finished Aug 13 04:40:39 PM PDT 24
Peak memory 221748 kb
Host smart-132e7b12-6974-4a63-b314-db613f02c7b3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4103682442 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.4103682442 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/14.kmac_entropy_mode_error.3041599604
Short name T240
Test name
Test status
Simulation time 13224915 ps
CPU time 0.88 seconds
Started Aug 13 04:40:32 PM PDT 24
Finished Aug 13 04:40:34 PM PDT 24
Peak memory 220544 kb
Host smart-3be0423d-de2f-4fc4-b989-182afcaabb46
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3041599604 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.3041599604 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/14.kmac_error.1895636029
Short name T370
Test name
Test status
Simulation time 44966889905 ps
CPU time 318.65 seconds
Started Aug 13 04:40:29 PM PDT 24
Finished Aug 13 04:45:48 PM PDT 24
Peak memory 476440 kb
Host smart-a17b82ba-c37f-4fc5-8cb3-e0ff5540a423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895636029 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.1895636029 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_error/latest

Test location /workspace/coverage/default/14.kmac_key_error.230733292
Short name T269
Test name
Test status
Simulation time 2695454183 ps
CPU time 5.26 seconds
Started Aug 13 04:40:35 PM PDT 24
Finished Aug 13 04:40:41 PM PDT 24
Peak memory 226436 kb
Host smart-8650b5b5-7c27-4040-aa3e-296fc8093be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230733292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.230733292 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_key_error/latest

Test location /workspace/coverage/default/14.kmac_long_msg_and_output.1706398357
Short name T621
Test name
Test status
Simulation time 13050856642 ps
CPU time 538.83 seconds
Started Aug 13 04:40:34 PM PDT 24
Finished Aug 13 04:49:33 PM PDT 24
Peak memory 795308 kb
Host smart-966f76ce-2277-4b76-a4f6-cdd531debbc1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706398357 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_a
nd_output.1706398357 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/14.kmac_sideload.2161606102
Short name T20
Test name
Test status
Simulation time 105457769971 ps
CPU time 532.99 seconds
Started Aug 13 04:40:32 PM PDT 24
Finished Aug 13 04:49:25 PM PDT 24
Peak memory 625996 kb
Host smart-55c032fd-0a05-48cc-8b76-c5205c549d12
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161606102 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.2161606102 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_sideload/latest

Test location /workspace/coverage/default/14.kmac_smoke.885207093
Short name T594
Test name
Test status
Simulation time 17504023053 ps
CPU time 90.33 seconds
Started Aug 13 04:40:17 PM PDT 24
Finished Aug 13 04:41:48 PM PDT 24
Peak memory 227956 kb
Host smart-ced7cdbb-234b-48c4-8f5e-9dfe173ddbc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885207093 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.885207093 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_smoke/latest

Test location /workspace/coverage/default/14.kmac_stress_all.3658709366
Short name T347
Test name
Test status
Simulation time 104782454 ps
CPU time 2.27 seconds
Started Aug 13 04:40:27 PM PDT 24
Finished Aug 13 04:40:29 PM PDT 24
Peak memory 219384 kb
Host smart-6795487f-cbf5-4758-af99-ce019a5dcc9a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3658709366 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.3658709366 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_stress_all/latest

Test location /workspace/coverage/default/15.kmac_app.2028226727
Short name T227
Test name
Test status
Simulation time 20916752179 ps
CPU time 88.04 seconds
Started Aug 13 04:40:17 PM PDT 24
Finished Aug 13 04:41:45 PM PDT 24
Peak memory 293728 kb
Host smart-560f3f46-e301-43d4-a039-b74522a2d16b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028226727 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.2028226727 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/15.kmac_app/latest

Test location /workspace/coverage/default/15.kmac_burst_write.2042848580
Short name T224
Test name
Test status
Simulation time 18985071846 ps
CPU time 940.59 seconds
Started Aug 13 04:40:30 PM PDT 24
Finished Aug 13 04:56:11 PM PDT 24
Peak memory 241688 kb
Host smart-4596247d-65c6-4cff-84ef-75497e04230f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042848580 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.204284858
0 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_burst_write/latest

Test location /workspace/coverage/default/15.kmac_edn_timeout_error.1220233534
Short name T59
Test name
Test status
Simulation time 125906752 ps
CPU time 1.17 seconds
Started Aug 13 04:40:17 PM PDT 24
Finished Aug 13 04:40:18 PM PDT 24
Peak memory 218352 kb
Host smart-d2fb4ee7-9425-43a3-bd05-e7f4546dafef
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1220233534 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.1220233534 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/15.kmac_entropy_mode_error.4078828307
Short name T497
Test name
Test status
Simulation time 285626405 ps
CPU time 1.12 seconds
Started Aug 13 04:40:19 PM PDT 24
Finished Aug 13 04:40:21 PM PDT 24
Peak memory 221596 kb
Host smart-3b1addd7-172c-466b-bf3d-b8155a9b7611
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4078828307 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.4078828307 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/15.kmac_entropy_refresh.851695718
Short name T416
Test name
Test status
Simulation time 11626851084 ps
CPU time 245.2 seconds
Started Aug 13 04:40:31 PM PDT 24
Finished Aug 13 04:44:37 PM PDT 24
Peak memory 410840 kb
Host smart-b7fd21ae-a505-4f31-90c0-266d72715faf
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851695718 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.85
1695718 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/15.kmac_error.1228871626
Short name T465
Test name
Test status
Simulation time 4379496847 ps
CPU time 93.9 seconds
Started Aug 13 04:40:19 PM PDT 24
Finished Aug 13 04:41:53 PM PDT 24
Peak memory 270200 kb
Host smart-8b4a5fe7-df99-4c67-86db-8f2f8bc0d201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228871626 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.1228871626 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_error/latest

Test location /workspace/coverage/default/15.kmac_key_error.3395695093
Short name T551
Test name
Test status
Simulation time 3051993668 ps
CPU time 5.97 seconds
Started Aug 13 04:40:50 PM PDT 24
Finished Aug 13 04:40:56 PM PDT 24
Peak memory 226560 kb
Host smart-a59ad030-c559-4665-9802-1365497c8a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395695093 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.3395695093 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_key_error/latest

Test location /workspace/coverage/default/15.kmac_lc_escalation.1568707303
Short name T48
Test name
Test status
Simulation time 6634165973 ps
CPU time 21.34 seconds
Started Aug 13 04:40:24 PM PDT 24
Finished Aug 13 04:40:45 PM PDT 24
Peak memory 251452 kb
Host smart-4c908fe9-fe2c-41d6-806b-5defb7908edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568707303 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.1568707303 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/15.kmac_lc_escalation/latest

Test location /workspace/coverage/default/15.kmac_long_msg_and_output.3983870072
Short name T520
Test name
Test status
Simulation time 80149986452 ps
CPU time 497.12 seconds
Started Aug 13 04:40:27 PM PDT 24
Finished Aug 13 04:48:45 PM PDT 24
Peak memory 740300 kb
Host smart-cc5e4055-5071-49e1-92dc-f22518200cf7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983870072 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_a
nd_output.3983870072 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/15.kmac_sideload.3618719116
Short name T527
Test name
Test status
Simulation time 6564114295 ps
CPU time 60.26 seconds
Started Aug 13 04:40:21 PM PDT 24
Finished Aug 13 04:41:22 PM PDT 24
Peak memory 239612 kb
Host smart-b9fa6ceb-ddef-480e-95e0-e476b0ceaf2e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618719116 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.3618719116 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_sideload/latest

Test location /workspace/coverage/default/15.kmac_smoke.2926131604
Short name T265
Test name
Test status
Simulation time 655794170 ps
CPU time 4.64 seconds
Started Aug 13 04:40:27 PM PDT 24
Finished Aug 13 04:40:32 PM PDT 24
Peak memory 221340 kb
Host smart-7b356e66-f58d-4e91-b853-33b3d63cd315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926131604 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.2926131604 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_smoke/latest

Test location /workspace/coverage/default/15.kmac_stress_all.4111648013
Short name T386
Test name
Test status
Simulation time 8244484379 ps
CPU time 622.52 seconds
Started Aug 13 04:40:31 PM PDT 24
Finished Aug 13 04:50:55 PM PDT 24
Peak memory 449324 kb
Host smart-5bd8eec5-b8a7-4316-a2be-bda658d83638
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4111648013 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.4111648013 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_stress_all/latest

Test location /workspace/coverage/default/16.kmac_alert_test.2742135107
Short name T545
Test name
Test status
Simulation time 22924854 ps
CPU time 0.86 seconds
Started Aug 13 04:40:32 PM PDT 24
Finished Aug 13 04:40:34 PM PDT 24
Peak memory 218160 kb
Host smart-f96555c2-b952-4e5d-97c3-535bdfd15e39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742135107 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.2742135107 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_alert_test/latest

Test location /workspace/coverage/default/16.kmac_app.388193278
Short name T664
Test name
Test status
Simulation time 15054134889 ps
CPU time 110.68 seconds
Started Aug 13 04:40:32 PM PDT 24
Finished Aug 13 04:42:23 PM PDT 24
Peak memory 259888 kb
Host smart-1b369b16-fcce-4021-bcc2-da7310220c93
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388193278 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.388193278 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/16.kmac_app/latest

Test location /workspace/coverage/default/16.kmac_burst_write.793947348
Short name T574
Test name
Test status
Simulation time 58537762843 ps
CPU time 674.85 seconds
Started Aug 13 04:40:29 PM PDT 24
Finished Aug 13 04:51:45 PM PDT 24
Peak memory 245844 kb
Host smart-b6c42027-211e-4ffd-9d4e-973f4dbb7271
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793947348 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.793947348
+enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_burst_write/latest

Test location /workspace/coverage/default/16.kmac_edn_timeout_error.4132252629
Short name T692
Test name
Test status
Simulation time 64076704 ps
CPU time 1.14 seconds
Started Aug 13 04:40:28 PM PDT 24
Finished Aug 13 04:40:29 PM PDT 24
Peak memory 218348 kb
Host smart-2e413483-2a57-45ee-b9af-861b4f119ed3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4132252629 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.4132252629 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/16.kmac_entropy_mode_error.4095674278
Short name T278
Test name
Test status
Simulation time 36182449 ps
CPU time 1.15 seconds
Started Aug 13 04:40:31 PM PDT 24
Finished Aug 13 04:40:33 PM PDT 24
Peak memory 221972 kb
Host smart-5d25c2be-a9f8-4d1e-bc3c-a593d6b8f30e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4095674278 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.4095674278 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/16.kmac_entropy_refresh.767332570
Short name T537
Test name
Test status
Simulation time 2695851357 ps
CPU time 51.78 seconds
Started Aug 13 04:40:33 PM PDT 24
Finished Aug 13 04:41:25 PM PDT 24
Peak memory 253760 kb
Host smart-f1e73a7a-b10c-4a57-9458-d1591b1536db
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767332570 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.76
7332570 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/16.kmac_error.2892417741
Short name T95
Test name
Test status
Simulation time 26812159421 ps
CPU time 261.32 seconds
Started Aug 13 04:40:32 PM PDT 24
Finished Aug 13 04:44:54 PM PDT 24
Peak memory 413792 kb
Host smart-ff323d69-5e73-4d44-9407-9d9f2d5f947d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892417741 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.2892417741 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_error/latest

Test location /workspace/coverage/default/16.kmac_key_error.2697784255
Short name T300
Test name
Test status
Simulation time 1309425288 ps
CPU time 8.81 seconds
Started Aug 13 04:40:28 PM PDT 24
Finished Aug 13 04:40:37 PM PDT 24
Peak memory 226392 kb
Host smart-b79ea35f-dba9-4844-8cc8-fa0ba7f99592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697784255 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.2697784255 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_key_error/latest

Test location /workspace/coverage/default/16.kmac_lc_escalation.4248693742
Short name T53
Test name
Test status
Simulation time 29029238 ps
CPU time 1.24 seconds
Started Aug 13 04:40:27 PM PDT 24
Finished Aug 13 04:40:29 PM PDT 24
Peak memory 226568 kb
Host smart-f1125c3f-8785-47a0-aa12-efaa038abce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248693742 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.4248693742 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/16.kmac_lc_escalation/latest

Test location /workspace/coverage/default/16.kmac_long_msg_and_output.1596525797
Short name T713
Test name
Test status
Simulation time 145392250564 ps
CPU time 648.81 seconds
Started Aug 13 04:40:32 PM PDT 24
Finished Aug 13 04:51:22 PM PDT 24
Peak memory 881416 kb
Host smart-f245499d-add3-4714-a744-250655868980
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596525797 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_a
nd_output.1596525797 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/16.kmac_sideload.1034523248
Short name T580
Test name
Test status
Simulation time 25313974833 ps
CPU time 590.6 seconds
Started Aug 13 04:40:26 PM PDT 24
Finished Aug 13 04:50:17 PM PDT 24
Peak memory 655112 kb
Host smart-43c2abd6-c21b-4278-92c5-df7b89a8628f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034523248 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.1034523248 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_sideload/latest

Test location /workspace/coverage/default/16.kmac_smoke.3744597421
Short name T658
Test name
Test status
Simulation time 1786955014 ps
CPU time 64.07 seconds
Started Aug 13 04:40:33 PM PDT 24
Finished Aug 13 04:41:37 PM PDT 24
Peak memory 226620 kb
Host smart-1a0a7f36-44da-4525-b09c-ba0a7d3150e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744597421 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.3744597421 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_smoke/latest

Test location /workspace/coverage/default/16.kmac_stress_all.640205967
Short name T651
Test name
Test status
Simulation time 11975925739 ps
CPU time 1005.45 seconds
Started Aug 13 04:40:34 PM PDT 24
Finished Aug 13 04:57:20 PM PDT 24
Peak memory 531432 kb
Host smart-c8454317-277c-4853-b3d9-6306cdc82dbd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=640205967 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all.640205967 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_stress_all/latest

Test location /workspace/coverage/default/17.kmac_alert_test.4139090340
Short name T409
Test name
Test status
Simulation time 13148478 ps
CPU time 0.79 seconds
Started Aug 13 04:40:27 PM PDT 24
Finished Aug 13 04:40:28 PM PDT 24
Peak memory 218256 kb
Host smart-533f6b52-0e54-44ab-8176-e7759287ab5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139090340 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.4139090340 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_alert_test/latest

Test location /workspace/coverage/default/17.kmac_app.3002029820
Short name T211
Test name
Test status
Simulation time 602364923 ps
CPU time 2.6 seconds
Started Aug 13 04:40:29 PM PDT 24
Finished Aug 13 04:40:32 PM PDT 24
Peak memory 226668 kb
Host smart-35279394-607d-485d-a4ca-57ad28268a5d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002029820 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.3002029820 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/17.kmac_app/latest

Test location /workspace/coverage/default/17.kmac_burst_write.643956036
Short name T573
Test name
Test status
Simulation time 2162699693 ps
CPU time 130.41 seconds
Started Aug 13 04:40:25 PM PDT 24
Finished Aug 13 04:42:35 PM PDT 24
Peak memory 226416 kb
Host smart-79f54ddf-edd4-40ba-93c9-7546da314079
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643956036 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.643956036
+enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_burst_write/latest

Test location /workspace/coverage/default/17.kmac_edn_timeout_error.4129020534
Short name T475
Test name
Test status
Simulation time 18750300 ps
CPU time 1 seconds
Started Aug 13 04:40:33 PM PDT 24
Finished Aug 13 04:40:34 PM PDT 24
Peak memory 218028 kb
Host smart-ea7a88ea-03fe-4bf7-95f8-be609da2bdcd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4129020534 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.4129020534 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/17.kmac_entropy_mode_error.2931326895
Short name T690
Test name
Test status
Simulation time 300597920 ps
CPU time 1.36 seconds
Started Aug 13 04:40:30 PM PDT 24
Finished Aug 13 04:40:31 PM PDT 24
Peak memory 218404 kb
Host smart-95a260bf-74eb-408e-b391-152eafdaac72
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2931326895 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.2931326895 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/17.kmac_entropy_refresh.2716173950
Short name T316
Test name
Test status
Simulation time 67915510706 ps
CPU time 242.28 seconds
Started Aug 13 04:40:28 PM PDT 24
Finished Aug 13 04:44:30 PM PDT 24
Peak memory 402568 kb
Host smart-08865421-fef8-4abe-8208-da6278921a92
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716173950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.2
716173950 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/17.kmac_error.944683120
Short name T657
Test name
Test status
Simulation time 16153385999 ps
CPU time 335.18 seconds
Started Aug 13 04:40:31 PM PDT 24
Finished Aug 13 04:46:07 PM PDT 24
Peak memory 333228 kb
Host smart-ed2f8926-85df-4d55-9d49-5607ea3d0eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944683120 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.944683120 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_error/latest

Test location /workspace/coverage/default/17.kmac_key_error.2028597155
Short name T674
Test name
Test status
Simulation time 1907512235 ps
CPU time 7.23 seconds
Started Aug 13 04:40:25 PM PDT 24
Finished Aug 13 04:40:33 PM PDT 24
Peak memory 226416 kb
Host smart-8de5b27c-fa0a-4736-815f-1593d23e3409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028597155 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.2028597155 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_key_error/latest

Test location /workspace/coverage/default/17.kmac_lc_escalation.1835778112
Short name T663
Test name
Test status
Simulation time 821689119 ps
CPU time 10.82 seconds
Started Aug 13 04:40:31 PM PDT 24
Finished Aug 13 04:40:43 PM PDT 24
Peak memory 234948 kb
Host smart-b221db72-af7a-4812-9ab4-cdb1ca65fc94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835778112 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.1835778112 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/17.kmac_lc_escalation/latest

Test location /workspace/coverage/default/17.kmac_long_msg_and_output.1556002123
Short name T202
Test name
Test status
Simulation time 20930381436 ps
CPU time 891.63 seconds
Started Aug 13 04:40:30 PM PDT 24
Finished Aug 13 04:55:22 PM PDT 24
Peak memory 1128984 kb
Host smart-179d74c7-f9ef-49b0-8740-d1f4c639e1f8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556002123 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_a
nd_output.1556002123 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/17.kmac_sideload.928069440
Short name T292
Test name
Test status
Simulation time 17034063790 ps
CPU time 254.37 seconds
Started Aug 13 04:40:28 PM PDT 24
Finished Aug 13 04:44:42 PM PDT 24
Peak memory 413788 kb
Host smart-ec2f97ad-1569-4848-9670-b560f86bf3de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928069440 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.928069440 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_sideload/latest

Test location /workspace/coverage/default/17.kmac_smoke.1106771031
Short name T419
Test name
Test status
Simulation time 6362574499 ps
CPU time 95.22 seconds
Started Aug 13 04:40:34 PM PDT 24
Finished Aug 13 04:42:09 PM PDT 24
Peak memory 230192 kb
Host smart-83a3416d-2338-4289-adf8-fb038acc83ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106771031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.1106771031 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_smoke/latest

Test location /workspace/coverage/default/18.kmac_alert_test.1351592998
Short name T562
Test name
Test status
Simulation time 89888879 ps
CPU time 0.88 seconds
Started Aug 13 04:40:31 PM PDT 24
Finished Aug 13 04:40:32 PM PDT 24
Peak memory 218252 kb
Host smart-3afad9fc-f739-4bab-b906-005ebcce36e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351592998 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.1351592998 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_alert_test/latest

Test location /workspace/coverage/default/18.kmac_app.3294933486
Short name T342
Test name
Test status
Simulation time 2311364071 ps
CPU time 124.1 seconds
Started Aug 13 04:40:34 PM PDT 24
Finished Aug 13 04:42:39 PM PDT 24
Peak memory 263836 kb
Host smart-26c9b50d-3581-40b3-9465-c3c774dfda50
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294933486 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.3294933486 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/18.kmac_app/latest

Test location /workspace/coverage/default/18.kmac_burst_write.327370540
Short name T649
Test name
Test status
Simulation time 57057385348 ps
CPU time 1402.99 seconds
Started Aug 13 04:40:28 PM PDT 24
Finished Aug 13 05:03:51 PM PDT 24
Peak memory 246548 kb
Host smart-9db88951-9b32-4768-b2be-3cb9364eac21
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327370540 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.327370540
+enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_burst_write/latest

Test location /workspace/coverage/default/18.kmac_edn_timeout_error.2506581894
Short name T648
Test name
Test status
Simulation time 581210435 ps
CPU time 41.03 seconds
Started Aug 13 04:40:27 PM PDT 24
Finished Aug 13 04:41:08 PM PDT 24
Peak memory 242848 kb
Host smart-7dfb5f1d-17c6-400b-8ef9-ff04fc037bf0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2506581894 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.2506581894 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/18.kmac_entropy_mode_error.1985872534
Short name T345
Test name
Test status
Simulation time 159276192 ps
CPU time 1.21 seconds
Started Aug 13 04:40:33 PM PDT 24
Finished Aug 13 04:40:35 PM PDT 24
Peak memory 221924 kb
Host smart-a7038d83-d29d-494d-a2fe-fe2f5142c7e3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1985872534 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.1985872534 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/18.kmac_error.767330858
Short name T189
Test name
Test status
Simulation time 7674904074 ps
CPU time 202.32 seconds
Started Aug 13 04:40:28 PM PDT 24
Finished Aug 13 04:43:50 PM PDT 24
Peak memory 379008 kb
Host smart-6d8b9c50-8058-48f6-b48d-b753a2128cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767330858 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.767330858 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_error/latest

Test location /workspace/coverage/default/18.kmac_key_error.2730173351
Short name T286
Test name
Test status
Simulation time 1818347268 ps
CPU time 12.68 seconds
Started Aug 13 04:40:32 PM PDT 24
Finished Aug 13 04:40:45 PM PDT 24
Peak memory 226364 kb
Host smart-467f029e-9eee-4890-aa3c-3cc5bad7e8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730173351 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.2730173351 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_key_error/latest

Test location /workspace/coverage/default/18.kmac_lc_escalation.2569656709
Short name T511
Test name
Test status
Simulation time 60383113 ps
CPU time 1.39 seconds
Started Aug 13 04:40:34 PM PDT 24
Finished Aug 13 04:40:36 PM PDT 24
Peak memory 226636 kb
Host smart-c3fd9eda-fb4f-45ab-9c30-69e4f17a3469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569656709 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.2569656709 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/18.kmac_lc_escalation/latest

Test location /workspace/coverage/default/18.kmac_long_msg_and_output.4104728765
Short name T338
Test name
Test status
Simulation time 170019829294 ps
CPU time 1636.05 seconds
Started Aug 13 04:40:26 PM PDT 24
Finished Aug 13 05:07:42 PM PDT 24
Peak memory 1847764 kb
Host smart-ddd08e06-7164-49d5-b6a0-72d8365e87a2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104728765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_a
nd_output.4104728765 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/18.kmac_sideload.2534996247
Short name T646
Test name
Test status
Simulation time 35444218002 ps
CPU time 225.05 seconds
Started Aug 13 04:40:26 PM PDT 24
Finished Aug 13 04:44:11 PM PDT 24
Peak memory 399848 kb
Host smart-6cf30aaa-b4bf-4c75-9d9a-466a76bfedc5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534996247 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.2534996247 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_sideload/latest

Test location /workspace/coverage/default/18.kmac_smoke.28013374
Short name T456
Test name
Test status
Simulation time 1918577860 ps
CPU time 35.72 seconds
Started Aug 13 04:40:27 PM PDT 24
Finished Aug 13 04:41:03 PM PDT 24
Peak memory 226628 kb
Host smart-fd31a1be-415f-4d14-801b-5a74cdae1f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28013374 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.28013374 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_smoke/latest

Test location /workspace/coverage/default/18.kmac_stress_all.3913950614
Short name T544
Test name
Test status
Simulation time 26830080720 ps
CPU time 140.3 seconds
Started Aug 13 04:40:38 PM PDT 24
Finished Aug 13 04:42:58 PM PDT 24
Peak memory 280584 kb
Host smart-b9a55090-3097-4525-93ae-66a19a1d65b0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3913950614 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all.3913950614 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_stress_all/latest

Test location /workspace/coverage/default/19.kmac_alert_test.870217227
Short name T201
Test name
Test status
Simulation time 18594226 ps
CPU time 0.9 seconds
Started Aug 13 04:40:31 PM PDT 24
Finished Aug 13 04:40:32 PM PDT 24
Peak memory 218160 kb
Host smart-4c4944fd-fe0c-4254-8fac-daef7344edc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870217227 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.870217227 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/19.kmac_alert_test/latest

Test location /workspace/coverage/default/19.kmac_app.3133422499
Short name T206
Test name
Test status
Simulation time 18924282899 ps
CPU time 273.42 seconds
Started Aug 13 04:40:31 PM PDT 24
Finished Aug 13 04:45:06 PM PDT 24
Peak memory 413476 kb
Host smart-7e57b8ea-6a6f-4a77-8195-016b67c700d8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133422499 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.3133422499 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/19.kmac_app/latest

Test location /workspace/coverage/default/19.kmac_burst_write.3000928172
Short name T147
Test name
Test status
Simulation time 28308052527 ps
CPU time 1287.88 seconds
Started Aug 13 04:40:29 PM PDT 24
Finished Aug 13 05:01:57 PM PDT 24
Peak memory 260680 kb
Host smart-57b1942d-7a38-4aba-9e26-a2f13c80d96c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000928172 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.300092817
2 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_burst_write/latest

Test location /workspace/coverage/default/19.kmac_edn_timeout_error.741059373
Short name T57
Test name
Test status
Simulation time 22153130 ps
CPU time 1.05 seconds
Started Aug 13 04:40:33 PM PDT 24
Finished Aug 13 04:40:34 PM PDT 24
Peak memory 218428 kb
Host smart-4aff396f-6477-4b1e-a531-64198c649e12
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=741059373 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.741059373 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/19.kmac_entropy_mode_error.2397376010
Short name T714
Test name
Test status
Simulation time 15793572 ps
CPU time 0.85 seconds
Started Aug 13 04:40:31 PM PDT 24
Finished Aug 13 04:40:33 PM PDT 24
Peak memory 220448 kb
Host smart-5ef0f320-1f75-4801-9075-47556cbf1a9b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2397376010 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.2397376010 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/19.kmac_entropy_refresh.4143454520
Short name T121
Test name
Test status
Simulation time 4826594213 ps
CPU time 83.03 seconds
Started Aug 13 04:40:34 PM PDT 24
Finished Aug 13 04:41:57 PM PDT 24
Peak memory 249980 kb
Host smart-4be435a4-730c-42ec-9c4c-f3ab299d3656
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143454520 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.4
143454520 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/19.kmac_error.4248675706
Short name T361
Test name
Test status
Simulation time 31123796322 ps
CPU time 180.26 seconds
Started Aug 13 04:40:34 PM PDT 24
Finished Aug 13 04:43:34 PM PDT 24
Peak memory 357812 kb
Host smart-e7c85206-712a-4f08-8fc0-09e98f94b99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248675706 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.4248675706 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_error/latest

Test location /workspace/coverage/default/19.kmac_lc_escalation.1091959921
Short name T492
Test name
Test status
Simulation time 53343627 ps
CPU time 1.97 seconds
Started Aug 13 04:40:35 PM PDT 24
Finished Aug 13 04:40:37 PM PDT 24
Peak memory 226584 kb
Host smart-0f6229be-16ca-429c-8583-35030cc2fa47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091959921 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.1091959921 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/19.kmac_lc_escalation/latest

Test location /workspace/coverage/default/19.kmac_smoke.2903497741
Short name T319
Test name
Test status
Simulation time 3210935187 ps
CPU time 59.5 seconds
Started Aug 13 04:40:27 PM PDT 24
Finished Aug 13 04:41:27 PM PDT 24
Peak memory 226884 kb
Host smart-6aca3e4c-f830-404c-80e2-03f68c990687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903497741 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.2903497741 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_smoke/latest

Test location /workspace/coverage/default/2.kmac_alert_test.3985224902
Short name T428
Test name
Test status
Simulation time 280033314 ps
CPU time 0.85 seconds
Started Aug 13 04:40:00 PM PDT 24
Finished Aug 13 04:40:01 PM PDT 24
Peak memory 218180 kb
Host smart-ee2fff05-723c-4b04-8dcc-e55bbb4d099a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985224902 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.3985224902 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_alert_test/latest

Test location /workspace/coverage/default/2.kmac_app.1445812069
Short name T608
Test name
Test status
Simulation time 18764335681 ps
CPU time 129.27 seconds
Started Aug 13 04:40:08 PM PDT 24
Finished Aug 13 04:42:17 PM PDT 24
Peak memory 307660 kb
Host smart-ef2be901-87f9-483c-90de-4dc2c9ab54c9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445812069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.1445812069 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/2.kmac_app/latest

Test location /workspace/coverage/default/2.kmac_app_with_partial_data.2541897396
Short name T268
Test name
Test status
Simulation time 5959977762 ps
CPU time 260.86 seconds
Started Aug 13 04:40:03 PM PDT 24
Finished Aug 13 04:44:24 PM PDT 24
Peak memory 303448 kb
Host smart-3cf3a9c5-f18a-4227-b547-c4745b68bb78
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541897396 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_par
tial_data.2541897396 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/2.kmac_burst_write.3557791581
Short name T376
Test name
Test status
Simulation time 23032458192 ps
CPU time 1181.09 seconds
Started Aug 13 04:39:54 PM PDT 24
Finished Aug 13 04:59:36 PM PDT 24
Peak memory 259076 kb
Host smart-3aa50bca-157a-475c-84fd-9ab0f86c5761
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557791581 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.3557791581
+enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_burst_write/latest

Test location /workspace/coverage/default/2.kmac_edn_timeout_error.209658596
Short name T673
Test name
Test status
Simulation time 59763793 ps
CPU time 0.98 seconds
Started Aug 13 04:39:55 PM PDT 24
Finished Aug 13 04:39:57 PM PDT 24
Peak memory 218112 kb
Host smart-747357ea-3b59-413d-8004-3f092c7a25a7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=209658596 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.209658596 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_mode_error.811630475
Short name T697
Test name
Test status
Simulation time 135679252 ps
CPU time 1.3 seconds
Started Aug 13 04:40:02 PM PDT 24
Finished Aug 13 04:40:03 PM PDT 24
Peak memory 222264 kb
Host smart-e3ba0e98-a365-423b-bd93-3ce747b6fb36
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=811630475 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.811630475 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_ready_error.1337772752
Short name T424
Test name
Test status
Simulation time 6409143104 ps
CPU time 73.16 seconds
Started Aug 13 04:40:09 PM PDT 24
Finished Aug 13 04:41:22 PM PDT 24
Peak memory 224688 kb
Host smart-56445b16-f25c-49a9-9cf5-f183c7b3a530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337772752 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.1337772752 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_refresh.1530370201
Short name T236
Test name
Test status
Simulation time 12717268918 ps
CPU time 379.12 seconds
Started Aug 13 04:40:05 PM PDT 24
Finished Aug 13 04:46:24 PM PDT 24
Peak memory 497256 kb
Host smart-8b20573d-be1d-48ae-9dda-a39ce369e1fd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530370201 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.15
30370201 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/2.kmac_error.4173655923
Short name T394
Test name
Test status
Simulation time 40878903662 ps
CPU time 369.77 seconds
Started Aug 13 04:39:58 PM PDT 24
Finished Aug 13 04:46:08 PM PDT 24
Peak memory 504832 kb
Host smart-af51d7b2-6205-45a7-bc13-b848af23f8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173655923 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.4173655923 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_error/latest

Test location /workspace/coverage/default/2.kmac_key_error.2177847050
Short name T4
Test name
Test status
Simulation time 405188692 ps
CPU time 2.09 seconds
Started Aug 13 04:40:04 PM PDT 24
Finished Aug 13 04:40:07 PM PDT 24
Peak memory 226168 kb
Host smart-8a54d097-e922-4a77-a135-63c1edcb80f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177847050 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.2177847050 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_key_error/latest

Test location /workspace/coverage/default/2.kmac_lc_escalation.2238674412
Short name T628
Test name
Test status
Simulation time 2784313427 ps
CPU time 16.3 seconds
Started Aug 13 04:40:11 PM PDT 24
Finished Aug 13 04:40:28 PM PDT 24
Peak memory 242544 kb
Host smart-6ab664a3-d1a5-4d9e-9963-e42343f6aafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238674412 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.2238674412 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/2.kmac_lc_escalation/latest

Test location /workspace/coverage/default/2.kmac_long_msg_and_output.1713979203
Short name T263
Test name
Test status
Simulation time 1192202278148 ps
CPU time 5238.61 seconds
Started Aug 13 04:39:50 PM PDT 24
Finished Aug 13 06:07:10 PM PDT 24
Peak memory 3545464 kb
Host smart-56b65494-ceba-4be8-9035-0dcf4924e56a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713979203 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_an
d_output.1713979203 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/2.kmac_mubi.53341211
Short name T290
Test name
Test status
Simulation time 11045425010 ps
CPU time 147.47 seconds
Started Aug 13 04:39:52 PM PDT 24
Finished Aug 13 04:42:20 PM PDT 24
Peak memory 326772 kb
Host smart-2e6985a4-41f7-421c-95a8-40e7aa4f5e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53341211 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.53341211 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_mubi/latest

Test location /workspace/coverage/default/2.kmac_sideload.4189948677
Short name T638
Test name
Test status
Simulation time 13642582685 ps
CPU time 315.63 seconds
Started Aug 13 04:39:56 PM PDT 24
Finished Aug 13 04:45:11 PM PDT 24
Peak memory 325220 kb
Host smart-4377c971-e8ea-4987-9c7a-badeda56e26f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189948677 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.4189948677 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_sideload/latest

Test location /workspace/coverage/default/2.kmac_smoke.63971214
Short name T374
Test name
Test status
Simulation time 16556062307 ps
CPU time 70.79 seconds
Started Aug 13 04:39:51 PM PDT 24
Finished Aug 13 04:41:02 PM PDT 24
Peak memory 226868 kb
Host smart-4c2b0567-20a6-4fde-a9f3-5502122d720f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63971214 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.63971214 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_smoke/latest

Test location /workspace/coverage/default/2.kmac_stress_all.1857403904
Short name T512
Test name
Test status
Simulation time 91227785442 ps
CPU time 1512.59 seconds
Started Aug 13 04:39:58 PM PDT 24
Finished Aug 13 05:05:11 PM PDT 24
Peak memory 519540 kb
Host smart-4928dc77-f781-4213-96a0-f12594e1bcbc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1857403904 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.1857403904 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_stress_all/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_kmac.3623879126
Short name T585
Test name
Test status
Simulation time 198077525 ps
CPU time 2.78 seconds
Started Aug 13 04:40:15 PM PDT 24
Finished Aug 13 04:40:18 PM PDT 24
Peak memory 219484 kb
Host smart-b00fafb5-0c17-4b47-bd18-4ef7773b0f8b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623879126 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.kmac_test_vectors_kmac.3623879126 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_kmac_xof.1257427386
Short name T468
Test name
Test status
Simulation time 45642277 ps
CPU time 2.52 seconds
Started Aug 13 04:39:54 PM PDT 24
Finished Aug 13 04:39:56 PM PDT 24
Peak memory 219564 kb
Host smart-f5b982ab-7b34-4f3a-b0b3-c1cf6f9cf8b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257427386 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.kmac_test_vectors_kmac_xof.1257427386 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_224.3460675709
Short name T464
Test name
Test status
Simulation time 206367146701 ps
CPU time 2231.89 seconds
Started Aug 13 04:39:59 PM PDT 24
Finished Aug 13 05:17:12 PM PDT 24
Peak memory 1205240 kb
Host smart-2bb0ef64-8e37-4463-b25d-3764d2603f6d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3460675709 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.3460675709 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_256.3397215630
Short name T477
Test name
Test status
Simulation time 5295543758 ps
CPU time 50.47 seconds
Started Aug 13 04:40:07 PM PDT 24
Finished Aug 13 04:40:58 PM PDT 24
Peak memory 248248 kb
Host smart-ce313862-865d-4772-8685-03567db40a88
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3397215630 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.3397215630 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_384.4076464510
Short name T557
Test name
Test status
Simulation time 77843335097 ps
CPU time 2409.74 seconds
Started Aug 13 04:39:51 PM PDT 24
Finished Aug 13 05:20:01 PM PDT 24
Peak memory 2398948 kb
Host smart-9685c15c-9493-4899-ab89-769f2e796c88
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4076464510 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.4076464510 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_512.2849588266
Short name T341
Test name
Test status
Simulation time 4530984876 ps
CPU time 18.99 seconds
Started Aug 13 04:39:58 PM PDT 24
Finished Aug 13 04:40:17 PM PDT 24
Peak memory 224120 kb
Host smart-d7b38a8c-4356-434f-83d9-95176b76a40b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2849588266 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.2849588266 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_shake_128.2326413246
Short name T391
Test name
Test status
Simulation time 15328415757 ps
CPU time 216.76 seconds
Started Aug 13 04:40:13 PM PDT 24
Finished Aug 13 04:43:50 PM PDT 24
Peak memory 437856 kb
Host smart-7904222d-fb01-4057-a772-7b1cd11b72d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2326413246 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.2326413246 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_shake_256.3493570592
Short name T704
Test name
Test status
Simulation time 19033114718 ps
CPU time 454.36 seconds
Started Aug 13 04:39:57 PM PDT 24
Finished Aug 13 04:47:32 PM PDT 24
Peak memory 359760 kb
Host smart-1c9ec187-a7d9-4fab-871a-423a85606e2d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3493570592 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.3493570592 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/20.kmac_alert_test.3434681448
Short name T247
Test name
Test status
Simulation time 13402369 ps
CPU time 0.79 seconds
Started Aug 13 04:40:37 PM PDT 24
Finished Aug 13 04:40:38 PM PDT 24
Peak memory 218192 kb
Host smart-c87575e8-847d-4ff0-89c5-e14663a7eb23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434681448 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.3434681448 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_alert_test/latest

Test location /workspace/coverage/default/20.kmac_app.2760017124
Short name T35
Test name
Test status
Simulation time 11843414693 ps
CPU time 296.57 seconds
Started Aug 13 04:40:35 PM PDT 24
Finished Aug 13 04:45:31 PM PDT 24
Peak memory 316388 kb
Host smart-7bb0f0e1-a849-4b67-bf81-cca44401ee51
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760017124 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.2760017124 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/20.kmac_app/latest

Test location /workspace/coverage/default/20.kmac_burst_write.798174603
Short name T656
Test name
Test status
Simulation time 4876757143 ps
CPU time 55.44 seconds
Started Aug 13 04:40:32 PM PDT 24
Finished Aug 13 04:41:28 PM PDT 24
Peak memory 226804 kb
Host smart-9cbd0185-8b99-4ba9-9fcd-3acaa3e418b9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798174603 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.798174603
+enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_burst_write/latest

Test location /workspace/coverage/default/20.kmac_entropy_refresh.1017863892
Short name T288
Test name
Test status
Simulation time 13893397483 ps
CPU time 196.77 seconds
Started Aug 13 04:40:34 PM PDT 24
Finished Aug 13 04:43:51 PM PDT 24
Peak memory 347328 kb
Host smart-8624df5d-a4cb-4766-90c2-13ad55de0a45
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017863892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.1
017863892 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/20.kmac_error.1420446479
Short name T228
Test name
Test status
Simulation time 6285026487 ps
CPU time 85.37 seconds
Started Aug 13 04:40:35 PM PDT 24
Finished Aug 13 04:42:01 PM PDT 24
Peak memory 300420 kb
Host smart-d05ede83-9971-4300-954d-dcfc8f39365f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420446479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.1420446479 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_error/latest

Test location /workspace/coverage/default/20.kmac_key_error.1084534033
Short name T220
Test name
Test status
Simulation time 695682034 ps
CPU time 5.3 seconds
Started Aug 13 04:40:34 PM PDT 24
Finished Aug 13 04:40:39 PM PDT 24
Peak memory 226440 kb
Host smart-e37ce2e1-564d-4de0-8584-676abb213c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084534033 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.1084534033 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_key_error/latest

Test location /workspace/coverage/default/20.kmac_lc_escalation.4183803499
Short name T39
Test name
Test status
Simulation time 113626700 ps
CPU time 1.67 seconds
Started Aug 13 04:40:30 PM PDT 24
Finished Aug 13 04:40:33 PM PDT 24
Peak memory 226560 kb
Host smart-98290fa7-af24-45c2-aae7-932f3edcbd4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183803499 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.4183803499 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/20.kmac_lc_escalation/latest

Test location /workspace/coverage/default/20.kmac_long_msg_and_output.1516652195
Short name T634
Test name
Test status
Simulation time 28883717521 ps
CPU time 803.8 seconds
Started Aug 13 04:40:33 PM PDT 24
Finished Aug 13 04:53:57 PM PDT 24
Peak memory 639568 kb
Host smart-14e6a8c1-42a6-4e49-b956-a6f67ffe0ddc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516652195 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_a
nd_output.1516652195 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/20.kmac_sideload.1155803133
Short name T447
Test name
Test status
Simulation time 1894088659 ps
CPU time 141.22 seconds
Started Aug 13 04:40:32 PM PDT 24
Finished Aug 13 04:42:53 PM PDT 24
Peak memory 274672 kb
Host smart-90a6263e-53b8-4aac-ba45-de456e36c637
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155803133 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.1155803133 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_sideload/latest

Test location /workspace/coverage/default/20.kmac_smoke.1603377726
Short name T232
Test name
Test status
Simulation time 3584261102 ps
CPU time 61.41 seconds
Started Aug 13 04:40:30 PM PDT 24
Finished Aug 13 04:41:31 PM PDT 24
Peak memory 226700 kb
Host smart-7579b8fb-879e-46c0-8f77-f27b03eb5ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603377726 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.1603377726 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_smoke/latest

Test location /workspace/coverage/default/20.kmac_stress_all.3114312118
Short name T61
Test name
Test status
Simulation time 11147144143 ps
CPU time 947.33 seconds
Started Aug 13 04:40:32 PM PDT 24
Finished Aug 13 04:56:20 PM PDT 24
Peak memory 534904 kb
Host smart-6ab78b62-0db1-49eb-85f1-649bd9075030
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3114312118 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.3114312118 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_stress_all/latest

Test location /workspace/coverage/default/21.kmac_alert_test.375547060
Short name T418
Test name
Test status
Simulation time 53387632 ps
CPU time 0.82 seconds
Started Aug 13 04:40:30 PM PDT 24
Finished Aug 13 04:40:32 PM PDT 24
Peak memory 218196 kb
Host smart-56c1b973-3fef-4fd2-8d96-0ccb3da8696c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375547060 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.375547060 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/21.kmac_alert_test/latest

Test location /workspace/coverage/default/21.kmac_app.1371189789
Short name T701
Test name
Test status
Simulation time 11084106724 ps
CPU time 46.89 seconds
Started Aug 13 04:40:33 PM PDT 24
Finished Aug 13 04:41:20 PM PDT 24
Peak memory 259052 kb
Host smart-5a3289b1-7dbf-46cb-b083-dca7d1f54f52
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371189789 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.1371189789 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/21.kmac_app/latest

Test location /workspace/coverage/default/21.kmac_burst_write.3900630650
Short name T285
Test name
Test status
Simulation time 120611751937 ps
CPU time 1389.39 seconds
Started Aug 13 04:40:32 PM PDT 24
Finished Aug 13 05:03:42 PM PDT 24
Peak memory 260996 kb
Host smart-55c5e9e3-7e76-4272-8e48-e54648c7409f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900630650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.390063065
0 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_burst_write/latest

Test location /workspace/coverage/default/21.kmac_entropy_refresh.2250118158
Short name T302
Test name
Test status
Simulation time 68508283285 ps
CPU time 372.68 seconds
Started Aug 13 04:40:35 PM PDT 24
Finished Aug 13 04:46:48 PM PDT 24
Peak memory 333924 kb
Host smart-38ebd268-587a-43c7-a6f1-8df58492f499
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250118158 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_entropy_refresh.2
250118158 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/21.kmac_error.3159365009
Short name T267
Test name
Test status
Simulation time 8063632682 ps
CPU time 153.27 seconds
Started Aug 13 04:40:30 PM PDT 24
Finished Aug 13 04:43:04 PM PDT 24
Peak memory 278608 kb
Host smart-5ec9ef07-3f7b-49ac-ae20-60d300b3001c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159365009 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_error.3159365009 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_error/latest

Test location /workspace/coverage/default/21.kmac_key_error.800756364
Short name T382
Test name
Test status
Simulation time 6931454360 ps
CPU time 8.8 seconds
Started Aug 13 04:40:35 PM PDT 24
Finished Aug 13 04:40:44 PM PDT 24
Peak memory 226600 kb
Host smart-44b9edc0-6c07-406e-a3e4-02ea7f81e2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800756364 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.800756364 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_key_error/latest

Test location /workspace/coverage/default/21.kmac_sideload.3563626027
Short name T660
Test name
Test status
Simulation time 7435793833 ps
CPU time 279.48 seconds
Started Aug 13 04:40:31 PM PDT 24
Finished Aug 13 04:45:11 PM PDT 24
Peak memory 327228 kb
Host smart-56ba3260-b77c-41f1-b045-b675493a5c15
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563626027 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.3563626027 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_sideload/latest

Test location /workspace/coverage/default/21.kmac_smoke.991004710
Short name T351
Test name
Test status
Simulation time 510332143 ps
CPU time 9.79 seconds
Started Aug 13 04:40:30 PM PDT 24
Finished Aug 13 04:40:41 PM PDT 24
Peak memory 226708 kb
Host smart-f52d115c-3b3d-4995-a26b-6b57a19ba971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991004710 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.991004710 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_smoke/latest

Test location /workspace/coverage/default/21.kmac_stress_all.3291323535
Short name T617
Test name
Test status
Simulation time 89263432537 ps
CPU time 2509.43 seconds
Started Aug 13 04:40:32 PM PDT 24
Finished Aug 13 05:22:23 PM PDT 24
Peak memory 1018696 kb
Host smart-86723ee3-0982-45aa-b1da-0ae2abe0e5a4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3291323535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.3291323535 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_stress_all/latest

Test location /workspace/coverage/default/22.kmac_alert_test.3151884295
Short name T323
Test name
Test status
Simulation time 15899332 ps
CPU time 0.82 seconds
Started Aug 13 04:40:37 PM PDT 24
Finished Aug 13 04:40:38 PM PDT 24
Peak memory 218236 kb
Host smart-c51b3704-b49c-4239-aad3-412b8e470854
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151884295 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.3151884295 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_alert_test/latest

Test location /workspace/coverage/default/22.kmac_app.1168811792
Short name T243
Test name
Test status
Simulation time 5709666338 ps
CPU time 31.07 seconds
Started Aug 13 04:40:36 PM PDT 24
Finished Aug 13 04:41:08 PM PDT 24
Peak memory 243176 kb
Host smart-de87851a-798d-46d9-b4ab-ee22208ed3df
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168811792 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.1168811792 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/22.kmac_app/latest

Test location /workspace/coverage/default/22.kmac_burst_write.3111819385
Short name T563
Test name
Test status
Simulation time 23085159382 ps
CPU time 621.64 seconds
Started Aug 13 04:40:45 PM PDT 24
Finished Aug 13 04:51:07 PM PDT 24
Peak memory 244000 kb
Host smart-b28a3ca6-73cf-43c4-930e-a131b8300b52
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111819385 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.311181938
5 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_burst_write/latest

Test location /workspace/coverage/default/22.kmac_entropy_refresh.1402609203
Short name T244
Test name
Test status
Simulation time 50058972371 ps
CPU time 287.19 seconds
Started Aug 13 04:40:43 PM PDT 24
Finished Aug 13 04:45:31 PM PDT 24
Peak memory 408300 kb
Host smart-7b2a5818-eb47-4043-87e7-d32322367d85
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402609203 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.1
402609203 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/22.kmac_error.2970527972
Short name T448
Test name
Test status
Simulation time 12169110257 ps
CPU time 441.61 seconds
Started Aug 13 04:40:39 PM PDT 24
Finished Aug 13 04:48:01 PM PDT 24
Peak memory 530348 kb
Host smart-5b62f4c0-ee92-4be6-95ad-db9329138d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970527972 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.2970527972 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_error/latest

Test location /workspace/coverage/default/22.kmac_key_error.2427708416
Short name T675
Test name
Test status
Simulation time 7507270775 ps
CPU time 8.69 seconds
Started Aug 13 04:40:52 PM PDT 24
Finished Aug 13 04:41:00 PM PDT 24
Peak memory 226512 kb
Host smart-99a50e73-58b5-487c-8d1b-e4af25b99d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427708416 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.2427708416 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_key_error/latest

Test location /workspace/coverage/default/22.kmac_lc_escalation.889373103
Short name T44
Test name
Test status
Simulation time 1291963263 ps
CPU time 15.69 seconds
Started Aug 13 04:40:44 PM PDT 24
Finished Aug 13 04:41:00 PM PDT 24
Peak memory 243188 kb
Host smart-5d2d1722-7d63-41bd-b849-631708985f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889373103 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.889373103 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/22.kmac_lc_escalation/latest

Test location /workspace/coverage/default/22.kmac_long_msg_and_output.2337731048
Short name T423
Test name
Test status
Simulation time 9970355651 ps
CPU time 1087.98 seconds
Started Aug 13 04:40:38 PM PDT 24
Finished Aug 13 04:58:46 PM PDT 24
Peak memory 760816 kb
Host smart-d1b710b1-f0d0-4018-b76c-cd80568685cc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337731048 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_a
nd_output.2337731048 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/22.kmac_sideload.3750071808
Short name T717
Test name
Test status
Simulation time 18961629172 ps
CPU time 520.67 seconds
Started Aug 13 04:40:36 PM PDT 24
Finished Aug 13 04:49:16 PM PDT 24
Peak memory 623528 kb
Host smart-1ccfd74c-1b36-445c-b9a9-449fb0e321a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750071808 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.3750071808 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_sideload/latest

Test location /workspace/coverage/default/22.kmac_smoke.2155344000
Short name T308
Test name
Test status
Simulation time 252735111 ps
CPU time 2.01 seconds
Started Aug 13 04:40:43 PM PDT 24
Finished Aug 13 04:40:45 PM PDT 24
Peak memory 226700 kb
Host smart-8520e03f-2ba4-46c6-84f6-a80033e8b8b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155344000 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.2155344000 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_smoke/latest

Test location /workspace/coverage/default/22.kmac_stress_all.2844829161
Short name T420
Test name
Test status
Simulation time 30257513520 ps
CPU time 2665.4 seconds
Started Aug 13 04:40:36 PM PDT 24
Finished Aug 13 05:25:02 PM PDT 24
Peak memory 820320 kb
Host smart-29c034f2-1b4e-41d8-aeef-c2e27e83a9b8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2844829161 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.2844829161 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_stress_all/latest

Test location /workspace/coverage/default/23.kmac_alert_test.1728555656
Short name T666
Test name
Test status
Simulation time 24937538 ps
CPU time 0.82 seconds
Started Aug 13 04:40:41 PM PDT 24
Finished Aug 13 04:40:42 PM PDT 24
Peak memory 218192 kb
Host smart-ba06cb1c-03e0-4183-a520-e1440e11fae1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728555656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.1728555656 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_alert_test/latest

Test location /workspace/coverage/default/23.kmac_app.301050833
Short name T471
Test name
Test status
Simulation time 16054633332 ps
CPU time 306.43 seconds
Started Aug 13 04:40:45 PM PDT 24
Finished Aug 13 04:45:52 PM PDT 24
Peak memory 429384 kb
Host smart-1bd0f082-f8fb-4374-baef-519d54eb5216
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301050833 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.301050833 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/23.kmac_app/latest

Test location /workspace/coverage/default/23.kmac_burst_write.3361057881
Short name T331
Test name
Test status
Simulation time 14852043902 ps
CPU time 1528.85 seconds
Started Aug 13 04:40:37 PM PDT 24
Finished Aug 13 05:06:06 PM PDT 24
Peak memory 248680 kb
Host smart-d2b998f6-62c9-4b1a-a546-41b65d440247
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361057881 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.336105788
1 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_burst_write/latest

Test location /workspace/coverage/default/23.kmac_entropy_refresh.2948063261
Short name T579
Test name
Test status
Simulation time 53583993429 ps
CPU time 332.92 seconds
Started Aug 13 04:40:39 PM PDT 24
Finished Aug 13 04:46:12 PM PDT 24
Peak memory 464440 kb
Host smart-e8d42217-5b0d-476e-99fb-1eff115b1f7a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948063261 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.2
948063261 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/23.kmac_error.953787428
Short name T463
Test name
Test status
Simulation time 29714811511 ps
CPU time 396.8 seconds
Started Aug 13 04:40:48 PM PDT 24
Finished Aug 13 04:47:25 PM PDT 24
Peak memory 528472 kb
Host smart-90e933fb-01bf-4e16-8b45-66fb2bb39647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953787428 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.953787428 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_error/latest

Test location /workspace/coverage/default/23.kmac_key_error.3808214326
Short name T5
Test name
Test status
Simulation time 68744296 ps
CPU time 1.36 seconds
Started Aug 13 04:40:41 PM PDT 24
Finished Aug 13 04:40:43 PM PDT 24
Peak memory 226080 kb
Host smart-9ea78191-b4bf-4d09-9c25-8ed512748bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808214326 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.3808214326 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_key_error/latest

Test location /workspace/coverage/default/23.kmac_lc_escalation.2118154183
Short name T481
Test name
Test status
Simulation time 386357414 ps
CPU time 1.49 seconds
Started Aug 13 04:40:48 PM PDT 24
Finished Aug 13 04:40:49 PM PDT 24
Peak memory 226480 kb
Host smart-fd627a15-f4e2-4dce-b65b-c509ca033b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118154183 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.2118154183 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/23.kmac_lc_escalation/latest

Test location /workspace/coverage/default/23.kmac_long_msg_and_output.2218991986
Short name T375
Test name
Test status
Simulation time 154879952359 ps
CPU time 3110.28 seconds
Started Aug 13 04:40:38 PM PDT 24
Finished Aug 13 05:32:28 PM PDT 24
Peak memory 1543984 kb
Host smart-109d5422-1b95-4a2e-92ea-e87e30b9accb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218991986 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_a
nd_output.2218991986 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/23.kmac_sideload.149644657
Short name T591
Test name
Test status
Simulation time 10953920150 ps
CPU time 259.71 seconds
Started Aug 13 04:40:49 PM PDT 24
Finished Aug 13 04:45:08 PM PDT 24
Peak memory 308356 kb
Host smart-169ba104-ce2a-4631-bdee-6516ec2c5514
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149644657 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.149644657 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_sideload/latest

Test location /workspace/coverage/default/23.kmac_smoke.3345428326
Short name T543
Test name
Test status
Simulation time 6172642374 ps
CPU time 37.24 seconds
Started Aug 13 04:40:38 PM PDT 24
Finished Aug 13 04:41:16 PM PDT 24
Peak memory 223016 kb
Host smart-314cc686-9662-4862-ba62-d5e105d0da42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345428326 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.3345428326 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_smoke/latest

Test location /workspace/coverage/default/23.kmac_stress_all.278102083
Short name T681
Test name
Test status
Simulation time 20670172492 ps
CPU time 114.33 seconds
Started Aug 13 04:40:38 PM PDT 24
Finished Aug 13 04:42:32 PM PDT 24
Peak memory 282736 kb
Host smart-c5fa1ca8-1a04-4de6-b1a8-44cc54b1a500
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=278102083 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.278102083 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_stress_all/latest

Test location /workspace/coverage/default/24.kmac_alert_test.607116058
Short name T262
Test name
Test status
Simulation time 25732432 ps
CPU time 0.9 seconds
Started Aug 13 04:40:45 PM PDT 24
Finished Aug 13 04:40:46 PM PDT 24
Peak memory 218172 kb
Host smart-a0fcfe5d-8089-453a-88a8-ebd7cfa0dfe0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607116058 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.607116058 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/24.kmac_alert_test/latest

Test location /workspace/coverage/default/24.kmac_app.3644350504
Short name T249
Test name
Test status
Simulation time 6054038451 ps
CPU time 62.28 seconds
Started Aug 13 04:40:37 PM PDT 24
Finished Aug 13 04:41:39 PM PDT 24
Peak memory 245076 kb
Host smart-4dde4f42-1883-4296-8b0f-f9ecca30ebab
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644350504 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.3644350504 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/24.kmac_app/latest

Test location /workspace/coverage/default/24.kmac_burst_write.2656486625
Short name T451
Test name
Test status
Simulation time 19220318225 ps
CPU time 824.88 seconds
Started Aug 13 04:40:37 PM PDT 24
Finished Aug 13 04:54:22 PM PDT 24
Peak memory 251872 kb
Host smart-297b2ec5-b349-4534-8436-f8e555a0bc00
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656486625 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.265648662
5 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_burst_write/latest

Test location /workspace/coverage/default/24.kmac_entropy_refresh.1096888606
Short name T56
Test name
Test status
Simulation time 20040517880 ps
CPU time 292.54 seconds
Started Aug 13 04:40:49 PM PDT 24
Finished Aug 13 04:45:42 PM PDT 24
Peak memory 313192 kb
Host smart-d1b337dd-f9b5-4211-82ac-b5355405afdf
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096888606 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.1
096888606 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/24.kmac_error.3478455069
Short name T139
Test name
Test status
Simulation time 7638045727 ps
CPU time 266.27 seconds
Started Aug 13 04:40:45 PM PDT 24
Finished Aug 13 04:45:11 PM PDT 24
Peak memory 428668 kb
Host smart-e3dcef96-3a7c-46d1-9d69-1e25bfa40c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478455069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.3478455069 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_error/latest

Test location /workspace/coverage/default/24.kmac_key_error.2172146025
Short name T112
Test name
Test status
Simulation time 7055960494 ps
CPU time 12.83 seconds
Started Aug 13 04:40:47 PM PDT 24
Finished Aug 13 04:40:59 PM PDT 24
Peak memory 226512 kb
Host smart-9f05b573-736b-4489-9836-f9c33c4df5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172146025 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.2172146025 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_key_error/latest

Test location /workspace/coverage/default/24.kmac_lc_escalation.38953080
Short name T421
Test name
Test status
Simulation time 121966305 ps
CPU time 1.29 seconds
Started Aug 13 04:40:45 PM PDT 24
Finished Aug 13 04:40:46 PM PDT 24
Peak memory 226548 kb
Host smart-18cb1493-9bd1-40bf-89dc-06c584f41bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38953080 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.38953080 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_lc_escalation/latest

Test location /workspace/coverage/default/24.kmac_long_msg_and_output.3559045930
Short name T334
Test name
Test status
Simulation time 10559017527 ps
CPU time 1287.47 seconds
Started Aug 13 04:40:51 PM PDT 24
Finished Aug 13 05:02:19 PM PDT 24
Peak memory 831312 kb
Host smart-1dae1b94-0480-4a76-a1df-1c3e04c138f8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559045930 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_a
nd_output.3559045930 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/24.kmac_sideload.3086336124
Short name T531
Test name
Test status
Simulation time 10981389763 ps
CPU time 249.1 seconds
Started Aug 13 04:40:37 PM PDT 24
Finished Aug 13 04:44:47 PM PDT 24
Peak memory 303784 kb
Host smart-6b6dfec6-7e68-44c0-867e-ea87711fb950
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086336124 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.3086336124 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_sideload/latest

Test location /workspace/coverage/default/24.kmac_smoke.2645818865
Short name T339
Test name
Test status
Simulation time 672525732 ps
CPU time 18.61 seconds
Started Aug 13 04:40:36 PM PDT 24
Finished Aug 13 04:40:55 PM PDT 24
Peak memory 226632 kb
Host smart-bb92a7ae-6770-4e4c-9ea2-cacc9148eaac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645818865 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.2645818865 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_smoke/latest

Test location /workspace/coverage/default/24.kmac_stress_all.2215115993
Short name T64
Test name
Test status
Simulation time 221849174497 ps
CPU time 1565.66 seconds
Started Aug 13 04:40:40 PM PDT 24
Finished Aug 13 05:06:46 PM PDT 24
Peak memory 883724 kb
Host smart-90a07891-832a-42ac-873a-64cf7bf69b0d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2215115993 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.2215115993 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_stress_all/latest

Test location /workspace/coverage/default/25.kmac_alert_test.2075442246
Short name T108
Test name
Test status
Simulation time 14437064 ps
CPU time 0.82 seconds
Started Aug 13 04:40:54 PM PDT 24
Finished Aug 13 04:40:55 PM PDT 24
Peak memory 218196 kb
Host smart-287226ca-1262-46e1-9573-d957e32ad27b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075442246 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.2075442246 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_alert_test/latest

Test location /workspace/coverage/default/25.kmac_app.883159252
Short name T590
Test name
Test status
Simulation time 908098336 ps
CPU time 15.23 seconds
Started Aug 13 04:40:40 PM PDT 24
Finished Aug 13 04:40:55 PM PDT 24
Peak memory 242208 kb
Host smart-e6037894-8b86-400d-aa1c-446d47b75894
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883159252 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.883159252 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/25.kmac_app/latest

Test location /workspace/coverage/default/25.kmac_burst_write.575674437
Short name T330
Test name
Test status
Simulation time 14438595584 ps
CPU time 598.96 seconds
Started Aug 13 04:40:58 PM PDT 24
Finished Aug 13 04:50:57 PM PDT 24
Peak memory 237908 kb
Host smart-050b6516-03dc-4db9-89ad-4d290793a44e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575674437 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.575674437
+enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_burst_write/latest

Test location /workspace/coverage/default/25.kmac_entropy_refresh.1508560491
Short name T383
Test name
Test status
Simulation time 7942596614 ps
CPU time 223.64 seconds
Started Aug 13 04:40:49 PM PDT 24
Finished Aug 13 04:44:32 PM PDT 24
Peak memory 384660 kb
Host smart-d70423c1-0ff3-4210-9459-bc21fb40f01b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508560491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.1
508560491 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/25.kmac_error.2934592917
Short name T615
Test name
Test status
Simulation time 3898431084 ps
CPU time 328.54 seconds
Started Aug 13 04:40:56 PM PDT 24
Finished Aug 13 04:46:25 PM PDT 24
Peak memory 338180 kb
Host smart-15471b1e-4099-4750-b804-22750f83cf59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934592917 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_error.2934592917 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_error/latest

Test location /workspace/coverage/default/25.kmac_key_error.3847781474
Short name T572
Test name
Test status
Simulation time 803279938 ps
CPU time 7.59 seconds
Started Aug 13 04:40:49 PM PDT 24
Finished Aug 13 04:40:56 PM PDT 24
Peak memory 226440 kb
Host smart-f760867c-b8fc-4700-ba08-5504b60b42dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847781474 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.3847781474 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_key_error/latest

Test location /workspace/coverage/default/25.kmac_lc_escalation.337647847
Short name T364
Test name
Test status
Simulation time 136555361 ps
CPU time 1.31 seconds
Started Aug 13 04:40:52 PM PDT 24
Finished Aug 13 04:40:54 PM PDT 24
Peak memory 226528 kb
Host smart-c15308c3-695e-43d0-a343-ce1c4304ea3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337647847 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.337647847 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/25.kmac_lc_escalation/latest

Test location /workspace/coverage/default/25.kmac_long_msg_and_output.2722531020
Short name T378
Test name
Test status
Simulation time 67386918708 ps
CPU time 1188.12 seconds
Started Aug 13 04:40:40 PM PDT 24
Finished Aug 13 05:00:28 PM PDT 24
Peak memory 802544 kb
Host smart-c0688912-f1d4-40c6-b835-d20f015a7231
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722531020 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_a
nd_output.2722531020 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/25.kmac_sideload.3969209592
Short name T602
Test name
Test status
Simulation time 5445414634 ps
CPU time 72.4 seconds
Started Aug 13 04:40:45 PM PDT 24
Finished Aug 13 04:41:57 PM PDT 24
Peak memory 244000 kb
Host smart-c638883f-4b84-4be6-b424-0957e492dfed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969209592 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.3969209592 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_sideload/latest

Test location /workspace/coverage/default/25.kmac_smoke.3203380150
Short name T525
Test name
Test status
Simulation time 2223859461 ps
CPU time 12.06 seconds
Started Aug 13 04:40:44 PM PDT 24
Finished Aug 13 04:40:56 PM PDT 24
Peak memory 226632 kb
Host smart-6271923f-337f-4d6a-ae64-06d1d018af8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203380150 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.3203380150 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_smoke/latest

Test location /workspace/coverage/default/25.kmac_stress_all.204713043
Short name T415
Test name
Test status
Simulation time 52764578149 ps
CPU time 1750.39 seconds
Started Aug 13 04:40:49 PM PDT 24
Finished Aug 13 05:10:00 PM PDT 24
Peak memory 1356920 kb
Host smart-9e7ed001-cba8-4a20-99a6-9212a6d551e8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=204713043 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.204713043 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_stress_all/latest

Test location /workspace/coverage/default/26.kmac_alert_test.1110551636
Short name T446
Test name
Test status
Simulation time 25719818 ps
CPU time 0.76 seconds
Started Aug 13 04:40:47 PM PDT 24
Finished Aug 13 04:40:48 PM PDT 24
Peak memory 218148 kb
Host smart-8541522b-f8ad-4f1a-8a77-c0ef0fa953b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110551636 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.1110551636 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_alert_test/latest

Test location /workspace/coverage/default/26.kmac_app.360999190
Short name T720
Test name
Test status
Simulation time 24466331587 ps
CPU time 165.8 seconds
Started Aug 13 04:40:47 PM PDT 24
Finished Aug 13 04:43:33 PM PDT 24
Peak memory 347076 kb
Host smart-c4f85337-b959-4680-9f33-ab9d81883306
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360999190 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.360999190 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/26.kmac_app/latest

Test location /workspace/coverage/default/26.kmac_burst_write.2312862151
Short name T669
Test name
Test status
Simulation time 54055883913 ps
CPU time 1420.52 seconds
Started Aug 13 04:40:48 PM PDT 24
Finished Aug 13 05:04:29 PM PDT 24
Peak memory 262752 kb
Host smart-c11ae75b-ac6f-48ca-8874-10d3389c89be
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312862151 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.231286215
1 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_burst_write/latest

Test location /workspace/coverage/default/26.kmac_entropy_refresh.1805341299
Short name T476
Test name
Test status
Simulation time 13037678903 ps
CPU time 236.9 seconds
Started Aug 13 04:40:48 PM PDT 24
Finished Aug 13 04:44:45 PM PDT 24
Peak memory 297128 kb
Host smart-c72b3a52-4214-401a-a560-1cfc4f58c693
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805341299 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.1
805341299 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/26.kmac_error.757059912
Short name T397
Test name
Test status
Simulation time 10769967096 ps
CPU time 328.08 seconds
Started Aug 13 04:40:49 PM PDT 24
Finished Aug 13 04:46:17 PM PDT 24
Peak memory 481436 kb
Host smart-e8a3f061-7284-44fa-a3d1-11516728be01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757059912 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.757059912 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_error/latest

Test location /workspace/coverage/default/26.kmac_key_error.20033850
Short name T214
Test name
Test status
Simulation time 7648740612 ps
CPU time 14.33 seconds
Started Aug 13 04:40:50 PM PDT 24
Finished Aug 13 04:41:04 PM PDT 24
Peak memory 226644 kb
Host smart-f85f4589-ebb3-4afa-8898-ae9a5f807bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20033850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.20033850 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_key_error/latest

Test location /workspace/coverage/default/26.kmac_sideload.835676802
Short name T703
Test name
Test status
Simulation time 5511771218 ps
CPU time 146.47 seconds
Started Aug 13 04:40:47 PM PDT 24
Finished Aug 13 04:43:14 PM PDT 24
Peak memory 347900 kb
Host smart-fb887b9f-832c-4001-8fda-653f3a4dba1f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835676802 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.835676802 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_sideload/latest

Test location /workspace/coverage/default/26.kmac_smoke.3606370067
Short name T523
Test name
Test status
Simulation time 1958638375 ps
CPU time 76.87 seconds
Started Aug 13 04:41:00 PM PDT 24
Finished Aug 13 04:42:17 PM PDT 24
Peak memory 223152 kb
Host smart-38c6a94f-6555-41fa-895e-fe9b0d513743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606370067 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.3606370067 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_smoke/latest

Test location /workspace/coverage/default/26.kmac_stress_all.800300081
Short name T600
Test name
Test status
Simulation time 189385293356 ps
CPU time 1183.98 seconds
Started Aug 13 04:40:49 PM PDT 24
Finished Aug 13 05:00:33 PM PDT 24
Peak memory 774196 kb
Host smart-32f5b181-d993-40f9-a311-fe028f70b865
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=800300081 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.800300081 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_stress_all/latest

Test location /workspace/coverage/default/27.kmac_alert_test.1903382733
Short name T283
Test name
Test status
Simulation time 90627993 ps
CPU time 0.81 seconds
Started Aug 13 04:40:50 PM PDT 24
Finished Aug 13 04:40:51 PM PDT 24
Peak memory 218192 kb
Host smart-158c5f22-8626-4c96-a264-bce059ec8d22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903382733 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.1903382733 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_alert_test/latest

Test location /workspace/coverage/default/27.kmac_app.3377042170
Short name T229
Test name
Test status
Simulation time 68761095708 ps
CPU time 405.25 seconds
Started Aug 13 04:40:54 PM PDT 24
Finished Aug 13 04:47:40 PM PDT 24
Peak memory 353904 kb
Host smart-54962bf4-7e16-4ba1-9a00-8c5ae22d4c1a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377042170 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.3377042170 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/27.kmac_app/latest

Test location /workspace/coverage/default/27.kmac_burst_write.4292925350
Short name T359
Test name
Test status
Simulation time 14274826320 ps
CPU time 1277.76 seconds
Started Aug 13 04:40:48 PM PDT 24
Finished Aug 13 05:02:06 PM PDT 24
Peak memory 244460 kb
Host smart-db5026bc-fdd6-44e6-8fb4-d477b04c1074
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292925350 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.429292535
0 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_burst_write/latest

Test location /workspace/coverage/default/27.kmac_entropy_refresh.4000598795
Short name T332
Test name
Test status
Simulation time 6629807660 ps
CPU time 168.53 seconds
Started Aug 13 04:40:49 PM PDT 24
Finished Aug 13 04:43:37 PM PDT 24
Peak memory 331456 kb
Host smart-9c4ce513-401c-4578-8326-95a452623be1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000598795 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.4
000598795 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/27.kmac_key_error.3683981620
Short name T380
Test name
Test status
Simulation time 9113604753 ps
CPU time 6.15 seconds
Started Aug 13 04:40:52 PM PDT 24
Finished Aug 13 04:40:58 PM PDT 24
Peak memory 226540 kb
Host smart-f9e505c9-56de-4eee-970a-da0c2f076052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683981620 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.3683981620 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_key_error/latest

Test location /workspace/coverage/default/27.kmac_lc_escalation.3155420815
Short name T635
Test name
Test status
Simulation time 97569705 ps
CPU time 1.36 seconds
Started Aug 13 04:40:51 PM PDT 24
Finished Aug 13 04:40:53 PM PDT 24
Peak memory 226592 kb
Host smart-5a8d9dc4-4ab4-4805-9be0-c76d69984d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155420815 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.3155420815 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/27.kmac_lc_escalation/latest

Test location /workspace/coverage/default/27.kmac_long_msg_and_output.2931828815
Short name T303
Test name
Test status
Simulation time 138807273459 ps
CPU time 3256.07 seconds
Started Aug 13 04:40:48 PM PDT 24
Finished Aug 13 05:35:05 PM PDT 24
Peak memory 2767304 kb
Host smart-2352b66e-54c9-44a0-9981-e11d245ddf6a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931828815 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_a
nd_output.2931828815 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/27.kmac_sideload.4239730274
Short name T252
Test name
Test status
Simulation time 16988122763 ps
CPU time 312.47 seconds
Started Aug 13 04:40:50 PM PDT 24
Finished Aug 13 04:46:03 PM PDT 24
Peak memory 318388 kb
Host smart-870e5281-b1eb-4be4-958e-c9d4ee1b71f4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239730274 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.4239730274 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_sideload/latest

Test location /workspace/coverage/default/27.kmac_smoke.2741077001
Short name T215
Test name
Test status
Simulation time 579537981 ps
CPU time 13.94 seconds
Started Aug 13 04:40:49 PM PDT 24
Finished Aug 13 04:41:03 PM PDT 24
Peak memory 226644 kb
Host smart-87d32c1d-5e0b-4f49-835a-c5ad73ba95fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741077001 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.2741077001 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_smoke/latest

Test location /workspace/coverage/default/27.kmac_stress_all.3577526573
Short name T588
Test name
Test status
Simulation time 6683620495 ps
CPU time 105.63 seconds
Started Aug 13 04:41:01 PM PDT 24
Finished Aug 13 04:42:47 PM PDT 24
Peak memory 298816 kb
Host smart-52f04811-e97d-4460-ba31-64dc6f94f8ac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3577526573 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all.3577526573 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_stress_all/latest

Test location /workspace/coverage/default/28.kmac_alert_test.127338796
Short name T257
Test name
Test status
Simulation time 17706446 ps
CPU time 0.81 seconds
Started Aug 13 04:40:54 PM PDT 24
Finished Aug 13 04:40:55 PM PDT 24
Peak memory 218208 kb
Host smart-22c0a222-443d-4286-9fb5-243c7d558ae8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127338796 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.127338796 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/28.kmac_alert_test/latest

Test location /workspace/coverage/default/28.kmac_app.983323765
Short name T443
Test name
Test status
Simulation time 3363198881 ps
CPU time 40.23 seconds
Started Aug 13 04:40:47 PM PDT 24
Finished Aug 13 04:41:27 PM PDT 24
Peak memory 235396 kb
Host smart-5116fbbf-8845-47ec-9b2a-87b7acd0044e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983323765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.983323765 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/28.kmac_app/latest

Test location /workspace/coverage/default/28.kmac_burst_write.4050556073
Short name T546
Test name
Test status
Simulation time 5318180053 ps
CPU time 122.04 seconds
Started Aug 13 04:40:52 PM PDT 24
Finished Aug 13 04:42:55 PM PDT 24
Peak memory 228212 kb
Host smart-06ade567-6710-47fb-9860-eb1e5885eb68
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050556073 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.405055607
3 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_burst_write/latest

Test location /workspace/coverage/default/28.kmac_entropy_refresh.3279309818
Short name T208
Test name
Test status
Simulation time 4359403543 ps
CPU time 100.48 seconds
Started Aug 13 04:40:49 PM PDT 24
Finished Aug 13 04:42:30 PM PDT 24
Peak memory 289660 kb
Host smart-4342350e-d8f6-4598-aa8a-a3832699f4ed
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279309818 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_entropy_refresh.3
279309818 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/28.kmac_error.1365273230
Short name T507
Test name
Test status
Simulation time 1706525816 ps
CPU time 123.6 seconds
Started Aug 13 04:40:53 PM PDT 24
Finished Aug 13 04:42:57 PM PDT 24
Peak memory 284584 kb
Host smart-0f381493-0769-45d3-b42a-9d021083cef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365273230 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.1365273230 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_error/latest

Test location /workspace/coverage/default/28.kmac_key_error.420402892
Short name T686
Test name
Test status
Simulation time 3526699591 ps
CPU time 11.25 seconds
Started Aug 13 04:40:53 PM PDT 24
Finished Aug 13 04:41:04 PM PDT 24
Peak memory 226504 kb
Host smart-5322c016-8aa3-45a9-8966-06bd13a5b880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420402892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.420402892 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_key_error/latest

Test location /workspace/coverage/default/28.kmac_lc_escalation.2636654653
Short name T69
Test name
Test status
Simulation time 120255642 ps
CPU time 1.57 seconds
Started Aug 13 04:40:59 PM PDT 24
Finished Aug 13 04:41:01 PM PDT 24
Peak memory 226728 kb
Host smart-66e4620c-9c4f-468f-8548-1c3a6f26f3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636654653 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.2636654653 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/28.kmac_lc_escalation/latest

Test location /workspace/coverage/default/28.kmac_long_msg_and_output.3479764635
Short name T496
Test name
Test status
Simulation time 16069988686 ps
CPU time 153.56 seconds
Started Aug 13 04:40:50 PM PDT 24
Finished Aug 13 04:43:24 PM PDT 24
Peak memory 409636 kb
Host smart-ad591641-3c49-4481-9a54-5f0666c0a592
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479764635 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_a
nd_output.3479764635 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/28.kmac_sideload.3147156999
Short name T266
Test name
Test status
Simulation time 21001618490 ps
CPU time 523.26 seconds
Started Aug 13 04:40:51 PM PDT 24
Finished Aug 13 04:49:34 PM PDT 24
Peak memory 648216 kb
Host smart-ee8eb1c6-a4a9-4e55-b864-5677780d7a4e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147156999 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.3147156999 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_sideload/latest

Test location /workspace/coverage/default/28.kmac_smoke.1910556560
Short name T430
Test name
Test status
Simulation time 480535207 ps
CPU time 8.45 seconds
Started Aug 13 04:40:54 PM PDT 24
Finished Aug 13 04:41:03 PM PDT 24
Peak memory 226596 kb
Host smart-4f23433f-fc2d-4394-b6d0-2aa84d033522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910556560 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.1910556560 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_smoke/latest

Test location /workspace/coverage/default/28.kmac_stress_all.28019594
Short name T281
Test name
Test status
Simulation time 1360908690 ps
CPU time 71.79 seconds
Started Aug 13 04:41:02 PM PDT 24
Finished Aug 13 04:42:14 PM PDT 24
Peak memory 243432 kb
Host smart-28d3d854-9823-411d-bb31-bd8611fd0499
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=28019594 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.28019594 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_stress_all/latest

Test location /workspace/coverage/default/29.kmac_alert_test.698620412
Short name T627
Test name
Test status
Simulation time 57030582 ps
CPU time 0.82 seconds
Started Aug 13 04:40:57 PM PDT 24
Finished Aug 13 04:40:58 PM PDT 24
Peak memory 218292 kb
Host smart-053f4fb3-be07-49a3-9981-0cf6060dcec9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698620412 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.698620412 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/29.kmac_alert_test/latest

Test location /workspace/coverage/default/29.kmac_app.1465172098
Short name T541
Test name
Test status
Simulation time 28169761409 ps
CPU time 139.19 seconds
Started Aug 13 04:40:57 PM PDT 24
Finished Aug 13 04:43:16 PM PDT 24
Peak memory 315964 kb
Host smart-e7c8e2dc-3926-4843-8a27-5941a052a45e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465172098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.1465172098 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/29.kmac_app/latest

Test location /workspace/coverage/default/29.kmac_burst_write.1412042782
Short name T54
Test name
Test status
Simulation time 8251736795 ps
CPU time 922.58 seconds
Started Aug 13 04:41:03 PM PDT 24
Finished Aug 13 04:56:26 PM PDT 24
Peak memory 243080 kb
Host smart-c3274a07-dc9f-4529-b12f-6e0f9bf3eead
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412042782 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.141204278
2 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_burst_write/latest

Test location /workspace/coverage/default/29.kmac_entropy_refresh.2959603324
Short name T535
Test name
Test status
Simulation time 307177150 ps
CPU time 8.44 seconds
Started Aug 13 04:41:04 PM PDT 24
Finished Aug 13 04:41:12 PM PDT 24
Peak memory 219856 kb
Host smart-5b39aa37-a9b5-4d47-a1ea-788d809eee80
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959603324 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.2
959603324 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/29.kmac_error.2346324316
Short name T433
Test name
Test status
Simulation time 36426509328 ps
CPU time 313.05 seconds
Started Aug 13 04:41:01 PM PDT 24
Finished Aug 13 04:46:14 PM PDT 24
Peak memory 469248 kb
Host smart-63cebd13-ee4c-4b25-aa07-e9da16f82a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346324316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.2346324316 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_error/latest

Test location /workspace/coverage/default/29.kmac_key_error.2347260981
Short name T6
Test name
Test status
Simulation time 835818775 ps
CPU time 6.35 seconds
Started Aug 13 04:41:04 PM PDT 24
Finished Aug 13 04:41:10 PM PDT 24
Peak memory 226436 kb
Host smart-ef75971f-783a-4487-8496-8fb87a4d708d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347260981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.2347260981 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_key_error/latest

Test location /workspace/coverage/default/29.kmac_lc_escalation.1167537192
Short name T315
Test name
Test status
Simulation time 58414864 ps
CPU time 1.62 seconds
Started Aug 13 04:40:57 PM PDT 24
Finished Aug 13 04:40:59 PM PDT 24
Peak memory 226552 kb
Host smart-b5772529-2e22-44a2-ad1f-84bd1211e854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167537192 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.1167537192 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/29.kmac_lc_escalation/latest

Test location /workspace/coverage/default/29.kmac_long_msg_and_output.4279293851
Short name T568
Test name
Test status
Simulation time 28672414769 ps
CPU time 237.78 seconds
Started Aug 13 04:40:56 PM PDT 24
Finished Aug 13 04:44:54 PM PDT 24
Peak memory 507380 kb
Host smart-04f44887-c534-4b0d-8150-de640574a44e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279293851 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_a
nd_output.4279293851 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/29.kmac_sideload.3565749177
Short name T670
Test name
Test status
Simulation time 7826869248 ps
CPU time 255.64 seconds
Started Aug 13 04:40:58 PM PDT 24
Finished Aug 13 04:45:14 PM PDT 24
Peak memory 427300 kb
Host smart-daca8ef2-6aec-4c29-bbe0-be10a66d0cb2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565749177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.3565749177 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_sideload/latest

Test location /workspace/coverage/default/29.kmac_smoke.2729176735
Short name T440
Test name
Test status
Simulation time 1890985165 ps
CPU time 38.69 seconds
Started Aug 13 04:40:57 PM PDT 24
Finished Aug 13 04:41:36 PM PDT 24
Peak memory 226584 kb
Host smart-8a5d6b40-cef3-49d5-a22c-e4bd17f7d552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729176735 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.2729176735 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_smoke/latest

Test location /workspace/coverage/default/29.kmac_stress_all.1817626254
Short name T355
Test name
Test status
Simulation time 11777571281 ps
CPU time 1084.45 seconds
Started Aug 13 04:40:58 PM PDT 24
Finished Aug 13 04:59:03 PM PDT 24
Peak memory 519508 kb
Host smart-4517cea9-ca89-4b70-adac-828b71f4f5d6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1817626254 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.1817626254 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_stress_all/latest

Test location /workspace/coverage/default/3.kmac_alert_test.28606900
Short name T408
Test name
Test status
Simulation time 57015818 ps
CPU time 0.83 seconds
Started Aug 13 04:40:09 PM PDT 24
Finished Aug 13 04:40:10 PM PDT 24
Peak memory 218168 kb
Host smart-677c7882-b529-4d85-8da4-1a09beab9cfc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28606900 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.28606900 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/3.kmac_alert_test/latest

Test location /workspace/coverage/default/3.kmac_app.1605768979
Short name T582
Test name
Test status
Simulation time 96056511643 ps
CPU time 365.5 seconds
Started Aug 13 04:39:54 PM PDT 24
Finished Aug 13 04:46:00 PM PDT 24
Peak memory 459232 kb
Host smart-1cf55dda-990e-4126-81e0-e05803826da1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605768979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.1605768979 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/3.kmac_app/latest

Test location /workspace/coverage/default/3.kmac_app_with_partial_data.3855828180
Short name T295
Test name
Test status
Simulation time 46289426653 ps
CPU time 236.04 seconds
Started Aug 13 04:40:24 PM PDT 24
Finished Aug 13 04:44:20 PM PDT 24
Peak memory 373892 kb
Host smart-2a0ff8ce-cbc3-4523-825b-c926b6d11d29
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855828180 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_par
tial_data.3855828180 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/3.kmac_burst_write.246917708
Short name T700
Test name
Test status
Simulation time 6537544015 ps
CPU time 764.27 seconds
Started Aug 13 04:39:54 PM PDT 24
Finished Aug 13 04:52:39 PM PDT 24
Peak memory 243120 kb
Host smart-83aaf4e1-d77e-44b2-9ddd-8a3967830606
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246917708 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.246917708 +
enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_burst_write/latest

Test location /workspace/coverage/default/3.kmac_edn_timeout_error.1829567672
Short name T694
Test name
Test status
Simulation time 1480086813 ps
CPU time 21.83 seconds
Started Aug 13 04:40:05 PM PDT 24
Finished Aug 13 04:40:29 PM PDT 24
Peak memory 227532 kb
Host smart-85be74ca-a1c6-4d37-bb32-8c12c1bec5b0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1829567672 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.1829567672 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_mode_error.2208145637
Short name T550
Test name
Test status
Simulation time 69205188 ps
CPU time 1.28 seconds
Started Aug 13 04:40:01 PM PDT 24
Finished Aug 13 04:40:02 PM PDT 24
Peak memory 222080 kb
Host smart-5769a8a3-75b3-41f8-a8b2-28adf2af71f7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2208145637 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.2208145637 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_ready_error.1758777693
Short name T10
Test name
Test status
Simulation time 1973808461 ps
CPU time 10.3 seconds
Started Aug 13 04:39:58 PM PDT 24
Finished Aug 13 04:40:08 PM PDT 24
Peak memory 226828 kb
Host smart-ad5b6df6-395d-4245-b454-fa7362a0bb81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758777693 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.1758777693 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/3.kmac_error.1299290086
Short name T297
Test name
Test status
Simulation time 39002533632 ps
CPU time 306.52 seconds
Started Aug 13 04:40:18 PM PDT 24
Finished Aug 13 04:45:24 PM PDT 24
Peak memory 472676 kb
Host smart-51600f20-3ab2-4cdd-829b-554d8d882df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299290086 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.1299290086 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_error/latest

Test location /workspace/coverage/default/3.kmac_key_error.1466324555
Short name T438
Test name
Test status
Simulation time 3790378606 ps
CPU time 4.64 seconds
Started Aug 13 04:40:13 PM PDT 24
Finished Aug 13 04:40:17 PM PDT 24
Peak memory 226596 kb
Host smart-49b7552f-a5f1-4ddc-9739-fbbee799a633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466324555 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.1466324555 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_key_error/latest

Test location /workspace/coverage/default/3.kmac_lc_escalation.4195169300
Short name T40
Test name
Test status
Simulation time 54161808 ps
CPU time 1.41 seconds
Started Aug 13 04:39:58 PM PDT 24
Finished Aug 13 04:39:59 PM PDT 24
Peak memory 226612 kb
Host smart-f5b8e831-0430-4e81-8cff-822cf5c1de33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195169300 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.4195169300 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/3.kmac_lc_escalation/latest

Test location /workspace/coverage/default/3.kmac_long_msg_and_output.1094526562
Short name T309
Test name
Test status
Simulation time 42297044786 ps
CPU time 721.51 seconds
Started Aug 13 04:40:23 PM PDT 24
Finished Aug 13 04:52:25 PM PDT 24
Peak memory 1001212 kb
Host smart-b5ac1506-9b72-48a2-9f2f-2c573cc19aff
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094526562 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_an
d_output.1094526562 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/3.kmac_mubi.3730833566
Short name T385
Test name
Test status
Simulation time 2646100987 ps
CPU time 79.75 seconds
Started Aug 13 04:40:10 PM PDT 24
Finished Aug 13 04:41:30 PM PDT 24
Peak memory 287196 kb
Host smart-855c8939-cbad-40c2-9b42-b6afbb3db5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730833566 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.3730833566 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_mubi/latest

Test location /workspace/coverage/default/3.kmac_sec_cm.3597713565
Short name T29
Test name
Test status
Simulation time 3142339848 ps
CPU time 37.12 seconds
Started Aug 13 04:39:58 PM PDT 24
Finished Aug 13 04:40:35 PM PDT 24
Peak memory 249104 kb
Host smart-7bb9e71a-c4e8-42f5-a0e6-4b1af44ea79b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597713565 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.3597713565 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspace/3.kmac_sec_cm/latest

Test location /workspace/coverage/default/3.kmac_sideload.1735335450
Short name T622
Test name
Test status
Simulation time 5256454422 ps
CPU time 425.49 seconds
Started Aug 13 04:39:56 PM PDT 24
Finished Aug 13 04:47:02 PM PDT 24
Peak memory 356352 kb
Host smart-41de6d64-bf2a-487a-a1ce-49e8543a257b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735335450 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.1735335450 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_sideload/latest

Test location /workspace/coverage/default/3.kmac_smoke.3568345029
Short name T306
Test name
Test status
Simulation time 5309501684 ps
CPU time 49.55 seconds
Started Aug 13 04:39:56 PM PDT 24
Finished Aug 13 04:40:45 PM PDT 24
Peak memory 226756 kb
Host smart-a5042ff8-27c9-4645-940a-7a05d642109a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568345029 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.3568345029 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_smoke/latest

Test location /workspace/coverage/default/3.kmac_stress_all.2278533721
Short name T407
Test name
Test status
Simulation time 14252413984 ps
CPU time 528.53 seconds
Started Aug 13 04:40:09 PM PDT 24
Finished Aug 13 04:48:57 PM PDT 24
Peak memory 355772 kb
Host smart-bbef29a7-9c72-450f-9715-cd147a704224
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2278533721 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.2278533721 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_stress_all/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_kmac.3980279593
Short name T261
Test name
Test status
Simulation time 234352553 ps
CPU time 2.26 seconds
Started Aug 13 04:39:59 PM PDT 24
Finished Aug 13 04:40:02 PM PDT 24
Peak memory 219428 kb
Host smart-6591ea46-7cfe-4659-8332-d8191a7ed12b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980279593 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.kmac_test_vectors_kmac.3980279593 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_kmac_xof.2685273873
Short name T253
Test name
Test status
Simulation time 107825501 ps
CPU time 2.35 seconds
Started Aug 13 04:39:59 PM PDT 24
Finished Aug 13 04:40:01 PM PDT 24
Peak memory 219524 kb
Host smart-049ebbe5-0700-485a-ba42-3d6e44fef676
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685273873 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.kmac_test_vectors_kmac_xof.2685273873 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_224.2384196986
Short name T320
Test name
Test status
Simulation time 61161313016 ps
CPU time 3081.28 seconds
Started Aug 13 04:39:56 PM PDT 24
Finished Aug 13 05:31:18 PM PDT 24
Peak memory 3102844 kb
Host smart-eb6b7f21-c335-4ab0-829d-c5b98021de2b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2384196986 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.2384196986 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_256.3920811990
Short name T606
Test name
Test status
Simulation time 5196017751 ps
CPU time 39.69 seconds
Started Aug 13 04:40:03 PM PDT 24
Finished Aug 13 04:40:43 PM PDT 24
Peak memory 224644 kb
Host smart-2f4b904f-587e-4381-9e4c-3f3db40aacd0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3920811990 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.3920811990 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_384.455956491
Short name T410
Test name
Test status
Simulation time 45930595362 ps
CPU time 2149.48 seconds
Started Aug 13 04:40:07 PM PDT 24
Finished Aug 13 05:15:57 PM PDT 24
Peak memory 2329296 kb
Host smart-52c64e2f-1512-4877-876f-f69866cabb3c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=455956491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.455956491 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_512.601237690
Short name T219
Test name
Test status
Simulation time 56158992400 ps
CPU time 1121.13 seconds
Started Aug 13 04:40:22 PM PDT 24
Finished Aug 13 04:59:04 PM PDT 24
Peak memory 683708 kb
Host smart-5aab2d36-1b00-487b-8e58-05b042e2c312
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=601237690 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.601237690 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_shake_128.263257604
Short name T494
Test name
Test status
Simulation time 41969629807 ps
CPU time 232.74 seconds
Started Aug 13 04:39:58 PM PDT 24
Finished Aug 13 04:43:51 PM PDT 24
Peak memory 437188 kb
Host smart-d6e2ca45-1857-4e66-8340-d91f755bcabe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=263257604 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.263257604 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_shake_256.2901222862
Short name T706
Test name
Test status
Simulation time 43442713817 ps
CPU time 393.32 seconds
Started Aug 13 04:39:55 PM PDT 24
Finished Aug 13 04:46:28 PM PDT 24
Peak memory 262288 kb
Host smart-2cc6bf8f-9344-4639-b46c-5e8de8bd70b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2901222862 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.2901222862 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/30.kmac_alert_test.3874679455
Short name T581
Test name
Test status
Simulation time 19207659 ps
CPU time 0.81 seconds
Started Aug 13 04:40:57 PM PDT 24
Finished Aug 13 04:40:58 PM PDT 24
Peak memory 218180 kb
Host smart-f94d22a4-4e2f-4f03-80ed-afd4dec50b02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874679455 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.3874679455 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_alert_test/latest

Test location /workspace/coverage/default/30.kmac_app.395747397
Short name T687
Test name
Test status
Simulation time 51681328854 ps
CPU time 424.57 seconds
Started Aug 13 04:41:01 PM PDT 24
Finished Aug 13 04:48:06 PM PDT 24
Peak memory 511032 kb
Host smart-fb7e2d01-b251-468e-8e1e-48c0d4d1cf1c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395747397 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.395747397 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/30.kmac_app/latest

Test location /workspace/coverage/default/30.kmac_burst_write.3506178066
Short name T453
Test name
Test status
Simulation time 127359983206 ps
CPU time 1388.36 seconds
Started Aug 13 04:41:01 PM PDT 24
Finished Aug 13 05:04:10 PM PDT 24
Peak memory 258424 kb
Host smart-6f9c9153-1b5a-49b9-a92e-aa0dc936062d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506178066 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.350617806
6 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_burst_write/latest

Test location /workspace/coverage/default/30.kmac_error.2349653354
Short name T611
Test name
Test status
Simulation time 11161467121 ps
CPU time 386.36 seconds
Started Aug 13 04:41:02 PM PDT 24
Finished Aug 13 04:47:28 PM PDT 24
Peak memory 518228 kb
Host smart-80d1baf8-103e-4e73-b2e7-1b464d314111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349653354 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.2349653354 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_error/latest

Test location /workspace/coverage/default/30.kmac_key_error.481598683
Short name T479
Test name
Test status
Simulation time 1337094078 ps
CPU time 10.13 seconds
Started Aug 13 04:41:01 PM PDT 24
Finished Aug 13 04:41:11 PM PDT 24
Peak memory 226552 kb
Host smart-ae92fb33-4cb1-40f5-b9c0-cad722b442bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481598683 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.481598683 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_key_error/latest

Test location /workspace/coverage/default/30.kmac_lc_escalation.1088931675
Short name T25
Test name
Test status
Simulation time 64977558 ps
CPU time 1.31 seconds
Started Aug 13 04:40:58 PM PDT 24
Finished Aug 13 04:40:59 PM PDT 24
Peak memory 226636 kb
Host smart-6e2b38fc-a138-4f45-822f-1396d82c67e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088931675 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.1088931675 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/30.kmac_lc_escalation/latest

Test location /workspace/coverage/default/30.kmac_long_msg_and_output.1173315561
Short name T296
Test name
Test status
Simulation time 21686796143 ps
CPU time 2421.87 seconds
Started Aug 13 04:41:02 PM PDT 24
Finished Aug 13 05:21:24 PM PDT 24
Peak memory 1379240 kb
Host smart-2276560d-8a31-4529-abb8-efec64de0189
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173315561 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_a
nd_output.1173315561 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/30.kmac_sideload.3042372854
Short name T123
Test name
Test status
Simulation time 11501617517 ps
CPU time 384.97 seconds
Started Aug 13 04:41:00 PM PDT 24
Finished Aug 13 04:47:25 PM PDT 24
Peak memory 351428 kb
Host smart-0d9712bf-b21f-43d3-beda-709dc3309094
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042372854 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.3042372854 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_sideload/latest

Test location /workspace/coverage/default/30.kmac_smoke.2676177118
Short name T458
Test name
Test status
Simulation time 189579062 ps
CPU time 4.65 seconds
Started Aug 13 04:40:59 PM PDT 24
Finished Aug 13 04:41:04 PM PDT 24
Peak memory 226092 kb
Host smart-b59a7f8c-52e4-44b8-b073-c739b40af906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676177118 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.2676177118 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_smoke/latest

Test location /workspace/coverage/default/30.kmac_stress_all.1488703748
Short name T393
Test name
Test status
Simulation time 70332332989 ps
CPU time 2581.2 seconds
Started Aug 13 04:40:58 PM PDT 24
Finished Aug 13 05:23:59 PM PDT 24
Peak memory 1365060 kb
Host smart-8b98ad10-9893-4838-8a84-12e3eca99421
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1488703748 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.1488703748 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_stress_all/latest

Test location /workspace/coverage/default/31.kmac_alert_test.344500229
Short name T233
Test name
Test status
Simulation time 20175134 ps
CPU time 0.88 seconds
Started Aug 13 04:41:05 PM PDT 24
Finished Aug 13 04:41:06 PM PDT 24
Peak memory 218196 kb
Host smart-8685b6fe-17a0-4ef0-a206-1d16138f99dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344500229 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.344500229 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/31.kmac_alert_test/latest

Test location /workspace/coverage/default/31.kmac_app.1746827513
Short name T205
Test name
Test status
Simulation time 1333767541 ps
CPU time 38.09 seconds
Started Aug 13 04:41:06 PM PDT 24
Finished Aug 13 04:41:44 PM PDT 24
Peak memory 248800 kb
Host smart-2b573f86-f53b-4b16-b77d-fbd81b2ead3d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746827513 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.1746827513 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/31.kmac_app/latest

Test location /workspace/coverage/default/31.kmac_burst_write.1275326918
Short name T100
Test name
Test status
Simulation time 5454406023 ps
CPU time 142.09 seconds
Started Aug 13 04:40:55 PM PDT 24
Finished Aug 13 04:43:17 PM PDT 24
Peak memory 229012 kb
Host smart-21a724b8-2668-48bb-ac64-a083f1944a35
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275326918 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_write.127532691
8 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_burst_write/latest

Test location /workspace/coverage/default/31.kmac_entropy_refresh.754517508
Short name T329
Test name
Test status
Simulation time 12580824159 ps
CPU time 91.06 seconds
Started Aug 13 04:41:01 PM PDT 24
Finished Aug 13 04:42:32 PM PDT 24
Peak memory 252964 kb
Host smart-389a9757-8aa2-4ae2-b845-2a14415e240b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754517508 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.75
4517508 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/31.kmac_error.2147561711
Short name T213
Test name
Test status
Simulation time 4541004703 ps
CPU time 73.96 seconds
Started Aug 13 04:41:00 PM PDT 24
Finished Aug 13 04:42:14 PM PDT 24
Peak memory 292540 kb
Host smart-856e1b72-1cdc-4113-9fb5-c60da09cbf53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147561711 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.2147561711 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_error/latest

Test location /workspace/coverage/default/31.kmac_key_error.1337525372
Short name T689
Test name
Test status
Simulation time 3161000393 ps
CPU time 7.77 seconds
Started Aug 13 04:41:00 PM PDT 24
Finished Aug 13 04:41:08 PM PDT 24
Peak memory 226412 kb
Host smart-bc764032-92d1-4be3-af77-55bfd509262a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337525372 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.1337525372 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_key_error/latest

Test location /workspace/coverage/default/31.kmac_lc_escalation.2813964821
Short name T363
Test name
Test status
Simulation time 63099042 ps
CPU time 1.37 seconds
Started Aug 13 04:40:59 PM PDT 24
Finished Aug 13 04:41:01 PM PDT 24
Peak memory 226600 kb
Host smart-9f530001-710e-43cd-9882-302746d7320e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813964821 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.2813964821 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/31.kmac_lc_escalation/latest

Test location /workspace/coverage/default/31.kmac_long_msg_and_output.80598133
Short name T587
Test name
Test status
Simulation time 21459266607 ps
CPU time 152.67 seconds
Started Aug 13 04:41:01 PM PDT 24
Finished Aug 13 04:43:34 PM PDT 24
Peak memory 426360 kb
Host smart-db0870b3-ba07-4dae-9829-b5ac887a8e55
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80598133 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and
_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_and
_output.80598133 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/31.kmac_sideload.1144775464
Short name T190
Test name
Test status
Simulation time 221449896040 ps
CPU time 483.82 seconds
Started Aug 13 04:41:02 PM PDT 24
Finished Aug 13 04:49:06 PM PDT 24
Peak memory 557076 kb
Host smart-f290560e-422d-404c-99c1-982fcdbbdea1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144775464 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.1144775464 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_sideload/latest

Test location /workspace/coverage/default/31.kmac_smoke.3308983701
Short name T624
Test name
Test status
Simulation time 2045308478 ps
CPU time 42.3 seconds
Started Aug 13 04:40:56 PM PDT 24
Finished Aug 13 04:41:38 PM PDT 24
Peak memory 226736 kb
Host smart-90ae42d0-624c-4ed6-80c1-eef74efa0aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308983701 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.3308983701 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_smoke/latest

Test location /workspace/coverage/default/31.kmac_stress_all.1784580575
Short name T559
Test name
Test status
Simulation time 5933379219 ps
CPU time 607.27 seconds
Started Aug 13 04:41:05 PM PDT 24
Finished Aug 13 04:51:12 PM PDT 24
Peak memory 500748 kb
Host smart-5c8c9354-7f5b-4ede-aea3-ff6839c118b6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1784580575 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.1784580575 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_stress_all/latest

Test location /workspace/coverage/default/32.kmac_alert_test.3196240786
Short name T314
Test name
Test status
Simulation time 41075215 ps
CPU time 0.82 seconds
Started Aug 13 04:41:06 PM PDT 24
Finished Aug 13 04:41:07 PM PDT 24
Peak memory 218200 kb
Host smart-941c816a-ffd2-4598-95df-83723d0a86da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196240786 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.3196240786 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_alert_test/latest

Test location /workspace/coverage/default/32.kmac_app.974603585
Short name T291
Test name
Test status
Simulation time 12569096815 ps
CPU time 336.35 seconds
Started Aug 13 04:41:12 PM PDT 24
Finished Aug 13 04:46:48 PM PDT 24
Peak memory 472724 kb
Host smart-b04e8af7-8296-4ba2-aa69-e126c14fd457
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974603585 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.974603585 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/32.kmac_app/latest

Test location /workspace/coverage/default/32.kmac_burst_write.3299812879
Short name T718
Test name
Test status
Simulation time 140332424292 ps
CPU time 1207.19 seconds
Started Aug 13 04:41:06 PM PDT 24
Finished Aug 13 05:01:13 PM PDT 24
Peak memory 255292 kb
Host smart-19770d2b-92a3-4f0f-8dbb-eec692e82f03
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299812879 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.329981287
9 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_burst_write/latest

Test location /workspace/coverage/default/32.kmac_entropy_refresh.1563932548
Short name T569
Test name
Test status
Simulation time 1114042369 ps
CPU time 23.8 seconds
Started Aug 13 04:41:06 PM PDT 24
Finished Aug 13 04:41:29 PM PDT 24
Peak memory 243092 kb
Host smart-792be2d7-e2fc-4738-9552-6272ffea9a2d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563932548 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.1
563932548 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/32.kmac_error.4090796267
Short name T625
Test name
Test status
Simulation time 12482262054 ps
CPU time 278.48 seconds
Started Aug 13 04:41:06 PM PDT 24
Finished Aug 13 04:45:45 PM PDT 24
Peak memory 316860 kb
Host smart-311dd51d-eb82-46c5-8f52-6b89c4c0ad49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090796267 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.4090796267 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_error/latest

Test location /workspace/coverage/default/32.kmac_key_error.418102648
Short name T103
Test name
Test status
Simulation time 2608180988 ps
CPU time 4.39 seconds
Started Aug 13 04:41:10 PM PDT 24
Finished Aug 13 04:41:15 PM PDT 24
Peak memory 226624 kb
Host smart-8ea697a7-5c09-466e-9492-54cdddde0632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418102648 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.418102648 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_key_error/latest

Test location /workspace/coverage/default/32.kmac_lc_escalation.3312858233
Short name T42
Test name
Test status
Simulation time 64095364 ps
CPU time 1.62 seconds
Started Aug 13 04:41:05 PM PDT 24
Finished Aug 13 04:41:06 PM PDT 24
Peak memory 226616 kb
Host smart-074ef6d9-68e7-4302-af0c-19ccdc20a4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312858233 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.3312858233 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/32.kmac_lc_escalation/latest

Test location /workspace/coverage/default/32.kmac_sideload.244708187
Short name T469
Test name
Test status
Simulation time 1797497654 ps
CPU time 86.21 seconds
Started Aug 13 04:41:08 PM PDT 24
Finished Aug 13 04:42:34 PM PDT 24
Peak memory 255540 kb
Host smart-7767ea12-59a9-4e1d-a71d-9d1aea1f9954
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244708187 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.244708187 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_sideload/latest

Test location /workspace/coverage/default/32.kmac_smoke.791515871
Short name T216
Test name
Test status
Simulation time 3558001807 ps
CPU time 65.81 seconds
Started Aug 13 04:41:11 PM PDT 24
Finished Aug 13 04:42:17 PM PDT 24
Peak memory 226728 kb
Host smart-67eacd8a-2ccc-4c12-860b-5770ee375df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791515871 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.791515871 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_smoke/latest

Test location /workspace/coverage/default/32.kmac_stress_all.1868526911
Short name T77
Test name
Test status
Simulation time 16439906856 ps
CPU time 398.76 seconds
Started Aug 13 04:41:06 PM PDT 24
Finished Aug 13 04:47:45 PM PDT 24
Peak memory 325072 kb
Host smart-80589c9b-b2e8-40d9-88eb-19ec571d5a87
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1868526911 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.1868526911 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_stress_all/latest

Test location /workspace/coverage/default/33.kmac_alert_test.22180996
Short name T566
Test name
Test status
Simulation time 165295894 ps
CPU time 0.84 seconds
Started Aug 13 04:41:07 PM PDT 24
Finished Aug 13 04:41:07 PM PDT 24
Peak memory 218244 kb
Host smart-10b12d4f-5afc-4c7a-a106-9101325a7097
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22180996 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.22180996 +enable_mas
king=1 +sw_key_masked=0
Directory /workspace/33.kmac_alert_test/latest

Test location /workspace/coverage/default/33.kmac_app.671690259
Short name T595
Test name
Test status
Simulation time 243574203 ps
CPU time 8.57 seconds
Started Aug 13 04:41:05 PM PDT 24
Finished Aug 13 04:41:14 PM PDT 24
Peak memory 226556 kb
Host smart-18eb9c00-bf17-43d7-af52-48027799b8a7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671690259 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.671690259 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/33.kmac_app/latest

Test location /workspace/coverage/default/33.kmac_burst_write.2636407458
Short name T414
Test name
Test status
Simulation time 8075181044 ps
CPU time 225.17 seconds
Started Aug 13 04:41:05 PM PDT 24
Finished Aug 13 04:44:50 PM PDT 24
Peak memory 229512 kb
Host smart-c6402c7a-1932-46d6-9ba7-f9e4b07c516a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636407458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.263640745
8 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_burst_write/latest

Test location /workspace/coverage/default/33.kmac_entropy_refresh.4071249618
Short name T462
Test name
Test status
Simulation time 17191038299 ps
CPU time 310.81 seconds
Started Aug 13 04:41:06 PM PDT 24
Finished Aug 13 04:46:17 PM PDT 24
Peak memory 321956 kb
Host smart-4cf75249-7d2d-49fb-8bc2-3bf07d4444d0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071249618 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.4
071249618 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/33.kmac_error.3666327556
Short name T159
Test name
Test status
Simulation time 2569989376 ps
CPU time 182.08 seconds
Started Aug 13 04:41:04 PM PDT 24
Finished Aug 13 04:44:06 PM PDT 24
Peak memory 292236 kb
Host smart-fc3793b9-0902-4463-99db-155657566973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666327556 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.3666327556 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_error/latest

Test location /workspace/coverage/default/33.kmac_key_error.1150069909
Short name T111
Test name
Test status
Simulation time 974258984 ps
CPU time 7.97 seconds
Started Aug 13 04:41:13 PM PDT 24
Finished Aug 13 04:41:21 PM PDT 24
Peak memory 226404 kb
Host smart-f4d897c1-613d-4b40-b076-66837d273aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150069909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.1150069909 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_key_error/latest

Test location /workspace/coverage/default/33.kmac_lc_escalation.1572386689
Short name T97
Test name
Test status
Simulation time 2761020110 ps
CPU time 21.19 seconds
Started Aug 13 04:41:08 PM PDT 24
Finished Aug 13 04:41:29 PM PDT 24
Peak memory 243200 kb
Host smart-955e405d-db8a-433a-923b-201bf5381dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572386689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.1572386689 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/33.kmac_lc_escalation/latest

Test location /workspace/coverage/default/33.kmac_long_msg_and_output.420289455
Short name T274
Test name
Test status
Simulation time 12963168245 ps
CPU time 1532.95 seconds
Started Aug 13 04:41:05 PM PDT 24
Finished Aug 13 05:06:38 PM PDT 24
Peak memory 934092 kb
Host smart-11985e98-3984-450f-a7c5-376eb9e6cfdc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420289455 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_an
d_output.420289455 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/33.kmac_sideload.3765496228
Short name T78
Test name
Test status
Simulation time 191377499912 ps
CPU time 350.1 seconds
Started Aug 13 04:41:09 PM PDT 24
Finished Aug 13 04:46:59 PM PDT 24
Peak memory 466528 kb
Host smart-e4a03367-835a-4cc7-be42-ab3a25b4f61f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765496228 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.3765496228 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_sideload/latest

Test location /workspace/coverage/default/33.kmac_smoke.2653828339
Short name T194
Test name
Test status
Simulation time 1832177275 ps
CPU time 73.72 seconds
Started Aug 13 04:41:06 PM PDT 24
Finished Aug 13 04:42:20 PM PDT 24
Peak memory 226576 kb
Host smart-22541081-1654-4b1d-bca4-9f3fa322cd52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653828339 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.2653828339 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_smoke/latest

Test location /workspace/coverage/default/33.kmac_stress_all.519640767
Short name T352
Test name
Test status
Simulation time 10700153252 ps
CPU time 740.77 seconds
Started Aug 13 04:41:10 PM PDT 24
Finished Aug 13 04:53:31 PM PDT 24
Peak memory 350120 kb
Host smart-75ab3af8-36cc-44f0-b622-e1b9a2e536cd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=519640767 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.519640767 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_stress_all/latest

Test location /workspace/coverage/default/34.kmac_alert_test.4276165353
Short name T683
Test name
Test status
Simulation time 45578210 ps
CPU time 0.82 seconds
Started Aug 13 04:41:16 PM PDT 24
Finished Aug 13 04:41:17 PM PDT 24
Peak memory 218196 kb
Host smart-224404bf-24f6-40cc-a732-153003884196
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276165353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.4276165353 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_alert_test/latest

Test location /workspace/coverage/default/34.kmac_app.151869548
Short name T287
Test name
Test status
Simulation time 23783682902 ps
CPU time 125.44 seconds
Started Aug 13 04:41:13 PM PDT 24
Finished Aug 13 04:43:19 PM PDT 24
Peak memory 297596 kb
Host smart-fe0df9b6-a359-43c7-b9a9-acd5b8f8f786
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151869548 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.151869548 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/34.kmac_app/latest

Test location /workspace/coverage/default/34.kmac_burst_write.449353222
Short name T626
Test name
Test status
Simulation time 3618081170 ps
CPU time 161.13 seconds
Started Aug 13 04:41:10 PM PDT 24
Finished Aug 13 04:43:51 PM PDT 24
Peak memory 243104 kb
Host smart-51e245e1-7a5c-4a9f-b13e-3f1cd5f68850
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449353222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.449353222
+enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_burst_write/latest

Test location /workspace/coverage/default/34.kmac_entropy_refresh.779620174
Short name T65
Test name
Test status
Simulation time 15272773718 ps
CPU time 235.46 seconds
Started Aug 13 04:41:06 PM PDT 24
Finished Aug 13 04:45:02 PM PDT 24
Peak memory 378404 kb
Host smart-1c81e892-32f0-4780-bd5e-5cf77251d205
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779620174 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.77
9620174 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/34.kmac_error.2253115465
Short name T413
Test name
Test status
Simulation time 14362867539 ps
CPU time 531.15 seconds
Started Aug 13 04:41:05 PM PDT 24
Finished Aug 13 04:49:56 PM PDT 24
Peak memory 589004 kb
Host smart-590e582d-4487-4efa-95f5-51aaf860979a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253115465 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.2253115465 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_error/latest

Test location /workspace/coverage/default/34.kmac_key_error.91642298
Short name T716
Test name
Test status
Simulation time 782498546 ps
CPU time 2.94 seconds
Started Aug 13 04:41:17 PM PDT 24
Finished Aug 13 04:41:20 PM PDT 24
Peak memory 226416 kb
Host smart-6b69da9c-5aa2-4df1-995a-40dfe40cc360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91642298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.91642298 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_key_error/latest

Test location /workspace/coverage/default/34.kmac_lc_escalation.2749072374
Short name T556
Test name
Test status
Simulation time 182542419 ps
CPU time 1.4 seconds
Started Aug 13 04:41:16 PM PDT 24
Finished Aug 13 04:41:17 PM PDT 24
Peak memory 226528 kb
Host smart-81053de7-e6f8-4fee-8c64-4d0dbb67c345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749072374 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.2749072374 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/34.kmac_lc_escalation/latest

Test location /workspace/coverage/default/34.kmac_long_msg_and_output.835475452
Short name T522
Test name
Test status
Simulation time 38028089003 ps
CPU time 297.6 seconds
Started Aug 13 04:41:10 PM PDT 24
Finished Aug 13 04:46:08 PM PDT 24
Peak memory 575612 kb
Host smart-b8e10010-2ecd-4da2-9023-543ef15f0549
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835475452 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_an
d_output.835475452 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/34.kmac_sideload.3392263461
Short name T223
Test name
Test status
Simulation time 8397642938 ps
CPU time 291.36 seconds
Started Aug 13 04:41:10 PM PDT 24
Finished Aug 13 04:46:01 PM PDT 24
Peak memory 452112 kb
Host smart-01d1eb9d-3226-455c-b329-2a8c171b3de4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392263461 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.3392263461 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_sideload/latest

Test location /workspace/coverage/default/34.kmac_smoke.3743209051
Short name T461
Test name
Test status
Simulation time 1440705316 ps
CPU time 53.54 seconds
Started Aug 13 04:41:05 PM PDT 24
Finished Aug 13 04:41:59 PM PDT 24
Peak memory 226812 kb
Host smart-a71f0673-ad2e-4e29-be93-71731247ab81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743209051 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.3743209051 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_smoke/latest

Test location /workspace/coverage/default/34.kmac_stress_all.478451848
Short name T73
Test name
Test status
Simulation time 103951185391 ps
CPU time 1187.96 seconds
Started Aug 13 04:41:17 PM PDT 24
Finished Aug 13 05:01:06 PM PDT 24
Peak memory 644528 kb
Host smart-993acfe0-b8fa-4c8b-b633-9291c5463933
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=478451848 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.478451848 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_stress_all/latest

Test location /workspace/coverage/default/35.kmac_alert_test.4011643819
Short name T340
Test name
Test status
Simulation time 15827802 ps
CPU time 0.85 seconds
Started Aug 13 04:41:16 PM PDT 24
Finished Aug 13 04:41:17 PM PDT 24
Peak memory 218288 kb
Host smart-91409469-fb56-47d8-9873-8f16d5348702
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011643819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.4011643819 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_alert_test/latest

Test location /workspace/coverage/default/35.kmac_app.120261213
Short name T682
Test name
Test status
Simulation time 4930547527 ps
CPU time 121.92 seconds
Started Aug 13 04:41:20 PM PDT 24
Finished Aug 13 04:43:23 PM PDT 24
Peak memory 306640 kb
Host smart-c6756ee5-f158-46ef-8efb-595616afb549
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120261213 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.120261213 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/35.kmac_app/latest

Test location /workspace/coverage/default/35.kmac_burst_write.567173030
Short name T384
Test name
Test status
Simulation time 3035482739 ps
CPU time 278.22 seconds
Started Aug 13 04:41:16 PM PDT 24
Finished Aug 13 04:45:55 PM PDT 24
Peak memory 231848 kb
Host smart-d029ed51-6120-4909-8c69-19baa2f53507
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567173030 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.567173030
+enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_burst_write/latest

Test location /workspace/coverage/default/35.kmac_entropy_refresh.239884176
Short name T174
Test name
Test status
Simulation time 9787817140 ps
CPU time 208.63 seconds
Started Aug 13 04:41:18 PM PDT 24
Finished Aug 13 04:44:47 PM PDT 24
Peak memory 374408 kb
Host smart-b61d0626-4a7c-4abd-b6f5-e0e06551405b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239884176 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.23
9884176 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/35.kmac_error.1702867917
Short name T311
Test name
Test status
Simulation time 5447771865 ps
CPU time 104.6 seconds
Started Aug 13 04:41:17 PM PDT 24
Finished Aug 13 04:43:02 PM PDT 24
Peak memory 275456 kb
Host smart-db37ba05-67d0-4397-8572-24ed7d4f2b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702867917 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.1702867917 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_error/latest

Test location /workspace/coverage/default/35.kmac_key_error.3515176263
Short name T457
Test name
Test status
Simulation time 248244018 ps
CPU time 1.57 seconds
Started Aug 13 04:41:16 PM PDT 24
Finished Aug 13 04:41:17 PM PDT 24
Peak memory 225916 kb
Host smart-08e5a130-1fad-45a4-9283-77840cde09f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515176263 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.3515176263 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_key_error/latest

Test location /workspace/coverage/default/35.kmac_lc_escalation.3374493623
Short name T47
Test name
Test status
Simulation time 2009779137 ps
CPU time 19.9 seconds
Started Aug 13 04:41:17 PM PDT 24
Finished Aug 13 04:41:37 PM PDT 24
Peak memory 251444 kb
Host smart-951ea7ad-ac10-41c1-8dfb-7df20871bf31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374493623 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.3374493623 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/35.kmac_lc_escalation/latest

Test location /workspace/coverage/default/35.kmac_long_msg_and_output.147945061
Short name T241
Test name
Test status
Simulation time 213347484950 ps
CPU time 3713.6 seconds
Started Aug 13 04:41:15 PM PDT 24
Finished Aug 13 05:43:10 PM PDT 24
Peak memory 2903624 kb
Host smart-4e62c7c0-9678-46c2-a1bd-05673526d5f4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147945061 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_an
d_output.147945061 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/35.kmac_sideload.3668938346
Short name T488
Test name
Test status
Simulation time 6543638346 ps
CPU time 336.05 seconds
Started Aug 13 04:41:20 PM PDT 24
Finished Aug 13 04:46:57 PM PDT 24
Peak memory 332268 kb
Host smart-99dca575-1276-4e18-b20d-3b11925e4a5e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668938346 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.3668938346 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_sideload/latest

Test location /workspace/coverage/default/35.kmac_smoke.1912140012
Short name T317
Test name
Test status
Simulation time 12254194398 ps
CPU time 82.73 seconds
Started Aug 13 04:41:21 PM PDT 24
Finished Aug 13 04:42:44 PM PDT 24
Peak memory 227928 kb
Host smart-b139452d-6e43-492d-b34a-c7c6bca3c4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912140012 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.1912140012 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_smoke/latest

Test location /workspace/coverage/default/35.kmac_stress_all.902970966
Short name T14
Test name
Test status
Simulation time 120686709443 ps
CPU time 916.4 seconds
Started Aug 13 04:41:21 PM PDT 24
Finished Aug 13 04:56:37 PM PDT 24
Peak memory 307988 kb
Host smart-87c48a1c-fe7b-47ec-89e1-54294b68c89e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=902970966 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.902970966 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_stress_all/latest

Test location /workspace/coverage/default/36.kmac_alert_test.3215277445
Short name T198
Test name
Test status
Simulation time 18461200 ps
CPU time 0.84 seconds
Started Aug 13 04:41:19 PM PDT 24
Finished Aug 13 04:41:20 PM PDT 24
Peak memory 218168 kb
Host smart-490ffd1d-67ce-4dc5-9422-dbdf39790da8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215277445 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.3215277445 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_alert_test/latest

Test location /workspace/coverage/default/36.kmac_app.2825712586
Short name T437
Test name
Test status
Simulation time 1737849731 ps
CPU time 42.43 seconds
Started Aug 13 04:41:16 PM PDT 24
Finished Aug 13 04:41:58 PM PDT 24
Peak memory 242948 kb
Host smart-be42a2a6-2628-4e8e-bc6d-23c7c11a76e9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825712586 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.2825712586 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/36.kmac_app/latest

Test location /workspace/coverage/default/36.kmac_burst_write.1728237475
Short name T432
Test name
Test status
Simulation time 28837061951 ps
CPU time 1259.4 seconds
Started Aug 13 04:41:16 PM PDT 24
Finished Aug 13 05:02:15 PM PDT 24
Peak memory 261628 kb
Host smart-d85d9bc8-7e26-4291-8e07-e188d979f5e4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728237475 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.172823747
5 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_burst_write/latest

Test location /workspace/coverage/default/36.kmac_entropy_refresh.625868064
Short name T538
Test name
Test status
Simulation time 23564092355 ps
CPU time 284.77 seconds
Started Aug 13 04:41:20 PM PDT 24
Finished Aug 13 04:46:05 PM PDT 24
Peak memory 412868 kb
Host smart-672aa404-2b61-4fbc-a893-0b7fa961dcbf
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625868064 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.62
5868064 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/36.kmac_error.3244614144
Short name T518
Test name
Test status
Simulation time 110106812753 ps
CPU time 561.11 seconds
Started Aug 13 04:41:17 PM PDT 24
Finished Aug 13 04:50:38 PM PDT 24
Peak memory 620320 kb
Host smart-4192bff2-eef7-45e4-930b-c9ccfbaf05a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244614144 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.3244614144 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_error/latest

Test location /workspace/coverage/default/36.kmac_key_error.6984988
Short name T356
Test name
Test status
Simulation time 956003900 ps
CPU time 3.31 seconds
Started Aug 13 04:41:17 PM PDT 24
Finished Aug 13 04:41:20 PM PDT 24
Peak memory 226356 kb
Host smart-5f54e302-530b-4382-b1b2-0d73bb27ef61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6984988 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.6984988 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_key_error/latest

Test location /workspace/coverage/default/36.kmac_lc_escalation.2567302257
Short name T514
Test name
Test status
Simulation time 27391349 ps
CPU time 1.17 seconds
Started Aug 13 04:41:15 PM PDT 24
Finished Aug 13 04:41:16 PM PDT 24
Peak memory 226644 kb
Host smart-80500c32-0e5c-4821-a41f-9ef86255c6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567302257 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.2567302257 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/36.kmac_lc_escalation/latest

Test location /workspace/coverage/default/36.kmac_long_msg_and_output.3071739803
Short name T709
Test name
Test status
Simulation time 553618386483 ps
CPU time 2586.37 seconds
Started Aug 13 04:41:16 PM PDT 24
Finished Aug 13 05:24:22 PM PDT 24
Peak memory 2285160 kb
Host smart-615b6de3-6312-4fed-9031-283440a8fab6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071739803 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_a
nd_output.3071739803 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/36.kmac_sideload.3632029850
Short name T485
Test name
Test status
Simulation time 39836021546 ps
CPU time 539.51 seconds
Started Aug 13 04:41:20 PM PDT 24
Finished Aug 13 04:50:20 PM PDT 24
Peak memory 641184 kb
Host smart-4ecf0c03-3805-455b-8094-9d91c5ed281d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632029850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.3632029850 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_sideload/latest

Test location /workspace/coverage/default/36.kmac_smoke.2341707777
Short name T601
Test name
Test status
Simulation time 3260670143 ps
CPU time 54.36 seconds
Started Aug 13 04:41:15 PM PDT 24
Finished Aug 13 04:42:09 PM PDT 24
Peak memory 226700 kb
Host smart-6603afd2-b019-4cc4-a17b-b75100eaaf14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341707777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.2341707777 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_smoke/latest

Test location /workspace/coverage/default/37.kmac_alert_test.2227119989
Short name T258
Test name
Test status
Simulation time 59879830 ps
CPU time 0.85 seconds
Started Aug 13 04:41:19 PM PDT 24
Finished Aug 13 04:41:20 PM PDT 24
Peak memory 218196 kb
Host smart-80b41358-8069-4f89-9f58-00f735f7d587
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227119989 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.2227119989 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_alert_test/latest

Test location /workspace/coverage/default/37.kmac_app.3764746230
Short name T653
Test name
Test status
Simulation time 1948262899 ps
CPU time 123.49 seconds
Started Aug 13 04:41:17 PM PDT 24
Finished Aug 13 04:43:21 PM PDT 24
Peak memory 262728 kb
Host smart-30fa749a-4306-47c1-b97a-d7cdc18ae01c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764746230 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.3764746230 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/37.kmac_app/latest

Test location /workspace/coverage/default/37.kmac_burst_write.2606842760
Short name T146
Test name
Test status
Simulation time 3807765396 ps
CPU time 190.67 seconds
Started Aug 13 04:41:19 PM PDT 24
Finished Aug 13 04:44:29 PM PDT 24
Peak memory 230116 kb
Host smart-a8ce9b28-3bb3-4ed6-9fb7-dc7832f9d763
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606842760 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.260684276
0 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_burst_write/latest

Test location /workspace/coverage/default/37.kmac_entropy_refresh.2023828988
Short name T676
Test name
Test status
Simulation time 35618586119 ps
CPU time 375.61 seconds
Started Aug 13 04:41:16 PM PDT 24
Finished Aug 13 04:47:32 PM PDT 24
Peak memory 334820 kb
Host smart-5b7f7350-8716-4872-a9c1-b1cd0f88eac6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023828988 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.2
023828988 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/37.kmac_error.3048082615
Short name T576
Test name
Test status
Simulation time 1868984034 ps
CPU time 161.19 seconds
Started Aug 13 04:41:21 PM PDT 24
Finished Aug 13 04:44:02 PM PDT 24
Peak memory 290408 kb
Host smart-520d0456-2be0-447c-88d7-7ed0a948bec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048082615 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.3048082615 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_error/latest

Test location /workspace/coverage/default/37.kmac_key_error.3229494663
Short name T444
Test name
Test status
Simulation time 218197716 ps
CPU time 1.42 seconds
Started Aug 13 04:41:16 PM PDT 24
Finished Aug 13 04:41:17 PM PDT 24
Peak memory 225028 kb
Host smart-523b16ee-147c-4cd0-8c2d-5952c9c148aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229494663 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.3229494663 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_key_error/latest

Test location /workspace/coverage/default/37.kmac_lc_escalation.2476099149
Short name T571
Test name
Test status
Simulation time 116122997 ps
CPU time 1.54 seconds
Started Aug 13 04:41:17 PM PDT 24
Finished Aug 13 04:41:18 PM PDT 24
Peak memory 226572 kb
Host smart-daad6f6f-ccbf-43ac-ac70-93d7dea328b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476099149 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.2476099149 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/37.kmac_lc_escalation/latest

Test location /workspace/coverage/default/37.kmac_long_msg_and_output.3400758409
Short name T493
Test name
Test status
Simulation time 14613514034 ps
CPU time 1801.54 seconds
Started Aug 13 04:41:20 PM PDT 24
Finished Aug 13 05:11:22 PM PDT 24
Peak memory 1050392 kb
Host smart-031a14d9-0323-4b35-a981-0c70087aa07c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400758409 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_a
nd_output.3400758409 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/37.kmac_sideload.1543962327
Short name T325
Test name
Test status
Simulation time 95652620185 ps
CPU time 552.09 seconds
Started Aug 13 04:41:16 PM PDT 24
Finished Aug 13 04:50:28 PM PDT 24
Peak memory 637384 kb
Host smart-20398995-b75c-45b2-9be3-f004b8a580dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543962327 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.1543962327 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_sideload/latest

Test location /workspace/coverage/default/37.kmac_smoke.3847434827
Short name T586
Test name
Test status
Simulation time 22402839323 ps
CPU time 91.77 seconds
Started Aug 13 04:41:16 PM PDT 24
Finished Aug 13 04:42:48 PM PDT 24
Peak memory 228872 kb
Host smart-28d562d7-7185-4b71-a3dc-e075aa5ca2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847434827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.3847434827 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_smoke/latest

Test location /workspace/coverage/default/37.kmac_stress_all.793833526
Short name T593
Test name
Test status
Simulation time 103814929595 ps
CPU time 953.89 seconds
Started Aug 13 04:41:17 PM PDT 24
Finished Aug 13 04:57:11 PM PDT 24
Peak memory 637816 kb
Host smart-240fd10e-e854-4889-ad06-6280f4fe2716
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=793833526 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.793833526 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_stress_all/latest

Test location /workspace/coverage/default/38.kmac_alert_test.3043763506
Short name T282
Test name
Test status
Simulation time 40623211 ps
CPU time 0.81 seconds
Started Aug 13 04:41:18 PM PDT 24
Finished Aug 13 04:41:19 PM PDT 24
Peak memory 218192 kb
Host smart-5a037ddc-6492-47ba-8224-209327ce0804
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043763506 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.3043763506 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_alert_test/latest

Test location /workspace/coverage/default/38.kmac_app.1134172702
Short name T104
Test name
Test status
Simulation time 1873655129 ps
CPU time 20.06 seconds
Started Aug 13 04:41:22 PM PDT 24
Finished Aug 13 04:41:42 PM PDT 24
Peak memory 242912 kb
Host smart-ffe8f997-2743-4690-a6fb-bc8fcee08ee3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134172702 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.1134172702 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/38.kmac_app/latest

Test location /workspace/coverage/default/38.kmac_burst_write.3596929391
Short name T644
Test name
Test status
Simulation time 2007896232 ps
CPU time 221.76 seconds
Started Aug 13 04:41:19 PM PDT 24
Finished Aug 13 04:45:01 PM PDT 24
Peak memory 228896 kb
Host smart-360d100c-8896-4541-9a14-2ca50f8c9956
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596929391 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.359692939
1 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_burst_write/latest

Test location /workspace/coverage/default/38.kmac_entropy_refresh.954772605
Short name T598
Test name
Test status
Simulation time 74956505113 ps
CPU time 186.79 seconds
Started Aug 13 04:41:16 PM PDT 24
Finished Aug 13 04:44:23 PM PDT 24
Peak memory 348368 kb
Host smart-2cdb188a-a005-408c-bd4c-0bd93bb5de95
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954772605 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.95
4772605 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/38.kmac_error.1712524514
Short name T46
Test name
Test status
Simulation time 13348974235 ps
CPU time 94.84 seconds
Started Aug 13 04:41:19 PM PDT 24
Finished Aug 13 04:42:54 PM PDT 24
Peak memory 300312 kb
Host smart-372657d0-765e-45c1-9838-75e98721ab46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712524514 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.1712524514 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_error/latest

Test location /workspace/coverage/default/38.kmac_key_error.51051401
Short name T234
Test name
Test status
Simulation time 1102384526 ps
CPU time 5.51 seconds
Started Aug 13 04:41:15 PM PDT 24
Finished Aug 13 04:41:20 PM PDT 24
Peak memory 226496 kb
Host smart-c2f19ad0-b99f-4fa2-9ff4-6890618b7ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51051401 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.51051401 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_key_error/latest

Test location /workspace/coverage/default/38.kmac_lc_escalation.3143037608
Short name T23
Test name
Test status
Simulation time 37792381 ps
CPU time 1.27 seconds
Started Aug 13 04:41:22 PM PDT 24
Finished Aug 13 04:41:23 PM PDT 24
Peak memory 226480 kb
Host smart-5327a5b6-aa97-48ba-bd78-91b0c6e3aef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143037608 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.3143037608 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/38.kmac_lc_escalation/latest

Test location /workspace/coverage/default/38.kmac_long_msg_and_output.3230704366
Short name T276
Test name
Test status
Simulation time 20152559596 ps
CPU time 2496.74 seconds
Started Aug 13 04:41:16 PM PDT 24
Finished Aug 13 05:22:53 PM PDT 24
Peak memory 1295264 kb
Host smart-6e1823b1-9349-46f9-b4fc-305a419afc81
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230704366 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_a
nd_output.3230704366 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/38.kmac_sideload.3578715086
Short name T327
Test name
Test status
Simulation time 17998563184 ps
CPU time 414.65 seconds
Started Aug 13 04:41:20 PM PDT 24
Finished Aug 13 04:48:15 PM PDT 24
Peak memory 352792 kb
Host smart-e7b56669-6b63-4824-8940-24ed135b72f3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578715086 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.3578715086 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_sideload/latest

Test location /workspace/coverage/default/38.kmac_smoke.2568814634
Short name T242
Test name
Test status
Simulation time 1287120653 ps
CPU time 8.45 seconds
Started Aug 13 04:41:16 PM PDT 24
Finished Aug 13 04:41:25 PM PDT 24
Peak memory 222064 kb
Host smart-865a39dc-b3bb-453e-8e65-ff7b3883e2be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568814634 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.2568814634 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_smoke/latest

Test location /workspace/coverage/default/38.kmac_stress_all.1748825024
Short name T642
Test name
Test status
Simulation time 213168995360 ps
CPU time 1968.1 seconds
Started Aug 13 04:41:18 PM PDT 24
Finished Aug 13 05:14:06 PM PDT 24
Peak memory 400660 kb
Host smart-11b9b064-14f4-469d-8dc2-96a5ba5e0cd1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1748825024 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.1748825024 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_stress_all/latest

Test location /workspace/coverage/default/39.kmac_alert_test.453552712
Short name T693
Test name
Test status
Simulation time 120917148 ps
CPU time 0.87 seconds
Started Aug 13 04:41:24 PM PDT 24
Finished Aug 13 04:41:25 PM PDT 24
Peak memory 218192 kb
Host smart-f2eef0f3-82ef-470a-9e22-5b9afc7fd67f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453552712 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.453552712 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/39.kmac_alert_test/latest

Test location /workspace/coverage/default/39.kmac_app.422862125
Short name T275
Test name
Test status
Simulation time 12059267348 ps
CPU time 327.96 seconds
Started Aug 13 04:41:24 PM PDT 24
Finished Aug 13 04:46:52 PM PDT 24
Peak memory 469604 kb
Host smart-ff5688e0-6765-428c-833c-8c756f1dafdb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422862125 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.422862125 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/39.kmac_app/latest

Test location /workspace/coverage/default/39.kmac_burst_write.2356423771
Short name T583
Test name
Test status
Simulation time 27260568010 ps
CPU time 242.44 seconds
Started Aug 13 04:41:27 PM PDT 24
Finished Aug 13 04:45:30 PM PDT 24
Peak memory 243056 kb
Host smart-ddc0667a-7693-43fc-a337-432d0d8f06a3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356423771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.235642377
1 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_burst_write/latest

Test location /workspace/coverage/default/39.kmac_entropy_refresh.2221815909
Short name T401
Test name
Test status
Simulation time 12833950933 ps
CPU time 44.84 seconds
Started Aug 13 04:41:25 PM PDT 24
Finished Aug 13 04:42:10 PM PDT 24
Peak memory 251516 kb
Host smart-d477bd06-5810-4fb4-ae7c-faa09f32620d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221815909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.2
221815909 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/39.kmac_error.532744804
Short name T245
Test name
Test status
Simulation time 5172158257 ps
CPU time 208.58 seconds
Started Aug 13 04:41:25 PM PDT 24
Finished Aug 13 04:44:54 PM PDT 24
Peak memory 301244 kb
Host smart-153c2f55-6eef-4e97-856a-a7e1cd86222c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532744804 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.532744804 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_error/latest

Test location /workspace/coverage/default/39.kmac_key_error.2608426197
Short name T371
Test name
Test status
Simulation time 120314320 ps
CPU time 1.56 seconds
Started Aug 13 04:41:24 PM PDT 24
Finished Aug 13 04:41:26 PM PDT 24
Peak memory 226132 kb
Host smart-94b4e8e5-6aa0-4765-b777-8f9ececf5447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608426197 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.2608426197 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_key_error/latest

Test location /workspace/coverage/default/39.kmac_long_msg_and_output.2946084085
Short name T570
Test name
Test status
Simulation time 555157255 ps
CPU time 55.85 seconds
Started Aug 13 04:41:16 PM PDT 24
Finished Aug 13 04:42:12 PM PDT 24
Peak memory 243060 kb
Host smart-62239dc2-5a58-44e8-b096-d3f28a04286a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946084085 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_a
nd_output.2946084085 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/39.kmac_sideload.156769292
Short name T499
Test name
Test status
Simulation time 22568188266 ps
CPU time 381.09 seconds
Started Aug 13 04:41:20 PM PDT 24
Finished Aug 13 04:47:42 PM PDT 24
Peak memory 520908 kb
Host smart-c31c7d73-75f2-4922-92ca-8f12455666f3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156769292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.156769292 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_sideload/latest

Test location /workspace/coverage/default/39.kmac_smoke.4237398570
Short name T273
Test name
Test status
Simulation time 2125207991 ps
CPU time 78.23 seconds
Started Aug 13 04:41:17 PM PDT 24
Finished Aug 13 04:42:36 PM PDT 24
Peak memory 226704 kb
Host smart-40991f45-0369-4250-adf4-8d97a74a383c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237398570 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.4237398570 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_smoke/latest

Test location /workspace/coverage/default/39.kmac_stress_all.1909779107
Short name T260
Test name
Test status
Simulation time 12196748705 ps
CPU time 119.13 seconds
Started Aug 13 04:41:27 PM PDT 24
Finished Aug 13 04:43:26 PM PDT 24
Peak memory 260564 kb
Host smart-6d6c8155-27e1-4bbf-b940-1d8760cd0da3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1909779107 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.1909779107 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_stress_all/latest

Test location /workspace/coverage/default/4.kmac_alert_test.3243843390
Short name T529
Test name
Test status
Simulation time 33362257 ps
CPU time 0.83 seconds
Started Aug 13 04:40:12 PM PDT 24
Finished Aug 13 04:40:13 PM PDT 24
Peak memory 218288 kb
Host smart-f5c4225c-77b1-46b9-8ccb-dbacabd40c33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243843390 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.3243843390 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_alert_test/latest

Test location /workspace/coverage/default/4.kmac_app.236902826
Short name T519
Test name
Test status
Simulation time 11288992224 ps
CPU time 283.08 seconds
Started Aug 13 04:40:12 PM PDT 24
Finished Aug 13 04:44:55 PM PDT 24
Peak memory 423052 kb
Host smart-d8d7ebe9-cb6b-470a-bb0a-964693e67509
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236902826 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.236902826 +enable_masking=1
+sw_key_masked=0
Directory /workspace/4.kmac_app/latest

Test location /workspace/coverage/default/4.kmac_app_with_partial_data.611550708
Short name T612
Test name
Test status
Simulation time 251353803 ps
CPU time 3.62 seconds
Started Aug 13 04:40:09 PM PDT 24
Finished Aug 13 04:40:13 PM PDT 24
Peak memory 226640 kb
Host smart-e7937543-667d-4a06-a48e-4dd1270a2ebe
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611550708 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_parti
al_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_part
ial_data.611550708 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/4.kmac_burst_write.1596843682
Short name T30
Test name
Test status
Simulation time 10238289315 ps
CPU time 517.94 seconds
Started Aug 13 04:40:26 PM PDT 24
Finished Aug 13 04:49:05 PM PDT 24
Peak memory 242884 kb
Host smart-6144e9f5-bcd4-4f2a-b960-c72379b7533f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596843682 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.1596843682
+enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_burst_write/latest

Test location /workspace/coverage/default/4.kmac_edn_timeout_error.345225837
Short name T335
Test name
Test status
Simulation time 1609660776 ps
CPU time 24.55 seconds
Started Aug 13 04:40:08 PM PDT 24
Finished Aug 13 04:40:32 PM PDT 24
Peak memory 232660 kb
Host smart-a9db2c7c-fac7-4a9e-bb55-12998dd8e647
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=345225837 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.345225837 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_mode_error.2732273145
Short name T434
Test name
Test status
Simulation time 20949848 ps
CPU time 0.87 seconds
Started Aug 13 04:40:08 PM PDT 24
Finished Aug 13 04:40:09 PM PDT 24
Peak memory 220104 kb
Host smart-b81c028d-89eb-4381-97b2-b68a1462cdc3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2732273145 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.2732273145 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_ready_error.1294798431
Short name T710
Test name
Test status
Simulation time 3095756394 ps
CPU time 32.61 seconds
Started Aug 13 04:40:17 PM PDT 24
Finished Aug 13 04:40:50 PM PDT 24
Peak memory 226628 kb
Host smart-05cb8834-524d-424e-98f2-0f1b79057193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294798431 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.1294798431 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_refresh.404067576
Short name T377
Test name
Test status
Simulation time 10851376336 ps
CPU time 171.18 seconds
Started Aug 13 04:40:07 PM PDT 24
Finished Aug 13 04:42:58 PM PDT 24
Peak memory 334920 kb
Host smart-6ae228e3-6486-40be-8308-1c7e28d5af55
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404067576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.404
067576 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/4.kmac_error.536413310
Short name T122
Test name
Test status
Simulation time 26060846768 ps
CPU time 350.72 seconds
Started Aug 13 04:40:05 PM PDT 24
Finished Aug 13 04:45:56 PM PDT 24
Peak memory 345812 kb
Host smart-16c0b1bc-f096-4c08-8f7e-c788262f94df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536413310 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.536413310 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_error/latest

Test location /workspace/coverage/default/4.kmac_key_error.1519735532
Short name T324
Test name
Test status
Simulation time 950072874 ps
CPU time 7.43 seconds
Started Aug 13 04:40:13 PM PDT 24
Finished Aug 13 04:40:21 PM PDT 24
Peak memory 226440 kb
Host smart-07676142-bace-41bb-a3b4-996a3543a09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519735532 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.1519735532 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_key_error/latest

Test location /workspace/coverage/default/4.kmac_lc_escalation.1744940414
Short name T264
Test name
Test status
Simulation time 280583300 ps
CPU time 3 seconds
Started Aug 13 04:40:19 PM PDT 24
Finished Aug 13 04:40:22 PM PDT 24
Peak memory 226644 kb
Host smart-14f987fb-f4e3-4ab8-a10e-2fd9da96d2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744940414 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.1744940414 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/4.kmac_lc_escalation/latest

Test location /workspace/coverage/default/4.kmac_long_msg_and_output.2683506889
Short name T565
Test name
Test status
Simulation time 224249740209 ps
CPU time 3404.03 seconds
Started Aug 13 04:40:02 PM PDT 24
Finished Aug 13 05:36:47 PM PDT 24
Peak memory 1692864 kb
Host smart-2aa7ea15-3a2c-4bf9-a68e-67605319841c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683506889 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_an
d_output.2683506889 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/4.kmac_mubi.1321268814
Short name T534
Test name
Test status
Simulation time 10683858165 ps
CPU time 52.63 seconds
Started Aug 13 04:40:05 PM PDT 24
Finished Aug 13 04:40:58 PM PDT 24
Peak memory 266488 kb
Host smart-02d6d020-723a-4c43-9f18-c4bcecbc626b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321268814 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.1321268814 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_mubi/latest

Test location /workspace/coverage/default/4.kmac_sec_cm.1225481589
Short name T28
Test name
Test status
Simulation time 4391721012 ps
CPU time 66.67 seconds
Started Aug 13 04:40:13 PM PDT 24
Finished Aug 13 04:41:19 PM PDT 24
Peak memory 272296 kb
Host smart-a422ebc6-9cac-40a8-9c74-f69a471d230e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225481589 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.1225481589 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspace/4.kmac_sec_cm/latest

Test location /workspace/coverage/default/4.kmac_sideload.974767193
Short name T259
Test name
Test status
Simulation time 34350940664 ps
CPU time 559.78 seconds
Started Aug 13 04:40:11 PM PDT 24
Finished Aug 13 04:49:31 PM PDT 24
Peak memory 638460 kb
Host smart-99fb0689-b493-4c56-81df-f5a030eb8adc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974767193 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.974767193 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_sideload/latest

Test location /workspace/coverage/default/4.kmac_smoke.4178697423
Short name T650
Test name
Test status
Simulation time 15244554903 ps
CPU time 77.99 seconds
Started Aug 13 04:40:02 PM PDT 24
Finished Aug 13 04:41:20 PM PDT 24
Peak memory 226880 kb
Host smart-89ade29e-3c03-481c-a9bb-3b91a2ec21f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178697423 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.4178697423 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_smoke/latest

Test location /workspace/coverage/default/4.kmac_stress_all.1157635446
Short name T427
Test name
Test status
Simulation time 16343634714 ps
CPU time 716.11 seconds
Started Aug 13 04:40:12 PM PDT 24
Finished Aug 13 04:52:08 PM PDT 24
Peak memory 487960 kb
Host smart-dbc9eebc-19fe-4a31-b611-5e144313212d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1157635446 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.1157635446 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_stress_all/latest

Test location /workspace/coverage/default/4.kmac_stress_all_with_rand_reset.3386479191
Short name T132
Test name
Test status
Simulation time 49279507650 ps
CPU time 295.18 seconds
Started Aug 13 04:40:12 PM PDT 24
Finished Aug 13 04:45:08 PM PDT 24
Peak memory 284456 kb
Host smart-8960bcad-ae8c-44da-80c3-5cc54f4fd826
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3386479191 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all_with_rand_reset.3386479191 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_kmac.1553097370
Short name T613
Test name
Test status
Simulation time 120199101 ps
CPU time 3.41 seconds
Started Aug 13 04:40:27 PM PDT 24
Finished Aug 13 04:40:30 PM PDT 24
Peak memory 219476 kb
Host smart-2fec2884-4db0-452b-8734-257433c5dcda
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553097370 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.kmac_test_vectors_kmac.1553097370 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_kmac_xof.3457493558
Short name T661
Test name
Test status
Simulation time 224828512 ps
CPU time 3.04 seconds
Started Aug 13 04:40:03 PM PDT 24
Finished Aug 13 04:40:06 PM PDT 24
Peak memory 219564 kb
Host smart-7d610408-7bff-4815-a87b-71c6ddfed60a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457493558 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.kmac_test_vectors_kmac_xof.3457493558 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_224.573261843
Short name T597
Test name
Test status
Simulation time 80708913822 ps
CPU time 3482.56 seconds
Started Aug 13 04:40:06 PM PDT 24
Finished Aug 13 05:38:09 PM PDT 24
Peak memory 3062080 kb
Host smart-3741cf69-a429-46fe-968c-18a9a7b381a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=573261843 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.573261843 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_256.1216309228
Short name T489
Test name
Test status
Simulation time 67706758276 ps
CPU time 2075.77 seconds
Started Aug 13 04:40:13 PM PDT 24
Finished Aug 13 05:14:49 PM PDT 24
Peak memory 1115960 kb
Host smart-9effc93f-90d6-4b14-ab93-198b89750c8e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1216309228 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.1216309228 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_384.2089457891
Short name T501
Test name
Test status
Simulation time 1810212856 ps
CPU time 31.07 seconds
Started Aug 13 04:40:12 PM PDT 24
Finished Aug 13 04:40:43 PM PDT 24
Peak memory 233760 kb
Host smart-808234d8-a3ce-4e02-b522-dd140565b793
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2089457891 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.2089457891 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_512.2110542380
Short name T379
Test name
Test status
Simulation time 219693806110 ps
CPU time 1848.97 seconds
Started Aug 13 04:40:09 PM PDT 24
Finished Aug 13 05:10:59 PM PDT 24
Peak memory 1683340 kb
Host smart-7e153c7f-3bb9-486f-b6ee-f4bf1e256f44
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2110542380 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.2110542380 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_shake_128.1784992134
Short name T372
Test name
Test status
Simulation time 145900195149 ps
CPU time 312.3 seconds
Started Aug 13 04:40:20 PM PDT 24
Finished Aug 13 04:45:33 PM PDT 24
Peak memory 276268 kb
Host smart-1aa93610-6b09-448a-8858-3e0061c42e1c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1784992134 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.1784992134 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_shake_256.3163737169
Short name T32
Test name
Test status
Simulation time 53851958810 ps
CPU time 163.34 seconds
Started Aug 13 04:40:11 PM PDT 24
Finished Aug 13 04:42:55 PM PDT 24
Peak memory 355644 kb
Host smart-3c2fc270-5d66-40ba-8c41-74480b56e029
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3163737169 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.3163737169 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/40.kmac_alert_test.305538192
Short name T715
Test name
Test status
Simulation time 14530762 ps
CPU time 0.84 seconds
Started Aug 13 04:41:23 PM PDT 24
Finished Aug 13 04:41:24 PM PDT 24
Peak memory 218156 kb
Host smart-0ae01ed7-7412-4417-abd9-1b404b7f5bd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305538192 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.305538192 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/40.kmac_alert_test/latest

Test location /workspace/coverage/default/40.kmac_app.1495404459
Short name T435
Test name
Test status
Simulation time 12398734210 ps
CPU time 85.96 seconds
Started Aug 13 04:41:27 PM PDT 24
Finished Aug 13 04:42:53 PM PDT 24
Peak memory 284472 kb
Host smart-6af1b7a9-7635-4c48-a490-166fe5ecb16c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495404459 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.1495404459 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/40.kmac_app/latest

Test location /workspace/coverage/default/40.kmac_burst_write.725680423
Short name T449
Test name
Test status
Simulation time 34859582101 ps
CPU time 580.15 seconds
Started Aug 13 04:41:26 PM PDT 24
Finished Aug 13 04:51:07 PM PDT 24
Peak memory 235828 kb
Host smart-484a750c-d252-4515-bd60-47dcce1a8b07
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725680423 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.725680423
+enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_burst_write/latest

Test location /workspace/coverage/default/40.kmac_entropy_refresh.3272597301
Short name T502
Test name
Test status
Simulation time 943540913 ps
CPU time 6.6 seconds
Started Aug 13 04:41:25 PM PDT 24
Finished Aug 13 04:41:31 PM PDT 24
Peak memory 220548 kb
Host smart-7208a517-6006-42bd-90d6-d7d0799519c8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272597301 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.3
272597301 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/40.kmac_error.2425847416
Short name T643
Test name
Test status
Simulation time 16189314535 ps
CPU time 257.87 seconds
Started Aug 13 04:41:28 PM PDT 24
Finished Aug 13 04:45:46 PM PDT 24
Peak memory 414680 kb
Host smart-bb03a8c7-1e50-4bf3-8bd1-1c2600a3404c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425847416 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.2425847416 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_error/latest

Test location /workspace/coverage/default/40.kmac_key_error.2808563446
Short name T210
Test name
Test status
Simulation time 1679015841 ps
CPU time 6.9 seconds
Started Aug 13 04:41:27 PM PDT 24
Finished Aug 13 04:41:34 PM PDT 24
Peak memory 226492 kb
Host smart-4e1bba41-d0fa-4e93-86fd-354b01623593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808563446 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.2808563446 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_key_error/latest

Test location /workspace/coverage/default/40.kmac_lc_escalation.1754265313
Short name T399
Test name
Test status
Simulation time 8259867482 ps
CPU time 17.59 seconds
Started Aug 13 04:41:27 PM PDT 24
Finished Aug 13 04:41:44 PM PDT 24
Peak memory 243140 kb
Host smart-8de698b6-9e5f-40a2-a5cf-13c33fd9455f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754265313 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.1754265313 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/40.kmac_lc_escalation/latest

Test location /workspace/coverage/default/40.kmac_long_msg_and_output.2756175401
Short name T117
Test name
Test status
Simulation time 30292394036 ps
CPU time 1055.67 seconds
Started Aug 13 04:41:27 PM PDT 24
Finished Aug 13 04:59:03 PM PDT 24
Peak memory 1268716 kb
Host smart-1db2da5f-721f-4d1f-b699-4e76373c7156
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756175401 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_a
nd_output.2756175401 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/40.kmac_sideload.784381249
Short name T513
Test name
Test status
Simulation time 47514576 ps
CPU time 4.2 seconds
Started Aug 13 04:41:25 PM PDT 24
Finished Aug 13 04:41:29 PM PDT 24
Peak memory 226580 kb
Host smart-c970af0c-4271-4449-a695-b675c97f25c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784381249 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.784381249 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_sideload/latest

Test location /workspace/coverage/default/40.kmac_smoke.1726424388
Short name T398
Test name
Test status
Simulation time 26973802431 ps
CPU time 66.44 seconds
Started Aug 13 04:41:25 PM PDT 24
Finished Aug 13 04:42:32 PM PDT 24
Peak memory 225636 kb
Host smart-384b6fc5-9826-42d1-a0d0-059894505fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726424388 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.1726424388 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_smoke/latest

Test location /workspace/coverage/default/40.kmac_stress_all.517849826
Short name T293
Test name
Test status
Simulation time 143193325062 ps
CPU time 3727.59 seconds
Started Aug 13 04:41:24 PM PDT 24
Finished Aug 13 05:43:33 PM PDT 24
Peak memory 2802624 kb
Host smart-d1887294-22bb-4c2e-9a6a-6605ab9e5c93
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=517849826 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.517849826 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_stress_all/latest

Test location /workspace/coverage/default/41.kmac_alert_test.2713189558
Short name T685
Test name
Test status
Simulation time 124680321 ps
CPU time 0.91 seconds
Started Aug 13 04:41:28 PM PDT 24
Finished Aug 13 04:41:29 PM PDT 24
Peak memory 218108 kb
Host smart-77568334-ceeb-47fb-a8d3-79e9d81e812a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713189558 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.2713189558 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_alert_test/latest

Test location /workspace/coverage/default/41.kmac_app.872129499
Short name T578
Test name
Test status
Simulation time 6589177669 ps
CPU time 162.03 seconds
Started Aug 13 04:41:26 PM PDT 24
Finished Aug 13 04:44:09 PM PDT 24
Peak memory 334452 kb
Host smart-6988f8db-14bd-4ece-a184-fe0c9acf5bd1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872129499 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.872129499 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/41.kmac_app/latest

Test location /workspace/coverage/default/41.kmac_burst_write.4201267015
Short name T368
Test name
Test status
Simulation time 28187153025 ps
CPU time 1530.78 seconds
Started Aug 13 04:41:25 PM PDT 24
Finished Aug 13 05:06:56 PM PDT 24
Peak memory 247524 kb
Host smart-44de9170-80ea-4ba3-97bb-9e5b324cdf34
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201267015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.420126701
5 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_burst_write/latest

Test location /workspace/coverage/default/41.kmac_entropy_refresh.2006776508
Short name T55
Test name
Test status
Simulation time 13322174501 ps
CPU time 274.91 seconds
Started Aug 13 04:41:27 PM PDT 24
Finished Aug 13 04:46:02 PM PDT 24
Peak memory 406928 kb
Host smart-60b59cb6-2e14-44b0-a822-68563a8aa8f9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006776508 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_entropy_refresh.2
006776508 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/41.kmac_error.2112419816
Short name T21
Test name
Test status
Simulation time 16291000167 ps
CPU time 228.45 seconds
Started Aug 13 04:41:26 PM PDT 24
Finished Aug 13 04:45:15 PM PDT 24
Peak memory 398228 kb
Host smart-f598df9c-00f3-4b3a-98e6-6e25cd000096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112419816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.2112419816 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_error/latest

Test location /workspace/coverage/default/41.kmac_key_error.3576709520
Short name T596
Test name
Test status
Simulation time 2731575747 ps
CPU time 10.84 seconds
Started Aug 13 04:41:24 PM PDT 24
Finished Aug 13 04:41:35 PM PDT 24
Peak memory 226504 kb
Host smart-4a8f5848-0750-44b7-8785-752cc307f05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576709520 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.3576709520 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_key_error/latest

Test location /workspace/coverage/default/41.kmac_lc_escalation.1268843811
Short name T2
Test name
Test status
Simulation time 182421652 ps
CPU time 1.53 seconds
Started Aug 13 04:41:25 PM PDT 24
Finished Aug 13 04:41:27 PM PDT 24
Peak memory 226536 kb
Host smart-c0873430-5e19-4b14-894f-457364ffdde0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268843811 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.1268843811 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/41.kmac_lc_escalation/latest

Test location /workspace/coverage/default/41.kmac_long_msg_and_output.479461016
Short name T114
Test name
Test status
Simulation time 10070533563 ps
CPU time 1001.13 seconds
Started Aug 13 04:41:27 PM PDT 24
Finished Aug 13 04:58:08 PM PDT 24
Peak memory 741752 kb
Host smart-d0e0d6e2-ad9d-4842-9259-9671e198a517
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479461016 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_an
d_output.479461016 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/41.kmac_sideload.3499755883
Short name T279
Test name
Test status
Simulation time 11505018453 ps
CPU time 352.39 seconds
Started Aug 13 04:41:27 PM PDT 24
Finished Aug 13 04:47:19 PM PDT 24
Peak memory 480276 kb
Host smart-b1bd80a8-e5ef-4aa2-b3e6-dc9eaba7a829
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499755883 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.3499755883 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_sideload/latest

Test location /workspace/coverage/default/41.kmac_smoke.1828095630
Short name T719
Test name
Test status
Simulation time 25594005373 ps
CPU time 55.35 seconds
Started Aug 13 04:41:27 PM PDT 24
Finished Aug 13 04:42:23 PM PDT 24
Peak memory 225488 kb
Host smart-eb3e5858-4b80-40e8-95fa-89a43e9d1024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828095630 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.1828095630 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_smoke/latest

Test location /workspace/coverage/default/41.kmac_stress_all.3390629215
Short name T603
Test name
Test status
Simulation time 30053577971 ps
CPU time 1644.98 seconds
Started Aug 13 04:41:28 PM PDT 24
Finished Aug 13 05:08:53 PM PDT 24
Peak memory 654560 kb
Host smart-235bd474-db31-49a7-9811-851e07f0c86b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3390629215 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.3390629215 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_stress_all/latest

Test location /workspace/coverage/default/42.kmac_alert_test.2358751907
Short name T1
Test name
Test status
Simulation time 49710265 ps
CPU time 0.82 seconds
Started Aug 13 04:41:33 PM PDT 24
Finished Aug 13 04:41:34 PM PDT 24
Peak memory 218132 kb
Host smart-6abebfb3-400c-440f-87db-900650c3a91c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358751907 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.2358751907 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_alert_test/latest

Test location /workspace/coverage/default/42.kmac_app.258567939
Short name T175
Test name
Test status
Simulation time 56649973427 ps
CPU time 403.44 seconds
Started Aug 13 04:41:34 PM PDT 24
Finished Aug 13 04:48:17 PM PDT 24
Peak memory 497856 kb
Host smart-0e2cb709-31c5-4126-bd46-fb03e12f35b9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258567939 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.258567939 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/42.kmac_app/latest

Test location /workspace/coverage/default/42.kmac_burst_write.437528724
Short name T684
Test name
Test status
Simulation time 92738353934 ps
CPU time 717.61 seconds
Started Aug 13 04:41:32 PM PDT 24
Finished Aug 13 04:53:30 PM PDT 24
Peak memory 247028 kb
Host smart-a6c79dcb-a650-4654-9117-d1802ac3d4fd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437528724 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.437528724
+enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_burst_write/latest

Test location /workspace/coverage/default/42.kmac_entropy_refresh.1674641338
Short name T554
Test name
Test status
Simulation time 2779011018 ps
CPU time 92.88 seconds
Started Aug 13 04:41:33 PM PDT 24
Finished Aug 13 04:43:06 PM PDT 24
Peak memory 253216 kb
Host smart-f7ec7a30-279d-4a9c-a441-ee2556f3599f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674641338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.1
674641338 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/42.kmac_error.4140996430
Short name T439
Test name
Test status
Simulation time 9377367044 ps
CPU time 123.39 seconds
Started Aug 13 04:41:30 PM PDT 24
Finished Aug 13 04:43:33 PM PDT 24
Peak memory 276300 kb
Host smart-c6d6b23d-4723-4aed-ba80-2c4bb0444393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140996430 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.4140996430 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_error/latest

Test location /workspace/coverage/default/42.kmac_key_error.3357767719
Short name T509
Test name
Test status
Simulation time 15286039838 ps
CPU time 9.24 seconds
Started Aug 13 04:41:34 PM PDT 24
Finished Aug 13 04:41:43 PM PDT 24
Peak memory 226560 kb
Host smart-4aa0bee0-e7e7-4d61-a588-d5dd9cd49333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357767719 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.3357767719 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_key_error/latest

Test location /workspace/coverage/default/42.kmac_lc_escalation.1090631004
Short name T671
Test name
Test status
Simulation time 419900568 ps
CPU time 1.52 seconds
Started Aug 13 04:41:33 PM PDT 24
Finished Aug 13 04:41:34 PM PDT 24
Peak memory 226536 kb
Host smart-ed818e9c-27b0-4127-b510-cff626271c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090631004 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.1090631004 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/42.kmac_lc_escalation/latest

Test location /workspace/coverage/default/42.kmac_long_msg_and_output.3413907091
Short name T659
Test name
Test status
Simulation time 178737534921 ps
CPU time 2288.77 seconds
Started Aug 13 04:41:36 PM PDT 24
Finished Aug 13 05:19:45 PM PDT 24
Peak memory 2224020 kb
Host smart-578eee56-35c5-4520-86ff-22ff9e319733
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413907091 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_a
nd_output.3413907091 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/42.kmac_sideload.1408491512
Short name T256
Test name
Test status
Simulation time 5968834449 ps
CPU time 243.09 seconds
Started Aug 13 04:41:35 PM PDT 24
Finished Aug 13 04:45:38 PM PDT 24
Peak memory 310088 kb
Host smart-81ee99b1-9c6a-4594-b851-12ef63612da2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408491512 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.1408491512 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_sideload/latest

Test location /workspace/coverage/default/42.kmac_smoke.1537929629
Short name T555
Test name
Test status
Simulation time 1743979778 ps
CPU time 41.9 seconds
Started Aug 13 04:41:25 PM PDT 24
Finished Aug 13 04:42:07 PM PDT 24
Peak memory 221996 kb
Host smart-4b889760-144e-4ea5-8557-166eb22a17bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537929629 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.1537929629 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_smoke/latest

Test location /workspace/coverage/default/42.kmac_stress_all.3606288328
Short name T75
Test name
Test status
Simulation time 182482404856 ps
CPU time 652.94 seconds
Started Aug 13 04:41:36 PM PDT 24
Finished Aug 13 04:52:29 PM PDT 24
Peak memory 348624 kb
Host smart-e95daf8c-f030-462d-9a43-e78988c67c54
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3606288328 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.3606288328 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_stress_all/latest

Test location /workspace/coverage/default/43.kmac_alert_test.3345327431
Short name T109
Test name
Test status
Simulation time 37825086 ps
CPU time 0.82 seconds
Started Aug 13 04:41:37 PM PDT 24
Finished Aug 13 04:41:38 PM PDT 24
Peak memory 218128 kb
Host smart-ee9b2611-193d-4132-b08a-8833595b54f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345327431 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.3345327431 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_alert_test/latest

Test location /workspace/coverage/default/43.kmac_app.4044840548
Short name T99
Test name
Test status
Simulation time 41186111329 ps
CPU time 283.69 seconds
Started Aug 13 04:41:40 PM PDT 24
Finished Aug 13 04:46:24 PM PDT 24
Peak memory 429232 kb
Host smart-971f9c93-76a5-4b83-a906-091776660470
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044840548 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.4044840548 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/43.kmac_app/latest

Test location /workspace/coverage/default/43.kmac_burst_write.3568462426
Short name T564
Test name
Test status
Simulation time 27968216324 ps
CPU time 1542.34 seconds
Started Aug 13 04:41:32 PM PDT 24
Finished Aug 13 05:07:15 PM PDT 24
Peak memory 262504 kb
Host smart-72cea4e7-3c0e-4fc7-a9ee-d5d6416b2f10
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568462426 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.356846242
6 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_burst_write/latest

Test location /workspace/coverage/default/43.kmac_entropy_refresh.3861064207
Short name T60
Test name
Test status
Simulation time 7651936562 ps
CPU time 204.18 seconds
Started Aug 13 04:41:32 PM PDT 24
Finished Aug 13 04:44:56 PM PDT 24
Peak memory 337164 kb
Host smart-8a613eae-13cd-4b87-9324-3bf637ad16b4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861064207 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.3
861064207 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/43.kmac_error.381270135
Short name T610
Test name
Test status
Simulation time 37576698842 ps
CPU time 198.98 seconds
Started Aug 13 04:41:31 PM PDT 24
Finished Aug 13 04:44:50 PM PDT 24
Peak memory 406460 kb
Host smart-ddefc805-0b14-4ace-8a17-b9973e24a5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381270135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.381270135 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_error/latest

Test location /workspace/coverage/default/43.kmac_key_error.3329677228
Short name T721
Test name
Test status
Simulation time 1969472771 ps
CPU time 13.71 seconds
Started Aug 13 04:41:32 PM PDT 24
Finished Aug 13 04:41:46 PM PDT 24
Peak memory 218440 kb
Host smart-9e8506cb-14fb-4949-ac4b-7502aa934d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329677228 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.3329677228 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_key_error/latest

Test location /workspace/coverage/default/43.kmac_lc_escalation.2699156868
Short name T52
Test name
Test status
Simulation time 450345672 ps
CPU time 1.56 seconds
Started Aug 13 04:41:37 PM PDT 24
Finished Aug 13 04:41:39 PM PDT 24
Peak memory 226636 kb
Host smart-58e4a788-7dbd-40c4-ba74-53e563c59251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699156868 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.2699156868 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/43.kmac_lc_escalation/latest

Test location /workspace/coverage/default/43.kmac_long_msg_and_output.2056941142
Short name T528
Test name
Test status
Simulation time 971843595999 ps
CPU time 4581.24 seconds
Started Aug 13 04:41:36 PM PDT 24
Finished Aug 13 05:57:58 PM PDT 24
Peak memory 3370452 kb
Host smart-c359d922-f3d7-4529-92e6-e8be7c71bb9f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056941142 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_a
nd_output.2056941142 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/43.kmac_sideload.3719457480
Short name T589
Test name
Test status
Simulation time 6195562157 ps
CPU time 491.11 seconds
Started Aug 13 04:41:33 PM PDT 24
Finished Aug 13 04:49:44 PM PDT 24
Peak memory 396708 kb
Host smart-d259e92a-3834-4b4b-baf8-aea1469d6e18
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719457480 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.3719457480 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_sideload/latest

Test location /workspace/coverage/default/43.kmac_smoke.2541739012
Short name T255
Test name
Test status
Simulation time 2437289412 ps
CPU time 60.5 seconds
Started Aug 13 04:41:34 PM PDT 24
Finished Aug 13 04:42:34 PM PDT 24
Peak memory 226672 kb
Host smart-38979315-7d6f-4051-9935-4e6b6e124f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541739012 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.2541739012 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_smoke/latest

Test location /workspace/coverage/default/43.kmac_stress_all.4157379618
Short name T652
Test name
Test status
Simulation time 3013581825 ps
CPU time 98.29 seconds
Started Aug 13 04:41:32 PM PDT 24
Finished Aug 13 04:43:10 PM PDT 24
Peak memory 260396 kb
Host smart-4ae201e5-bc47-4727-ad6a-5192ec932424
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4157379618 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.4157379618 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_stress_all/latest

Test location /workspace/coverage/default/44.kmac_alert_test.1423345089
Short name T246
Test name
Test status
Simulation time 16706443 ps
CPU time 0.87 seconds
Started Aug 13 04:41:40 PM PDT 24
Finished Aug 13 04:41:41 PM PDT 24
Peak memory 218196 kb
Host smart-6b6c70f6-c409-45e0-9621-a6919b9df265
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423345089 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.1423345089 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_alert_test/latest

Test location /workspace/coverage/default/44.kmac_app.437017650
Short name T647
Test name
Test status
Simulation time 8706035253 ps
CPU time 222.96 seconds
Started Aug 13 04:41:40 PM PDT 24
Finished Aug 13 04:45:23 PM PDT 24
Peak memory 393100 kb
Host smart-5ca6978c-98ee-4006-8713-fc218f3fbae6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437017650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.437017650 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/44.kmac_app/latest

Test location /workspace/coverage/default/44.kmac_burst_write.321307790
Short name T542
Test name
Test status
Simulation time 307816201935 ps
CPU time 1134.99 seconds
Started Aug 13 04:41:33 PM PDT 24
Finished Aug 13 05:00:28 PM PDT 24
Peak memory 257684 kb
Host smart-7b584adb-c150-45d4-8688-12e5778307b2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321307790 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.321307790
+enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_burst_write/latest

Test location /workspace/coverage/default/44.kmac_entropy_refresh.1063114490
Short name T19
Test name
Test status
Simulation time 7719941254 ps
CPU time 296.28 seconds
Started Aug 13 04:41:41 PM PDT 24
Finished Aug 13 04:46:37 PM PDT 24
Peak memory 317444 kb
Host smart-fc015f1c-7f69-4fb6-b09f-97d7beab41a3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063114490 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.1
063114490 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/44.kmac_error.2702720102
Short name T605
Test name
Test status
Simulation time 13969872873 ps
CPU time 182.06 seconds
Started Aug 13 04:41:40 PM PDT 24
Finished Aug 13 04:44:42 PM PDT 24
Peak memory 283428 kb
Host smart-416ae401-4680-4ac0-ac5e-643f30209e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702720102 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_error.2702720102 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_error/latest

Test location /workspace/coverage/default/44.kmac_key_error.2554194723
Short name T442
Test name
Test status
Simulation time 4028199014 ps
CPU time 6.72 seconds
Started Aug 13 04:41:40 PM PDT 24
Finished Aug 13 04:41:47 PM PDT 24
Peak memory 226632 kb
Host smart-a10fc9f5-dbfa-4ee7-8d0f-90f6d4ae4b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554194723 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.2554194723 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_key_error/latest

Test location /workspace/coverage/default/44.kmac_lc_escalation.2794089473
Short name T110
Test name
Test status
Simulation time 165334827 ps
CPU time 1.56 seconds
Started Aug 13 04:41:42 PM PDT 24
Finished Aug 13 04:41:44 PM PDT 24
Peak memory 226772 kb
Host smart-ef3abcc2-24cd-4898-aaf1-644d7e995d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794089473 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.2794089473 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/44.kmac_lc_escalation/latest

Test location /workspace/coverage/default/44.kmac_long_msg_and_output.2660816926
Short name T337
Test name
Test status
Simulation time 292833272651 ps
CPU time 3771.32 seconds
Started Aug 13 04:41:37 PM PDT 24
Finished Aug 13 05:44:29 PM PDT 24
Peak memory 2895284 kb
Host smart-bde2112a-7df1-4f42-a552-49b84abe562a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660816926 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_a
nd_output.2660816926 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/44.kmac_sideload.2602465991
Short name T712
Test name
Test status
Simulation time 12622107188 ps
CPU time 429.47 seconds
Started Aug 13 04:41:38 PM PDT 24
Finished Aug 13 04:48:48 PM PDT 24
Peak memory 549400 kb
Host smart-2b14fce9-b2a6-44b4-b0bc-4ec6b65b247f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602465991 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.2602465991 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_sideload/latest

Test location /workspace/coverage/default/44.kmac_smoke.3223482679
Short name T218
Test name
Test status
Simulation time 4940786137 ps
CPU time 26.83 seconds
Started Aug 13 04:41:34 PM PDT 24
Finished Aug 13 04:42:01 PM PDT 24
Peak memory 226776 kb
Host smart-fb006548-42d5-4945-b589-5766447670d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223482679 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.3223482679 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_smoke/latest

Test location /workspace/coverage/default/44.kmac_stress_all.2292870260
Short name T313
Test name
Test status
Simulation time 26224649505 ps
CPU time 140.26 seconds
Started Aug 13 04:41:38 PM PDT 24
Finished Aug 13 04:43:59 PM PDT 24
Peak memory 357028 kb
Host smart-6c5315b8-1427-4e9b-ae8b-eaa8f3cbf4b4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2292870260 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all.2292870260 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_stress_all/latest

Test location /workspace/coverage/default/45.kmac_alert_test.1619906515
Short name T636
Test name
Test status
Simulation time 81051581 ps
CPU time 0.94 seconds
Started Aug 13 04:41:41 PM PDT 24
Finished Aug 13 04:41:42 PM PDT 24
Peak memory 218152 kb
Host smart-a6725183-6b15-4380-ac69-3defd2aac36f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619906515 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.1619906515 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_alert_test/latest

Test location /workspace/coverage/default/45.kmac_app.3994689231
Short name T707
Test name
Test status
Simulation time 26448167225 ps
CPU time 202.75 seconds
Started Aug 13 04:41:41 PM PDT 24
Finished Aug 13 04:45:04 PM PDT 24
Peak memory 343284 kb
Host smart-c85d9e41-9064-43dd-953d-ecf3aeed5ace
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994689231 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.3994689231 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/45.kmac_app/latest

Test location /workspace/coverage/default/45.kmac_burst_write.4187439237
Short name T322
Test name
Test status
Simulation time 8874143719 ps
CPU time 873.14 seconds
Started Aug 13 04:41:41 PM PDT 24
Finished Aug 13 04:56:14 PM PDT 24
Peak memory 242764 kb
Host smart-a74fafcc-17b5-4c53-a4c5-4a1df0b4ad44
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187439237 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.418743923
7 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_burst_write/latest

Test location /workspace/coverage/default/45.kmac_entropy_refresh.1414445853
Short name T533
Test name
Test status
Simulation time 13393005322 ps
CPU time 89.32 seconds
Started Aug 13 04:41:40 PM PDT 24
Finished Aug 13 04:43:09 PM PDT 24
Peak memory 281952 kb
Host smart-89369921-4a27-4b74-8e54-22078cb13047
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414445853 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_entropy_refresh.1
414445853 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/45.kmac_error.1224506613
Short name T305
Test name
Test status
Simulation time 1012303622 ps
CPU time 91.67 seconds
Started Aug 13 04:41:38 PM PDT 24
Finished Aug 13 04:43:10 PM PDT 24
Peak memory 267516 kb
Host smart-086f2f50-54a0-4d8b-bb1f-46b78ef38db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224506613 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.1224506613 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_error/latest

Test location /workspace/coverage/default/45.kmac_key_error.2673887908
Short name T633
Test name
Test status
Simulation time 801687595 ps
CPU time 1.54 seconds
Started Aug 13 04:41:41 PM PDT 24
Finished Aug 13 04:41:43 PM PDT 24
Peak memory 226408 kb
Host smart-fac0ef47-f433-4a1c-b1bb-c3771d3d20ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673887908 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.2673887908 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_key_error/latest

Test location /workspace/coverage/default/45.kmac_long_msg_and_output.2263662817
Short name T672
Test name
Test status
Simulation time 17068626857 ps
CPU time 89.46 seconds
Started Aug 13 04:41:41 PM PDT 24
Finished Aug 13 04:43:11 PM PDT 24
Peak memory 324584 kb
Host smart-c918c5fc-25b9-4128-8d18-18d978be05bd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263662817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_a
nd_output.2263662817 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/45.kmac_sideload.2041016446
Short name T217
Test name
Test status
Simulation time 19549269653 ps
CPU time 532.98 seconds
Started Aug 13 04:41:40 PM PDT 24
Finished Aug 13 04:50:33 PM PDT 24
Peak memory 407144 kb
Host smart-67b10eb8-9645-40f3-81c3-968171a95b63
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041016446 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.2041016446 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_sideload/latest

Test location /workspace/coverage/default/45.kmac_smoke.3747087118
Short name T191
Test name
Test status
Simulation time 9122712344 ps
CPU time 56.19 seconds
Started Aug 13 04:41:40 PM PDT 24
Finished Aug 13 04:42:36 PM PDT 24
Peak memory 223744 kb
Host smart-d64ec498-246f-4ceb-8410-ec907e729e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747087118 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.3747087118 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_smoke/latest

Test location /workspace/coverage/default/45.kmac_stress_all.3580403818
Short name T93
Test name
Test status
Simulation time 2462799219 ps
CPU time 94.99 seconds
Started Aug 13 04:41:42 PM PDT 24
Finished Aug 13 04:43:17 PM PDT 24
Peak memory 267620 kb
Host smart-24f0b909-0f7c-4bf0-923b-4683aa944254
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3580403818 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.3580403818 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_stress_all/latest

Test location /workspace/coverage/default/46.kmac_alert_test.3180770286
Short name T708
Test name
Test status
Simulation time 210093963 ps
CPU time 0.84 seconds
Started Aug 13 04:41:42 PM PDT 24
Finished Aug 13 04:41:43 PM PDT 24
Peak memory 218276 kb
Host smart-26025cf0-076c-47e1-9ace-7deb919cd37d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180770286 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.3180770286 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_alert_test/latest

Test location /workspace/coverage/default/46.kmac_app.1774635065
Short name T645
Test name
Test status
Simulation time 14103184088 ps
CPU time 388.51 seconds
Started Aug 13 04:41:39 PM PDT 24
Finished Aug 13 04:48:08 PM PDT 24
Peak memory 484312 kb
Host smart-7f24e1b0-3a8d-4f25-8c56-d6fd3a3baef6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774635065 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.1774635065 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/46.kmac_app/latest

Test location /workspace/coverage/default/46.kmac_burst_write.767303529
Short name T304
Test name
Test status
Simulation time 10992085764 ps
CPU time 936.19 seconds
Started Aug 13 04:41:41 PM PDT 24
Finished Aug 13 04:57:17 PM PDT 24
Peak memory 242092 kb
Host smart-06c98936-ab6a-4bda-a568-c4078e8d77a5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767303529 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.767303529
+enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_burst_write/latest

Test location /workspace/coverage/default/46.kmac_entropy_refresh.3330689102
Short name T63
Test name
Test status
Simulation time 22925996455 ps
CPU time 236.94 seconds
Started Aug 13 04:41:40 PM PDT 24
Finished Aug 13 04:45:37 PM PDT 24
Peak memory 410872 kb
Host smart-7bfe86d5-dc17-4c1f-8e5d-0e89d2ed0336
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330689102 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_entropy_refresh.3
330689102 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/46.kmac_error.3389885908
Short name T350
Test name
Test status
Simulation time 20170499093 ps
CPU time 308.66 seconds
Started Aug 13 04:41:40 PM PDT 24
Finished Aug 13 04:46:49 PM PDT 24
Peak memory 337404 kb
Host smart-9f9017a6-d69a-4e47-9e62-2d9b29f153ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389885908 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.3389885908 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_error/latest

Test location /workspace/coverage/default/46.kmac_lc_escalation.3350594699
Short name T508
Test name
Test status
Simulation time 2707865771 ps
CPU time 20.35 seconds
Started Aug 13 04:41:43 PM PDT 24
Finished Aug 13 04:42:04 PM PDT 24
Peak memory 251536 kb
Host smart-a194c3dc-6e40-4ed8-96fe-16eb90cef784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350594699 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.3350594699 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/46.kmac_lc_escalation/latest

Test location /workspace/coverage/default/46.kmac_long_msg_and_output.1423941706
Short name T360
Test name
Test status
Simulation time 106758346255 ps
CPU time 4244.28 seconds
Started Aug 13 04:41:40 PM PDT 24
Finished Aug 13 05:52:25 PM PDT 24
Peak memory 1905020 kb
Host smart-6f6f1eea-9911-4c0c-92a6-f86c7710aa1e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423941706 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_a
nd_output.1423941706 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/46.kmac_sideload.2243274596
Short name T38
Test name
Test status
Simulation time 9499936217 ps
CPU time 65.27 seconds
Started Aug 13 04:41:41 PM PDT 24
Finished Aug 13 04:42:46 PM PDT 24
Peak memory 280796 kb
Host smart-d62700c3-9dd0-4568-b0ba-747ea2b130f3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243274596 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.2243274596 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_sideload/latest

Test location /workspace/coverage/default/46.kmac_smoke.950364188
Short name T362
Test name
Test status
Simulation time 6145188482 ps
CPU time 63.08 seconds
Started Aug 13 04:41:40 PM PDT 24
Finished Aug 13 04:42:43 PM PDT 24
Peak memory 224700 kb
Host smart-203e36b1-fdfa-46d2-b23b-88d2fef4404b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950364188 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.950364188 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_smoke/latest

Test location /workspace/coverage/default/46.kmac_stress_all.619201918
Short name T76
Test name
Test status
Simulation time 105872443403 ps
CPU time 818.89 seconds
Started Aug 13 04:41:41 PM PDT 24
Finished Aug 13 04:55:20 PM PDT 24
Peak memory 489120 kb
Host smart-8943e2ed-0577-4467-8a62-d37ad07eb1f3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=619201918 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.619201918 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_stress_all/latest

Test location /workspace/coverage/default/47.kmac_alert_test.819131384
Short name T530
Test name
Test status
Simulation time 36250940 ps
CPU time 0.83 seconds
Started Aug 13 04:41:47 PM PDT 24
Finished Aug 13 04:41:48 PM PDT 24
Peak memory 218148 kb
Host smart-f0abb45c-ba74-4ee3-9e63-a2b6f4d133b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819131384 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.819131384 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/47.kmac_alert_test/latest

Test location /workspace/coverage/default/47.kmac_app.865385032
Short name T173
Test name
Test status
Simulation time 11178295258 ps
CPU time 363.56 seconds
Started Aug 13 04:41:47 PM PDT 24
Finished Aug 13 04:47:50 PM PDT 24
Peak memory 479832 kb
Host smart-19fda475-35e3-4118-939b-18ff29f0a63f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865385032 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.865385032 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/47.kmac_app/latest

Test location /workspace/coverage/default/47.kmac_burst_write.2198043192
Short name T403
Test name
Test status
Simulation time 18020409125 ps
CPU time 466.42 seconds
Started Aug 13 04:41:39 PM PDT 24
Finished Aug 13 04:49:26 PM PDT 24
Peak memory 238968 kb
Host smart-b2860e80-114a-47ff-9173-73108dcfca98
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198043192 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.219804319
2 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_burst_write/latest

Test location /workspace/coverage/default/47.kmac_entropy_refresh.94235902
Short name T426
Test name
Test status
Simulation time 12622577946 ps
CPU time 279.41 seconds
Started Aug 13 04:41:51 PM PDT 24
Finished Aug 13 04:46:31 PM PDT 24
Peak memory 398736 kb
Host smart-0f82dbbf-80a7-405b-961d-34050056a16a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94235902 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.942
35902 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/47.kmac_error.3414825825
Short name T668
Test name
Test status
Simulation time 2161704507 ps
CPU time 51.36 seconds
Started Aug 13 04:41:47 PM PDT 24
Finished Aug 13 04:42:38 PM PDT 24
Peak memory 255208 kb
Host smart-515c9f9d-cba3-4b33-8259-3040ba408b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414825825 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.3414825825 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_error/latest

Test location /workspace/coverage/default/47.kmac_key_error.3602382445
Short name T552
Test name
Test status
Simulation time 17323852674 ps
CPU time 12.97 seconds
Started Aug 13 04:41:47 PM PDT 24
Finished Aug 13 04:42:00 PM PDT 24
Peak memory 226608 kb
Host smart-760101b3-d10c-4672-9e8d-449727170f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602382445 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.3602382445 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_key_error/latest

Test location /workspace/coverage/default/47.kmac_lc_escalation.2991630158
Short name T51
Test name
Test status
Simulation time 1556620186 ps
CPU time 18.68 seconds
Started Aug 13 04:41:48 PM PDT 24
Finished Aug 13 04:42:07 PM PDT 24
Peak memory 243084 kb
Host smart-e6d88f0a-8786-465a-bd3e-f23cb0cfc4bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991630158 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.2991630158 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/47.kmac_lc_escalation/latest

Test location /workspace/coverage/default/47.kmac_long_msg_and_output.706880934
Short name T105
Test name
Test status
Simulation time 65564759998 ps
CPU time 4120.72 seconds
Started Aug 13 04:41:42 PM PDT 24
Finished Aug 13 05:50:23 PM PDT 24
Peak memory 3158696 kb
Host smart-735a7f83-910d-4f1a-a8fd-57c88af79581
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706880934 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_an
d_output.706880934 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/47.kmac_sideload.3533434894
Short name T702
Test name
Test status
Simulation time 674161758 ps
CPU time 48.54 seconds
Started Aug 13 04:41:40 PM PDT 24
Finished Aug 13 04:42:28 PM PDT 24
Peak memory 240860 kb
Host smart-f11b3601-a5c8-46b9-acc3-d35ec6e88ed3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533434894 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.3533434894 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_sideload/latest

Test location /workspace/coverage/default/47.kmac_smoke.35967752
Short name T251
Test name
Test status
Simulation time 1140872129 ps
CPU time 23.74 seconds
Started Aug 13 04:41:41 PM PDT 24
Finished Aug 13 04:42:05 PM PDT 24
Peak memory 226564 kb
Host smart-9732010b-9774-4063-bd35-e06ce434fd67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35967752 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.35967752 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_smoke/latest

Test location /workspace/coverage/default/48.kmac_alert_test.3362942319
Short name T204
Test name
Test status
Simulation time 108930117 ps
CPU time 0.78 seconds
Started Aug 13 04:41:55 PM PDT 24
Finished Aug 13 04:41:55 PM PDT 24
Peak memory 218204 kb
Host smart-63060ba9-ac36-4489-94e9-19ac25942236
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362942319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.3362942319 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_alert_test/latest

Test location /workspace/coverage/default/48.kmac_app.1902565317
Short name T381
Test name
Test status
Simulation time 3182979099 ps
CPU time 46.24 seconds
Started Aug 13 04:41:47 PM PDT 24
Finished Aug 13 04:42:34 PM PDT 24
Peak memory 252236 kb
Host smart-f0744c36-c442-4424-805d-a5e56a1ae949
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902565317 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.1902565317 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/48.kmac_app/latest

Test location /workspace/coverage/default/48.kmac_burst_write.3058094148
Short name T667
Test name
Test status
Simulation time 30422425935 ps
CPU time 1316.95 seconds
Started Aug 13 04:41:47 PM PDT 24
Finished Aug 13 05:03:44 PM PDT 24
Peak memory 261484 kb
Host smart-12907432-466f-411b-91ad-49c1dda4912d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058094148 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.305809414
8 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_burst_write/latest

Test location /workspace/coverage/default/48.kmac_entropy_refresh.1653857972
Short name T172
Test name
Test status
Simulation time 7163652088 ps
CPU time 163.68 seconds
Started Aug 13 04:41:47 PM PDT 24
Finished Aug 13 04:44:31 PM PDT 24
Peak memory 336132 kb
Host smart-c302b5bd-7193-42e9-b34b-d789a1432fa1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653857972 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.1
653857972 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/48.kmac_error.443385983
Short name T699
Test name
Test status
Simulation time 12146205811 ps
CPU time 435.23 seconds
Started Aug 13 04:41:49 PM PDT 24
Finished Aug 13 04:49:04 PM PDT 24
Peak memory 364800 kb
Host smart-99915066-015a-4b53-816e-add5ca3d4471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443385983 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.443385983 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_error/latest

Test location /workspace/coverage/default/48.kmac_key_error.3971831001
Short name T235
Test name
Test status
Simulation time 1572002128 ps
CPU time 10.92 seconds
Started Aug 13 04:41:50 PM PDT 24
Finished Aug 13 04:42:01 PM PDT 24
Peak memory 226496 kb
Host smart-a09ef4d1-5128-4869-b230-8abf441ee274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971831001 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.3971831001 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_key_error/latest

Test location /workspace/coverage/default/48.kmac_lc_escalation.4281782975
Short name T698
Test name
Test status
Simulation time 48128949 ps
CPU time 1.5 seconds
Started Aug 13 04:41:47 PM PDT 24
Finished Aug 13 04:41:49 PM PDT 24
Peak memory 226592 kb
Host smart-9bec7624-2d63-40de-9279-160165b990ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281782975 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.4281782975 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/48.kmac_lc_escalation/latest

Test location /workspace/coverage/default/48.kmac_long_msg_and_output.3874877527
Short name T639
Test name
Test status
Simulation time 123093278867 ps
CPU time 1187.29 seconds
Started Aug 13 04:41:48 PM PDT 24
Finished Aug 13 05:01:35 PM PDT 24
Peak memory 1286592 kb
Host smart-342a942a-899b-4803-8f1d-4183c9158a4f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874877527 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_a
nd_output.3874877527 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/48.kmac_sideload.3630266746
Short name T195
Test name
Test status
Simulation time 31354860318 ps
CPU time 558.65 seconds
Started Aug 13 04:41:47 PM PDT 24
Finished Aug 13 04:51:06 PM PDT 24
Peak memory 634920 kb
Host smart-4a503037-79cc-499b-8788-946f56b48d79
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630266746 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.3630266746 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_sideload/latest

Test location /workspace/coverage/default/48.kmac_smoke.4141567165
Short name T592
Test name
Test status
Simulation time 2717855604 ps
CPU time 49.03 seconds
Started Aug 13 04:41:46 PM PDT 24
Finished Aug 13 04:42:35 PM PDT 24
Peak memory 226776 kb
Host smart-1629d8fd-b526-417d-842d-5c7871bd6dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141567165 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.4141567165 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_smoke/latest

Test location /workspace/coverage/default/48.kmac_stress_all.3929545289
Short name T72
Test name
Test status
Simulation time 7798226289 ps
CPU time 830.08 seconds
Started Aug 13 04:41:48 PM PDT 24
Finished Aug 13 04:55:38 PM PDT 24
Peak memory 496020 kb
Host smart-c1f8cf0c-3ad7-4af2-b3f9-cc5e1e85bce8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3929545289 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.3929545289 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_stress_all/latest

Test location /workspace/coverage/default/49.kmac_alert_test.1026112827
Short name T452
Test name
Test status
Simulation time 22364579 ps
CPU time 0.83 seconds
Started Aug 13 04:41:55 PM PDT 24
Finished Aug 13 04:41:56 PM PDT 24
Peak memory 218172 kb
Host smart-5017dfae-ea38-44cf-8476-133e2a932c6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026112827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.1026112827 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_alert_test/latest

Test location /workspace/coverage/default/49.kmac_app.916607847
Short name T203
Test name
Test status
Simulation time 14157163679 ps
CPU time 233.96 seconds
Started Aug 13 04:41:56 PM PDT 24
Finished Aug 13 04:45:50 PM PDT 24
Peak memory 294132 kb
Host smart-e03a6f93-25bf-4903-8dd7-385d3adb7c3e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916607847 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.916607847 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/49.kmac_app/latest

Test location /workspace/coverage/default/49.kmac_entropy_refresh.371361729
Short name T515
Test name
Test status
Simulation time 7436284516 ps
CPU time 207.49 seconds
Started Aug 13 04:41:55 PM PDT 24
Finished Aug 13 04:45:23 PM PDT 24
Peak memory 382360 kb
Host smart-79c11541-d38b-4c15-bdf6-af6eca41b91d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371361729 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.37
1361729 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/49.kmac_error.2005336813
Short name T654
Test name
Test status
Simulation time 3156029648 ps
CPU time 77.17 seconds
Started Aug 13 04:41:59 PM PDT 24
Finished Aug 13 04:43:16 PM PDT 24
Peak memory 289960 kb
Host smart-a17c3eef-1283-43b5-a163-75b48d042a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005336813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.2005336813 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_error/latest

Test location /workspace/coverage/default/49.kmac_key_error.1751416694
Short name T113
Test name
Test status
Simulation time 215964509 ps
CPU time 1.68 seconds
Started Aug 13 04:41:57 PM PDT 24
Finished Aug 13 04:41:59 PM PDT 24
Peak memory 226224 kb
Host smart-5f5d962a-7a45-4270-8ba5-f93984719d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751416694 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.1751416694 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_key_error/latest

Test location /workspace/coverage/default/49.kmac_lc_escalation.2556401747
Short name T70
Test name
Test status
Simulation time 52802725 ps
CPU time 1.31 seconds
Started Aug 13 04:41:55 PM PDT 24
Finished Aug 13 04:41:56 PM PDT 24
Peak memory 226660 kb
Host smart-e9834e74-af65-4fd5-ae83-85172701fc1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556401747 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.2556401747 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/49.kmac_lc_escalation/latest

Test location /workspace/coverage/default/49.kmac_sideload.1133294953
Short name T353
Test name
Test status
Simulation time 64577900124 ps
CPU time 290.27 seconds
Started Aug 13 04:41:55 PM PDT 24
Finished Aug 13 04:46:45 PM PDT 24
Peak memory 437260 kb
Host smart-f84c00e2-6c69-4753-84ea-95ae79ab0028
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133294953 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.1133294953 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_sideload/latest

Test location /workspace/coverage/default/49.kmac_smoke.388691775
Short name T480
Test name
Test status
Simulation time 794852945 ps
CPU time 29.14 seconds
Started Aug 13 04:42:00 PM PDT 24
Finished Aug 13 04:42:29 PM PDT 24
Peak memory 226720 kb
Host smart-a785e35a-13e6-4807-8136-ffbc1c887dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388691775 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.388691775 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_smoke/latest

Test location /workspace/coverage/default/49.kmac_stress_all.4097259903
Short name T474
Test name
Test status
Simulation time 6664353281 ps
CPU time 551.76 seconds
Started Aug 13 04:41:57 PM PDT 24
Finished Aug 13 04:51:09 PM PDT 24
Peak memory 484256 kb
Host smart-3e49a4d7-01ce-420f-a23c-2a7a04a2d62f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4097259903 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.4097259903 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_stress_all/latest

Test location /workspace/coverage/default/5.kmac_alert_test.3738606932
Short name T422
Test name
Test status
Simulation time 32033976 ps
CPU time 0.82 seconds
Started Aug 13 04:40:31 PM PDT 24
Finished Aug 13 04:40:32 PM PDT 24
Peak memory 218164 kb
Host smart-e63058a9-80dd-4693-bda1-640572accb3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738606932 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.3738606932 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_alert_test/latest

Test location /workspace/coverage/default/5.kmac_app.4076249326
Short name T618
Test name
Test status
Simulation time 6380601647 ps
CPU time 167.19 seconds
Started Aug 13 04:40:28 PM PDT 24
Finished Aug 13 04:43:16 PM PDT 24
Peak memory 346240 kb
Host smart-7a45d0fa-a62c-4957-b26b-2a3e34e0b3f6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076249326 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.4076249326 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/5.kmac_app/latest

Test location /workspace/coverage/default/5.kmac_app_with_partial_data.2042314466
Short name T691
Test name
Test status
Simulation time 8073301487 ps
CPU time 303.06 seconds
Started Aug 13 04:40:10 PM PDT 24
Finished Aug 13 04:45:13 PM PDT 24
Peak memory 313520 kb
Host smart-8760ace5-51ed-471b-a567-06d37ab86931
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042314466 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_par
tial_data.2042314466 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/5.kmac_burst_write.3693500182
Short name T333
Test name
Test status
Simulation time 25153500234 ps
CPU time 663.8 seconds
Started Aug 13 04:40:18 PM PDT 24
Finished Aug 13 04:51:22 PM PDT 24
Peak memory 244980 kb
Host smart-44a8d626-ee5c-43dc-9344-24bc515e7e71
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693500182 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.3693500182
+enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_burst_write/latest

Test location /workspace/coverage/default/5.kmac_edn_timeout_error.682202512
Short name T614
Test name
Test status
Simulation time 41406922 ps
CPU time 0.94 seconds
Started Aug 13 04:40:18 PM PDT 24
Finished Aug 13 04:40:19 PM PDT 24
Peak memory 218056 kb
Host smart-408df77e-a8dc-4060-84ef-c255f1421a8c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=682202512 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.682202512 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_mode_error.1175351062
Short name T271
Test name
Test status
Simulation time 44866510 ps
CPU time 1.34 seconds
Started Aug 13 04:40:17 PM PDT 24
Finished Aug 13 04:40:19 PM PDT 24
Peak memory 222160 kb
Host smart-7eed681e-8ce3-490e-b114-413c56312c38
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1175351062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.1175351062 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_ready_error.1924947418
Short name T354
Test name
Test status
Simulation time 7556848080 ps
CPU time 40.24 seconds
Started Aug 13 04:40:07 PM PDT 24
Finished Aug 13 04:40:47 PM PDT 24
Peak memory 226792 kb
Host smart-8c5569fd-1566-4edf-b943-16b6bb6f5ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924947418 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.1924947418 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_refresh.2417041621
Short name T521
Test name
Test status
Simulation time 2619304839 ps
CPU time 162.6 seconds
Started Aug 13 04:40:16 PM PDT 24
Finished Aug 13 04:42:58 PM PDT 24
Peak memory 277136 kb
Host smart-ea3c8ca0-2671-4775-9b6c-59083e7b976c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417041621 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.24
17041621 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/5.kmac_error.2389478714
Short name T222
Test name
Test status
Simulation time 3401346730 ps
CPU time 91.23 seconds
Started Aug 13 04:40:23 PM PDT 24
Finished Aug 13 04:41:54 PM PDT 24
Peak memory 267640 kb
Host smart-74ab34b6-08a8-4fae-956d-4054d29ee33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389478714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.2389478714 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_error/latest

Test location /workspace/coverage/default/5.kmac_key_error.3667693066
Short name T270
Test name
Test status
Simulation time 2806169039 ps
CPU time 7.33 seconds
Started Aug 13 04:40:12 PM PDT 24
Finished Aug 13 04:40:19 PM PDT 24
Peak memory 226464 kb
Host smart-b2534aea-5083-4305-8e31-51f919ae2def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667693066 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.3667693066 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_key_error/latest

Test location /workspace/coverage/default/5.kmac_lc_escalation.586158493
Short name T460
Test name
Test status
Simulation time 83483569 ps
CPU time 1.43 seconds
Started Aug 13 04:40:11 PM PDT 24
Finished Aug 13 04:40:12 PM PDT 24
Peak memory 226556 kb
Host smart-b571d610-c257-4b2b-92f6-52fdeea9d4d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586158493 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.586158493 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_lc_escalation/latest

Test location /workspace/coverage/default/5.kmac_long_msg_and_output.2516205788
Short name T209
Test name
Test status
Simulation time 417720621837 ps
CPU time 4565.6 seconds
Started Aug 13 04:40:09 PM PDT 24
Finished Aug 13 05:56:16 PM PDT 24
Peak memory 3345632 kb
Host smart-bd3d5d24-d253-48ea-9ca9-d0455ee0bcdf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516205788 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_an
d_output.2516205788 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/5.kmac_mubi.2115478061
Short name T358
Test name
Test status
Simulation time 17889457285 ps
CPU time 459.77 seconds
Started Aug 13 04:40:05 PM PDT 24
Finished Aug 13 04:47:45 PM PDT 24
Peak memory 569564 kb
Host smart-6b4d6b2e-553c-4fbd-8ea6-3a4ab7b711c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115478061 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.2115478061 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_mubi/latest

Test location /workspace/coverage/default/5.kmac_sideload.2035342538
Short name T467
Test name
Test status
Simulation time 10218275915 ps
CPU time 220.81 seconds
Started Aug 13 04:40:17 PM PDT 24
Finished Aug 13 04:43:58 PM PDT 24
Peak memory 293492 kb
Host smart-7e6184ae-9d80-4f7a-8142-788ca199b235
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035342538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.2035342538 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_sideload/latest

Test location /workspace/coverage/default/5.kmac_smoke.2689013236
Short name T138
Test name
Test status
Simulation time 866632509 ps
CPU time 8.99 seconds
Started Aug 13 04:40:13 PM PDT 24
Finished Aug 13 04:40:22 PM PDT 24
Peak memory 226684 kb
Host smart-e1de78ef-22e7-47f4-a616-df8c8a0eae1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689013236 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.2689013236 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_smoke/latest

Test location /workspace/coverage/default/5.kmac_stress_all.3567812932
Short name T561
Test name
Test status
Simulation time 55330816615 ps
CPU time 1025.4 seconds
Started Aug 13 04:40:15 PM PDT 24
Finished Aug 13 04:57:21 PM PDT 24
Peak memory 571656 kb
Host smart-58f2c41a-7a8b-4154-bcae-a709faea59c4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3567812932 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.3567812932 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_stress_all/latest

Test location /workspace/coverage/default/6.kmac_alert_test.191288278
Short name T487
Test name
Test status
Simulation time 18210139 ps
CPU time 0.81 seconds
Started Aug 13 04:40:02 PM PDT 24
Finished Aug 13 04:40:03 PM PDT 24
Peak memory 218236 kb
Host smart-e3ec1dc5-dcc9-44c2-af24-8d6ee65b1338
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191288278 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.191288278 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/6.kmac_alert_test/latest

Test location /workspace/coverage/default/6.kmac_app.3599526094
Short name T526
Test name
Test status
Simulation time 21246248150 ps
CPU time 158.41 seconds
Started Aug 13 04:40:20 PM PDT 24
Finished Aug 13 04:42:59 PM PDT 24
Peak memory 337672 kb
Host smart-54d3b2d4-4813-44e8-8c62-baebda438781
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599526094 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.3599526094 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/6.kmac_app/latest

Test location /workspace/coverage/default/6.kmac_app_with_partial_data.2953307075
Short name T696
Test name
Test status
Simulation time 757335300 ps
CPU time 25.38 seconds
Started Aug 13 04:40:15 PM PDT 24
Finished Aug 13 04:40:40 PM PDT 24
Peak memory 227056 kb
Host smart-0c964d0b-f858-43e4-8317-72259b0a2018
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953307075 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_par
tial_data.2953307075 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/6.kmac_burst_write.902780196
Short name T284
Test name
Test status
Simulation time 5234651224 ps
CPU time 210.43 seconds
Started Aug 13 04:40:23 PM PDT 24
Finished Aug 13 04:43:54 PM PDT 24
Peak memory 231092 kb
Host smart-6b72485f-dbd8-4124-8fbc-bd5616258af0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902780196 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.902780196 +
enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_burst_write/latest

Test location /workspace/coverage/default/6.kmac_edn_timeout_error.3197829256
Short name T392
Test name
Test status
Simulation time 15889396 ps
CPU time 0.94 seconds
Started Aug 13 04:40:06 PM PDT 24
Finished Aug 13 04:40:07 PM PDT 24
Peak memory 218104 kb
Host smart-d070b4cb-8ae9-4558-95c7-162052554664
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3197829256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.3197829256 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_mode_error.2404166108
Short name T67
Test name
Test status
Simulation time 28484006 ps
CPU time 1.07 seconds
Started Aug 13 04:40:10 PM PDT 24
Finished Aug 13 04:40:11 PM PDT 24
Peak memory 221692 kb
Host smart-07e25107-9106-4368-8dcd-86600371e36a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2404166108 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.2404166108 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_ready_error.1314444783
Short name T11
Test name
Test status
Simulation time 442001988 ps
CPU time 4.11 seconds
Started Aug 13 04:40:28 PM PDT 24
Finished Aug 13 04:40:32 PM PDT 24
Peak memory 219280 kb
Host smart-581c2ffb-b425-4185-89ac-5b0d07e32cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314444783 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.1314444783 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_refresh.3904686392
Short name T294
Test name
Test status
Simulation time 10361247289 ps
CPU time 315.13 seconds
Started Aug 13 04:40:05 PM PDT 24
Finished Aug 13 04:45:20 PM PDT 24
Peak memory 317588 kb
Host smart-d7a73dd4-aaa2-4c70-a5e8-c30b908735e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904686392 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.39
04686392 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/6.kmac_key_error.1587790952
Short name T137
Test name
Test status
Simulation time 659993365 ps
CPU time 5.07 seconds
Started Aug 13 04:40:03 PM PDT 24
Finished Aug 13 04:40:08 PM PDT 24
Peak memory 226392 kb
Host smart-df28b5f1-1577-4d69-b8be-69efda38f8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587790952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.1587790952 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_key_error/latest

Test location /workspace/coverage/default/6.kmac_lc_escalation.1422464954
Short name T41
Test name
Test status
Simulation time 138583554 ps
CPU time 1.3 seconds
Started Aug 13 04:40:03 PM PDT 24
Finished Aug 13 04:40:05 PM PDT 24
Peak memory 226576 kb
Host smart-c18a5e7b-4e3f-48da-9b89-a768998551d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422464954 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.1422464954 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/6.kmac_lc_escalation/latest

Test location /workspace/coverage/default/6.kmac_long_msg_and_output.3614146611
Short name T225
Test name
Test status
Simulation time 21273329534 ps
CPU time 2765.7 seconds
Started Aug 13 04:40:19 PM PDT 24
Finished Aug 13 05:26:25 PM PDT 24
Peak memory 1458596 kb
Host smart-8765e89b-ce12-4673-8a8c-4fea7759b0b6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614146611 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_an
d_output.3614146611 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/6.kmac_mubi.2359323765
Short name T425
Test name
Test status
Simulation time 35963972841 ps
CPU time 294.26 seconds
Started Aug 13 04:40:17 PM PDT 24
Finished Aug 13 04:45:12 PM PDT 24
Peak memory 415108 kb
Host smart-e0409840-11d3-4600-96d3-e9e114b75455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359323765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.2359323765 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_mubi/latest

Test location /workspace/coverage/default/6.kmac_sideload.715807775
Short name T655
Test name
Test status
Simulation time 1301970258 ps
CPU time 13.44 seconds
Started Aug 13 04:40:33 PM PDT 24
Finished Aug 13 04:40:47 PM PDT 24
Peak memory 226512 kb
Host smart-5d7bd9d0-fc46-4d54-9e6f-9ab10449bdf1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715807775 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.715807775 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_sideload/latest

Test location /workspace/coverage/default/6.kmac_smoke.1013478169
Short name T196
Test name
Test status
Simulation time 177565793 ps
CPU time 4.33 seconds
Started Aug 13 04:40:16 PM PDT 24
Finished Aug 13 04:40:21 PM PDT 24
Peak memory 225056 kb
Host smart-d2ea33b3-7625-4e5f-882d-45da72701b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013478169 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.1013478169 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_smoke/latest

Test location /workspace/coverage/default/6.kmac_stress_all.1584137215
Short name T301
Test name
Test status
Simulation time 29042034796 ps
CPU time 867.2 seconds
Started Aug 13 04:40:03 PM PDT 24
Finished Aug 13 04:54:30 PM PDT 24
Peak memory 605976 kb
Host smart-43d39b4a-90f9-4c22-89cc-4839fe675d9e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1584137215 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.1584137215 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_stress_all/latest

Test location /workspace/coverage/default/7.kmac_alert_test.3800441902
Short name T495
Test name
Test status
Simulation time 14039899 ps
CPU time 0.8 seconds
Started Aug 13 04:40:13 PM PDT 24
Finished Aug 13 04:40:14 PM PDT 24
Peak memory 218140 kb
Host smart-3c5624fc-f989-4d64-a361-73b25174ff9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800441902 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.3800441902 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_alert_test/latest

Test location /workspace/coverage/default/7.kmac_app.1386611215
Short name T94
Test name
Test status
Simulation time 4706010427 ps
CPU time 148.18 seconds
Started Aug 13 04:40:00 PM PDT 24
Finished Aug 13 04:42:28 PM PDT 24
Peak memory 318224 kb
Host smart-98794919-8a14-465c-890b-f5a2d72b222d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386611215 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.1386611215 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/7.kmac_app/latest

Test location /workspace/coverage/default/7.kmac_app_with_partial_data.3463107372
Short name T101
Test name
Test status
Simulation time 811302123 ps
CPU time 21.36 seconds
Started Aug 13 04:40:05 PM PDT 24
Finished Aug 13 04:40:27 PM PDT 24
Peak memory 241804 kb
Host smart-795548c8-df7a-4d05-afe0-3b7831a1da81
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463107372 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_par
tial_data.3463107372 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/7.kmac_burst_write.2652939621
Short name T640
Test name
Test status
Simulation time 36507865055 ps
CPU time 799.35 seconds
Started Aug 13 04:40:23 PM PDT 24
Finished Aug 13 04:53:42 PM PDT 24
Peak memory 251020 kb
Host smart-bf35c588-9fdb-4c39-ac47-312a527a9d5a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652939621 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.2652939621
+enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_burst_write/latest

Test location /workspace/coverage/default/7.kmac_edn_timeout_error.1172638028
Short name T516
Test name
Test status
Simulation time 46597227 ps
CPU time 1.35 seconds
Started Aug 13 04:40:02 PM PDT 24
Finished Aug 13 04:40:04 PM PDT 24
Peak memory 218424 kb
Host smart-4e1311b9-66e3-4abb-a048-a423f96a8846
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1172638028 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.1172638028 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_mode_error.821527037
Short name T119
Test name
Test status
Simulation time 181522706 ps
CPU time 1.4 seconds
Started Aug 13 04:40:04 PM PDT 24
Finished Aug 13 04:40:06 PM PDT 24
Peak memory 222220 kb
Host smart-1c5a4b6d-b5e9-455b-909e-cebfbc7166d9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=821527037 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.821527037 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_ready_error.346814312
Short name T575
Test name
Test status
Simulation time 1589373592 ps
CPU time 18.03 seconds
Started Aug 13 04:40:23 PM PDT 24
Finished Aug 13 04:40:42 PM PDT 24
Peak memory 221488 kb
Host smart-d2114e01-d7f5-4d3f-a873-19bbb6e8ac4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346814312 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.346814312 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_refresh.2917091330
Short name T326
Test name
Test status
Simulation time 48488800761 ps
CPU time 312.56 seconds
Started Aug 13 04:40:07 PM PDT 24
Finished Aug 13 04:45:20 PM PDT 24
Peak memory 425892 kb
Host smart-4f919e34-8b32-4d34-9363-038d3205b856
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917091330 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.29
17091330 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/7.kmac_error.2258900202
Short name T441
Test name
Test status
Simulation time 26913690840 ps
CPU time 79.39 seconds
Started Aug 13 04:40:19 PM PDT 24
Finished Aug 13 04:41:39 PM PDT 24
Peak memory 300436 kb
Host smart-a46b5f5e-b98d-4495-9bfa-9842450cc6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258900202 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.2258900202 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_error/latest

Test location /workspace/coverage/default/7.kmac_key_error.1002998112
Short name T116
Test name
Test status
Simulation time 827968172 ps
CPU time 6.28 seconds
Started Aug 13 04:40:21 PM PDT 24
Finished Aug 13 04:40:28 PM PDT 24
Peak memory 226488 kb
Host smart-82038581-34c5-4a6c-872f-4c11c99bd3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002998112 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.1002998112 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_key_error/latest

Test location /workspace/coverage/default/7.kmac_lc_escalation.4037108653
Short name T12
Test name
Test status
Simulation time 41144162 ps
CPU time 1.79 seconds
Started Aug 13 04:40:15 PM PDT 24
Finished Aug 13 04:40:17 PM PDT 24
Peak memory 226516 kb
Host smart-8f0835ac-2149-431c-acbc-a74615bc9fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037108653 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.4037108653 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/7.kmac_lc_escalation/latest

Test location /workspace/coverage/default/7.kmac_long_msg_and_output.541007855
Short name T102
Test name
Test status
Simulation time 101900243671 ps
CPU time 3896.3 seconds
Started Aug 13 04:40:00 PM PDT 24
Finished Aug 13 05:44:57 PM PDT 24
Peak memory 1799324 kb
Host smart-8d26db47-2332-40ac-8fbf-4a62fb9bee6e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541007855 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_and
_output.541007855 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/7.kmac_mubi.3832354613
Short name T344
Test name
Test status
Simulation time 36022208189 ps
CPU time 336.65 seconds
Started Aug 13 04:40:24 PM PDT 24
Finished Aug 13 04:46:06 PM PDT 24
Peak memory 334108 kb
Host smart-600f6615-d29e-4cc3-b66f-ab872e0f4fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832354613 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.3832354613 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_mubi/latest

Test location /workspace/coverage/default/7.kmac_sideload.662418173
Short name T678
Test name
Test status
Simulation time 6373335323 ps
CPU time 50.18 seconds
Started Aug 13 04:40:07 PM PDT 24
Finished Aug 13 04:40:57 PM PDT 24
Peak memory 257596 kb
Host smart-07533e98-6f2a-4ab1-ac48-4f40b33f49f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662418173 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.662418173 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_sideload/latest

Test location /workspace/coverage/default/7.kmac_smoke.2564846274
Short name T192
Test name
Test status
Simulation time 6157020738 ps
CPU time 60.87 seconds
Started Aug 13 04:40:28 PM PDT 24
Finished Aug 13 04:41:29 PM PDT 24
Peak memory 222572 kb
Host smart-0567d58c-67b2-4d30-b980-73274b4f9344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564846274 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.2564846274 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_smoke/latest

Test location /workspace/coverage/default/7.kmac_stress_all.4071106845
Short name T357
Test name
Test status
Simulation time 92952783336 ps
CPU time 837.79 seconds
Started Aug 13 04:40:14 PM PDT 24
Finished Aug 13 04:54:12 PM PDT 24
Peak memory 581872 kb
Host smart-039af84b-a97b-4aa0-b123-4d15e219a979
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4071106845 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.4071106845 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_stress_all/latest

Test location /workspace/coverage/default/7.kmac_stress_all_with_rand_reset.4279059821
Short name T50
Test name
Test status
Simulation time 4438955906 ps
CPU time 143.58 seconds
Started Aug 13 04:40:05 PM PDT 24
Finished Aug 13 04:42:28 PM PDT 24
Peak memory 257056 kb
Host smart-986ad5b2-fada-4515-9b77-b6b60abb32ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4279059821 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all_with_rand_reset.4279059821 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.kmac_alert_test.1100840856
Short name T118
Test name
Test status
Simulation time 19111001 ps
CPU time 0.86 seconds
Started Aug 13 04:40:18 PM PDT 24
Finished Aug 13 04:40:19 PM PDT 24
Peak memory 218252 kb
Host smart-1829d863-091c-4f4d-9b17-b0b6f2e8219d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100840856 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.1100840856 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_alert_test/latest

Test location /workspace/coverage/default/8.kmac_app.1134837672
Short name T289
Test name
Test status
Simulation time 47822502648 ps
CPU time 298.89 seconds
Started Aug 13 04:40:08 PM PDT 24
Finished Aug 13 04:45:08 PM PDT 24
Peak memory 418072 kb
Host smart-a8d536d9-93ce-48d8-8e82-82265898c9a1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134837672 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.1134837672 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/8.kmac_app/latest

Test location /workspace/coverage/default/8.kmac_app_with_partial_data.535450354
Short name T567
Test name
Test status
Simulation time 20038726044 ps
CPU time 129.35 seconds
Started Aug 13 04:40:09 PM PDT 24
Finished Aug 13 04:42:18 PM PDT 24
Peak memory 311440 kb
Host smart-da138aae-a355-4b8e-8b04-ab22e31cc839
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535450354 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_parti
al_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_part
ial_data.535450354 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/8.kmac_burst_write.2957894703
Short name T632
Test name
Test status
Simulation time 13429955208 ps
CPU time 156.1 seconds
Started Aug 13 04:40:10 PM PDT 24
Finished Aug 13 04:42:46 PM PDT 24
Peak memory 243180 kb
Host smart-b27dfd91-0b22-4833-a02e-f16ef1c41c73
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957894703 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.2957894703
+enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_burst_write/latest

Test location /workspace/coverage/default/8.kmac_edn_timeout_error.1404138328
Short name T197
Test name
Test status
Simulation time 2196045514 ps
CPU time 43.41 seconds
Started Aug 13 04:40:12 PM PDT 24
Finished Aug 13 04:40:56 PM PDT 24
Peak memory 235992 kb
Host smart-c2ca12d5-2d2d-4dc8-9e86-a2395671bebe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1404138328 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.1404138328 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_mode_error.1872160748
Short name T406
Test name
Test status
Simulation time 50018494 ps
CPU time 0.96 seconds
Started Aug 13 04:40:12 PM PDT 24
Finished Aug 13 04:40:13 PM PDT 24
Peak memory 220364 kb
Host smart-37624a37-78ca-4954-aa86-849d39910b50
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1872160748 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.1872160748 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_ready_error.1320400364
Short name T506
Test name
Test status
Simulation time 11723525519 ps
CPU time 21.98 seconds
Started Aug 13 04:40:10 PM PDT 24
Finished Aug 13 04:40:32 PM PDT 24
Peak memory 226752 kb
Host smart-5f05ab14-ae69-4487-bff2-f9126dc7403f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320400364 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.1320400364 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_refresh.487165570
Short name T17
Test name
Test status
Simulation time 13146435307 ps
CPU time 138.28 seconds
Started Aug 13 04:40:22 PM PDT 24
Finished Aug 13 04:42:41 PM PDT 24
Peak memory 319912 kb
Host smart-a9e51399-59e3-43c9-9cdc-6f19d146938a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487165570 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.487
165570 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/8.kmac_error.3976780248
Short name T470
Test name
Test status
Simulation time 27925176497 ps
CPU time 497.19 seconds
Started Aug 13 04:40:15 PM PDT 24
Finished Aug 13 04:48:33 PM PDT 24
Peak memory 380932 kb
Host smart-8e0e1eae-0e5e-4ddf-a3ea-0701c3bee9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976780248 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.3976780248 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_error/latest

Test location /workspace/coverage/default/8.kmac_key_error.3969802985
Short name T231
Test name
Test status
Simulation time 1688833593 ps
CPU time 11.86 seconds
Started Aug 13 04:40:24 PM PDT 24
Finished Aug 13 04:40:36 PM PDT 24
Peak memory 226436 kb
Host smart-295426d8-432f-48bf-91be-ad80e625ce30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969802985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.3969802985 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_key_error/latest

Test location /workspace/coverage/default/8.kmac_lc_escalation.1762623579
Short name T98
Test name
Test status
Simulation time 2316317250 ps
CPU time 14.25 seconds
Started Aug 13 04:40:14 PM PDT 24
Finished Aug 13 04:40:28 PM PDT 24
Peak memory 239576 kb
Host smart-3c75c19e-1705-4878-af29-66d7f03bf31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762623579 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.1762623579 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/8.kmac_lc_escalation/latest

Test location /workspace/coverage/default/8.kmac_long_msg_and_output.1844369985
Short name T641
Test name
Test status
Simulation time 25619674965 ps
CPU time 3117.58 seconds
Started Aug 13 04:40:10 PM PDT 24
Finished Aug 13 05:32:08 PM PDT 24
Peak memory 1611300 kb
Host smart-01531d39-49d4-4e1e-bf0f-229647218398
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844369985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_an
d_output.1844369985 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/8.kmac_mubi.3653798956
Short name T395
Test name
Test status
Simulation time 17987842962 ps
CPU time 272.88 seconds
Started Aug 13 04:40:20 PM PDT 24
Finished Aug 13 04:44:53 PM PDT 24
Peak memory 419768 kb
Host smart-ad5709c6-f0d0-497b-9730-ae41954ee8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653798956 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.3653798956 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_mubi/latest

Test location /workspace/coverage/default/8.kmac_sideload.3501118545
Short name T298
Test name
Test status
Simulation time 2466329105 ps
CPU time 44.72 seconds
Started Aug 13 04:40:07 PM PDT 24
Finished Aug 13 04:40:52 PM PDT 24
Peak memory 261840 kb
Host smart-c3f2196c-aa36-4dc0-8111-cc04b4dfab6c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501118545 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.3501118545 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_sideload/latest

Test location /workspace/coverage/default/8.kmac_smoke.3600516640
Short name T558
Test name
Test status
Simulation time 6692912635 ps
CPU time 49.51 seconds
Started Aug 13 04:40:12 PM PDT 24
Finished Aug 13 04:41:02 PM PDT 24
Peak memory 223936 kb
Host smart-5bfe324e-b058-450f-b28a-09fa116d1986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600516640 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.3600516640 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_smoke/latest

Test location /workspace/coverage/default/8.kmac_stress_all.539801481
Short name T348
Test name
Test status
Simulation time 86815447664 ps
CPU time 2190.48 seconds
Started Aug 13 04:40:26 PM PDT 24
Finished Aug 13 05:16:57 PM PDT 24
Peak memory 680664 kb
Host smart-74dcf7be-f892-48d1-bb66-552a900862cd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=539801481 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.539801481 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_stress_all/latest

Test location /workspace/coverage/default/9.kmac_alert_test.2031981717
Short name T619
Test name
Test status
Simulation time 42599101 ps
CPU time 0.8 seconds
Started Aug 13 04:40:10 PM PDT 24
Finished Aug 13 04:40:11 PM PDT 24
Peak memory 218180 kb
Host smart-6324547d-b81f-4b09-befc-11535a2183a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031981717 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.2031981717 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_alert_test/latest

Test location /workspace/coverage/default/9.kmac_app.2836421028
Short name T680
Test name
Test status
Simulation time 11442939782 ps
CPU time 274.14 seconds
Started Aug 13 04:40:11 PM PDT 24
Finished Aug 13 04:44:46 PM PDT 24
Peak memory 412660 kb
Host smart-63b8cfeb-9782-4932-bb42-9671adc9f34a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836421028 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.2836421028 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/9.kmac_app/latest

Test location /workspace/coverage/default/9.kmac_app_with_partial_data.2076568819
Short name T631
Test name
Test status
Simulation time 20085568758 ps
CPU time 221.14 seconds
Started Aug 13 04:40:08 PM PDT 24
Finished Aug 13 04:43:49 PM PDT 24
Peak memory 362056 kb
Host smart-718db896-3ece-448c-b356-fae487e7bfcb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076568819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_par
tial_data.2076568819 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/9.kmac_burst_write.2870557338
Short name T248
Test name
Test status
Simulation time 20858523713 ps
CPU time 1069.28 seconds
Started Aug 13 04:40:07 PM PDT 24
Finished Aug 13 04:57:57 PM PDT 24
Peak memory 244260 kb
Host smart-ad279b61-946d-47e3-90d1-b9b86cb3a196
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870557338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.2870557338
+enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_burst_write/latest

Test location /workspace/coverage/default/9.kmac_edn_timeout_error.159678532
Short name T455
Test name
Test status
Simulation time 8870656291 ps
CPU time 52.63 seconds
Started Aug 13 04:40:10 PM PDT 24
Finished Aug 13 04:41:02 PM PDT 24
Peak memory 236532 kb
Host smart-60611c54-f824-438c-a6bb-a0c274b77ba9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=159678532 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.159678532 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_mode_error.1518712595
Short name T454
Test name
Test status
Simulation time 49186213 ps
CPU time 1.34 seconds
Started Aug 13 04:40:16 PM PDT 24
Finished Aug 13 04:40:17 PM PDT 24
Peak memory 222236 kb
Host smart-8251faef-883b-48cf-a6b3-1d9d5dec7346
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1518712595 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.1518712595 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_ready_error.771063191
Short name T412
Test name
Test status
Simulation time 479345836 ps
CPU time 5.95 seconds
Started Aug 13 04:40:08 PM PDT 24
Finished Aug 13 04:40:14 PM PDT 24
Peak memory 221808 kb
Host smart-bff3e70b-bc70-42fd-8d63-b7b90fedf15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771063191 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.771063191 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_refresh.3272282118
Short name T226
Test name
Test status
Simulation time 5873293922 ps
CPU time 140.46 seconds
Started Aug 13 04:40:23 PM PDT 24
Finished Aug 13 04:42:43 PM PDT 24
Peak memory 328048 kb
Host smart-abdc2257-cba2-42e9-a069-513041094400
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272282118 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.32
72282118 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/9.kmac_error.840486527
Short name T160
Test name
Test status
Simulation time 29870581730 ps
CPU time 237.88 seconds
Started Aug 13 04:40:22 PM PDT 24
Finished Aug 13 04:44:21 PM PDT 24
Peak memory 403108 kb
Host smart-ab9ca9b4-bf29-4889-8c8e-e464abf8f2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840486527 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.840486527 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_error/latest

Test location /workspace/coverage/default/9.kmac_key_error.1526686871
Short name T207
Test name
Test status
Simulation time 436169476 ps
CPU time 3.46 seconds
Started Aug 13 04:40:13 PM PDT 24
Finished Aug 13 04:40:17 PM PDT 24
Peak memory 226388 kb
Host smart-3f7b349d-100b-41a3-9929-da18ff9849b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526686871 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.1526686871 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_key_error/latest

Test location /workspace/coverage/default/9.kmac_lc_escalation.4016830345
Short name T665
Test name
Test status
Simulation time 127405879 ps
CPU time 1.34 seconds
Started Aug 13 04:40:12 PM PDT 24
Finished Aug 13 04:40:14 PM PDT 24
Peak memory 226600 kb
Host smart-12bfc1e8-b02b-4eb7-8a6e-070f46be98ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016830345 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.4016830345 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/9.kmac_lc_escalation/latest

Test location /workspace/coverage/default/9.kmac_long_msg_and_output.1251097846
Short name T411
Test name
Test status
Simulation time 44505686128 ps
CPU time 1267.18 seconds
Started Aug 13 04:40:32 PM PDT 24
Finished Aug 13 05:01:40 PM PDT 24
Peak memory 869064 kb
Host smart-ab473af9-ef39-45c3-a6f8-ec3a90d6122f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251097846 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_an
d_output.1251097846 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/9.kmac_mubi.114152794
Short name T3
Test name
Test status
Simulation time 5286777146 ps
CPU time 134.29 seconds
Started Aug 13 04:40:22 PM PDT 24
Finished Aug 13 04:42:36 PM PDT 24
Peak memory 327388 kb
Host smart-c1c6bc83-a484-452d-876d-80b5ef9e7664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114152794 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.114152794 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_mubi/latest

Test location /workspace/coverage/default/9.kmac_sideload.2557306582
Short name T607
Test name
Test status
Simulation time 5940980486 ps
CPU time 238.41 seconds
Started Aug 13 04:40:19 PM PDT 24
Finished Aug 13 04:44:17 PM PDT 24
Peak memory 300468 kb
Host smart-f23e0507-e327-4af8-badd-9a66fa00a935
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557306582 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.2557306582 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_sideload/latest

Test location /workspace/coverage/default/9.kmac_smoke.1862539756
Short name T450
Test name
Test status
Simulation time 491435996 ps
CPU time 12.23 seconds
Started Aug 13 04:40:08 PM PDT 24
Finished Aug 13 04:40:20 PM PDT 24
Peak memory 221984 kb
Host smart-dcd08929-fad7-41c9-8203-08f356be037d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862539756 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.1862539756 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_smoke/latest

Test location /workspace/coverage/default/9.kmac_stress_all.2344672459
Short name T484
Test name
Test status
Simulation time 109721607398 ps
CPU time 603.3 seconds
Started Aug 13 04:40:26 PM PDT 24
Finished Aug 13 04:50:29 PM PDT 24
Peak memory 492548 kb
Host smart-471c7aae-a0f6-410a-91a9-78b1b43afda9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2344672459 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.2344672459 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_stress_all/latest

Test location /workspace/coverage/default/9.kmac_stress_all_with_rand_reset.4087342296
Short name T131
Test name
Test status
Simulation time 1918597984 ps
CPU time 38 seconds
Started Aug 13 04:40:18 PM PDT 24
Finished Aug 13 04:40:57 PM PDT 24
Peak memory 243144 kb
Host smart-6b531a8f-7b4f-47fe-ac99-b18a36d6aac5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4087342296 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all_with_rand_reset.4087342296 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_stress_all_with_rand_reset/latest
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