Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	14542921	1			T1	284		T2	14653		T7	1276
all_values[1]	14542921	1			T1	284		T2	14653		T7	1276
all_values[2]	14542921	1			T1	284		T2	14653		T7	1276

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

482362

1

T7

275

T22

150

T34

258

auto[1]

43146401

1

T1

852

T2

43959

T7

3553

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

43405092

1

T1

708

T2

43509

T7

3786

auto[1]

223671

1

T1

144

T2

450

T7

42

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	183077	1			T7	1		T34	127		T8	66
all_values[0]	auto[0]	auto[1]	1273	1			T34	2		T8	2		T15	6
all_values[0]	auto[1]	auto[0]	14285287	1			T1	236		T2	14503		T7	1261
all_values[0]	auto[1]	auto[1]	73284	1			T1	48		T2	150		T7	14
all_values[1]	auto[0]	auto[0]	145654	1			T7	273		T22	149		T34	127
all_values[1]	auto[0]	auto[1]	951	1			T7	1		T22	1		T34	2
all_values[1]	auto[1]	auto[0]	14322710	1			T1	236		T2	14503		T7	989
all_values[1]	auto[1]	auto[1]	73606	1			T1	48		T2	150		T7	13
all_values[2]	auto[0]	auto[0]	150450	1			T15	2666		T23	148		T57	2
all_values[2]	auto[0]	auto[1]	957	1			T15	6		T23	1		T57	1
all_values[2]	auto[1]	auto[0]	14317914	1			T1	236		T2	14503		T7	1262
all_values[2]	auto[1]	auto[1]	73600	1			T1	48		T2	150		T7	14