Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55878 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T7 |
2 |
auto[1] |
56430 |
1 |
|
|
T1 |
58 |
|
T2 |
212 |
|
T7 |
24 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
27728 |
1 |
|
|
T1 |
20 |
|
T2 |
45 |
|
T7 |
2 |
lower_val |
27796 |
1 |
|
|
T1 |
8 |
|
T2 |
44 |
|
T7 |
12 |
zero_val |
808 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
41612 |
1 |
|
|
T1 |
24 |
|
T2 |
62 |
|
T7 |
2 |
lower_val |
42340 |
1 |
|
|
T1 |
6 |
|
T2 |
38 |
|
T7 |
2 |
zero_val |
28356 |
1 |
|
|
T1 |
30 |
|
T2 |
114 |
|
T7 |
22 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
6676 |
1 |
|
|
T34 |
1 |
|
T8 |
23 |
|
T15 |
27 |
higher_val |
higher_val |
auto[1] |
3461 |
1 |
|
|
T1 |
6 |
|
T2 |
10 |
|
T22 |
3 |
higher_val |
lower_val |
auto[0] |
6917 |
1 |
|
|
T8 |
15 |
|
T15 |
30 |
|
T57 |
33 |
higher_val |
lower_val |
auto[1] |
3614 |
1 |
|
|
T1 |
3 |
|
T2 |
9 |
|
T22 |
2 |
higher_val |
zero_val |
auto[0] |
51 |
1 |
|
|
T61 |
1 |
|
T178 |
1 |
|
T50 |
2 |
higher_val |
zero_val |
auto[1] |
7009 |
1 |
|
|
T1 |
11 |
|
T2 |
26 |
|
T7 |
2 |
lower_val |
higher_val |
auto[0] |
6888 |
1 |
|
|
T8 |
25 |
|
T15 |
23 |
|
T20 |
1 |
lower_val |
higher_val |
auto[1] |
3540 |
1 |
|
|
T1 |
4 |
|
T2 |
10 |
|
T7 |
1 |
lower_val |
lower_val |
auto[0] |
6886 |
1 |
|
|
T8 |
16 |
|
T15 |
31 |
|
T23 |
1 |
lower_val |
lower_val |
auto[1] |
3462 |
1 |
|
|
T1 |
2 |
|
T2 |
5 |
|
T7 |
1 |
lower_val |
zero_val |
auto[0] |
64 |
1 |
|
|
T2 |
1 |
|
T7 |
1 |
|
T22 |
1 |
lower_val |
zero_val |
auto[1] |
6956 |
1 |
|
|
T1 |
2 |
|
T2 |
28 |
|
T7 |
9 |
zero_val |
higher_val |
auto[0] |
235 |
1 |
|
|
T34 |
1 |
|
T15 |
1 |
|
T20 |
1 |
zero_val |
higher_val |
auto[1] |
58 |
1 |
|
|
T15 |
2 |
|
T16 |
2 |
|
T80 |
1 |
zero_val |
lower_val |
auto[0] |
257 |
1 |
|
|
T8 |
1 |
|
T15 |
2 |
|
T23 |
1 |
zero_val |
lower_val |
auto[1] |
60 |
1 |
|
|
T16 |
1 |
|
T17 |
2 |
|
T51 |
1 |
zero_val |
zero_val |
auto[0] |
158 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
zero_val |
zero_val |
auto[1] |
40 |
1 |
|
|
T15 |
1 |
|
T16 |
1 |
|
T17 |
1 |